Methods for monitoring mechanical stress in EPI CMP

Abstract

This invention discloses a method for monitoring EPI CMP mechanical stress, comprising the following steps: providing an N-type substrate wafer with a deep trench structure; filling the deep trench with a P-type epitaxial layer of a predetermined doping concentration; performing EPI CMP planarization on the wafer after filling the P-type epitaxial layer; performing high-temperature heat treatment on the EPI CMP-treated wafer; growing a sacrificial oxide layer on the surface of the high-temperature heat-treated wafer and removing the sacrificial oxide layer; and performing defect scanning on the treated wafer to achieve monitoring of wafer lattice damage caused by EPI CMP mechanical stress. This invention utilizes high-temperature heat treatment to amplify and degrade the minute lattice damage caused by EPI CMP mechanical stress, and then, through the sacrificial oxide layer growth and removal process, further expands the degraded defects into detectable native crystal pit defects, ultimately achieving accurate monitoring through conventional defect scanning.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for monitoring mechanical stress in EPI CMP. Background Technology

[0002] Chemical Mechanical Polishing (CMP) is a key process in the manufacturing of very large-scale integrated circuits (VLSI) to achieve global planarization of the wafer surface, interlayer dielectric planarization, and planarization of metal gates and interconnect structures. It is also the only technology in current semiconductor manufacturing processes that can simultaneously achieve global and local planarization. The working principle of CMP is as follows: During polishing, a polishing slurry containing abrasive particles is uniformly supplied to the surface of the polishing pad by a polishing slurry delivery system. The wafer is held by the polishing head and pressed against the rotating polishing pad under a set pressure. The wafer surface material first reacts chemically with the chemically active components in the polishing slurry, forming a reaction layer on the wafer surface that is low in hardness, loosely structured, and easily removable. Subsequently, under the combined action of the relative rotational motion of the polishing head and the polishing table, the micro-cutting action of the abrasive particles, and the positive pressure applied by the polishing head, the surface layer formed by the chemical reaction is mechanically removed. Through the synergistic effect of chemical and mechanical action, the uneven protrusions on the wafer surface are gradually removed layer by layer, ultimately obtaining a wafer surface with atomically flatness.

[0003] In actual CMP polishing operations, wafers are subjected to unavoidable mechanical stress due to the combined effects of various process and structural factors. Specifically, factors such as uneven pressure applied to the wafer by the polishing head, differences in local contact states between the wafer and the polishing pad, uneven distribution of pattern density on the wafer surface, decay of the polishing pad surface condition, and uneven distribution of polishing slurry can all lead to localized concentrated mechanical stress or overall distributed mechanical stress on the wafer during polishing. This type of mechanical stress acts directly on the wafer surface and internal crystal structure, easily inducing multiple defects in the wafer: at the microscopic level, it can form defects such as microscratch, dislocations, lattice distortion, and lattice damage; at the macroscopic level, it can cause wafer warping, deformation, and edge chipping. Among these, lattice damage caused by mechanical stress is a highly concealed deep defect that cannot be directly detected by visual inspection or conventional surface testing. This type of defect significantly alters key electrical parameters within the wafer, such as carrier mobility, breakdown voltage, and leakage current, directly leading to a decline in the electrical performance and reliability of semiconductor devices, ultimately resulting in a substantial reduction in chip yield. Therefore, to ensure the stability of the CMP process and device performance, it is crucial to implement effective, accurate, and stable online monitoring of wafer lattice damage caused by mechanical stress during the CMP process.

[0004] In existing technologies, conventional monitoring methods for CMP processes mostly involve directly scanning the surface of the wafer after CMP polishing. These methods can only capture visible macroscopic defects and some obvious microscopic defects on the wafer surface, lacking the ability to effectively identify micro-lattice damage induced by mechanical stress. Such micro-lattice damage exhibits weak signals and insignificant characterization under conventional optical or electron microscopy conditions, making it easily overlooked by the detection system, resulting in numerous missed detections. This is particularly true for epitaxial layer chemical mechanical polishing (EPI CMP) processes, where the epitaxial layer itself requires extremely high lattice integrity; even minor mechanical stress damage can severely impact quality. Existing monitoring methods cannot accurately characterize and quantify EPI CMP mechanical stress damage, leading to untimely detection of process deviations, distorted monitoring results, and ultimately, decreased CMP process stability, continuous fluctuations in device yield, and increased production costs. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] This invention addresses the technical problem in existing technologies where direct defect scanning of wafers after CMP (Continuous Mechanical Processing) fails to effectively detect minute lattice damage caused by mechanical stress, leading to inaccurate monitoring of the EPI CMP process and low device yield. This invention provides a method for monitoring mechanical stress during EPI CMP.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for monitoring EPI CMP mechanical stress, comprising the following steps: Provide N-type substrate wafers with deep trench structures; A P-type epitaxial layer with a set doping concentration is filled into the deep trench; EPI CMP planarization was performed on the wafer after filling the P-type epitaxial layer; The wafers after EPI CMP treatment are subjected to high-temperature heat treatment; A sacrificial oxide layer is grown on the surface of the wafer after high-temperature heat treatment, and then the sacrificial oxide layer is removed; Defect scanning is performed on the processed wafers to monitor wafer lattice damage caused by EPI CMP mechanical stress.

[0008] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the wafer is a 12-inch wafer.

[0009] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the high-temperature heat treatment temperature range is 1000℃~1200℃.

[0010] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the high-temperature heat treatment temperature is 1100°C.

[0011] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the sacrificial oxide layer is a thermal oxide layer.

[0012] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the defect scanning is used to detect voids and crystal native pits (COPs) on the wafer surface.

[0013] Optionally, the method for monitoring EPI CMP mechanical stress can be further improved, wherein the micro lattice damage caused by the EPI CMP mechanical stress deteriorates after high-temperature heat treatment, and then expands into detectable defects after sacrificial oxide layer growth and removal.

[0014] The working principle of this invention is explained as follows: This invention addresses the problem of minute, hidden lattice damage on the wafer surface and interior that is difficult to detect by conventional methods due to mechanical stress during the EPI CMP process. It employs a two-step defect amplification mechanism: high-temperature heat treatment followed by sacrificial oxide layer growth and removal. First, a high-temperature furnace tube heat treatment process thermally activates, migrates, and aggregates the minute lattice defects introduced by EPI CMP mechanical stress in the wafer's P / N junction region and the surface of the P-type epitaxial layer, achieving initial defect degradation and amplification. Then, a thermal oxide layer is grown on the wafer surface as a sacrificial oxide layer, which is then completely removed. Utilizing the interfacial interaction between the lattice stress during oxidation and the oxide layer peeling, the degraded lattice defects are further amplified, fixed, and exposed on the wafer surface, transforming them into void defects and crystal native pit (COP) defects that can be reliably identified and captured by conventional defect detection equipment. Finally, standardized defect scanning of the wafer directly and accurately characterizes the EPI based on the number, size, and distribution characteristics of void and COP defects. The extent of lattice damage caused by CMP mechanical stress to the wafer is assessed, thereby enabling effective monitoring of EPI CMP mechanical stress.

[0015] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects: (1) The present invention significantly improves the defect detection rate compared with the prior art, and realizes the detectability of hidden lattice damage; High-temperature heat treatment can cause micro-lattice damage invisible under normal conditions to undergo thermal evolution and structural degradation, transforming atomic / submicron level hidden defects into primary defects with obvious structural characteristics. The sacrificial oxide layer growth and removal process further expands these primary defects into micron-level identifiable defects, fundamentally solving the technical pain point that existing technologies cannot directly detect micro-lattice damage induced by EPI CMP mechanical stress, significantly improving defect detection sensitivity and coverage, and can stably and reliably capture all lattice damage caused by EPI CMP mechanical stress.

[0016] (2) The monitoring results of this invention are accurate and reliable, and can achieve quantitative characterization and process stability judgment; This invention uses voids and crystal native pits (COPs) as direct characterization indicators of mechanical stress damage in EPI CMP. These defects exhibit high signal intensity, clear morphological characteristics, no background interference, and can be statistically analyzed in terms of quantity and size in the detection equipment. This enables quantitative, visual, and repeatable detection of defects, effectively avoiding the problems of weak signals, easy false detection, and high false negatives in conventional direct detection methods. The monitoring results truly reflect the mechanical stress level of EPI CMP, providing accurate data support for process adjustment and equipment maintenance.

[0017] (3) The process of this invention has strong adaptability and compatibility, and can be directly embedded into existing production line processes; This invention is based on a 12-inch standard wafer. The EPI CMP, high-temperature furnace tube, thermal oxidation, oxide layer removal, and defect scanning used are all standard processes and equipment used in semiconductor manufacturing lines. No new dedicated equipment, process modifications, or additional material systems are required. It can be directly integrated into the existing CMP process monitoring flow, is highly compatible with current semiconductor processes, has low implementation costs, is easy to operate, and can be mass-produced. It can meet the requirements of high efficiency, stability, and economy for process monitoring in large-scale manufacturing lines. Attached Figure Description

[0018] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0019] Figure 1 These are comparison images of wafer morphology with and without CMP process; Figure 2 This is a flowchart comparing the present invention with traditional monitoring methods; Figure 3 Schematic diagram of the mechanism of lattice damage degradation amplification Figure 1 ; Figure 4 Schematic diagram of the mechanism of lattice damage degradation amplification Figure 2 ; Figure 5 Schematic diagram of the mechanism of lattice damage degradation amplification Figure 3 .

[0020] Figure 6 Schematic diagram of the mechanism of lattice damage degradation amplification Figure 4 . Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. Example

[0022] This invention provides a method for monitoring the mechanical stress of EPI CMP, comprising the following steps: A 12-inch N-type substrate wafer with a deep trench structure is selected, and a P-type epitaxial layer (PEI) with a set doping concentration is filled in the deep trench of the wafer.

[0023] EPI CMP planarization is performed on the wafer after P EPI filling.

[0024] The CMP-treated wafers are then placed in a furnace tube for high-temperature heat treatment at 1100°C.

[0025] A thermal oxide layer, namely a sacrificial oxide layer, is grown on the surface of the wafer after high-temperature treatment.

[0026] After removing the sacrificial oxide layer on the wafer surface, the tiny lattice defects are amplified into Void and COP defects after growth and removal.

[0027] Defect scanning is performed on the wafers that have completed the above steps to detect the number and distribution of voids and lattice defects, and to complete EPI CMP mechanical stress damage monitoring.

[0028] The mechanical stress generated by EPI CMP in the above embodiment forms micro-lattice damage at the P / N interface and on the P EPI surface. After high-temperature treatment at 1100℃, the micro-lattice damage deteriorates further. After sacrificial oxide layer growth and removal, the deteriorated defects are further expanded and cannot be eliminated by the process. They are finally presented in the form of Void and COP, which can be stably captured by defect detection equipment and accurately characterize the degree of lattice damage to the wafer caused by CMP mechanical stress.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0030] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for monitoring mechanical stress in EPI CMP, characterized in that, Includes the following steps: Provide N-type substrate wafers with deep trench structures; A P-type epitaxial layer with a set doping concentration is filled into the deep trench; EPI CMP planarization was performed on the wafer after filling the P-type epitaxial layer; The wafers after EPI CMP treatment are subjected to high-temperature heat treatment; A sacrificial oxide layer is grown on the surface of the wafer after high-temperature heat treatment, and then the sacrificial oxide layer is removed; Defect scanning is performed on the processed wafers to monitor wafer lattice damage caused by EPI CMP mechanical stress.

2. The method for monitoring EPI CMP mechanical stress according to claim 1, characterized in that: The wafer is a 12-inch wafer.

3. The method for monitoring EPI CMP mechanical stress according to claim 1, characterized in that: The temperature range of the high-temperature heat treatment is 1000℃~1200℃.

4. The method for monitoring EPI CMP mechanical stress according to claim 3, characterized in that: The high-temperature heat treatment temperature is 1100℃.

5. The method for monitoring EPI CMP mechanical stress according to claim 1, characterized in that: The sacrificial oxide layer is a thermal oxide layer.

6. The method for monitoring EPI CMP mechanical stress according to claim 1, characterized in that: The defect scan is used to detect voids and crystal native pits (COPs) on the wafer surface.

7. The method for monitoring EPI CMP mechanical stress according to claim 1, characterized in that: The micro-lattice damage caused by the mechanical stress of EPI CMP deteriorates after high-temperature heat treatment, and then expands into detectable defects after sacrificial oxide layer growth and removal.

Images