Method for self-compensation of silicon piezoresistive chip single-bridge structure

Abstract

This invention provides a method for a self-compensation scheme of a single-bridge structure for silicon piezoresistive chips, belonging to the field of silicon piezoresistive chip technology. It includes the following steps: S1: Selecting crystal-oriented single-crystal silicon as the chip substrate, followed by pretreatment; S2: Preparing the sensitive film using wet etching or dry etching processes according to the target pressure range of the sensor; S3: Doping and shaping the piezoresistive strip using diffused silicon or SOI processes; S4: Dividing the sensitive film into a high-stress area at the edge and a secondary high-stress area on the inner side of the edge, and implementing differentiated partitioning. This invention overcomes the inherent technical shortcomings of traditional silicon piezoresistive chips through an innovative single-bridge differentiated structure self-compensation design, and achieves full-domain suppression of common-mode interference through a purely physical structure. The entire process requires no algorithm compensation, no modification to the hardware structure or packaging process, and possesses significant technical advantages and industrialization value compared to existing pressure sensors.

Description

Technical Field

[0001] This invention relates to the field of silicon piezoresistive chip technology, and in particular to a method for a self-compensation scheme of a single-bridge structure for silicon piezoresistive chips. Background Technology

[0002] Silicon piezoresistive pressure sensors are the most widely used pressure sensor devices in instrumentation, industrial testing, and semiconductor sensing. Their core sensing component is a silicon piezoresistive chip, which mainly consists of a substrate, a piezoresistive strip, and a base plate. The substrate primarily isolates packaging stress and determines the overall measurement method of the chip. The substrate is prepared by removing redundant structures using wet or dry etching processes to create a sensitive film capable of deformation under stress. The piezoresistive strip, as the core sensing element, is fabricated using diffused silicon or SOI processes. In conventional structures, it is uniformly arranged at the edge of the sensitive film and generates a resistance change after the sensitive film is deformed under stress, thus converting the mechanical pressure signal into an electrical signal.

[0003] However, traditional silicon piezoresistive chip structures have inherent technical defects. The conventional chip piezoresistive strip layout in the industry is simple, resulting in low pressure sensitivity and a large temperature coefficient. During chip packaging and actual use, factors such as packaging stress, manufacturing process deviations, ambient temperature fluctuations, and baseline pressure disturbances can generate global common-mode interference, causing the resistance values ​​of all piezoresistive strips to shift. Traditional single-bridge structures cannot cancel or filter this type of common-mode interference, directly leading to problems such as decreased sensor pressure measurement accuracy, poor measurement stability, and short calibration cycles, thus limiting the application of this type of sensor in high-end precision testing scenarios. Summary of the Invention

[0004] The purpose of this invention is to provide a self-compensation scheme for a single-bridge structure of silicon piezoresistive chips to solve the above-mentioned problems. By using a differentiated self-compensation design of the single-bridge structure, it overcomes the inherent technical shortcomings of traditional silicon piezoresistive chips and achieves global suppression of common-mode interference by relying on a purely physical structure. This solves the problems mentioned in the background art, such as the single layout of piezoresistive strips in conventional chips, low pressure sensitivity, and large temperature coefficient. In chip packaging and actual use, factors such as packaging stress, manufacturing process deviations, ambient temperature fluctuations, and baseline pressure disturbances can generate global common-mode interference, causing the resistance values ​​of all piezoresistive strips to shift in the same direction.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: The method for self-compensation of a single-bridge structure for silicon piezoresistive chips includes the following: S1: Select crystal-oriented single-crystal silicon as the chip substrate, and then perform pretreatment. S2: Based on the target pressure range of the sensor, a sensitive film is prepared using either wet etching or dry etching processes; S3: Piezoresistive strips are formed by doping using diffused silicon or SOI processes; S4: Divide the high-stress zone at the edge of the sensitive membrane into a secondary high-stress zone on the inner side of the edge, and implement a differentiated zoning layout; S5: Construct a single Wheatstone bridge according to the standard Wheatstone bridge circuit logic; S6: Determine the appropriate compensation scheme based on the actual measured absolute pressure, gauge pressure, and differential pressure of the sensor; S7: Fabricate the chip substrate structure to achieve chip packaging stress adaptation; S8: Perform operational testing on the packaged pressure sensor to calibrate its performance and verify its effectiveness.

[0006] Optionally, step S1 includes the following: S11: Based on the MEMS silicon piezoresistive chip fabrication standard, single crystal silicon is selected as the chip substrate, and the optimal crystal orientation (100) is matched. This crystal orientation can maximize the piezoresistive effect of silicon material, ensure the sensitivity and response accuracy of the subsequent piezoresistive strip, and avoid the measurement error caused by the material itself from the substrate level. S12: Perform comprehensive surface cleaning on the selected single-crystal silicon substrate. Through a standardized process of organic solvent cleaning, deionized water rinsing, and high-temperature drying, remove impurities such as dust, oil, and oxide layers from the substrate surface to ensure that the substrate surface cleanliness meets the stringent requirements of subsequent photolithography and ion doping processes. S13: Polish and stress homogenize the cleaned substrate to correct the microscopic flatness of the substrate surface, eliminate residual stress inside and on the surface of the substrate, avoid initial interference caused by the substrate's own stress, and ensure the uniformity and stability of subsequent sensitive film preparation and piezoresistive strip layout.

[0007] Optionally, step S2 includes the following: S21: Based on the target pressure measurement range of the sensor, set the thickness, size and deformation parameters of the sensitive film, combine with the overall chip structure layout, plan the etching area at the bottom of the substrate, and clarify the boundary range between the retained area and the removed area to ensure that the sensitive film structure is adapted to the measurement range requirements. S22: Using mature MEMS processes such as wet etching or dry etching, the substrate bottom area is etched and thinned, and the structure is shaped. Excess silicon structure is removed from the substrate layer by layer. The etching rate and etching depth are strictly controlled to avoid over-etching and under-etching, and to ensure the dimensional accuracy and thickness uniformity of the sensitive film. S23: After etching, the sensitive film is passivated to repair the edge structure of the film and eliminate the microstructural defects caused by the etching process. This process produces a flexible sensitive film with uniform stress response, regular elastic deformation, and strong structural stability, ensuring that uniform and reversible elastic deformation can occur under external pressure.

[0008] Optionally, step S3 includes the following: S31: Based on the chip sensitivity and resistance matching design requirements, diffused silicon process or SOI process is selected as the piezoresistive strip preparation process. Combined with the target electrical parameters, the ion doping concentration, doping junction depth and doping region range are preset to ensure the basic performance consistency of the four sets of piezoresistive strips. S32: In the pre-set piezoresistive strip arrangement area of ​​the sensitive membrane, ion implantation or concentrated boron diffusion doping process is implemented. The process parameters such as doping temperature, vacuum degree, and ion flux are strictly controlled to form four piezoresistive sensitive strips R1, R2, R3, and R4 in sequence, ensuring that the resistance value, piezoresistive coefficient, and stress response performance of each piezoresistive strip are highly matched. S33: After doping, high-temperature annealing and curing treatment is performed to activate the doped ions, repair the lattice defects generated during the doping process, stabilize the electrical performance of the piezoresistive strip, avoid resistance drift during subsequent use, and ensure the stability and consistency of the piezoresistive strip in long-term operation.

[0009] Optionally, step S4 includes the following: S41: By calibrating through simulation, the stress regions of the sensitive membrane are divided, the high stress region at the edge of the sensitive membrane and the secondary high stress region inside the edge are defined, the stress response characteristics of the two regions are clarified, and the core characteristics of high piezoresistive sensitivity and opposite deformation response directions of the two regions are confirmed, providing a structural basis for differentiated layout. S42: According to the core layout logic of this invention, the formed R1 and R4 piezoresistive strips are fixedly arranged in the high stress area at the edge of the sensitive membrane, and the R2 and R3 piezoresistive strips are fixedly arranged in the second highest stress area inside the edge of the sensitive membrane. The position, spacing and angle of each piezoresistive strip are strictly controlled to ensure layout accuracy. S43: After the layout is completed, verify the stress response characteristics of each group of pressure resistance strips to ensure that the stress sensitivity direction of the pressure resistance strips on the same side of R1 and R4 is consistent, and the stress sensitivity direction of the pressure resistance strips of R2 and R3 is opposite to that of R1 and R4, forming a stable differentiated stress response structure to meet the basic conditions for self-compensation.

[0010] Optionally, step S5 includes the following: S51: Based on the standard Wheatstone bridge electrical connection logic, the internal metal lead routing path of the chip is planned, the layout of the four sets of piezoresistive bars is matched, the routing length and layout are optimized, the problems of line crossing and signal interference are avoided, and the circuit conduction stability is guaranteed. S52: Metal leads are prepared by metal evaporation, photolithography and etching processes, and four sets of piezoresistive strips R1, R2, R3 and R4 are electrically connected to construct a complete and independent single Wheatstone bridge circuit, forming a symmetrical and stable bridge circuit structure. S53: Strictly matches the electrode layout specifications of traditional silicon piezoresistive chips, retaining only the conventional number of electrodes without adding any new electrodes or lead structures, ensuring that the chip hardware structure and packaging interface are compatible with traditional chips, and requiring no adaptation or modification of subsequent production line equipment.

[0011] Optionally, step S6 includes the following: S61: Based on the actual application scenarios of the sensor, different measurement conditions of absolute pressure, gauge pressure and differential pressure are distinguished. Combining the pressure change characteristics and stress response requirements of the working conditions, the optimal structural configuration is matched from four single bridge self-compensation schemes to complete the chip structure design. S62: Simulates common-mode interference scenarios in real-world applications such as packaging stress, ambient temperature fluctuations, and manufacturing process deviations. Performs full-domain detection on the resistance change characteristics of four sets of piezoresistive strips and records the resistance offset direction and amount of each set of piezoresistive strips. S63: By fine-tuning process parameters to complete stress adaptation calibration, it ensures that when all external common-mode interference acts on the chip, the resistance values ​​of the four sets of piezoresistive bars R1, R2, R3, and R4 remain in the same direction and with equal amplitude. This is the core premise for stable bridge differential cancellation and ensures the interference compensation effect.

[0012] Optionally, step S7 includes the following: S71: A dedicated substrate structure is prepared on the back side of the substrate. The substrate is made of a highly stable insulating material. The substrate is formed through a precision bonding and curing process. The substrate structure is used to isolate external packaging stress and block the interference of packaging stress on the sensitive film and piezoresistive strip. S72: Adopts industry-standard MEMS chip packaging technology to encapsulate and solidify the formed bridge chip as a whole, strictly controlling parameters such as packaging temperature, pressure, and curing time to avoid additional stress deviations and structural deformations caused by the packaging process. S73: After packaging, structural curing is performed, static aging is allowed to stabilize the internal structure of the chip, eliminate residual stress from packaging, lock the piezoresistive strip layout and bridge circuit structure, and ensure that the structural and electrical performance of the chip does not drift during long-term use.

[0013] Optionally, step S8 includes the following: S81: Build a standard pressure and temperature test platform to perform multi-condition tests on the packaged silicon piezoresistive pressure sensor. Apply standard pressure and ambient temperature of different gradients respectively, and collect the differential output voltage signals V1-V2 of the bridge. S82: Detects the pressure response accuracy of the sensor and verifies that the chip output signal can correspond to pressure changes under external pressure. S83: Then, the suppression effect of common-mode interference such as temperature and residual stress in the packaging is tested to confirm that the interference signal can be canceled out through differential operation.

[0014] Optionally, step S8 further includes: S84: Completes multi-point precision calibration and stability testing, corrects minor process errors, and solidifies chip operating parameters; S85: Based on the above, the product is finalized by achieving high-precision and high-stability pressure detection with no algorithm involvement and pure structural self-compensation.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: This invention overcomes the inherent technical shortcomings of traditional silicon piezoresistive chips through an innovative single-bridge differentiated structure self-compensation design, and achieves full-domain suppression of common-mode interference by relying on a purely physical structure. This makes the entire process require no algorithm compensation, no modification to hardware structure or packaging process, and has significant technical advantages and industrialization value compared to existing pressure sensors. The special design of this invention can offset various common-mode interferences such as packaging stress, temperature changes, process deviations, and baseline pressure, solving the problems of accuracy drift and poor stability of traditional silicon piezoresistive sensors, effectively improving pressure detection accuracy, while significantly extending the equipment calibration cycle and improving the long-term service reliability of the product. While retaining the advantages of traditional products such as low cost, high versatility, high response speed, and mature technology, this invention overcomes the shortcomings of low pressure sensitivity, large temperature drift, and weak anti-common-mode interference capability, achieving a leapfrog upgrade in the overall performance of the product. The overall process of this invention does not require complex closed-loop control circuits and precision resonant structures, making the fabrication process simpler and the production cost lower. At the same time, it is compatible with all scenarios of absolute pressure, gauge pressure and differential pressure measurement, with faster frequency response and a wider range of applications. This invention is superior to silicon capacitive pressure sensors. It has no large mass block structure, the chip is smaller and more integrated, it has stronger resistance to electromagnetic interference and mechanical vibration interference, lower production and packaging costs, and lower barriers to industrialization. This invention only optimizes the layout structure of the piezoresistive strip. The number of chip electrodes, overall size, manufacturing process, and packaging technology are compatible with traditional chips. No modification is required to the existing MEMS production line. The pure structural self-compensation method has a low failure rate and strong stability, and has extremely high value for large-scale mass production and market promotion.

[0016] The above-mentioned scheme is the method of self-compensation scheme for silicon piezoresistive chip single bridge structure provided in this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the invention and, together with the specification, further serve to explain the principles of the invention and enable those skilled in the art to practice and use the invention.

[0018] Figure 1 This is a schematic diagram illustrating the change in resistance value of the pressure resistance strip under external pressure according to the present invention; Figure 2 This is a schematic diagram illustrating the change in resistance value of the pressure resistance strip under encapsulation stress according to the present invention; Figure 3 This is a schematic diagram of configuration 1 of the present invention; Figure 4 This is a schematic diagram of configuration 2 of the present invention; Figure 5 This is a schematic diagram of four self-compensation schemes for single-bridge structures according to the present invention; Figure 6 This is a schematic diagram of the method steps of the present invention. Detailed Implementation

[0019] The self-compensation scheme for a single-bridge structure of a silicon piezoresistive chip provided by the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, to make the embodiments more detailed, the following embodiments are the best and preferred embodiments, and those skilled in the art can use other alternative methods to implement some well-known technologies; moreover, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0020] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0021] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, alternatively, depending at least partly on the context, to allow for the presence of other factors that are not necessarily explicitly described.

[0022] It is understood that the meanings of “on”, “above”, and “above” in this invention should be interpreted in the broadest manner, such that “on” means not only “directly on” something, but also includes the meaning of being “on” something with an intervening feature or layer, and that “above” or “above” means not only “on” something, but also includes the meaning of being “on” something without an intervening feature or layer.

[0023] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially related terms are intended to cover different orientations in the use or operation of the device other than those depicted in the accompanying drawings. The device may be oriented in other ways, and the spatially related descriptive terms used herein can be interpreted similarly.

[0024] like Figures 1 to 5 As shown, the embodiments of the present invention provide a method for a self-compensation scheme of a silicon piezoresistive chip single-bridge structure, including the following: S1: Select crystal-oriented single-crystal silicon as the chip substrate, and then perform pretreatment. S2: Based on the target pressure range of the sensor, a sensitive film is prepared using either wet etching or dry etching processes; S3: Piezoresistive strips are formed by doping using diffused silicon or SOI processes; S4: Divide the high-stress zone at the edge of the sensitive membrane into a secondary high-stress zone on the inner side of the edge, and implement a differentiated zoning layout; S5: Construct a single Wheatstone bridge according to the standard Wheatstone bridge circuit logic; S6: Determine the appropriate compensation scheme based on the actual measured absolute pressure, gauge pressure, and differential pressure of the sensor; S7: Fabricate the chip substrate structure to achieve chip packaging stress adaptation; S8: Perform operational testing on the packaged pressure sensor to calibrate its performance and verify its effectiveness.

[0025] In this embodiment, step S1 includes the following: S11: Based on the MEMS silicon piezoresistive chip fabrication standard, single crystal silicon is selected as the chip substrate, and the optimal crystal orientation (100) is matched. This crystal orientation can maximize the piezoresistive effect of silicon material, ensure the sensitivity and response accuracy of the subsequent piezoresistive strip, and avoid the measurement error caused by the material itself from the substrate level. S12: Perform comprehensive surface cleaning on the selected single-crystal silicon substrate. Through a standardized process of organic solvent cleaning, deionized water rinsing, and high-temperature drying, remove impurities such as dust, oil, and oxide layers from the substrate surface to ensure that the substrate surface cleanliness meets the stringent requirements of subsequent photolithography and ion doping processes. S13: Polish and stress homogenize the cleaned substrate to correct the microscopic flatness of the substrate surface, eliminate residual stress inside and on the surface of the substrate, avoid initial interference caused by the substrate's own stress, and ensure the uniformity and stability of subsequent sensitive film preparation and piezoresistive strip layout.

[0026] In this embodiment, step S2 includes the following: S21: Based on the target pressure measurement range of the sensor, set the thickness, size and deformation parameters of the sensitive film, combine with the overall chip structure layout, plan the etching area at the bottom of the substrate, and clarify the boundary range between the retained area and the removed area to ensure that the sensitive film structure is adapted to the measurement range requirements. S22: Using mature MEMS processes such as wet etching or dry etching, the substrate bottom area is etched and thinned, and the structure is shaped. Excess silicon structure is removed from the substrate layer by layer. The etching rate and etching depth are strictly controlled to avoid over-etching and under-etching, and to ensure the dimensional accuracy and thickness uniformity of the sensitive film. S23: After etching, the sensitive film is passivated to repair the edge structure of the film and eliminate the microstructural defects caused by the etching process. This process produces a flexible sensitive film with uniform stress response, regular elastic deformation, and strong structural stability, ensuring that uniform and reversible elastic deformation can occur under external pressure.

[0027] In this embodiment, step S3 includes the following: S31: Based on the chip sensitivity and resistance matching design requirements, diffused silicon process or SOI process is selected as the piezoresistive strip preparation process. Combined with the target electrical parameters, the ion doping concentration, doping junction depth and doping region range are preset to ensure the basic performance consistency of the four sets of piezoresistive strips. S32: In the pre-set piezoresistive strip arrangement area of ​​the sensitive membrane, ion implantation or concentrated boron diffusion doping process is implemented. The process parameters such as doping temperature, vacuum degree, and ion flux are strictly controlled to form four piezoresistive sensitive strips R1, R2, R3, and R4 in sequence, ensuring that the resistance value, piezoresistive coefficient, and stress response performance of each piezoresistive strip are highly matched. S33: After doping, high-temperature annealing and curing treatment is performed to activate the doped ions, repair the lattice defects generated during the doping process, stabilize the electrical performance of the piezoresistive strip, avoid resistance drift during subsequent use, and ensure the stability and consistency of the piezoresistive strip in long-term operation.

[0028] In this embodiment, step S4 includes the following: S41: By calibrating through simulation, the stress regions of the sensitive membrane are divided, the high stress region at the edge of the sensitive membrane and the secondary high stress region inside the edge are defined, the stress response characteristics of the two regions are clarified, and the core characteristics of high piezoresistive sensitivity and opposite deformation response directions of the two regions are confirmed, providing a structural basis for differentiated layout. S42: According to the core layout logic of this invention, the formed R1 and R4 piezoresistive strips are fixedly arranged in the high stress area at the edge of the sensitive membrane, and the R2 and R3 piezoresistive strips are fixedly arranged in the second highest stress area inside the edge of the sensitive membrane. The position, spacing and angle of each piezoresistive strip are strictly controlled to ensure layout accuracy. S43: After the layout is completed, verify the stress response characteristics of each group of pressure resistance strips to ensure that the stress sensitivity direction of the pressure resistance strips on the same side of R1 and R4 is consistent, and the stress sensitivity direction of the pressure resistance strips of R2 and R3 is opposite to that of R1 and R4, forming a stable differentiated stress response structure to meet the basic conditions for self-compensation.

[0029] In this embodiment, step S5 includes the following: S51: Based on the standard Wheatstone bridge electrical connection logic, the internal metal lead routing path of the chip is planned, the layout of the four sets of piezoresistive bars is matched, the routing length and layout are optimized, the problems of line crossing and signal interference are avoided, and the circuit conduction stability is guaranteed. S52: Metal leads are prepared by metal evaporation, photolithography and etching processes, and four sets of piezoresistive strips R1, R2, R3 and R4 are electrically connected to construct a complete and independent single Wheatstone bridge circuit, forming a symmetrical and stable bridge circuit structure. S53: Strictly matches the electrode layout specifications of traditional silicon piezoresistive chips, retaining only the conventional number of electrodes without adding any new electrodes or lead structures, ensuring that the chip hardware structure and packaging interface are compatible with traditional chips, and requiring no adaptation or modification of subsequent production line equipment.

[0030] In this embodiment, step S6 includes the following: S61: Based on the actual application scenarios of the sensor, different measurement conditions of absolute pressure, gauge pressure and differential pressure are distinguished. Combining the pressure change characteristics and stress response requirements of the working conditions, the optimal structural configuration is matched from four single bridge self-compensation schemes to complete the chip structure design. S62: Simulates common-mode interference scenarios in real-world applications such as packaging stress, ambient temperature fluctuations, and manufacturing process deviations. Performs full-domain detection on the resistance change characteristics of four sets of piezoresistive strips and records the resistance offset direction and amount of each set of piezoresistive strips. S63: By fine-tuning process parameters to complete stress adaptation calibration, it ensures that when all external common-mode interference acts on the chip, the resistance values ​​of the four sets of piezoresistive bars R1, R2, R3, and R4 remain in the same direction and with equal amplitude. This is the core premise for stable bridge differential cancellation and ensures the interference compensation effect.

[0031] In this embodiment, step S7 includes the following: S71: A dedicated substrate structure is prepared on the back side of the substrate. The substrate is made of a highly stable insulating material. The substrate is formed through a precision bonding and curing process. The substrate structure is used to isolate external packaging stress and block the interference of packaging stress on the sensitive film and piezoresistive strip. S72: Adopts industry-standard MEMS chip packaging technology to encapsulate and solidify the formed bridge chip as a whole, strictly controlling parameters such as packaging temperature, pressure, and curing time to avoid additional stress deviations and structural deformations caused by the packaging process. S73: After packaging, structural curing is performed, static aging is allowed to stabilize the internal structure of the chip, eliminate residual stress from packaging, lock the piezoresistive strip layout and bridge circuit structure, and ensure that the structural and electrical performance of the chip does not drift during long-term use.

[0032] In this embodiment, step S8 includes the following: S81: Build a standard pressure and temperature test platform to perform multi-condition tests on the packaged silicon piezoresistive pressure sensor. Apply standard pressure and ambient temperature of different gradients respectively, and collect the differential output voltage signals V1-V2 of the bridge. S82: Detects the pressure response accuracy of the sensor and verifies that the chip output signal can correspond to pressure changes under external pressure.

[0033] In this embodiment, step S8 further includes: S83: To detect the suppression effect of common-mode interference such as temperature and residual stress in packaging, and to confirm that the interference signal can be canceled out through differential operation; S84: Completes multi-point precision calibration and stability testing, corrects minor process errors, and solidifies chip operating parameters; S85: Based on the above, the product is finalized by achieving high-precision and high-stability pressure detection with no algorithm involvement and pure structural self-compensation.

[0034] Working principle of the invention: According to the MEMS silicon piezoresistive chip fabrication standard, single crystal silicon was selected as the chip substrate, and the optimal crystal orientation (100) was matched. This crystal orientation can maximize the piezoresistive effect of silicon material, ensure the sensitivity and response accuracy of the subsequent piezoresistive strip, and avoid the measurement error caused by the material itself from the substrate level. The selected single crystal silicon substrate was subjected to all-round surface cleaning treatment. Through the standardized process of organic solvent cleaning, deionized water rinsing and high temperature drying, the dust, oil stains, oxide layer and other impurities on the substrate surface were removed to ensure that the cleanliness of the substrate surface meets the stringent requirements of subsequent photolithography and ion doping processes. The cleaned substrate was polished and stress homogenized to correct the micro-flatness of the substrate surface, eliminate the residual stress inside the substrate and on the surface, avoid the initial interference caused by the stress of the substrate itself, and ensure the uniformity and stability of the subsequent sensitive film preparation and piezoresistive strip layout. Based on the target pressure measurement range of the sensor, the thickness, size, and deformation parameters of the sensitive film are set. Combined with the overall chip structure layout, the etching area at the bottom of the substrate is planned, and the boundary range between the retained and removed areas is clearly defined to ensure that the sensitive film structure is adapted to the measurement range requirements. Mature MEMS processes such as wet etching or dry etching are used to etch and thin the preset area at the bottom of the substrate, shape the structure, and remove excess silicon structure from the substrate layer by layer. The etching rate and etching depth are strictly controlled to avoid over-etching and under-etching, ensuring the dimensional accuracy and thickness uniformity of the sensitive film. After etching, the sensitive film is passivated to trim the edge structure of the film and eliminate microstructural defects caused by the etching process. A flexible sensitive film with uniform stress response, regular elastic deformation, and strong structural stability is prepared to ensure that uniform and reversible elastic deformation can occur under external pressure. Based on the chip sensitivity and resistance matching design requirements, diffused silicon or SOI process was selected as the fabrication process for the piezoresistive strips. Combined with the target electrical parameters, the ion doping concentration, doping junction depth, and doping region range were preset to ensure the consistency of the basic performance of the four sets of piezoresistive strips. In the preset piezoresistive strip arrangement area of ​​the sensitive film, ion implantation or concentrated boron diffusion doping process was implemented, strictly controlling process parameters such as doping temperature, vacuum degree, and ion flux. Four piezoresistive sensitive strips, R1, R2, R3, and R4, were formed sequentially to ensure a high degree of matching in resistance, piezoresistive coefficient, and stress response performance of each strip. After doping, high-temperature annealing and curing treatment was performed to activate the doped ions, repair lattice defects generated during the doping process, stabilize the electrical performance of the piezoresistive strips, avoid resistance drift during subsequent use, and ensure the stability and consistency of the piezoresistive strips during long-term operation. By calibrating through simulation, the stress regions of the sensitive membrane are divided, defining the high-stress area at the edge of the sensitive membrane and the second-highest stress area inside the edge. The stress response characteristics of the two areas are clarified, and the core characteristics of high piezoresistive sensitivity and opposite deformation response directions are confirmed, providing a structural basis for differentiated layout. According to the core layout logic of this invention, the formed R1 and R4 piezoresistive strips are fixedly placed in the high-stress area at the edge of the sensitive membrane, and the R2 and R3 piezoresistive strips are fixedly placed in the second-highest stress area inside the edge of the sensitive membrane. The position, spacing, and angle of each piezoresistive strip are strictly controlled to ensure layout accuracy. After the layout is completed, the stress response characteristics of each group of piezoresistive strips are verified to ensure that the stress sensitivity direction of the piezoresistive strips on the same side of R1 and R4 is consistent, and the stress sensitivity direction of the piezoresistive strips of R2 and R3 is opposite to that of R1 and R4, forming a stable differentiated stress response structure that meets the basic conditions for self-compensation. Based on the standard Wheatstone bridge electrical connection logic, the internal metal lead routing path of the chip is planned, matching the layout of the four sets of piezoresistive bars, optimizing the trace length and layout, avoiding line crossing and signal interference issues, and ensuring circuit conduction stability. Metal leads are prepared through metal evaporation, photolithography, and etching processes to electrically connect the four sets of piezoresistive bars R1, R2, R3, and R4, constructing a complete and independent single Wheatstone bridge circuit, forming a symmetrical and stable bridge circuit structure. The electrode layout specifications of traditional ordinary silicon piezoresistive chips are strictly matched, retaining only the conventional number of electrodes without adding any electrodes or lead structures, ensuring that the chip hardware structure and packaging interface are compatible with traditional chips, without requiring adaptation and modification of subsequent production line equipment. Based on the actual application scenarios of the sensor, different measurement conditions of absolute pressure, gauge pressure, and differential pressure are distinguished. Combining the pressure change characteristics and stress response requirements of the operating conditions, the optimal structural configuration is matched from four single-bridge self-compensation schemes to complete the chip structure design. Simulating common-mode interference scenarios in actual applications such as packaging stress, ambient temperature fluctuations, and manufacturing process deviations, the resistance change characteristics of the four sets of piezoresistive bars are detected across the entire domain, and the resistance offset direction and offset amount of each set of piezoresistive bars are recorded. By fine-tuning the process parameters, stress adaptation calibration is completed to ensure that when all external common-mode interference acts on the chip, the resistance offset of the four sets of piezoresistive bars R1, R2, R3, and R4 remains in the same direction and with equal amplitude. This is the core premise of stable bridge differential cancellation and ensures the interference compensation effect. A dedicated substrate structure is fabricated on the back of the substrate. The substrate is made of a highly stable insulating material. The substrate is formed through a precision bonding and curing process. The substrate structure is used to isolate external packaging stress and block the interference of packaging stress on the sensitive film and piezoresistive strip. The formed bridge chip is encapsulated and cured as a whole using industry-standard MEMS chip packaging technology. The packaging temperature, pressure, curing time and other parameters are strictly controlled to avoid additional stress deviations and structural deformations caused by the packaging process. After packaging, structural curing treatment is performed. The chip's internal structure is stabilized by static aging, the residual packaging stress is eliminated, and the piezoresistive strip layout and bridge circuit structure are locked to ensure that the structure and electrical performance of the chip do not drift during long-term use. A standard pressure and temperature testing platform was built to conduct multi-condition tests on the packaged silicon piezoresistive pressure sensor. Different gradients of standard pressure and ambient temperature were applied, and the differential output voltage signals V1-V2 of the bridge were collected. The sensor's pressure response accuracy was tested, verifying that the chip's output signal could correspond to pressure changes under external pressure. The suppression effect of common-mode interference such as temperature and residual packaging stress was tested, confirming that interference signals could be canceled out through differential operations. Multi-point accuracy calibration and stability testing were completed, minor process errors were corrected, and chip operating parameters were solidified. Based on the above, a high-precision, high-stability pressure detection function with no algorithm involvement and pure structural self-compensation was achieved, and the overall product design was finalized.

[0035] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with an understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0036] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for a self-compensation scheme using a single-bridge structure of a silicon piezoresistive chip, characterized in that, Includes the following: S1: Select crystal-oriented single-crystal silicon as the chip substrate, and then perform pretreatment. S2: Based on the target pressure range of the sensor, a sensitive film is prepared using either wet etching or dry etching processes; S3: Piezoresistive strips are formed by doping using diffused silicon or SOI processes; S4: Divide the high-stress zone at the edge of the sensitive membrane into a secondary high-stress zone on the inner side of the edge, and implement a differentiated zoning layout; S5: Construct a single Wheatstone bridge according to the standard Wheatstone bridge circuit logic; S6: Determine the appropriate compensation scheme based on the actual measured absolute pressure, gauge pressure, and differential pressure of the sensor; S7: Fabricate the chip substrate structure to achieve chip packaging stress adaptation; S8: Perform operational testing on the packaged pressure sensor to calibrate its performance and verify its effectiveness.

2. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S1 includes the following: S11: Based on the MEMS silicon piezoresistive chip fabrication standard, single crystal silicon is selected as the chip substrate, and the optimal crystal orientation (100) is matched. This crystal orientation can maximize the piezoresistive effect of silicon material, ensure the sensitivity and response accuracy of the subsequent piezoresistive strip, and avoid the measurement error caused by the material itself from the substrate level. S12: Perform comprehensive surface cleaning on the selected single-crystal silicon substrate. Through a standardized process of organic solvent cleaning, deionized water rinsing, and high-temperature drying, remove impurities such as dust, oil, and oxide layers from the substrate surface to ensure that the substrate surface cleanliness meets the stringent requirements of subsequent photolithography and ion doping processes. S13: Polish and stress homogenize the cleaned substrate to correct the microscopic flatness of the substrate surface, eliminate residual stress inside and on the surface of the substrate, avoid initial interference caused by the substrate's own stress, and ensure the uniformity and stability of subsequent sensitive film preparation and piezoresistive strip layout.

3. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S2 includes the following: S21: Based on the target pressure measurement range of the sensor, set the thickness, size and deformation parameters of the sensitive film, combine with the overall chip structure layout, plan the etching area at the bottom of the substrate, and clarify the boundary range between the retained area and the removed area to ensure that the sensitive film structure is adapted to the measurement range requirements. S22: Using mature MEMS processes such as wet etching or dry etching, the substrate bottom area is etched and thinned, and the structure is shaped. Excess silicon structure is removed from the substrate layer by layer. The etching rate and etching depth are strictly controlled to avoid over-etching and under-etching, and to ensure the dimensional accuracy and thickness uniformity of the sensitive film. S23: After etching, the sensitive film is passivated to repair the edge structure of the film and eliminate the microstructural defects caused by the etching process. This process produces a flexible sensitive film with uniform stress response, regular elastic deformation, and strong structural stability, ensuring that uniform and reversible elastic deformation can occur under external pressure.

4. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S3 includes the following: S31: Based on the chip sensitivity and resistance matching design requirements, diffused silicon process or SOI process is selected as the piezoresistive strip preparation process. Combined with the target electrical parameters, the ion doping concentration, doping junction depth and doping region range are preset to ensure the basic performance consistency of the four sets of piezoresistive strips. S32: In the pre-set piezoresistive strip arrangement area of ​​the sensitive membrane, ion implantation or concentrated boron diffusion doping process is implemented. The process parameters such as doping temperature, vacuum degree, and ion flux are strictly controlled to form four piezoresistive sensitive strips R1, R2, R3, and R4 in sequence, ensuring that the resistance value, piezoresistive coefficient, and stress response performance of each piezoresistive strip are highly matched. S33: After doping, high-temperature annealing and curing treatment is performed to activate the doped ions, repair the lattice defects generated during the doping process, stabilize the electrical performance of the piezoresistive strip, avoid resistance drift during subsequent use, and ensure the stability and consistency of the piezoresistive strip in long-term operation.

5. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S4 includes the following: S41: By calibrating through simulation, the stress regions of the sensitive membrane are divided, the high stress region at the edge of the sensitive membrane and the secondary high stress region inside the edge are defined, the stress response characteristics of the two regions are clarified, and the core characteristics of high piezoresistive sensitivity and opposite deformation response directions of the two regions are confirmed, providing a structural basis for differentiated layout. S42: According to the core layout logic of this invention, the formed R1 and R4 piezoresistive strips are fixedly arranged in the high stress area at the edge of the sensitive membrane, and the R2 and R3 piezoresistive strips are fixedly arranged in the second highest stress area inside the edge of the sensitive membrane. The position, spacing and angle of each piezoresistive strip are strictly controlled to ensure layout accuracy. S43: After the layout is completed, verify the stress response characteristics of each group of pressure resistance strips to ensure that the stress sensitivity direction of the pressure resistance strips on the same side of R1 and R4 is consistent, and the stress sensitivity direction of the pressure resistance strips of R2 and R3 is opposite to that of R1 and R4, forming a stable differentiated stress response structure to meet the basic conditions for self-compensation.

6. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S5 includes the following: S51: Based on the standard Wheatstone bridge electrical connection logic, the internal metal lead routing path of the chip is planned, the layout of the four sets of piezoresistive bars is matched, the routing length and layout are optimized, the problems of line crossing and signal interference are avoided, and the circuit conduction stability is guaranteed. S52: Metal leads are prepared by metal evaporation, photolithography and etching processes, and four sets of piezoresistive strips R1, R2, R3 and R4 are electrically connected to construct a complete and independent single Wheatstone bridge circuit, forming a symmetrical and stable bridge circuit structure. S53: Strictly matches the electrode layout specifications of traditional silicon piezoresistive chips, retaining only the conventional number of electrodes without adding any new electrodes or lead structures, ensuring that the chip hardware structure and packaging interface are compatible with traditional chips, and requiring no adaptation or modification of subsequent production line equipment.

7. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S6 includes the following: S61: Based on the actual application scenarios of the sensor, different measurement conditions of absolute pressure, gauge pressure and differential pressure are distinguished. Combining the pressure change characteristics and stress response requirements of the working conditions, the optimal structural configuration is matched from four single bridge self-compensation schemes to complete the chip structure design. S62: Simulates common-mode interference scenarios in real-world applications such as packaging stress, ambient temperature fluctuations, and manufacturing process deviations. Performs full-domain detection on the resistance change characteristics of four sets of piezoresistive strips and records the resistance offset direction and amount of each set of piezoresistive strips. S63: By fine-tuning process parameters to complete stress adaptation calibration, it ensures that when all external common-mode interference acts on the chip, the resistance values ​​of the four sets of piezoresistive bars R1, R2, R3, and R4 remain in the same direction and with equal amplitude. This is the core premise for stable bridge differential cancellation and ensures the interference compensation effect.

8. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S7 includes the following: S71: A dedicated substrate structure is prepared on the back side of the substrate. The substrate is made of a highly stable insulating material. The substrate is formed through a precision bonding and curing process. The substrate structure is used to isolate external packaging stress and block the interference of packaging stress on the sensitive film and piezoresistive strip. S72: Adopts industry-standard MEMS chip packaging technology to encapsulate and solidify the formed bridge chip as a whole, strictly controlling parameters such as packaging temperature, pressure, and curing time to avoid additional stress deviations and structural deformations caused by the packaging process. S73: After packaging, structural curing is performed, static aging is allowed to stabilize the internal structure of the chip, eliminate residual stress from packaging, lock the piezoresistive strip layout and bridge circuit structure, and ensure that the structural and electrical performance of the chip does not drift during long-term use.

9. The method for self-compensation scheme of silicon piezoresistive chip single bridge structure according to claim 1, characterized in that, Step S8 includes the following: S81: Build a standard pressure and temperature test platform to perform multi-condition tests on the packaged silicon piezoresistive pressure sensor. Apply standard pressure and ambient temperature of different gradients respectively, and collect the differential output voltage signals V1-V2 of the bridge. S82: Detects the pressure response accuracy of the sensor and verifies that the chip output signal can correspond to pressure changes under external pressure.

10. The method of the self-compensation scheme for a single-bridge structure of a silicon piezoresistive chip according to claim 9, characterized in that, Step S8 further includes: S83: To detect the suppression effect of common-mode interference such as temperature and residual stress in packaging, and to confirm that the interference signal can be canceled out through differential operation; S84: Completes multi-point precision calibration and stability testing, corrects minor process errors, and solidifies chip operating parameters; S85: Based on the above, the product is finalized by achieving high-precision and high-stability pressure detection with no algorithm involvement and pure structural self-compensation.

Images