A gain-flattened high-speed balanced photodetector

Abstract

This invention discloses a high-speed balanced detector with gain flattening, comprising a housing, and a balanced detection module, a broadband amplification module, a gain flattening module, and a filter output module disposed within the housing and electrically connected sequentially along the radio frequency signal transmission direction. It also includes a power supply control module that provides operating bias to each functional module. The balanced detection module converts two incident optical signals into a differential radio frequency electrical signal. The broadband amplification module includes a first-stage transimpedance low-noise amplification unit, a second-stage broadband amplification unit, and a third-stage broadband amplification unit, used to perform transimpedance conversion and cascaded amplification. The gain flattening module is connected in series between the broadband amplification module and the filter output module. The filter output module suppresses out-of-band clutter and outputs the detection signal through an radio frequency interface. This invention achieves a balance between high-speed balanced detection, broadband amplification, gain flattening, and miniaturized packaging.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal processing technology, and in particular to a gain-flat high-speed balanced detector. Background Technology

[0002] Currently, balanced detectors typically receive two optical signals using two matched photodetectors and perform differential processing on the two photocurrents to suppress common-mode noise and improve detection sensitivity. With the development of high-speed optical communication, quantum communication, and high-precision optical sensing systems, balanced detectors not only need to have high response speed and low noise, but also need to maintain a stable and flat output gain over a wide radio frequency bandwidth.

[0003] Existing balanced detectors still have the following problems in practical use: First, insufficient consistency of photodetector pairs or multiple reflections in the light incident path can easily introduce differential errors and optical interference. Second, the detector output photocurrent is usually weak, requiring transimpedance amplification and subsequent broadband amplification. However, conventional broadband amplification links generally exhibit high gain in the low-frequency band and a gradual drop in gain in the high-frequency band, resulting in inconsistent output amplitude within the target bandwidth. Third, if ordinary surface-mount inductors are used for the bias inductor in the amplification link, they are easily limited by saturation current, DC resistance, and self-resonant frequency, affecting the stability of broadband amplification. Fourth, the amplified RF signal is prone to being mixed with out-of-band noise, power supply noise, and external electromagnetic interference. If the filter circuit order is insufficient or the integration is low, it will affect the purity of the output signal and the miniaturization of the entire device.

[0004] Therefore, it is necessary to provide a high-speed balanced detector that integrates balanced detection, current-to-voltage conversion, broadband amplification, gain flatness compensation, and out-of-band filtering as a continuous RF link, so that it has good gain flatness within the target bandwidth, while taking into account package size, interface layout, and replacement and installation requirements of existing equipment. Summary of the Invention

[0005] To address the aforementioned technical shortcomings, the present invention aims to propose a gain-flat high-speed balanced detector, which seeks to solve the problems of uneven RF amplification gain, high-frequency gain drop, insufficient bias stability, insufficient out-of-band clutter suppression capability, and insufficient packaging interface compatibility in existing balanced detectors.

[0006] To address the aforementioned technical problems, this invention provides a gain-flat high-speed balanced detector.

[0007] The gain-flat high-speed balanced detector includes: The enclosure is used to house and shield the various functional modules, and provides mounting interfaces for optical input, power supply, control and RF output; A balanced detection module, disposed within the encapsulation housing, is used to receive two incident light signals and convert the two incident light signals into a differential radio frequency electrical signal. A broadband amplification module is disposed within the package housing and electrically connected to the balanced detection module. It is used to perform transimpedance conversion and cascade amplification of the radio frequency electrical signal. The broadband amplification module includes a first-stage transimpedance low-noise amplification unit, a second-stage broadband amplification unit, and a third-stage broadband amplification unit connected in sequence. A gain flattening module is disposed inside the package housing and electrically connected to the output terminal of the broadband amplifier module. It is used to introduce a relatively higher attenuation to the low-frequency radio frequency signal within the target bandwidth by means of a frequency response that is opposite to the gain roll-off trend of the broadband amplifier module, so that the cascaded gain of the broadband amplifier module and the gain flattening module remains flat. A filter output module is disposed inside the package housing and electrically connected to the output terminal of the gain flattening module. It is used to suppress external noise in the target bandwidth and output the gain-flattened radio frequency detection signal through the radio frequency output interface. A power supply control module is disposed within the encapsulation housing and electrically connected to the balance detection module and the broadband amplification module respectively, for providing operating bias to the balance detection module and the broadband amplification module.

[0008] Preferably, the balanced detection module includes a first photodetector, a second photodetector, and a radio frequency synthesis node. The first photodetector and the second photodetector are connected to the radio frequency synthesis node in opposite polarities, so that the photocurrents generated by the two incident light signals are differentially canceled or superimposed at the radio frequency synthesis node and then output to the first stage transimpedance low noise amplifier unit.

[0009] Preferably, the first photodetector and the second photodetector are PIN-type silicon photodetectors manufactured in the same batch, and the deviation of their responsivity, dark current, junction capacitance and cutoff frequency parameters is no more than 5%; the photosensitive surfaces of the first photodetector and the second photodetector are provided with antireflection films that match the target operating wavelength, and the outside of the antireflection films is provided with apertures and antireflection isolation layers.

[0010] Preferably, the first-stage transimpedance low-noise amplifier unit includes a transimpedance amplifier and a feedback branch connected between its input and output terminals. The feedback branch includes a feedback resistor and a feedback capacitor, which are used to convert the differential photocurrent signal output by the balanced detection module into a radio frequency voltage signal.

[0011] Preferably, the first-stage transimpedance low-noise amplifier unit, the second-stage broadband amplifier unit, and the third-stage broadband amplifier unit are connected to each other through radio frequency coupling capacitors and impedance matching networks, respectively, to isolate DC bias and achieve inter-stage radio frequency matching.

[0012] Preferably, the first-stage transimpedance low-noise amplifier unit, the second-stage broadband amplifier unit, and the third-stage broadband amplifier unit are all provided with a bias network. The bias network includes a tapered bias inductor, a bias resistor, and a decoupling capacitor. The tapered bias inductor is connected in series between the power supply terminal and the bias terminal of the corresponding amplifier unit to provide RF high impedance within the target bandwidth and provide DC bias to the corresponding amplifier unit. The saturation current of the tapered bias inductor is greater than 1.5 times the upper limit of the operating current of the corresponding amplifier unit, and the ratio of the DC voltage drop of the tapered bias inductor to the operating voltage of the corresponding amplifier unit is less than 5%.

[0013] Preferably, the gain flattening module is a passive amplitude equalization network, including a first series resistor and a second series resistor disposed on the RF main path, a resistor-inductor branch grounded at the node between the first series resistor and the second series resistor, and a capacitor branch connected between the input and output terminals of the gain flattening module.

[0014] Preferably, the passive amplitude equalization network adopts a bridge T-type or equiripple equalization topology, so that its insertion loss in the low-frequency band of the target bandwidth is greater than that in the high-frequency band, in order to compensate for the gain drop of the broadband amplification module in the high-frequency band; the gain flattening module is fabricated using integrated passive device technology and is connected to the broadband amplification module and the filter output module through microstrip lines, coplanar waveguides or bonding wires.

[0015] Preferably, the filter output module includes a low-pass filter circuit, which is a passive high-order LC filter circuit, including a series inductor arranged along the main RF path and a parallel capacitor connected between the main RF path and ground. The low-pass filter circuit adopts a Chebyshev topology or a Butterworth topology and is fabricated using integrated passive device technology.

[0016] Preferably, the power supply control module includes positive and negative power input terminals, a photodetector bias circuit, an amplification unit bias circuit, and a power decoupling circuit. The package housing is electrically connected to the ground terminal of the power supply control module and serves as an RF ground and electromagnetic shielding structure. The package housing is a metal shell, and it is provided with a first optical input interface, a second optical input interface, a power interface, a control interface, and an RF output interface. The external dimensions, mounting holes, and interface positions of the package housing are compatible with the mounting structure of the predetermined 2.5G balanced detector. The target bandwidth is 0.5GHz to 2.5GHz, and the in-band gain flatness of the cascaded broadband amplification module and the gain flattening module is no greater than ±0.3dB.

[0017] The beneficial effects of this invention are as follows: (1) The present invention designs the balanced detection module, broadband amplification module, gain flattening module and filter output module as a continuous radio frequency link, which can control the radio frequency output quality from photocurrent generation, transimpedance conversion, cascade amplification, amplitude equalization to out-of-band filtering.

[0018] (2) The present invention connects a gain flattening module in series after the broadband amplification module. Through a passive amplitude equalization response that is opposite to the gain roll-off trend of the amplification link, it can relatively attenuate the low-frequency band and relatively compensate the high-frequency band, thereby improving the problem of high low-frequency gain and high-frequency gain drop of conventional broadband amplifiers.

[0019] (3) The present invention uses a tapered bias inductor in the bias network of the amplification unit, so that the bias path has both DC power supply and RF isolation functions under broadband RF conditions, which is beneficial to improving the stability of the amplification link and the consistency within the target bandwidth.

[0020] (4) The present invention uses a passive high-order low-pass filter circuit to suppress out-of-band noise, and can achieve gain flatness and miniaturization of the filter circuit through integrated passive device technology such as IPD, which is beneficial to reduce power consumption, improve integration and output signal purity.

[0021] (5) The present invention improves the electromagnetic interference resistance by using a metal package shell, power decoupling and radio frequency grounding structure, and reduces the system replacement cost by using a compatible form factor and interface layout. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a system module for a gain-flat high-speed balanced detector according to the present invention.

[0024] Figure 2 This is a schematic diagram showing the package size and dual optical input interface arrangement in an embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of the circuit link between the balanced detection module and the broadband amplification module in an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the topology of the gain flattening module in an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the passive high-order low-pass filter topology of the filter output module in an embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram showing the detector's compatible dimensions, mounting holes, and electrical interfaces in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Example 1: The specific embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the following examples are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention; without departing from the concept of the present invention, those skilled in the art can make equivalent substitutions or adaptive adjustments to the device model, specific parameters, connection method and process form.

[0031] like Figure 1 and Figure 6 As shown, the gain-flattened high-speed balanced detector of this embodiment includes a metal package. The package has a first optical input interface, a second optical input interface, a power interface, a control interface, and an RF output interface. The two optical input interfaces are used to receive two incident lights to be balanced and detected, respectively. The RF output interface is used to output the RF detection signal after balanced detection, broadband amplification, gain flattening, and low-pass filtering. The power interface can adopt a positive and negative power input form, such as ±12V power supply. The control interface can be used to select the operating mode, gain, or bias state. The package is connected to the internal circuitry and also serves as an RF ground and electromagnetic shielding structure.

[0032] like Figure 2 and Figure 6 As shown, the enclosure can adopt a size and mounting structure compatible with the predetermined 2.5G balanced detector. For example, the enclosure can be set to approximately 60mm × 58.5mm × 20mm in size, with M3 mounting holes, and the center distance between the first and second optical input interfaces can match the existing mounting structure. This size and interface arrangement allows the detector of this embodiment to be replaced without changing the original equipment mounting bracket and connecting cables. The above dimensions are one embodiment; in actual applications, adjustments can be made according to the predetermined mounting structure of the target equipment.

[0033] like Figure 3As shown, the balanced detection module includes a first photodetector, a second photodetector, and an RF combining node. The first and second photodetectors can be PIN-type silicon photodetectors, connected to the RF combining node with opposite polarities. When two optical signals are input to the first and second optical input interfaces respectively, the two photodetectors generate photocurrents. Due to their opposite polarities, the two photocurrents differentially cancel or superimpose at the RF combining node, thereby suppressing common-mode optical noise and obtaining a differential RF signal.

[0034] In one embodiment, the first and second photodetectors are fabricated in the same batch using the same process, and their responsivity, dark current, junction capacitance, and cutoff frequency parameters deviate by no more than 5%. An antireflection coating matching the target operating wavelength can be applied to the photosensitive surfaces of both photodetectors. The antireflection coating can be formed by alternating layers of SiO2 / Ta2O5, SiO2 / Nb2O5, or other high and low refractive index materials, and the center wavelength can be adjusted according to the target operating wavelength in the range of 700nm to 1100nm. An aperture and / or an anti-reflection isolation layer can also be provided outside the antireflection coating to limit the incident light path and reduce multiple reflections between the photosensitive surface, the antireflection coating, and the encapsulation window, thereby reducing the impact of optical interference on the differential detection accuracy.

[0035] See also Figure 3 The broadband amplification module includes a first-stage transimpedance low-noise amplifier, a second-stage broadband amplification unit, and a third-stage broadband amplification unit connected in sequence. The first-stage transimpedance low-noise amplifier is connected after the RF combining node and is used to convert the differential photocurrent signal output by the balanced detection module into an RF voltage signal. The second-stage and third-stage broadband amplification units cascade and amplify the RF voltage signal in sequence to form an output amplitude that meets the requirements of subsequent RF processing.

[0036] In this embodiment, the first-stage transimpedance low-noise amplifier unit may include a transimpedance amplifier and a feedback branch connected between its input and output terminals. The feedback branch may include a feedback resistor and a feedback capacitor. The feedback resistor is used to determine the transimpedance gain, and the feedback capacitor is used to improve frequency response and stability. The second-stage and third-stage broadband amplifier units may employ GaAs pHEMTs, SiGe, CMOS RF amplifiers, or other broadband RF amplifier devices. Each stage of the amplifier unit is connected via RF coupling capacitors to isolate the DC bias of each stage; an impedance matching network may also be provided across the RF coupling capacitors to maintain good input-output matching between adjacent amplifier units within the target bandwidth.

[0037] Each amplification unit can be configured with a bias network. The bias network includes a tapered bias inductor, a bias resistor, and a decoupling capacitor. The tapered bias inductor is connected in series between the power supply terminal and the bias terminal of the corresponding amplification unit, providing DC power to the amplification unit while offering higher RF impedance within the target RF bandwidth, reducing RF signal leakage through the bias branch. Compared to ordinary surface-mount inductors, tapered bias inductors have a wider frequency coverage, larger saturation current, and lower DC resistance, making them suitable for broadband RF amplification links from 0.5GHz to 2.5GHz. As an optional parameter, the saturation current of the tapered bias inductor can be greater than 1.5 times the upper limit of the corresponding amplification unit's operating current, and its DC dropout to the corresponding amplification unit's operating voltage ratio can be less than 5%.

[0038] like Figure 4 As shown, the gain flattening module is connected in series between the broadband amplification module and the filter output module. The gain flattening module can employ a passive amplitude equalization network, including a first series resistor and a second series resistor on the RF main path, a ground equalization branch grounded at the node between the first and second series resistors, and a bridging capacitor branch connecting the input and output terminals of the gain flattening module. The ground equalization branch can be composed of a resistor and an inductor in series, and the bridging capacitor branch can be formed by a capacitor. By adjusting the parameters of the first series resistor, the second series resistor, the ground equalization branch, and the bridging capacitor branch, the insertion loss can vary with frequency.

[0039] The actual gain of a broadband amplifier module typically rolls off with increasing frequency, meaning it has a higher gain at low frequencies and a lower gain at high frequencies. The frequency response of a gain-flattening module is designed to counteract this roll-off trend: it introduces relatively large insertion loss in the low-frequency range of the target bandwidth and relatively small insertion loss in the high-frequency range. This allows the total gain of the cascaded broadband amplifier module and gain-flattening module to maintain minimal fluctuations within the target bandwidth. For example, when the target bandwidth is 0.5 GHz to 2.5 GHz, by adjusting the values ​​of the resistors, capacitors, and inductors in the gain-flattening module, the in-band gain flatness of the cascaded module can be achieved to no more than ±0.3 dB.

[0040] Gain flattening modules are not limited to Figure 4 The specific bridge T-structure shown can also employ a 5th-order equal-ripple equalization network, a π-type equalization network, a T-type equalization network, or other passive equalization topologies capable of providing frequency-dependent amplitude compensation. The gain flattening module can be implemented using discrete passive devices, or integrated using GaAs IPD, glass-based IPD, thin-film circuitry, or LTCC technology. When using integrated passive device technology, the gain flattening module can be connected to the broadband amplification module and the filter output module via microstrip lines, coplanar waveguides, or bonded wires to reduce parasitic parameters and improve batch consistency.

[0041] like Figure 5 As shown, the filter output module includes a low-pass filter circuit and an RF output interface. The low-pass filter circuit can be a passive high-order LC filter circuit, with a series inductor on its RF main path and a parallel capacitor between the RF main path and ground. Depending on the system's out-of-band rejection requirements, the low-pass filter circuit can use a 5th to 7th order Chebyshev topology or Butterworth topology. The Chebyshev topology is suitable for scenarios requiring a steeper cutoff characteristic, while the Butterworth topology is suitable for scenarios requiring a smoother passband response.

[0042] In one specific embodiment, the cutoff frequency of the low-pass filter circuit is matched to the target bandwidth of the broadband amplification module and the gain flattening module. When the target bandwidth is 0.5 GHz to 2.5 GHz, the low-pass filter circuit can set its cutoff frequency slightly above 2.5 GHz to ensure the passage of RF probe signals within the passband while suppressing noise, RF crosstalk, power supply ripple, and external electromagnetic interference above the target bandwidth. The low-pass filter circuit can be integrated with the gain flattening module using IPD technology on the same passive chip, or they can be set separately and connected via RF transmission lines.

[0043] like Figure 3 and Figure 6 As shown, the power supply control module provides operating bias to the balanced detection module and the broadband amplification module. The power supply control module includes positive and negative power input terminals, a photodetector bias circuit, an amplification unit bias circuit, and a power supply decoupling circuit. The positive and negative power input terminals can be connected to an external power supply via a power interface; the photodetector bias circuit provides reverse bias to the first and second photodetectors; the amplification unit bias circuit provides stable operating voltage to the first-stage transimpedance low-noise amplification unit, the second-stage broadband amplification unit, and the third-stage broadband amplification unit; the power supply decoupling circuit is located close to each amplification unit to reduce the impact of power supply noise on the RF link.

[0044] The signal processing procedure in this embodiment is as follows: Two optical signals enter the balanced detection module through the first optical input interface and the second optical input interface, respectively, and are converted into two photocurrents by the first photodetector and the second photodetector; the two photocurrents are differentially combined at the RF synthesis node to form a differential RF signal; the differential RF signal enters the first-stage transimpedance low-noise amplifier unit and is converted into an RF voltage signal; the RF voltage signal is amplified sequentially by the second-stage broadband amplifier unit and the third-stage broadband amplifier unit; the amplified RF signal enters the gain flattening module, and the high-frequency gain drop of the broadband amplifier module is compensated by frequency-dependent insertion loss; the gain-flattened RF signal enters the low-pass filter circuit to suppress out-of-band clutter, and is finally output by the RF output interface.

[0045] As can be seen from the above embodiments, this invention is not simply a series connection of several conventional modules, but rather a matching design that integrates balanced detection, transimpedance conversion, three-stage broadband amplification, tapered inductor biasing, gain flattening equalization, and passive high-order filtering as a continuous RF circuit system. By setting a gain flattening module with the opposite gain roll-off trend after the broadband amplification module, amplitude consistency within the target bandwidth can be improved without significantly increasing active power consumption; further suppression of out-of-band interference through a low-pass filter circuit results in a cleaner and flatter RF detection output.

[0046] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any equivalent substitutions, simple combinations, or adaptive adjustments made to the photodetector type, amplification device model, equalization topology, filter order, package size, or interface form within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A gain-flat high-speed balanced detector, characterized in that, include: The enclosure is used to house and shield the various functional modules, and provides mounting interfaces for optical input, power supply, control and RF output; A balanced detection module, disposed within the encapsulation housing, is used to receive two incident light signals and convert the two incident light signals into a differential radio frequency electrical signal. A broadband amplification module is disposed within the package housing and electrically connected to the balanced detection module. It is used to perform transimpedance conversion and cascade amplification of the radio frequency electrical signal. The broadband amplification module includes a first-stage transimpedance low-noise amplification unit, a second-stage broadband amplification unit, and a third-stage broadband amplification unit connected in sequence. A gain flattening module is disposed inside the package housing and electrically connected to the output terminal of the broadband amplifier module. It is used to introduce a relatively higher attenuation to the low-frequency radio frequency signal within the target bandwidth by means of a frequency response that is opposite to the gain roll-off trend of the broadband amplifier module, so that the cascaded gain of the broadband amplifier module and the gain flattening module remains flat. A filter output module is disposed inside the package housing and electrically connected to the output terminal of the gain flattening module. It is used to suppress external noise in the target bandwidth and output the gain-flattened radio frequency detection signal through the radio frequency output interface. A power supply control module is disposed within the encapsulation housing and electrically connected to the balance detection module and the broadband amplification module respectively, for providing operating bias to the balance detection module and the broadband amplification module.

2. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The balanced detection module includes a first photodetector, a second photodetector, and a radio frequency synthesis node. The first photodetector and the second photodetector are connected to the radio frequency synthesis node in opposite polarities, so that the photocurrents generated by the two incident light signals are differentially canceled or superimposed at the radio frequency synthesis node and then output to the first stage transimpedance low noise amplifier unit.

3. The gain-flat high-speed balanced detector according to claim 2, characterized in that, The first photodetector and the second photodetector are PIN-type silicon photodetectors manufactured in the same batch, and the deviation of their responsivity, dark current, junction capacitance and cutoff frequency parameters is no more than 5%; the first photodetector and the second photodetector are provided with an anti-reflection film matching the target operating wavelength on their photosensitive surfaces, and an aperture and an anti-reflection isolation layer are provided on the outside of the anti-reflection film.

4. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The first-stage transimpedance low-noise amplifier unit includes a transimpedance amplifier and a feedback branch connected between its input and output terminals. The feedback branch includes a feedback resistor and a feedback capacitor, which are used to convert the differential photocurrent signal output by the balanced detection module into a radio frequency voltage signal.

5. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The first-stage transimpedance low-noise amplifier unit, the second-stage broadband amplifier unit, and the third-stage broadband amplifier unit are connected to each other through radio frequency coupling capacitors and impedance matching networks, respectively, to isolate DC bias and achieve inter-stage radio frequency matching.

6. The gain-flat high-speed balanced detector according to claim 1 or 5, characterized in that, The first-stage transimpedance low-noise amplifier unit, the second-stage broadband amplifier unit, and the third-stage broadband amplifier unit are all equipped with a bias network. The bias network includes a tapered bias inductor, a bias resistor, and a decoupling capacitor. The tapered bias inductor is connected in series between the power supply terminal and the bias terminal of the corresponding amplifier unit to provide RF high impedance within the target bandwidth and provide DC bias to the corresponding amplifier unit. The saturation current of the tapered bias inductor is greater than 1.5 times the upper limit of the operating current of the corresponding amplifier unit, and the ratio of the DC voltage drop of the tapered bias inductor to the operating voltage of the corresponding amplifier unit is less than 5%.

7. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The gain flattening module is a passive amplitude equalization network, including a first series resistor and a second series resistor disposed on the RF main path, a resistor-inductor branch grounded at the node between the first series resistor and the second series resistor, and a capacitor branch connected between the input and output terminals of the gain flattening module.

8. The gain-flat high-speed balanced detector according to claim 7, characterized in that, The passive amplitude equalization network adopts a bridge T-type or equiripple equalization topology, making its insertion loss in the low-frequency band of the target bandwidth greater than that in the high-frequency band, in order to compensate for the gain drop of the broadband amplification module in the high-frequency band; the gain flattening module is fabricated using integrated passive device technology and is connected to the broadband amplification module and the filter output module through microstrip lines, coplanar waveguides or bonding wires.

9. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The filter output module includes a low-pass filter circuit, which is a passive high-order LC filter circuit. It includes a series inductor arranged along the main RF path and a parallel capacitor connected between the main RF path and ground. The low-pass filter circuit adopts a Chebyshev topology or a Butterworth topology and is fabricated using integrated passive device technology.

10. The gain-flat high-speed balanced detector according to claim 1, characterized in that, The power supply control module includes positive and negative power input terminals, a photodetector bias circuit, an amplification unit bias circuit, and a power decoupling circuit. The package shell is electrically connected to the ground terminal of the power supply control module and serves as an RF ground and electromagnetic shielding structure. The package shell is a metal shell and is provided with a first optical input interface, a second optical input interface, a power interface, a control interface, and an RF output interface. The external dimensions, mounting holes, and interface positions of the package shell are compatible with the mounting structure of the predetermined 2.5G balanced detector. The target bandwidth is 0.5GHz to 2.5GHz, and the in-band gain flatness of the cascaded broadband amplification module and the gain flattening module is no greater than ±0.3dB.

Images