Photoelectric detection device, control method and laser

Abstract

This application discloses a photoelectric detection device, control method, and laser, relating to the field of pulsed laser detection technology. The photoelectric detection device includes a linear array photodetector and a trigger array, with the trigger array connected to the linear array photodetector. The trigger array receives a master clock signal and a reference signal, and outputs a drive clock signal, a start signal, a sampling clock signal, and a reset clock signal to the linear array photodetector, driving the linear array photodetector to operate. Thus, by processing the master clock signal and reference signal through the trigger array, a timing signal adapted to the linear array photodetector is generated. The asynchronous clearing function of the triggers in the trigger array is used to adjust the duty cycle required for each signal, thereby enabling the linear array photodetector to complete signal processing within each laser pulse output cycle of the excimer laser, meeting the requirements for laser wavelength detection and improving laser wavelength detection accuracy.

Description

Technical Field

[0001] This application relates to the field of pulsed laser detection technology, and in particular to a photoelectric detection device, control method and laser. Background Technology

[0002] With the rapid development of technology, pulsed lasers, thanks to their superior performance, are showing increasingly broad application prospects in precision industrial processing, cutting-edge scientific research, and high-precision medical fields. As a crucial parameter of pulsed lasers, the accurate measurement of laser wavelength is essential to ensuring their performance and stability.

[0003] Linear array photodetectors, with their unique parallel detection architecture, exhibit significant technological advantages in the field of pulsed laser wavelength detection. Since pulsed lasers typically possess transient characteristics on the nanosecond (ns) or even picosecond (ps) scale, an ideal detection system needs to complete high-precision light intensity sampling and integration within an extremely narrow time window to accurately extract laser wavelength feature information. However, current linear array detectors are primarily designed for detecting conventional continuous optical signals. Their microsecond (µs) line period and fixed integration time are ill-suited to the high-speed transient characteristics of pulsed lasers, failing to meet the requirements for laser wavelength detection and leading to inaccurate detection in wavelength detection applications. Summary of the Invention

[0004] This application provides a photoelectric detection device, a control method, and a laser to meet the requirements for detecting laser wavelength and improve the accuracy of laser wavelength detection.

[0005] In a first aspect, embodiments of this application provide a photoelectric detection device applied to a laser. The photoelectric detection device includes a linear array photodetector and a trigger array, the trigger array being connected to the linear array photodetector. Furthermore, the trigger array is used to receive a master clock signal and a reference signal, and output a drive clock signal, a start signal, a sampling clock signal, and a reset clock signal to the linear array photodetector, thereby driving the linear array photodetector to operate.

[0006] In this embodiment, the master clock signal and reference signal can be processed by a trigger array to generate a timing signal adapted to the linear array photodetector. The asynchronous clearing function of the triggers in the trigger array can be used to adjust the duty cycle required by each signal. Thus, the linear array photodetector can complete signal processing within each laser pulse output cycle of the excimer laser, meet the requirements for detecting laser wavelength, and improve the laser wavelength detection accuracy.

[0007] In one possible implementation, the trigger array has multiple triggers that can be directly mounted on the circuit board. Compared to centralized or software-triggered Field Programmable Gate Array (FPGA) solutions, directly using hardware-level triggers for signal conversion provides stronger resistance to environmental interference. Furthermore, if a trigger fails, it can be directly replaced and repaired, facilitating future system maintenance.

[0008] In one possible implementation, the trigger array can also be integrated into a single chip, suitable for high-density, high-performance, low-power lasers.

[0009] In one possible implementation, the driving clock signal includes a first driving clock signal and a second driving clock signal, which have the same period but opposite phase. Therefore, the first and second driving clock signals can be used to drive the linear array photodetector, adapting to meet the requirements for detecting laser wavelengths and improving the accuracy of laser wavelength detection.

[0010] In one possible implementation, the flip-flop array includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop. The asynchronous set and asynchronous reset terminals of the first D flip-flop are used to receive power supply voltage signals. The clock input terminal of the first D flip-flop is used to receive a master clock signal. The data input terminal, complementary output terminal, clock input terminal, asynchronous reset terminal, and clock input terminal of the fifth D flip-flop are connected. The output terminal of the first D flip-flop is used to output a first drive clock signal, and the complementary output terminal is used to output a second drive clock signal. The asynchronous set and data input terminals of the second D flip-flop are both used to receive power supply voltage signals. The asynchronous reset terminal of the second D flip-flop is used to receive the master clock signal. The output terminal of the second D flip-flop is used to output a sampling clock signal. The complementary output terminal of the second D flip-flop is connected to the clock input terminals of the third and sixth D flip-flops, respectively. The asynchronous set and data input terminals of the third D flip-flop are both used to receive power supply voltage signals, and the output terminal of the third D flip-flop is used to output a reset clock signal. The asynchronous set and data input terminals of the fourth D flip-flop are used to receive the power supply voltage signal, and the clock input terminal is used to receive the reference signal. The asynchronous reset terminals of the fourth and fifth D flip-flops are connected, as are the complementary output terminals of the sixth D flip-flop. The output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop. The asynchronous set terminal of the fifth D flip-flop is used to receive the power supply voltage signal, and its output terminal is used to output the start signal. The asynchronous set and asynchronous reset terminals of the sixth D flip-flop are both used to receive the power supply voltage signal, and its data input terminal is connected to the output terminal of the fifth D flip-flop. Therefore, the flip-flop array can be implemented using multiple D flip-flops. Because the architecture of D flip-flops is relatively mature, the implementation of the flip-flop array is relatively simple, thus reducing design complexity and production costs.

[0011] In one possible implementation, the linear photodetector includes a linear charge-coupled device (CCD) and a signal processing circuit. The CCD is connected to a trigger array to receive a drive clock signal and a start signal. The signal processing circuit is also connected to the trigger array to receive a sampling clock signal and a reset clock signal. Therefore, the signals output from the trigger array can control the operation of the linear CCD and the signal processing circuit, meeting the requirements for detecting laser wavelengths and improving the accuracy of laser wavelength detection.

[0012] In one possible implementation, the frequencies of the driving clock signal, the reset clock signal, and the sampling clock signal are the same, that is, the periods of the driving clock signal, the reset clock signal, and the sampling clock signal are the same. This can meet the working requirements of the linear CCD and the signal processing circuit for detecting the laser wavelength, and further improve the laser wavelength detection accuracy.

[0013] In one possible implementation, the frequency of the master clock signal is twice the frequency of the drive clock signal, meaning the period of the drive clock signal is twice the period of the master clock signal. Therefore, by flexibly designing the frequency of the master clock signal, the flip-flop array can output master clock signals of different frequencies.

[0014] In one possible implementation, the frequencies of the master clock signal, drive clock signal, sampling clock signal, and reset clock signal are each greater than or equal to the product of the number of pixels in the linear photodetector and the laser pulse repetition frequency, and the frequency of the start signal is greater than or equal to the laser pulse repetition frequency. Based on this, the frequencies of these signals can be set according to the number of pixels in the linear photodetector and the laser pulse repetition frequency, thereby allowing the trigger array to convert the signals to meet the requirements for detecting the laser wavelength and improving the accuracy of laser wavelength detection.

[0015] In a second aspect, a control method for a photoelectric detection device includes: a trigger array in the photoelectric detection device receiving a master clock signal and a reference signal, and outputting a drive clock signal, a start signal, a sampling clock signal and a reset clock signal to the linear array photodetector in the photoelectric detection device to drive the linear array photodetector to work.

[0016] In one possible implementation, the driving clock signal includes a first driving clock signal and a second driving clock signal, wherein the first driving clock signal and the second driving clock signal have the same period but opposite phase.

[0017] In one possible implementation, the frequencies of the drive clock signal, the reset clock signal, and the sampling clock signal are the same.

[0018] In one possible implementation, the frequency of the master clock signal is twice the frequency of the drive clock signal.

[0019] In one possible implementation, the photodetector is applied to the laser, and the frequencies of the driving clock signal, the sampling clock signal, and the reset clock signal are respectively greater than or equal to the product of the number of pixels of the linear photodetector and the laser pulse repetition frequency of the laser, and the frequency of the start signal is greater than or equal to the laser pulse repetition frequency.

[0020] Thirdly, a laser includes a detection module and a photodetector, the photodetector being disposed within the detection module. The detection module is connected to the photodetector and is used to output a master clock signal and a reference signal, and to receive the detection signal output by the photodetector. The photodetector can be the same as that in the first aspect or any of the embodiments thereof, thereby improving the accuracy of laser wavelength detection.

[0021] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referred to the technical effects that can be obtained in the first aspect and the various embodiments of the first aspect, and the repeated parts will not be described in detail. Attached Figure Description

[0022] Figure 1 This is a structural block diagram of a laser in an embodiment of this application;

[0023] Figure 2A This is a schematic diagram of a single-cavity excimer laser in an embodiment of this application.

[0024] Figure 2B This is a schematic diagram of a dual-cavity excimer laser in an embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the photoelectric detection device in one embodiment of this application;

[0026] Figure 4 This is another structural schematic diagram of the photoelectric detection device in the embodiments of this application;

[0027] Figure 5 This is a signal timing diagram in one embodiment of this application;

[0028] Figure 6 This is a schematic diagram of a trigger array in one embodiment of this application.

[0029] Figure label:

[0030] 1-Laser; 10-Detection module; 20-Photodetector; 21-Flip-flop array; 211-First D flip-flop; 212-Second D flip-flop; 213-Third D flip-flop; 214-Fourth D flip-flop; 215-Fifth D flip-flop; 216-Sixth D flip-flop; 22-Linear array photodetector; 221-Linear array CCD; 222-Signal processing circuit; 100-Single-cavity excimer laser; 200-Dual-cavity excimer laser; 300-Linewidth compression module; 400-Discharge cavity; 401-Cathode; 402-Anode; 403-Fan; 500-Output coupling mirror; 60 0 - Laser shutter; 700 - Control system; 1400 - First discharge cavity; 2400 - Second discharge cavity; 800 - First optical path reversal module; 900 - Second optical path reversal module; 1000 - Optical path inversion module; MCLK - Master clock signal; MR - Reference signal; DCLK - Drive clock signal; ST - Start signal; SCLK - Sampling clock signal; RCLK - Reset clock signal; clk1 - First drive clock signal; clk2 - Second drive clock signal; PR - Asynchronous set terminal; CLR - Asynchronous reset terminal; D - Data input terminal; Q - Output terminal; QB - Complementary output terminal. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0032] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0033] The photoelectric detection device, control method, and laser provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0034] Figure 1 This is a structural block diagram of a laser according to an embodiment of this application. (Refer to...) Figure 1In this embodiment, the laser 1 may include a detection module 10 and a photodetector 20. The photodetector 20 is disposed in the detection module 10 of the pulsed laser 1, and the detection module 10 is connected to the photodetector 20. Thus, the photodetector 20 can capture the laser pulses output by the pulsed laser 1 and convert them into electrical signals to output a detection signal carrying wavelength information. The detection module 10 can receive the detection signal and feed it back to the laser's control system, enabling the laser 1's control system to adjust the laser's wavelength, ensuring the wavelength stability of the pulsed laser 1.

[0035] An excimer laser is a pulsed gas laser designed for deep ultraviolet applications, characterized by high repetition rate, high energy, short wavelength, and narrow linewidth. In one embodiment of this application, laser 1 can be an excimer laser. Exemplarily, the excimer laser can include, but is not limited to, single-cavity excimer lasers and dual-cavity excimer lasers.

[0036] Figure 2A This is a schematic diagram of a single-cavity excimer laser in an embodiment of this application, with reference to... Figure 2A The single-cavity excimer laser 100 may include: a linewidth narrowing module 300, a discharge cavity 400, an output coupling mirror 500, a detection module 10, a laser shutter 600, and a control system 700. The working electrodes in the discharge cavity 400 include a cathode 401 and an anode 402. The control system 700 controls the discharge of the discharge cavity 400, applying corresponding voltages to the cathode 401 and anode 402 to excite and discharge the working gas to generate laser light. The laser light is then output to the detection module 10 via the output coupling mirror 500 and finally output via the laser shutter 600. The detection module 10 is used to measure the laser wavelength, single-pulse energy, peak power, and time characteristics (such as pulse width and repetition frequency) of the output laser signal to ensure that the output laser meets the requirements of the application scenario.

[0037] For example, the photoelectric detection device 20 is integrated into the detection module 10 for use in the laser wavelength detection process, thereby reducing space occupation. Furthermore, the photoelectric detection device 20 can also be used for the detection of single-pulse energy, peak power, and time characteristics; specific applications are not limited here.

[0038] For example, metal fluoride particles are generated during the discharge process in the discharge chamber 400. These particulate contaminants can reduce the discharge performance of the cathode 401 and the anode 402. To address this, a fan 403 (e.g., a high-speed rotating fan) is also provided in the discharge chamber 400 to blow away the area between the cathode 401 and the anode 402, thereby keeping the particulate contaminants away from the discharge area of ​​the cathode 401 and the anode 402 and improving the discharge performance.

[0039] Figure 2B This is a schematic diagram of a dual-cavity excimer laser in an embodiment of this application, with reference to... Figure 2B The dual-cavity excimer laser 200 may include: a linewidth narrowing module 300, a first discharge cavity 1400, a second discharge cavity 2400, a first optical path reversal module 800, a second optical path reversal module 900, an optical path inversion module 1000, a detection module 10, a laser shutter 600, and a control system 700. The structures of the first discharge cavity 1400 and the second discharge cavity 2400 are essentially the same as those of the discharge cavity 400. The first optical path reversal module 800 reverses the laser output from the first discharge cavity 1400 to the second optical path reversal module 900, and the second optical path reversal module 900 reverses the laser to the second discharge cavity 2400. The second discharge cavity 2400 amplifies the laser from the first discharge cavity 1400. The optical path inversion module 1000 reflects the laser, and the laser is then output through the laser shutter 600. Furthermore, the control system 700 synchronously controls the discharge of the first discharge cavity 1400 and the second discharge cavity 2400. Figure 2B The remaining structure and function of the dual-cavity excimer laser shown can be referenced. Figure 2A The structure and function of the single-cavity excimer laser shown are not detailed here.

[0040] It is understandable that there are many types of lasers 1, and in this embodiment of the application, laser 1 is used as an example. Figure 2A and Figure 2B The structure of laser 1 in this application is illustrated using single-cavity excimer lasers and dual-cavity excimer lasers as examples. In other embodiments of this application, the structure of laser 1 is not limited to the structure provided in the embodiments of this disclosure, and may be other structures known to those skilled in the art, which are not specifically limited here.

[0041] This application provides a photoelectric detection device for lasers, which can complete signal processing within each output cycle of a laser pulse, meet the timing requirements for detecting laser wavelength, and improve wavelength detection accuracy.

[0042] Figure 3 This is a schematic diagram of a photoelectric detection device in an embodiment of this application, with reference to... Figure 3The photoelectric detection device 20 in this embodiment may include a linear array photodetector 22 and a trigger array 21, with the trigger array 21 connected to the linear array photodetector 22. The trigger array 21 can receive the master clock signal MCLK and the reference signal MR, and output a drive clock signal DCLK, a start signal ST, a sampling clock signal SCLK, and a reset clock signal RCLK to the linear array photodetector 22, driving the linear array photodetector 22 to operate. Thus, the master clock signal MCLK and the reference signal MR can be processed by the trigger array 21 to generate timing signals adapted to the linear array photodetector 22. Furthermore, the asynchronous clearing function of the triggers in the trigger array 21 can be used to adjust the duty cycle required for each signal, thereby enabling the linear array photodetector 22 to complete signal processing within each laser pulse output cycle of the excimer laser, meeting the requirements for laser wavelength detection and improving laser wavelength detection accuracy.

[0043] In one embodiment of this application, the circuit structure can be simplified by outputting the above signal through the trigger array 21, and the output signal has strong resistance to environmental interference.

[0044] In one embodiment of this application, the trigger array 21 may have multiple triggers, which can be directly mounted on a circuit board (e.g., a printed circuit board, PCB). Compared to centralized or software-triggered FPGA solutions, directly using hardware-level triggers for signal conversion provides stronger resistance to environmental interference. Furthermore, if a trigger malfunctions, it can be directly replaced and repaired, facilitating subsequent system maintenance.

[0045] In another embodiment of this application, the trigger array 21 can also be integrated into a single chip, suitable for high-density, high-performance, low-power lasers 1.

[0046] In one embodiment of this application, the master clock signal MCLK can be provided by the detection module 10 in the laser 1. Exemplarily, the detection module 10 of the laser 1 may have a crystal oscillator, and by controlling the oscillator's vibration, a master clock signal MCLK that meets the frequency requirements can be generated. As an example, the frequency of the master clock signal MCLK can be 5MHz, 10MHz, etc., and its high-level voltage is 5V.

[0047] In one embodiment of this application, the reference signal MR can also be provided by the detection module 10 in the laser 1. Exemplarily, the detection module 10 of the laser 1 may include a signal generator. By controlling the operation of the signal generator, a reference signal MR that meets the requirements can be generated. For example, the reference signal MR can be a high-level signal or a pulse signal, and it can be flexibly designed according to the actual application scenario requirements, without limitation here. As an example, when the reference signal MR is a high-level signal, its voltage can be, for example, 5V. When the reference signal MR is a pulse signal, its period can be 0.5ms, the pulse width is 2us, the high-level voltage is 5V, and the low-level voltage is 0V.

[0048] In one embodiment of this application, the linear array photodetector 22 can be of various types. This embodiment uses a charge-coupled device (CCD) type linear array photodetector 22 as an example for illustration. In other embodiments of this application, the structure of the linear array photodetector 22 is not limited to the structure provided in the embodiments of this disclosure, and can also be other structures known to those skilled in the art; specific details are not limited here.

[0049] Figure 4 This is another structural schematic diagram of the photoelectric detection device in the embodiments of this application, referring to... Figure 4 The linear photodetector 22 may include a linear CCD 221 and a signal processing circuit 222, both of which are connected to the trigger array 21. The linear CCD 221 receives a drive clock signal DCLK and a start signal ST. The start signal ST triggers the linear CCD 221 to begin operation, while the drive clock signal DCLK drives the switching transistors in the linear CCD, enabling the corresponding pixel's electrical signal output. The signal processing circuit 222 receives a sampling clock signal SCLK and a reset clock signal RCLK. The sampling clock signal SCLK controls the signal processing circuit 222 to integrate and amplify the electrical signal output from the pixel. Since excessively high potential accumulation after repeated integration can easily lead to signal distortion, the reset clock signal RCLK can be used to reset the signal processing circuit 222, ensuring that the output signal of the linear CCD 221 can be accurately acquired by the subsequent analog-to-digital converter (ADC) acquisition card. Therefore, the signal output from the trigger array 21 can control the linear CCD 221 and the signal processing circuit 222 to work, thereby meeting the requirements for detecting laser wavelength and improving the accuracy of laser wavelength detection.

[0050] In one embodiment of this application, pulsed lasers typically exhibit transient characteristics at the nanosecond (ns) or even picosecond (ps) level. Furthermore, the pixels in the linear array photodetector 22 are typically linearly arranged, and each pixel can receive optical signals for photoelectric conversion. Therefore, within each laser pulse output cycle, to meet the requirements of detecting the laser wavelength, all pixels in the linear array photodetector 22 can perform the processes of output, acquisition, and reset, thereby outputting a signal with high detection accuracy. In one embodiment of this application, the master clock signal MCLK, drive clock signal DCLK, sampling clock signal SCLK, reset clock signal RCLK, and start signal ST can satisfy the following relationship: the frequencies of the master clock signal MCLK, drive clock signal DCLK, sampling clock signal SCLK, and reset clock signal RCLK are respectively greater than or equal to the product of the number of pixels (N) of the linear array photodetector 22 (e.g., linear CCD 221) and the laser pulse repetition rate (PRR) f0 of the laser 1 (i.e., N*f0), and the frequency of the start signal ST is greater than or equal to the laser pulse repetition rate. Based on this, the frequency of these signals can be set based on the number of pixels (N) of the linear photodetector 22 (e.g., linear CCD 221) and the laser pulse repetition frequency, so that the trigger array 21 can convert the signals to meet the requirements of the laser wavelength detection and improve the laser wavelength detection accuracy.

[0051] For example, taking N=1024, if f0 is 2kHz, then the frequencies of the master clock signal MCLK, the drive clock signal DCLK, the sampling clock signal SCLK, and the reset clock signal RCLK are all greater than or equal to 2.048MHz. If f0 is 4kHz, then the frequencies of the master clock signal MCLK, the drive clock signal DCLK, the sampling clock signal SCLK, and the reset clock signal RCLK are all greater than or equal to 4.096MHz.

[0052] In one embodiment of this application, reference is made to... Figure 5 , Figure 5 As one example of the signal timing diagram in this application, the frequencies of the driving clock signal DCLK, the reset clock signal RCLK, and the sampling clock signal SCLK can be the same, that is, the periods of the driving clock signal DCLK, the reset clock signal RCLK, and the sampling clock signal SCLK are the same, thereby meeting the working requirements of the linear CCD 221 and the signal processing circuit 222 for detecting the laser wavelength and further improving the laser wavelength detection accuracy.

[0053] For example, refer to Figure 5The duty cycles of the reset clock signal RCLK and the sampling clock signal SCLK can both be less than the duty cycle of the drive clock signal DCLK. For example, the duty cycles of the reset clock signal RCLK and the sampling clock signal SCLK can be half the duty cycle of the drive clock signal DCLK.

[0054] For example, refer to Figure 5 The duty cycle of the reset clock signal RCLK and the duty cycle of the sampling clock signal SCLK can be the same. For example, the duty cycle of the reset clock signal RCLK and the duty cycle of the sampling clock signal SCLK can be 25%, or the duty cycle of the reset clock signal RCLK and the duty cycle of the sampling clock signal SCLK can be other values, which are not limited here.

[0055] In one embodiment of this application, reference is made to... Figure 5 The frequency of the master clock signal MCLK is twice the frequency of the drive clock signal DCLK, meaning the period of the drive clock signal DCLK is twice the period of the master clock signal MCLK. Therefore, by flexibly designing the frequency of the master clock signal MCLK, the flip-flop array 21 can generate master clock signals MCLK of different frequencies. For example, the period of the drive clock signal DCLK is 400ns, and the period of the master clock signal MCLK is 200ns.

[0056] Typically, in the design of a linear CCD221, to improve signal detection accuracy, the on-time of the switching transistors in its pixels needs to meet a specified on-time (Ton) requirement. For example, the specified on-time of the switching transistors in a linear CCD221 can be 100ns, 200ns, 300ns, 400ns, etc. Based on this, to meet the operational requirements of the linear CCD221, the driving clock signal DCLK also needs to meet the following requirement: the high level of the driving clock signal DCLK must be greater than or equal to this specified on-time to ensure complete charge collection. Therefore, the period of the driving clock signal DCLK is the ratio of the specified on-time (Ton) to its duty cycle (D) (i.e., Ton / D). Thus, the period of the driving clock signal DCLK can be flexibly designed by combining the period of the driving clock signal DCLK and the required frequency, thereby determining the period of the master clock signal MCLK. For example, taking D=50% as an example, the period of the driving clock signal DCLK is 2Ton, then the period of the master clock signal MCLK is Ton, and the frequency of the master clock signal MCLK can be determined.

[0057] Furthermore, in the linear CCD 221 array, some linear CCD 221 arrays can be driven by a single driving clock signal DCLK, while others require multiple driving clock signals DCLK. The trigger array 21 in one embodiment of this application can be applied to linear CCD 221 arrays driven by dual driving clock signals DCLK, for example, referring to... Figure 5 The driving clock signal DCLK output by the trigger array 21 may include a first driving clock signal clk1 and a second driving clock signal clk2, wherein the first driving clock signal clk1 and the second driving clock signal clk2 have the same period but opposite phase. Therefore, the first driving clock signal clk1 and the second driving clock signal clk2 can be used to drive the linear CCD 221 to meet the requirements for detecting laser wavelength and improve the laser wavelength detection accuracy. In other embodiments of this application, the trigger array 21 can also be applied to a linear CCD 221 driven by a single driving clock signal DCLK, a linear CCD 221 driven by three driving clock signals DCLK, etc., and is not limited thereto.

[0058] In one embodiment of this application, reference is made to... Figure 5 The pulse width t2 of the start signal ST (e.g., a high level pulse) can be 200ns to 600ns. This embodiment uses a 600ns pulse width t2 as an example. In other embodiments of this application, the pulse width t2 of the start signal ST can also be 200ns, 400ns, etc., and is not specifically limited here. Furthermore, the duration t1 of a high level of the second drive clock signal clk2 needs to fall within the pulse width t2 of the start signal ST, and the second drive clock signal clk2 must and can only switch from a complete high level to a low level once during the high level of the start signal ST, so that the shift register in the linear CCD 221 can function normally.

[0059] The following example, using the driving clock signal DCLK output by the flip-flop array 21, which includes the first driving clock signal clk1 and the second driving clock signal clk2, illustrates the implementation of the flip-flop array 21 in conjunction with the accompanying drawings.

[0060] Figure 6 This is a schematic diagram of a trigger array in an embodiment of this application, with reference to... Figure 6 The trigger array 21 may include a first D trigger 211, a second D trigger 212, a third D trigger 213, a fourth D trigger 214, a fifth D trigger 215, and a sixth D trigger 216. Thus, the trigger array 21 can be implemented using multiple D triggers. Since the architecture of D triggers is relatively mature, the implementation of the trigger array 21 is relatively simple, thereby reducing design difficulty and production costs.

[0061] The asynchronous set terminal PR and asynchronous reset terminal CLR of the first D flip-flop 211 are both used to receive the power supply voltage signal. The clock input terminal of the first D flip-flop 211 is used to receive the master clock signal MCLK. The data input terminal D of the first D flip-flop 211, the complementary output terminal QB of the first D flip-flop 211, the clock input terminal of the second D flip-flop 212, the asynchronous reset terminal CLR of the third D flip-flop 213, and the clock input terminal of the fifth D flip-flop 215 are connected. The output terminal Q of the first D flip-flop 211 is used to output the first drive clock signal clk1, and the complementary output terminal QB of the first D flip-flop 211 is used to output the second drive clock signal clk2.

[0062] The asynchronous set terminal PR and data input terminal D of the second D flip-flop 212 are both used to receive the power supply voltage signal. The asynchronous reset terminal CLR of the second D flip-flop 212 is used to receive the master clock signal MCLK. The output terminal Q of the second D flip-flop 212 is used to output the sampling clock signal SCLK. The complementary output terminal QB of the second D flip-flop 212 is connected to the clock input terminal of the third D flip-flop 213 and the clock input terminal of the sixth D flip-flop 216, respectively.

[0063] The asynchronous set terminal PR and the data input terminal D of the third D flip-flop 213 are both used to receive the power supply voltage signal, and the output terminal Q of the third D flip-flop 213 is used to output the reset clock signal RCLK. For example, the complementary output terminal QB of the third D flip-flop 213 is left floating and not connected to any other components.

[0064] The asynchronous set terminal PR and data input terminal D of the fourth D flip-flop 214 are both used to receive the power supply voltage signal. The clock input terminal of the fourth D flip-flop 214 is used to receive the reference signal MR. The asynchronous reset terminal CLR of the fourth D flip-flop 214, the asynchronous reset terminal CLR of the fifth D flip-flop 215, and the complementary output terminal QB of the sixth D flip-flop 216 are connected. The output terminal Q of the fourth D flip-flop 214 is connected to the data input terminal D of the fifth D flip-flop 215. Exemplarily, the complementary output terminal QB of the fourth D flip-flop 214 is left floating and not connected to any other components.

[0065] The asynchronous set terminal PR of the fifth D flip-flop 215 is used to receive the power supply voltage signal, and the output terminal Q of the fifth D flip-flop 215 is used to output the start signal ST. For example, the complementary output terminal QB of the fifth D flip-flop 215 is left floating and not connected to other components.

[0066] The asynchronous set terminal PR and the asynchronous reset terminal CLR of the sixth D flip-flop 216 are both used to receive the power supply voltage signal. The data input terminal D of the sixth D flip-flop 216 is connected to the output terminal Q of the fifth D flip-flop 215.

[0067] For example, when the asynchronous set terminal PR of any one of the first D flip-flops 211 to the sixth D flip-flops 216 is a low-level signal, its output terminal Q is a high-level signal, thus realizing its asynchronous set function. In one embodiment of this application, the power supply voltage signal is a high-level signal; therefore, the asynchronous set terminal PR of any D flip-flop is always a high-level signal, which is equivalent to the asynchronous set function of any D flip-flop not being enabled.

[0068] For example, when the signal at the asynchronous reset terminal CLR of any one of the first D flip-flops 211 to the sixth D flip-flops 216 is a low-level signal, its output terminal Q is a low-level signal, thereby realizing its asynchronous reset function.

[0069] For example, any one of the first D flip-flops 211 to the sixth D flip-flops 216, when the signal at its asynchronous reset terminal CLR is high, is triggered by the rising edge of the signal at its clock input terminal to output the signal at its data input terminal D to its output terminal Q. Furthermore, the signal at its output terminal Q is out of phase with the signal at its complementary output terminal QB.

[0070] The above are examples illustrating the specific structure of the trigger array 21 provided in the embodiments of this application. In specific implementation, the specific structure of the trigger array 21 is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art based on the inventive concept of this application. No specific limitations are made here.

[0071] The following is combined Figure 5 and Figure 6 The working process of the photoelectric detection device 20 in the embodiments of this application will be described in detail.

[0072] The clock input of the first D flip-flop 211 receives the master clock signal MCLK. Its output Q outputs a first driving clock signal clk1, and its complementary output QB outputs a second driving clock signal clk2. The asynchronous reset input CLR of the second D flip-flop 212 receives the master clock signal MCLK. Its clock input receives the second driving clock signal clk2, and its output Q outputs a sampling clock signal SCLK. The complementary output QB of the second D flip-flop 212 is input to the clock inputs of the third D flip-flop 213 and the sixth D flip-flop 216. The asynchronous reset input CLR of the third D flip-flop 213 receives the second driving clock signal clk2, and its output Q outputs a reset clock signal RCLK. The clock input of the fourth D flip-flop 214 receives the reference signal MR. The asynchronous reset input CLR of the fourth D flip-flop 214 receives the signal from the complementary output QB of the sixth D flip-flop 216. The signal from the output Q of the fourth D flip-flop 214 is input to the data input D of the fifth D flip-flop 215. The asynchronous reset inputs CLR of the fourth and fifth D flip-flops 214 and CLR of the fifth D flip-flop 215 receive the signal from the complementary output QB of the sixth D flip-flop 216 to control the fourth and fifth D flip-flops 214 and fifth D flip-flops 215 to perform an asynchronous reset function, enabling the output Q of the fifth D flip-flop 215 to output the start signal ST. Furthermore, the data input D of the sixth D flip-flop 216 is connected to the output Q of the fifth D flip-flop 215, ensuring that the signal from the complementary output QB of the sixth D flip-flop 216 meets timing requirements.

[0073] Based on the same inventive concept, this application also provides a control method for a photoelectric detection device. The method includes: a trigger array in the photoelectric detection device receives a master clock signal and a reference signal, and outputs a drive clock signal, a start signal, a sampling clock signal and a reset clock signal to the linear array photodetector in the photoelectric detection device to drive the linear array photodetector to work.

[0074] In some implementations of this application, the above content is related to Figures 3 to 6 The related descriptions can be regarded as different implementations of the method shown in this embodiment, and will not be elaborated here.

[0075] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A photoelectric detection device, wherein the photoelectric detection device is applied to a laser, characterized in that, The photoelectric detection device includes: a linear photoelectric detector and a trigger array; The trigger array is connected to the linear photodetector and is used to receive the master clock signal and the reference signal, and to output the drive clock signal, the start signal, the sampling clock signal and the reset clock signal to the linear photodetector to drive the linear photodetector to work.

2. The photoelectric detection device according to claim 1, characterized in that, The driving clock signal includes a first driving clock signal and a second driving clock signal, wherein the first driving clock signal and the second driving clock signal have the same period but opposite phase.

3. The photoelectric detection device according to claim 2, characterized in that, The trigger array includes a first D trigger, a second D trigger, a third D trigger, a fourth D trigger, a fifth D trigger, and a sixth D trigger; The asynchronous set and asynchronous reset terminals of the first D flip-flop are both used to receive the power supply voltage signal. The clock input terminal of the first D flip-flop is used to receive the master clock signal. The data input terminal of the first D flip-flop, the complementary output terminal of the first D flip-flop, the clock input terminal of the second D flip-flop, the asynchronous reset terminal of the third D flip-flop, and the clock input terminal of the fifth D flip-flop are connected. The output terminal of the first D flip-flop is used to output the first driving clock signal, and the complementary output terminal of the first D flip-flop is used to output the second driving clock signal. The asynchronous set terminal and data input terminal of the second D flip-flop are both used to receive the power supply voltage signal, the asynchronous reset terminal of the second D flip-flop is used to receive the master clock signal, the output terminal of the second D flip-flop is used to output the sampling clock signal, and the complementary output terminal of the second D flip-flop is connected to the clock input terminal of the third D flip-flop and the clock input terminal of the sixth D flip-flop, respectively. The asynchronous set terminal and data input terminal of the third D flip-flop are both used to receive the power supply voltage signal, and the output terminal of the third D flip-flop is used to output the reset clock signal. The asynchronous set terminal and data input terminal of the fourth D flip-flop are both used to receive the power supply voltage signal. The clock input terminal of the fourth D flip-flop is used to receive the reference signal. The asynchronous reset terminal of the fourth D flip-flop, the asynchronous reset terminal of the fifth D flip-flop, and the complementary output terminal of the sixth D flip-flop are connected. The output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop. The asynchronous set terminal of the fifth D flip-flop is used to receive the power supply voltage signal, and the output terminal of the fifth D flip-flop is used to output the start signal; The asynchronous set and asynchronous reset terminals of the sixth D flip-flop are both used to receive the power supply voltage signal, and the data input terminal of the sixth D flip-flop is connected to the output terminal of the fifth D flip-flop.

4. The photoelectric detection device according to any one of claims 1-3, characterized in that, The linear array photodetector includes: a linear array charge-coupled device and a signal processing circuit; The linear charge-coupled device is connected to the trigger array and is used to receive the drive clock signal and the start signal; The signal processing circuit is connected to the flip-flop array and is used to receive the sampling clock signal and the reset clock signal.

5. The photoelectric detection device according to any one of claims 1-3, characterized in that, The frequencies of the driving clock signal, the reset clock signal, and the sampling clock signal are the same; or... The frequency of the master clock signal is twice the frequency of the drive clock signal.

6. The photoelectric detection device according to any one of claims 1-3, characterized in that, in, The frequencies of the master clock signal, the drive clock signal, the sampling clock signal, and the reset clock signal are all greater than or equal to the product of the number of pixels in the linear photodetector and the laser pulse repetition frequency of the laser, and the frequency of the start signal is greater than or equal to the laser pulse repetition frequency.

7. A control method for a photoelectric detection device, characterized in that, include: The trigger array in the photoelectric detection device receives the master clock signal and the reference signal, and outputs the drive clock signal, start signal, sampling clock signal and reset clock signal to the linear array photodetector in the photoelectric detection device to drive the linear array photodetector to work.

8. The method according to claim 7, characterized in that, The driving clock signal includes a first driving clock signal and a second driving clock signal, wherein the first driving clock signal and the second driving clock signal have the same period but opposite phase.

9. The method according to claim 7 or 8, characterized in that, The frequencies of the driving clock signal, the reset clock signal, and the sampling clock signal are the same; or... The frequency of the master clock signal is twice the frequency of the drive clock signal.

10. The method according to claim 7 or 8, characterized in that, The photoelectric detection device is applied to the laser. The frequency of the driving clock signal, the frequency of the sampling clock signal, and the frequency of the reset clock signal are all greater than or equal to the product of the number of pixels of the linear photoelectric detector and the laser pulse repetition frequency of the laser. The frequency of the start signal is greater than or equal to the laser pulse repetition frequency.

11. A laser, characterized in that, include: The detection module and the photoelectric detection device as described in any one of claims 1-6, wherein the photoelectric detection device is disposed within the detection module; The detection module is connected to the photoelectric detection device and is used to output the master clock signal and the reference signal, and to receive the detection signal output by the photoelectric detection device.

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