A low-stray inductance dynamic test docking method for TO-247-4L packaged devices

Abstract

This application discloses a low-stray-inductance dynamic testing docking method for TO-247-4L packaged devices, relating to the field of dynamic testing technology for power semiconductor devices. It addresses the problems of high stray inductance, severe drive crosstalk, poor test repeatability, and waveform acquisition distortion in packaged device testing schemes. The method includes: extracting the inherent stray impedance parameters of the fixture as a de-embedding compensation reference; docking the four pins of the device with corresponding independent contact terminals on the fixture, and limiting the pin insertion depth using a limiting structure; docking the energy storage capacitor with the power circuit line of the fixture; connecting the drive signal line to the drive circuit traces on the fixture corresponding to the G and KS poles; docking the voltage measurement probe and current measurement probe with preset measurement terminals on the fixture; performing dynamic testing and acquiring the switching transient waveform; and compensating the calculation results using the de-embedding compensation reference to obtain the device's stray inductance and dynamic parameters.

Description

Technical Field

[0001] This application relates to the field of dynamic testing technology for power semiconductor devices, and in particular to a method for dynamic testing and docking of low stray inductance for TO-247-4L packaged devices. Background Technology

[0002] The TO-247-4L is a four-pin power device package with pins for drain (D), gate (G), power source (S), and Kelvin drive source (KS). Electrical decoupling between the power main circuit and the gate drive circuit is achieved via the KS pin. This is the mainstream packaging form for third-generation wide-bandgap semiconductor devices (such as SiC MOSFETs, IGBTs, and high-voltage superjunction MOSFETs). In the R&D and production verification of power semiconductor devices, dual-pulse dynamic testing is a core method for evaluating their switching characteristics (switching losses, di / dt, dv / dt, etc.).

[0003] Currently, the industry commonly uses universal sockets or single-plane PCB fixtures for dynamic testing of such devices. Device pins are inserted into the fixture's springs or sockets, and waveforms are acquired by holding the pins in the middle with an oscilloscope probe. An external wire connects the DC bus energy storage capacitor to the test circuit, thus completing the dual-pulse dynamic switching test. However, the existing testing and docking methods have the following inherent drawbacks: First, the routing loop area of ​​universal sockets or single-plane PCB fixtures is large, with stray inductance in the main power commutation circuit typically reaching 35-50nH. The gate drive circuit shares a power source return path, resulting in a stray inductance of 8-15nH in the drive loop. The large current di / dt in the power circuit induces a voltage on the parasitic inductance of the source, severely polluting the VGS drive waveform and failing to reproduce the chip's true switching characteristics. Second, the fixture wiring is asymmetrical, and there is no uniform limit on pin insertion length. Each insertion and removal results in circuit... The magnetic flux cancellation effect is inconsistent, the stray inductance test has large dispersion, and the error of repeated testing of the same device exceeds 10%, which cannot meet the requirements of batch comparison and specification verification of devices; third, the voltage and current probes of the oscilloscope are directly clamped to the middle of the device pins for measurement, which introduces additional lead loop inductance, and the acquired waveform has a significant deviation from the actual voltage and current inside the chip; fourth, the DC bus energy storage capacitor is transferred to the clamp through the wire, which lengthens the commutation loop and further amplifies the voltage overshoot, requiring an additional buffer absorption circuit, which in turn changes the original switching characteristics of the device. Summary of the Invention

[0004] This application provides a low stray inductance dynamic test docking method for TO-247-4L packaged devices, which can solve the problems of high stray inductance, severe drive crosstalk, poor test repeatability and waveform acquisition distortion in the test scheme of packaged devices.

[0005] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides a method for dynamic testing and docking of low stray inductance for TO-247-4L packaged devices, the method comprising: Without placing the device under test, the inherent stray impedance parameters of the fixture are extracted and stored in the test system as a de-embedding compensation reference. Connect the four pins of the TO-247-4L device to the independent contact terminals of the corresponding D, S, G, and KS poles on the fixture, and limit the insertion depth of the device pins by the limiting structure. Connect the energy storage capacitor to the power circuit line of the fixture so that the energy storage capacitor is connected to the power converter circuit. Connect the drive signal line to the drive circuit traces on the fixture corresponding to the G and KS poles so that the gate drive circuit and the power circuit are independent of each other. Connect the voltage measurement probe and the current measurement probe to the preset measurement terminals on the fixture, respectively; Perform dynamic testing and acquire the transient waveform of the switch. Calculate the total loop stray inductance based on the acquired waveform. After compensating the calculation result by calling the de-embedding compensation benchmark, obtain the device's own stray inductance and dynamic parameters.

[0006] In one embodiment, the extraction of the inherent stray impedance parameters of the fixture includes: A standard short-circuit fixture with a TO-247-4L package is mounted on a jig. The inherent stray impedance parameters of the jig are extracted by scanning with a vector network analyzer. The DS pin and G-KS pin of the standard short-circuit fixture are shorted.

[0007] In one embodiment, the limiting structure is disposed on the side of the fixture, and the side of the device encapsulation is attached to the limiting structure so that the exposed length of the device pins is limited to a uniform size. The energy storage capacitor is a thin-film composite capacitor, which is flatly bonded to the circuit area corresponding to the D and S poles on the PCB of the fixture.

[0008] In one embodiment, the drive signal line uses a shielded differential twisted pair cable connected to the differential traces between the G and KS poles on the fixture, so that the drive signal does not pass through the power source S conductor throughout the entire process.

[0009] In one embodiment, the voltage measurement probe is an oscilloscope differential voltage probe, which is soldered to a preset differential test pad on the fixture; The current measurement probe is a Rogowski current coil, integrated into the S-pole power busbar channel of the fixture.

[0010] In one embodiment, performing dynamic testing and acquiring switching transient waveforms includes: performing a double-pulse test to acquire VDS, IDS, and VGS waveforms of turn-on transients and turn-off transients; The calculation of total loop stray inductance based on the acquired waveform includes: calculating the total loop stray inductance based on the turn-off voltage overshoot and the rate of change of current.

[0011] In one embodiment, the fixture adopts a four-layer sandwich stacked structure, consisting of an insulating press-fit cover plate, a G and KS signal differential PCB layer, a D and S power thick copper busbar layer, and a bottom ground plane from top to bottom; the fixture is equipped with positioning pins and locking screws.

[0012] In one embodiment, an insulating dielectric layer is sandwiched between the D-pole line and the S-pole line of the power circuit of the clamp, so that the magnetic fields generated by the forward current and the reverse current cancel each other out. In the drive circuit routing, the G pole trace and the KS pole trace are parallel coupled differential pairs with a line width to spacing ratio of 1:1, and shielded conductors are laid on the upper and lower parts of the differential trace.

[0013] In one embodiment, the independent contact terminal is an elastic spring made of beryllium copper plated with gold, wherein the spring width of the D-pole contact terminal and the S-pole contact terminal is greater than the spring width of the G-pole contact terminal and the KS-pole contact terminal, and the springs of the G-pole contact terminal and the KS-pole contact terminal are parallel to each other and spaced apart from each other. The preset measurement terminals are differential test pads located at the bottom of the fixture. The differential test pads include a first pad group corresponding to the D and S poles and a second pad group corresponding to the G and KS poles.

[0014] A second aspect of this application provides a low stray inductance dynamic test docking system for TO-247-4L packaged devices, used in conjunction with the low stray inductance dynamic test docking method for TO-247-4L packaged devices described in the first aspect of this application. The system includes: The fixture is provided with a limiting structure, a device carrying area, and a pin docking area for positioning and accommodating the TO-247-4L device. The limiting structure is used to limit the insertion depth of the device pins when the device is placed on the fixture. Multiple independently configured contact terminals are located in the pin mating area, corresponding to the D, S, G and KS pins of the TO-247-4L device, respectively; A power circuit is provided on the fixture, connecting the D-pole contact terminal and the S-pole contact terminal to form a power commutation path. The end of the power circuit is provided with an energy storage capacitor docking part, which is used for direct connection of the energy storage capacitor. A drive circuit line is disposed on the fixture, connecting the G pole contact terminal and the KS pole contact terminal to form a gate drive path. The drive circuit line is electrically isolated from the power circuit line and physically separated from each other. The end of the drive circuit line is used for connection of the drive signal line. Measurement terminals are provided on the fixture, corresponding to the D and S poles and the G and KS poles respectively, for electrical connection of the voltage measurement probe and the current measurement probe; Furthermore, the fixture can extract inherent stray impedance parameters when the device under test is not placed, which can be used as a de-embedding compensation reference.

[0015] The beneficial effects of the technical solutions provided in this application include at least the following: The low stray inductance dynamic testing docking method for TO-247-4L packaged devices provided in this application extracts the inherent stray impedance parameters of the fixture without placing the device under test, and stores them in the test system as a de-embedding compensation reference. The four pins of the TO-247-4L device are respectively docked to the independent contact terminals on the fixture corresponding to the D, S, G, and KS poles, and the insertion depth of the device pins is limited by a limiting structure. The energy storage capacitor is docked to the power circuit line of the fixture so that the energy storage capacitor is connected to the power commutation circuit. The drive signal line is connected to the drive circuit traces on the fixture corresponding to the G and KS poles so that the gate drive circuit and the power circuit are independent of each other. The voltage measurement probe and the current measurement probe are respectively connected to the preset measurement terminals on the fixture. Dynamic testing is performed and the switching transient waveform is acquired. The total loop stray inductance is calculated based on the acquired waveform, and the calculation result is compensated by calling the de-embedding compensation reference to obtain the device's own stray inductance and dynamic parameters.

[0016] This application establishes a complete low stray inductance testing process through the organic coordination of six steps: no-load pre-calibration, standardized device positioning, direct connection of energy storage capacitors, independent wiring of drive circuits, in-situ probe measurement, and de-embedding compensation. It compresses the source of stray inductance at the physical structure level and removes residual system errors at the data processing level; these two aspects complement each other, enabling the entire testing system to approach ideal zero-stray testing conditions.

[0017] Furthermore, this application pre-extracts the stray impedance parameters of the fixture itself under no-load conditions as a reference, and calls this reference to perform de-embedding compensation on the total measured values ​​after dynamic testing, accurately subtracting the inductance contributed by the fixture, thereby obtaining the true stray inductance and dynamic parameters of the device package itself. This compensation mechanism makes the test results unaffected by factors such as fixture batch differences and wear and tear, significantly improving the accuracy and reliability of the test data.

[0018] Secondly, this application uses a limiting structure to unify the pin insertion depth, combined with the precise docking of four independent contact terminals, to ensure that the mechanical contact state and electrical connection path between the device and the fixture are completely consistent during each test, eliminating differences caused by human operation, thereby controlling the error of repeated testing within a very small range and meeting the stringent requirements for batch comparison and specification verification of devices.

[0019] Furthermore, this application connects the drive signal line directly to the independent drive circuit traces of the G and KS poles, without passing through the power source S throughout, so that the drive circuit and the power circuit are physically completely isolated, completely cutting off the path of power-side interference coupling into the drive side, thereby obtaining a pure VGS drive waveform, providing a reliable data foundation for accurately extracting key parameters such as switching time and Miller plateau. Attached Figure Description

[0020] Figure 1 A flowchart of a low stray inductance dynamic test docking method for TO-247-4L packaged devices provided in this application embodiment; Figure 2 This application provides a schematic diagram of a fixture PCB wiring. Figure 3 This is a schematic diagram of a clamp structure provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0023] In addition, the use of “based on” or “according to” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” or “according to” one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0024] This application provides a low-stray-inductance dynamic testing docking method for TO-247-4L packaged devices. This method completes dual-pulse dynamic switching testing of TO-247-4L packaged devices (including wide-bandgap power semiconductor devices such as SiC MOSFETs, IGBTs, and high-voltage superjunction MOSFETs) through a standardized and systematic process. The core concept of this method is to minimize the stray inductance of the test circuit and eliminate systematic errors introduced by the fixture itself through dual means at the physical structure and data processing levels, thereby obtaining the true stray inductance and dynamic parameters of the device package itself. Figure 1 As shown, the method specifically includes the following steps: Step 101: Extract the inherent stray impedance parameters of the fixture without placing the device under test, and store them in the test system as a de-embedding compensation reference.

[0025] Optionally, the above steps can be as follows: Remove the device under test (DUT), install a standard shorting fixture in a TO-247-4L package onto the fixture, shorting the DS pin and the G-KS pin. Use a vector network analyzer connected to the fixture's test port to scan the S-parameters in the 100kHz to 100MHz frequency band, extracting the fixture's inherent stray impedance parameters such as contact inductance and trace stray impedance. Store the extracted parameters in the dual-pulse test software as reference data for hardware de-embedding compensation. The essential function of this step is to provide a reference for subsequent data correction by pre-calibrating the fixture's parasitic parameters, thereby deducting the systematic errors introduced by the fixture structure from the final test results.

[0026] Step 102: Connect the four pins of the TO-247-4L device to the independent contact terminals of the corresponding D, S, G, and KS poles on the fixture, and limit the insertion depth of the device pins by the limiting structure.

[0027] During the process, the above steps can be as follows: Loosen the M2.5 fixing screws of the fixture and open the insulating cover; place the TO-247-4L device under test (e.g., a 1200V SiC MOSFET) in the device carrying area of ​​the fixture, ensuring that the side of the device's plastic package is tightly fitted to the limiting reference block set on the side of the fixture; align the four pins of the device vertically with the independent elastic springs corresponding to the D, S, G, and KS terminals on the fixture; press down the insulating cover and tighten the M2.5 screws, while simultaneously using the Φ2 locating pins to achieve precise alignment of the multi-layer stack, preventing wiring asymmetry caused by assembly misalignment. After completing the above assembly, the exposed length of the device pins is limited to a uniform size. Preferably, this uniform size is 1.1mm to 1.2mm.

[0028] The limiting structure standardizes and unifies the device insertion position, completely eliminating the drawbacks of traditional solutions that rely on operator feel to control the insertion depth. This also eliminates test variability caused by different pin insertion depths or contact position offsets. The four independent contact terminals ensure the independence of the electrical connection of each pin, laying the foundation for the decoupling of the subsequent drive circuit and power circuit.

[0029] Step 103: Connect the energy storage capacitor to the power circuit line of the fixture so that the energy storage capacitor is connected to the power converter circuit.

[0030] like Figure 2 The diagram shows the PCB layout of the fixture. Multilayer parallel low-ESL thin-film-ceramic composite capacitors are planarly bonded to the wide copper foil solder areas corresponding to the drain (D) and source (S) terminals on the bottom of the fixture PCB, ensuring full contact between the capacitor's positive and negative terminals and the copper foil, eliminating the need for wire connections. The energy storage capacitor is directly bonded to the end of the power circuit, forming the shortest possible commutation path.

[0031] In traditional solutions, the DC bus energy storage capacitor is connected to the fixture via a wire, which itself constitutes an additional source of inductance, significantly amplifying the turn-off voltage overshoot. This application eliminates the connecting wire by directly connecting the energy storage capacitor to the power circuit of the fixture, shortening the commutation path to its physical limit. This reduces stray inductance in the commutation loop from the source and avoids the problem of altering the original switching characteristics of the device due to the addition of a buffer absorption circuit.

[0032] Step 104: Connect the drive signal line to the drive circuit traces on the fixture corresponding to the G and KS poles, so that the gate drive circuit and the power circuit are independent of each other.

[0033] In this design, the shielded differential twisted-pair cable output from the drive power supply is directly soldered to the ends of the differential traces at the gate (G) and gate (KS) terminals of the fixture PCB. The twisted-pair cable runs flush against the underlying grounding shield copper foil throughout its path to minimize the drive loop area. The drive signal flows entirely through the independent differential traces at the gate and gate (G) terminals, bypassing the power source (S) conductor. This completely decouples the gate drive circuit from the main power circuit, effectively cutting off the path for power circuit interference to couple into the drive circuit, ensuring that the acquired VGS waveform accurately reflects the chip's drive characteristics.

[0034] Step 105: Connect the voltage measurement probe and the current measurement probe to the preset measurement terminals on the fixture, respectively.

[0035] Optionally, the oscilloscope's differential voltage probes are soldered to pre-reserved differential test pads on the bottom of the fixture PCB, including a first pad group corresponding to the D / S poles and a second pad group corresponding to the G / KS poles. The Rogowski current coil is integrated into the S-pole power bus channel of the fixture, and the power current passes completely through the center of the coil without any shunt branches. The measurement terminals are positioned close to the root of the device pins to ensure that the measurement point is as close as possible to the inside of the chip. This application achieves probe docking through in-situ test terminals on the bottom of the PCB, with the probe directly soldered to the test pads, eliminating the need to clamp the middle section of the device pins. This fundamentally eliminates the additional loop inductance caused by the leads, allowing the acquired transient waveforms to highly reproduce the true electrical state inside the chip.

[0036] Step 106: Perform dynamic testing and acquire the transient waveform of the switch. Calculate the total loop stray inductance based on the acquired waveform, and then compensate the calculation result by calling the de-embedding compensation reference to obtain the device's own stray inductance and dynamic parameters.

[0037] This application performs dynamic testing and acquires switching transient waveforms. Based on the acquired waveforms, the total loop stray inductance is calculated. After compensating the calculation results using the aforementioned de-embedding compensation reference, the device's own stray inductance and dynamic parameters are obtained. Specifically, the half-bridge dual-pulse test program is started, and the VDS, IDS, and VGS waveforms of the turn-on and turn-off transients are acquired using an oscilloscope. The total loop stray inductance is calculated based on the turn-off voltage overshoot ΔV_DS and the current change rate di_D / dt. The calculation formula is as follows:

[0038] The testing system automatically calls the pre-calibration de-embedding parameters stored in step one, subtracts the inherent stray inductance of the fixture from the calculated total loop stray inductance, and outputs the true stray inductance of the device package itself. At the same time, the software synchronously extracts dynamic parameters such as turn-on loss Eon, turn-off loss Eoff, switching time, di / dt, dv / dt, and reverse recovery characteristics.

[0039] This application employs a de-embedding compensation mechanism to precisely isolate the stray inductance of the fixture itself from the total measured value, thereby obtaining the true stray inductance and dynamic parameters of the device package. This compensation mechanism eliminates the influence of fixture batch differences, wear and tear, assembly conditions, and other factors on the test results, significantly improving the accuracy and reliability of the test data. Experimental verification shows that using this method to test a 1200V TO-247-4L SiC MOSFET, the total stray inductance of the power commutation main circuit can be as low as 10.7nH (compared to 42nH for traditional single-sided fixtures), the stray inductance of the G-KS drive loop is 2.1nH (compared to 12.3nH for traditional methods), the maximum deviation of switching losses after 10 consecutive insertion and removal tests is only 2.1% (compared to 11.6% for traditional methods), the turn-off voltage spike amplitude is reduced by more than 60% compared to traditional fixtures, and the VGS waveform shows no large current-induced spikes or high-frequency spurious oscillations.

[0040] Optionally, a standard shorting fixture in a TO-247-4L package is mounted on the jig, and the inherent stray impedance parameters of the jig are extracted using a vector network analyzer. The DS pin and G-KS pin of the standard shorting fixture are shorted.

[0041] The standard short-circuit fixture uses the same TO-247-4L package dimensions as the device under test (DUT), with the drain (D) and source (S) terminals already shorted, and the gate (G) and source (KS) terminals already shorted. By inserting this fixture into the jig in the same manner as the actual device, the electrical conditions when the device is in a conducting state can be simulated. Then, using a vector network analyzer connected to the TP_DS and TP_GS differential test terminals at the bottom of the jig, the S-parameters in the 100kHz to 100MHz frequency band can be scanned to extract the inherent parameters of the jig itself, such as contact inductance and stray impedance. The extracted data is stored in the dual-pulse test software in the form of a mathematical model or lookup table, serving as a reference for subsequent de-embedding compensation.

[0042] Optionally, the limiting structure is disposed on the side of the fixture, and the side of the device's plastic package is fitted with the limiting structure to limit the exposed length of the device pins to a uniform size. Specifically, a raised plastic package limiting reference block is provided on the side of the fixture. The position of the reference block is precision machined, and the relative distance between the reference block and the device pin mating terminal is a fixed value.

[0043] When the operator inserts the TO-247-4L device into the fixture, simply push the edge of the device's black plastic casing until it is tightly fitted against the limiting reference block; this indicates that the device is properly installed. At this point, the insertion depth of the device pins into the fixture is precisely limited, and the exposed pin length (i.e., the length from the pin root to the end protruding from the fixture surface) is uniformly between 1.1mm and 1.2mm. This limiting structure design ensures that the relative position of the device and the fixture is completely consistent during each test, eliminating the trace loop size variations caused by inconsistent pin insertion depths in traditional solutions.

[0044] Optionally, the energy storage capacitor is a thin-film composite capacitor, which is planarly bonded to the circuit area corresponding to the D and S poles on the fixture PCB.

[0045] Specifically, the energy storage capacitor employs a multi-layered, parallel-connected, low-ESL thin-film-ceramic composite capacitor. The capacitor's electrode plane is directly bonded to the wide copper foil solder pads on the bottom of the fixture PCB, forming a full-area electrical connection and mechanical fixation through reflow soldering. The capacitor's mounting position is adjacent to the power converter circuit, minimizing the commutation path between the energy storage capacitor and the power switching devices, completely eliminating the wire connection structure used in traditional solutions. With the structure implemented in this embodiment, the ESL (Equivalent Series Inductance) of the energy storage capacitor is controlled at an extremely low level. Combined with the flux cancellation effect of the stacked busbars, this ensures that the total stray inductance of the main power converter circuit is ≤12nH.

[0046] Optionally, the drive signal line uses shielded differential twisted pair cable, connected to the differential traces between the G and KS poles on the fixture, so that the drive signal does not pass through the power source S conductor throughout the entire process.

[0047] Specifically, the drive signal line is led out from the output of the drive power supply and adopts a differential twisted pair structure with a shielded layer. One core wire is connected to the positive terminal of the drive signal (corresponding to the G terminal), and the other core wire is connected to the drive signal loop (corresponding to the KS terminal). The two core wires are tightly twisted together to reduce the loop area.

[0048] The ends of the twisted pair are directly soldered to the pads corresponding to the G and KS differential traces on the fixture PCB. After soldering, the twisted pair is routed along the PCB surface, remaining flush with the underlying grounding shield copper foil throughout. The drive signal starts from the drive power supply output, flows through the differential twisted pair and the G-KS differential traces on the fixture PCB, and finally reaches the contact springs at the root of the G and KS pins of the device. The entire path is completely independent of the power loop and does not pass through the power source S conductor.

[0049] With the above wiring method, the stray inductance of the gate drive circuit is controlled within 2.5nH, the drive signal is protected from magnetic field interference generated by the large current di / dt of the power circuit, ensuring that the VGS waveform is pure and distortion-free, and providing a reliable drive signal basis for accurately extracting the switching characteristics of the device.

[0050] Optionally, the voltage measurement probe is an oscilloscope differential voltage probe, soldered to preset differential test pads on the fixture. Specifically, the two differential voltage probes are soldered to two preset differential test pads, TP_DS and TP_GS, on the bottom of the fixture PCB. The TP_DS pad group corresponds to the drain and source terminals of the device and is used to acquire the drain-source voltage VDS; the TP_GS pad group corresponds to the gate and source terminals of the device and is used to acquire the gate-source drive voltage VGS. The positive and negative input terminals of the differential probes are connected to their corresponding differential pads to achieve high common-mode rejection ratio (CMRR) high-voltage differential measurement. The probes are mounted close to the bottom of the PCB, and the solder joints are adjacent to the contact springs at the root of the device pins, minimizing the measurement loop.

[0051] The current measurement probe is a Rogowski current coil, integrated into the S-pole power busbar channel of the fixture. Specifically, the frame of the Rogowski coil is fixed within the S-pole power busbar channel of the fixture, and the power current passes completely through the central aperture of the Rogowski coil, forming a fully enclosed current measurement structure. This installation method ensures that all power current flowing through the S-pole is induced by the Rogowski coil, eliminating shunt branches and thus ensuring the integrity and accuracy of the current measurement.

[0052] By using the above probe docking method, the VDS, IDS, and VGS waveforms acquired by the oscilloscope are all taken from the in-situ measurement point at the root of the device pin, which eliminates the influence of lead inductance and probe clamping method on the measurement results to the greatest extent, and makes the acquired waveform highly restore the real electrical state inside the chip.

[0053] Optionally, the dynamic testing and acquisition of switching transient waveforms includes performing a dual-pulse test to acquire the VDS, IDS, and VGS waveforms during turn-on and turn-off transients. Specifically, a half-bridge dual-pulse test program is started, and a dual-pulse drive signal is applied to the gate (G) of the device under test. The first pulse turns the device on, establishing a test current in the load inductor; when the first pulse turns off, the turn-off transient waveform of the device is acquired, including the overshoot voltage spike of VDS and the falling edge of IDS; when the second pulse turns on, the turn-on transient waveform of the device is acquired, including the falling edge of VDS and the rising edge of IDS. The complete VDS, IDS, and VGS waveforms during turn-on and turn-off transients are recorded using an oscilloscope, providing raw data for subsequent parameter extraction.

[0054] Regarding the stray inductance calculation method: The calculation of the total loop stray inductance based on the acquired waveform includes calculating the total loop stray inductance based on the turn-off voltage overshoot and the current rate of change. Specifically, the turn-off voltage overshoot ΔV_DS (i.e., the difference between the peak voltage spike and the bus voltage) and the current rate of change di_D / dt (i.e., the slope of the falling edge of IDS) are read from the turn-off transient waveform and substituted into the formula L_stray=ΔV_DS / (di_D / dt) to calculate the total loop stray inductance. Under the test conditions achieved in this embodiment, the turn-off voltage overshoot amplitude is reduced by more than 60% compared to traditional fixtures, and the current rate of change di / dt can reach a high test level, providing high-quality waveform data for accurate calculation of stray inductance.

[0055] Optional, such as Figure 3 As shown, the fixture adopts a four-layer sandwich stacked structure, which consists of an insulating press-fit cover plate, a G and KS signal differential PCB layer, a D and S power thick copper busbar layer, and a bottom ground plane from top to bottom.

[0056] Specifically, the first layer—the insulating pressure cover—is made of high-strength insulating material. It applies uniform pressure after device mounting to ensure tight and reliable contact between the device's four leads and each contact terminal. The cover is secured to the lower structure with M2.5 locking screws and uses Φ2 locating pins for precise alignment.

[0057] The second layer—the G and KS differential PCB layer: This layer is a thin PCB with differential drive traces for the G and KS poles arranged on it. The two traces adopt a differential pair structure with parallel coupling at the top and bottom, and the line width to spacing ratio is 1:1. Single-point grounded shielding copper foil is laid on both the top and bottom sides of the differential traces to isolate the coupling interference of the high-frequency magnetic field of the power circuit.

[0058] The third layer—the D and S power thick copper busbar layer: This layer consists of a large-area thick copper foil busbar, corresponding to the power traces for the D and S terminals, respectively. An ultra-thin FR4 dielectric layer of 80 to 100 μm is sandwiched between the D and S return busbars, allowing the two power traces to be tightly stacked vertically. The magnetic fields generated by the currents in opposite directions cancel each other out, thus significantly reducing stray inductance in the power loop from a physical structure perspective. All power traces use a rounded transition design, with no 90° right-angle bends, to avoid parasitic effects caused by abrupt changes in the current path.

[0059] The fourth layer—the bottom ground plane: This layer is a complete covering grounding copper foil, which on the one hand provides a low impedance return path for high-frequency signals, and on the other hand serves as a shielding layer to reduce the impact of external electromagnetic interference on the test signal.

[0060] The four-layer structure achieves precise alignment between layers using Φ2 locating pins and secures each layer tightly using M2.5 locking screws. This layered stacked structure ensures that the insertion depth of device pins and the relative positions of traces in each layer are completely consistent after each assembly, providing the mechanical basis for achieving low stray and high repeatability testing.

[0061] Optionally, an insulating dielectric layer is sandwiched between the D-pole line and the S-pole line of the power circuit of the fixture, so that the magnetic fields generated by the forward current and the reverse current cancel each other out.

[0062] Specifically, the D-type power busbar and the S-type return busbar are stacked vertically on the PCB, with an ultra-thin FR4 dielectric layer of 80 to 100 μm sandwiched between them. In actual testing, the power current flows out from the positive terminal of the bus capacitor, through the D-type copper busbar into the D-type terminal of the device, and after passing through the internal switch of the device, flows out from the S-type terminal and returns to the negative terminal of the capacitor via the S-type return busbar. The current direction in the D-type copper busbar is opposite to that in the S-type copper busbar. The two copper busbars are closely stacked in space, so that the magnetic fields they generate are opposite in direction and similar in amplitude, thus canceling each other out in space. This flux cancellation structure physically eliminates the main inductive component of the power loop, eliminating the need for additional buffer absorption circuits, and thus achieving the technical specification of a total stray inductance of ≤12nH in the main power commutation circuit.

[0063] Optionally, in the drive circuit routing, the G pole trace and the KS pole trace are parallel coupled differential pairs with a line width to spacing ratio of 1:1, and shielded conductors are laid on the upper and lower parts of the differential trace.

[0064] Specifically, the G and KS traces are routed parallel to each other on the same layer of the PCB, with equal widths and a 1:1 spacing between them to achieve optimal differential signal coupling. Both the upper and lower surfaces of the differential traces are covered with single-point grounded shielding copper foil, placing the differential pair between the upper and lower shielding conductors and effectively isolating the drive signal from interference from the high-frequency magnetic field of the power circuit. This differential coupling structure significantly improves the signal integrity of the drive circuit, keeping the stray inductance of the drive loop below 2.5nH, ensuring the drive signal is unaffected by external interference.

[0065] Optionally, the independent contact terminal is a beryllium copper gold-plated elastic spring, wherein the spring width of the D-pole contact terminal and the S-pole contact terminal is greater than the spring width of the G-pole contact terminal and the KS-pole contact terminal, and the springs of the G-pole contact terminal and the KS-pole contact terminal are parallel to each other and spaced apart from each other.

[0066] Specifically, all four contact terminals use beryllium copper alloy as the base material with gold plating to ensure excellent conductivity and oxidation resistance. The D and S terminals, serving as power pins, carry continuous commutation current from 0 to 100A. Their contact springs are designed as wide-area, high-power springs with a large contact area and low contact resistance, fully covering the drain and source pins to ensure controllable temperature rise during high current flow. The G and KS terminals, serving as signal pins, carry only milliamp-level drive current. Their contact springs are designed as ultra-thin parallel differential springs, with two springs parallel to each other and spaced apart, consistent with the arrangement direction of the device's G and KS pins, achieving precise contact at the pin roots. The four sets of springs, through a pre-pressure design, achieve zero-gap contact between the pins and conductors, eliminating any additional inductance that air gaps might introduce.

[0067] Optionally, the preset measurement terminals are differential test pads located at the bottom of the fixture, the differential test pads including a first pad group corresponding to the D and S poles and a second pad group corresponding to the G and KS poles.

[0068] Specifically, the bottom of the fixture PCB has four sets of independent differential test pads. The first set of pads is located directly below the D and S terminals, used for soldering differential voltage probes to acquire the VDS waveform; the second set of pads is located directly below the G and KS terminals, used for soldering differential voltage probes to acquire the VGS waveform. The spacing between the two pads in each set matches the pin spacing of the differential voltage probes to facilitate direct probe soldering. All test pads are positioned directly below the root of the device pins, ensuring the measurement point is as close to the chip interior as possible, minimizing the measurement loop.

[0069] The low stray inductance dynamic testing docking method for TO-247-4L packaged devices provided in this application forms a complete low stray inductance testing process through the organic coordination of six steps: no-load pre-calibration, standardized device positioning, direct docking of energy storage capacitors, independent wiring of drive circuits, in-situ probe measurement, and de-embedding compensation. This method reduces the source of stray inductance at the physical structure level and removes residual system errors at the data processing level; these two aspects complement each other, enabling the entire testing system to approach ideal zero-stray testing conditions.

[0070] Furthermore, this application pre-extracts the stray impedance parameters of the fixture itself under no-load conditions as a benchmark, and calls this benchmark to perform de-embedding compensation on the total measured values ​​after dynamic testing, accurately subtracting the inductance contributed by the fixture, thereby obtaining the true stray inductance and dynamic parameters of the device package itself. This compensation mechanism makes the test results unaffected by factors such as fixture batch differences and wear and tear, significantly improving the accuracy and reliability of the test data. This application unifies the pin insertion depth through a limiting structure, and with the precise docking of four independent contact terminals, ensures that the mechanical contact state and electrical connection path between the device and the fixture are completely consistent in each test, eliminating differences in human operation, thereby controlling the error of repeated testing within a very small range, meeting the stringent requirements of device batch comparison and specification verification.

[0071] Secondly, this application connects the drive signal line directly to the independent drive circuit traces of the G and KS poles, without passing through the power source S throughout, so that the drive circuit and the power circuit are physically completely isolated, completely cutting off the path of power-side interference coupling into the drive side, thereby obtaining a pure VGS drive waveform, providing a reliable data foundation for accurately extracting key parameters such as switching time and Miller plateau.

[0072] Furthermore, traditional solutions suffer from two lead-induced inductance issues: first, the DC bus energy storage capacitor is connected to the fixture via a long wire, making the wire itself an additional source of inductance, amplifying the turn-off overshoot; second, the oscilloscope probe is clamped in the middle of the device pin, creating an additional loop inductance between the probe and the pin, causing the acquired waveform to deviate from the chip's true internal state. This application addresses these issues by directly connecting the energy storage capacitor to the fixture's power circuit line without wire connections, shortening the commutation path to its physical limit; and by connecting the measurement probe to the in-situ measurement terminal immediately adjacent to the root of the device pin, eliminating the need to clamp the middle of the pin. Both of these measures eliminate the additional inductance caused by the leads, enabling the acquired transient waveform to highly reproduce the chip's true internal electrical state.

[0073] In summary, this application controls the total stray inductance of the power commutation main circuit to within 12nH, the stray inductance of the gate drive loop to within 2.5nH, the stray inductance fluctuation of the same device after multiple insertions and removals does not exceed ±0.8nH, and the switching loss test error is less than 3%. The turn-off voltage spike amplitude is reduced by more than 60% compared with traditional fixtures, and the drive waveform has no high-frequency false oscillations. It provides a standardized and traceable low-spurious test solution for high-precision dynamic characteristic characterization of wide bandgap power semiconductor devices such as TO-247-4L packaged SiC MOSFETs, IGBTs, and high-voltage superjunction MOSFETs.

[0074] Based on the low stray inductance dynamic test docking method for TO-247-4L packaged devices provided in the embodiments of this application, this application also provides a low stray inductance dynamic test docking system for TO-247-4L packaged devices, the system comprising: The fixture is provided with a limiting structure, a device carrying area, and a pin docking area for positioning and accommodating the TO-247-4L device. The limiting structure is used to limit the insertion depth of the device pins when the device is placed on the fixture. Multiple independently configured contact terminals are located in the pin mating area, corresponding to the D, S, G and KS pins of the TO-247-4L device, respectively; A power circuit is provided on the fixture, connecting the D-pole contact terminal and the S-pole contact terminal to form a power commutation path. The end of the power circuit is provided with an energy storage capacitor docking part, which is used for direct connection of the energy storage capacitor. A drive circuit line is disposed on the fixture, connecting the G pole contact terminal and the KS pole contact terminal to form a gate drive path. The drive circuit line is electrically isolated from the power circuit line and physically separated from each other. The end of the drive circuit line is used for connection of the drive signal line. Measurement terminals are provided on the fixture, corresponding to the D and S poles and the G and KS poles respectively, for electrical connection of the voltage measurement probe and the current measurement probe; Furthermore, the fixture can extract inherent stray impedance parameters when the device under test is not placed, which can be used as a de-embedding compensation reference.

[0075] In one embodiment, the fixture adopts a four-layer sandwich stacked structure, consisting of an insulating press-fit cover plate, a G and KS signal differential PCB layer, a D and S power thick copper busbar layer, and a bottom ground plane from top to bottom; the fixture is equipped with positioning pins and locking screws to achieve precise alignment and tight locking of each layer.

[0076] In one embodiment, an insulating dielectric layer is sandwiched between the D-pole line and the S-pole line of the power circuit so that the magnetic fields generated by the forward current and the reverse current cancel each other out. In the drive circuit, the G pole trace and the KS pole trace are parallel coupled differential pairs with a line width to spacing ratio of 1:1, and shielded conductors are laid on the upper and lower parts of the differential trace.

[0077] In one embodiment, the contact terminal is a beryllium copper gold-plated elastic spring, wherein the spring width of the D-pole contact terminal and the S-pole contact terminal is greater than the spring width of the G-pole contact terminal and the KS-pole contact terminal, and the springs of the G-pole contact terminal and the KS-pole contact terminal are parallel to each other and spaced apart from each other.

[0078] In one embodiment, the measurement terminal is a differential test pad disposed at the bottom of the fixture. The differential test pad includes a first pad group corresponding to the D and S poles and a second pad group corresponding to the G and KS poles, for direct soldering of the oscilloscope differential voltage probe.

[0079] In one embodiment, the energy storage capacitor docking part is a wide copper foil soldering area located on the bottom of the fixture PCB corresponding to the D and S poles, used for planar bonding and soldering of the thin film composite capacitor without the need for wire connection.

[0080] In one embodiment, the limiting structure is disposed on the side of the fixture and is used to limit the exposed length of the device pins to a uniform size when the limiting structure is attached to the side of the device encapsulation.

[0081] In one embodiment, the power circuit wiring of the fixture adopts a rounded transition without 90° right angle turns; the bottom grounding plane is a complete covering grounding copper foil.

[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for dynamic testing and docking of low stray inductance for TO-247-4L packaged devices, characterized in that, The method includes: Without placing the device under test, the inherent stray impedance parameters of the fixture are extracted and stored in the test system as a de-embedding compensation reference. Connect the four pins of the TO-247-4L device to the independent contact terminals of the corresponding D, S, G, and KS poles on the fixture, and limit the insertion depth of the device pins by the limiting structure. Connect the energy storage capacitor to the power circuit line of the fixture so that the energy storage capacitor is connected to the power converter circuit. Connect the drive signal line to the drive circuit traces on the fixture corresponding to the G and KS poles so that the gate drive circuit and the power circuit are independent of each other. Connect the voltage measurement probe and the current measurement probe to the preset measurement terminals on the fixture, respectively; Perform dynamic testing and acquire the transient waveform of the switch. Calculate the total loop stray inductance based on the acquired waveform. After compensating the calculation result by calling the de-embedding compensation benchmark, obtain the device's own stray inductance and dynamic parameters.

2. The method according to claim 1, characterized in that, The extraction of the inherent stray impedance parameters of the fixture includes: A standard short-circuit fixture with a TO-247-4L package is mounted on a jig. The inherent stray impedance parameters of the jig are extracted by scanning with a vector network analyzer. The DS pin and G-KS pin of the standard short-circuit fixture are shorted.

3. The method according to claim 1, characterized in that, The limiting structure is disposed on the side of the fixture, and the side of the device encapsulation body is attached to the limiting structure so that the exposed length of the device pins is limited to a uniform size. The energy storage capacitor is a thin-film composite capacitor, which is flatly bonded to the circuit area corresponding to the D and S poles on the PCB of the fixture.

4. The method according to claim 1, characterized in that, The drive signal line uses shielded differential twisted pair cable, which is connected to the differential trace between the G and KS poles on the fixture, so that the drive signal does not pass through the power source S conductor throughout the entire process.

5. The method according to claim 1, characterized in that, The voltage measurement probe is an oscilloscope differential voltage probe, which is soldered to a preset differential test pad on the fixture; The current measurement probe is a Rogowski current coil, integrated into the S-pole power busbar channel of the fixture.

6. The method according to claim 1, characterized in that, The process of performing dynamic testing and acquiring switching transient waveforms includes: performing a double-pulse test to acquire the VDS, IDS, and VGS waveforms of the turn-on transient and turn-off transients; The calculation of total loop stray inductance based on the acquired waveform includes: calculating the total loop stray inductance based on the turn-off voltage overshoot and the rate of change of current.

7. The method according to claim 1, characterized in that, The fixture adopts a four-layer sandwich structure, consisting of an insulating press-fit cover plate, a G and KS signal differential PCB layer, a D and S power thick copper busbar layer, and a bottom ground plane from top to bottom; the fixture is equipped with positioning pins and locking screws.

8. The method according to claim 1, characterized in that, An insulating dielectric layer is sandwiched between the D-pole line and the S-pole line of the power circuit circuit of the fixture so that the magnetic fields generated by the forward current and the reverse current cancel each other out. In the drive circuit routing, the G pole trace and the KS pole trace are parallel coupled differential pairs with a line width to spacing ratio of 1:1, and shielded conductors are laid on the upper and lower parts of the differential trace.

9. The method according to claim 1, characterized in that, The independent contact terminals are elastic springs made of beryllium copper plated with gold. The spring widths of the D-pole contact terminals and S-pole contact terminals are greater than the spring widths of the G-pole contact terminals and KS-pole contact terminals. The springs of the G-pole contact terminals and KS-pole contact terminals are parallel to each other and spaced apart from each other. The preset measurement terminals are differential test pads located at the bottom of the fixture. The differential test pads include a first pad group corresponding to the D and S poles and a second pad group corresponding to the G and KS poles.

10. A low stray inductance dynamic test docking system for TO-247-4L packaged devices, characterized in that, The system for the low stray inductance dynamic test docking method for TO-247-4L packaged devices according to any one of claims 1-9 comprises: The fixture is provided with a limiting structure, a device carrying area, and a pin docking area for positioning and accommodating the TO-247-4L device. The limiting structure is used to limit the insertion depth of the device pins when the device is placed on the fixture. Multiple independently configured contact terminals are located in the pin mating area, corresponding to the D, S, G and KS pins of the TO-247-4L device, respectively; A power circuit is provided on the fixture, connecting the D-pole contact terminal and the S-pole contact terminal to form a power commutation path. The end of the power circuit is provided with an energy storage capacitor docking part, which is used for direct connection of the energy storage capacitor. A drive circuit line is disposed on the fixture, connecting the G pole contact terminal and the KS pole contact terminal to form a gate drive path. The drive circuit line is electrically isolated from the power circuit line and physically separated from each other. The end of the drive circuit line is used for connection of the drive signal line. Measurement terminals are provided on the fixture, corresponding to the D and S poles and the G and KS poles respectively, for electrical connection of the voltage measurement probe and the current measurement probe; Furthermore, the fixture can extract inherent stray impedance parameters when the device under test is not placed, which can be used as a de-embedding compensation reference.

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