voltage detection circuit

Abstract

This invention provides a voltage detection circuit. An input short-circuit unit (4) enables a short circuit between a pair of input nodes (Nip, Nim). A voltage detection unit (12) calculates the detected value of the differential voltage based on the output signal of an A / D conversion unit (5) that performs A / D conversion on the voltage output from the chopper unit (3). A level conversion unit (7) converts and outputs the levels of the driving signals for the chopper switches (Sc1~Sc4) used to drive the chopper unit (3) and the short-circuit switches (Ss1, Ss2) of the input short-circuit unit (4). A reference voltage generation unit (8) generates a reference voltage in the level conversion unit (7). An offset correction unit (9) obtains the detection value detected by the voltage detection unit (12) under the short-circuit condition between the input nodes (Nip, Nim) as an offset value, and corrects the offset by subtracting the offset value from the detection value detected by the voltage detection unit (6) under the non-short-circuit condition between the input nodes (Nip, Nim).

Description

Technical Field

[0001] This invention relates to a voltage detection circuit for detecting the voltage difference between the voltages of a pair of input nodes. Background Technology

[0002] Patent Document 1 discloses a voltage detection circuit with a fully differential structure employing a switching circuit called a CCSW circuit. CCSW is an abbreviation for Capacitively-Coupled Switch. Hereinafter, the voltage detection circuit disclosed in Patent Document 1 will be referred to as prior art. The prior art employs the following structure: it includes a selector that provides the higher of the voltages of the two input nodes as the substrate potential of a P-channel MOS transistor, and provides the lower of the voltages of the two input nodes as the substrate potential of an N-channel MOS transistor.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent No. 6673150 Summary of the Invention

[0004] Existing technology envisions switching at the input of an A / D converter, in which an external filter is considered to be placed before the voltage detection circuit. According to this concept, in the prior art, charge flows only from the high or low potential input, thus generating a voltage in the resistors such as the external filter. This voltage becomes the main cause of offset error. If offset error occurs and accumulates, it leads to a decrease in voltage detection accuracy.

[0005] The present invention was made in view of the above circumstances, and its object is to provide a voltage detection circuit that can improve the accuracy of voltage detection.

[0006] According to one aspect of this disclosure, a voltage detection circuit detects the voltage difference between a pair of input nodes, comprising: a chopper unit that receives the voltages of the pair of input nodes, reverses the polarity of these voltages, and outputs them from a pair of output nodes, and includes a chopper switch connected between the pair of input nodes and the pair of output nodes; an input short-circuit unit that includes a short-circuit switch connected between the pair of input nodes, enabling a short circuit between the pair of input nodes; an A / D conversion unit that performs A / D conversion on the voltage output from the chopper unit; a voltage detection unit that calculates a detected value of the voltage difference based on the output signal of the A / D conversion unit; a level conversion unit that converts and outputs the levels of a first drive signal for driving the chopper switch and a second drive signal for driving the short-circuit switch; a reference voltage generation unit that generates a reference voltage in the level conversion unit; and an offset correction unit that corrects for an offset of the detected value.

[0007] The offset correction unit obtains the detection value detected by the voltage detection unit when the pair of input nodes are short-circuited by the input short-circuit unit as the offset value, and corrects the offset by subtracting the offset value from the detection value detected by the voltage detection unit when the pair of input nodes are not short-circuited by the input short-circuit unit.

[0008] In the voltage detection circuit described above, a selector-like structure is absent, resulting in less offset compared to existing technologies. Furthermore, according to this structure, without activating the input short-circuit section and the reference voltage generation section, the impedance of the circuit observed from the input side becomes higher, thus reducing the amount of current flowing in and consequently decreasing the input offset before correction. Additionally, according to this structure, during normal operation, a balance of current flowing in each pair of input nodes can be achieved, preventing them from becoming the primary cause of offset, further reducing offset. Moreover, according to this structure, offset correction by the offset correction section further minimizes offset. Therefore, the voltage detection accuracy can be improved according to this structure. Attached Figure Description

[0009] Figure 1 This is a diagram schematically illustrating the structure of the voltage detection circuit according to the first embodiment.

[0010] Figure 2 This is a diagram schematically showing the signals of each part of the voltage detection circuit in the first embodiment.

[0011] Figure 3 This is a diagram illustrating an example of the specific structure of the chopper section, input short-circuit section, level conversion section, and reference voltage generation section in the first embodiment.

[0012] Figure 4 This is a diagram schematically illustrating an example of the operating waveforms of various parts of the voltage detection circuit in the first embodiment.

[0013] Figure 5 This is a diagram schematically illustrating the structure of the voltage detection circuit according to the second embodiment.

[0014] Figure 6 This is a diagram schematically illustrating an example of a calibration table stored in the memory of the second embodiment.

[0015] Figure 7 This is a diagram illustrating the method for estimating the offset value under the current temperature conditions in the second embodiment. Detailed Implementation

[0016] Hereinafter, several embodiments will be described with reference to the accompanying drawings. Furthermore, in each embodiment, substantially identical structures are labeled with the same reference numerals and their descriptions are omitted.

[0017] (First Implementation) The following is for reference Figures 1-4 The first embodiment will be described.

[0018] <Overall Structure> like Figure 1 As shown, the voltage detection circuit 1 in this embodiment is a circuit that detects the voltage difference between a pair of input nodes Nip and Nim. The voltage detection circuit 1 is used, for example, in a battery monitoring IC installed in a vehicle such as an automobile. IC is short for Integrated Circuit. Although not shown in the figure, a battery monitoring IC is an integrated circuit that integrates various operations for monitoring the voltage and other states of a battery pack composed of multiple battery cells connected in series.

[0019] In this case, voltage detection circuit 1 detects the voltage of the battery cell, and therefore provides the battery cell voltage to input nodes Nip and Nin. As mentioned above, the battery cell is connected in series with other battery cells in multiple stages, thus a common-mode voltage is superimposed on the battery cell. Regarding this common-mode voltage, the higher the battery cell is connected on the upper side of the battery pack, i.e., the higher the potential side, the higher the common-mode voltage, with a maximum value of, for example, a relatively high voltage of several hundred volts.

[0020] Furthermore, in this case, an external filter 2, which serves as an RC filter for noise removal, is provided before the voltage detection circuit 1. That is, in this case, the battery cell voltage is supplied to the input nodes Nip and Nim via the external filter 2. The external filter 2 is, for example, a low-pass filter comprising two resistors and one capacitor. Additionally, in this specification, the low-pass filter is sometimes referred to as an LPF.

[0021] The voltage detection circuit 1 is a differential structure that samples and detects the voltage Vinp of the high-potential side of input node Nip and the voltage Vinm of the low-potential side of input node Nim. The voltage detection circuit 1 includes a chopper section 3, an input short-circuit section 4, an A / D conversion section 5, a digital chopper section 11, a voltage detection section 12, a level conversion section 7, a reference voltage generation section 8, and an offset correction section 9.

[0022] The chopper 3 receives the voltages Vinp and Vinm from a pair of input nodes Nip and Nim, and reverses the polarity of these voltages to output them as voltages Voutp and Voutm from a pair of output nodes Nop and Nom. The chopper 3 has a structure that includes a chopper switch connected between the pair of input nodes Nip and Nim and the pair of output nodes Nop and Nom, as detailed later. In the following description, the operation of the chopper 3 will sometimes be referred to as chopping operation.

[0023] The input short-circuit unit 4 has a short-circuit switch connected between a pair of input nodes Nip and Nim, and is capable of performing a short-circuit operation to short-circuit the pair of input nodes Nip and Nim. The operation of the input short-circuit unit 4 is controlled by the offset correction unit 9, which will be described later. The short-circuit operation performed by the input short-circuit unit 4 is performed when the system equipped with the voltage detection circuit 1 stops operating or during pre-shipment inspection of products equipped with the voltage detection circuit 1. However, the short-circuit operation performed by the input short-circuit unit 4 is not performed during normal operation of the system equipped with the voltage detection circuit 1.

[0024] The A / D conversion unit 5 is, for example, a ΔΣ type A / D converter that performs A / D conversion on the voltage output from the chopper unit 3. Additionally, in Figure 1 In this configuration, the A / D converter is omitted and replaced with an ADC. The digital chopper 11 is a structure that performs polarity reversal digitally, outputting a signal after the input signal has been inverted. The voltage detection unit 12 is composed of a digital filter, which calculates the detected value of the differential voltage based on the output signal of the A / D converter 5. The filter of the voltage detection unit 12 is, for example, a moving average filter or an LPF. The output signal of the filter of the voltage detection unit 12 becomes a digital value corresponding to the detected value of the differential voltage.

[0025] A first drive signal for driving the chopper switch of the chopper unit 3 and a second drive signal for driving the short-circuit switch of the input short-circuit unit 4 are input to the level conversion unit 7. The level conversion unit 7 converts the level of the first drive signal and outputs it to the chopper unit 3, and converts the level of the second drive signal and outputs it to the input short-circuit unit 4. The reference voltage generation unit 8 is connected between a pair of input nodes Nip and Nim. The reference voltage generation unit 8 uses the voltages Vinp and Vinm of the input nodes Nip and Nim to generate the reference voltage for the level conversion unit 7.

[0026] The offset correction unit 9 corrects the offset of the detected value obtained by the voltage detection unit 12, and includes a correction control unit 13, a memory 14, and an offset subtraction unit 15. The correction control unit 13 can control the on / off state of the short-circuit switch provided in the input short-circuit unit 4. The correction control unit 13 obtains the detected value detected by the voltage detection unit 12 as the offset value when a pair of input nodes Nip and Nim are short-circuited by the input short-circuit unit 4.

[0027] That is, the calibration control unit 13 acquires the offset value when the system stops operating or during pre-shipment inspection of the product. The calibration control unit 13 writes the acquired offset value into the memory 14 and stores it. During normal operation, the calibration control unit 13 reads the offset value from the memory 14 and outputs it to the offset subtraction unit 15.

[0028] The offset subtraction unit 15 corrects the offset by subtracting the offset value provided by the correction control unit 13 from the detection value detected by the voltage detection unit 12 when the input nodes Nip and Nim are not short-circuited by the input short-circuit unit 4. In this case, the signal output from the offset subtraction unit 15 becomes the final differential voltage detection value ΔV. That is, the offset subtraction unit 15 corrects the offset by subtracting a pre-prepared offset value from the detection value detected by the voltage detection unit 12 during normal operation, and outputs the corrected value as the final differential voltage detection value ΔV.

[0029] The signals of each part in the voltage detection circuit 1 of the above structure are as follows: Figure 2 As shown. Additionally... Figure 2 The horizontal axis in the diagram represents the frequency f. That is, as shown... Figure 2 As shown in (signal a), the signal input to chopper 3 is only the differential voltage signal. Furthermore, in Figure 2 In this context, the frequency of the differential voltage signal is denoted as fin.

[0030] like Figure 2 As shown in (signal b), the signal output from chopper 3 and input to A / D converter 5 becomes a signal modulated at the chopping frequency fchop of chopper 3. That is, in chopper 3, modulation based on analog polarity reversal chopping is performed. In A / D converter 5, the signal output from chopper 3 is converted into a digital signal. In digital chopper 11, demodulation based on digital polarity reversal chopping is performed.

[0031] like Figure 2 As shown in (signal c), the signal output from the digital chopper 6 and input to the filter of the voltage detection unit 12 is a demodulated and digitally converted signal, which becomes a signal superimposed with high-frequency noise from the ΔΣ modulator of the A / D converter 5. In the digital filter of the voltage detection unit 12, noise and other noise are removed. Figure 2 As shown in (signal d), the signal output from the filter of the voltage detection unit 12 becomes the differential voltage signal after the high-frequency noise has been removed by the filter.

[0032] <Specific Structure of the Chopper Section> As a specific structure of the chopper section 3, for example, it can adopt Figure 3 The structure shown. (As illustrated) Figure 3As shown, in the chopper section 3, the structure corresponding to the input node Nip of one of the pair of input nodes Nip and Nim, and the structure corresponding to the input node Nim of the other of the pair of input nodes Nip and Nim, are symmetrical structures.

[0033] That is, the chopper unit 3 has four chopper switches Sc1 to Sc4 connected between a pair of input nodes Nip and Nim and a pair of output nodes Nop and Nom. Additionally, although not shown in the diagram, two sampling capacitors, which are paired in the differential structure, are connected to the pair of output nodes Nop and Nom. The chopper switches Sc1 to Sc4 can open and close the connection between the pair of input nodes Nip and Nim, the pair of output nodes Nop and Nom, and the aforementioned two sampling capacitors.

[0034] Chopper switch Sc1 is configured to open and close the connection between input node Nip and output node Nop. One terminal of chopper switch Sc1 is connected to input node Nip, and the other terminal is connected to output node Nop. Chopper switch Sc2 is configured to open and close the connection between input node Nim and output node Nom. One terminal of chopper switch Sc2 is connected to input node Nim, and the other terminal is connected to output node Nom.

[0035] Chopper switch Sc3 is configured to open and close the connection between input node Nip and output node Nom. One terminal of chopper switch Sc3 is connected to input node Nip, and the other terminal is connected to output node Nom. Chopper switch Sc4 is configured to open and close the connection between input node Nim and output node Nop. One terminal of chopper switch Sc4 is connected to input node Nim, and the other terminal is connected to output node Nop.

[0036] Each of the chopper switches Sc1 to Sc4 is composed of two MOSFETs whose drains are connected to each other and whose gates are connected to each other. That is, chopper switches Sc1 to Sc4 are all back-to-back opposing structures and are composed of two MOSFETs sharing a common drain. In this embodiment, the MOSFETs constituting chopper switches Sc1 to Sc4 are all N-channel MOSFETs. In addition, in this specification, N-channel MOSFETs are sometimes omitted and referred to as NMOS.

[0037] The chopper switch Sc1 is structured as two NMOS transistors 21 and 22 connected in series. The source of NMOS 21 is connected to the input node Nip, and the source of NMOS 22 is connected to the output node Nop. The drains of NMOS 21 and 22 are interconnected. The gates of NMOS 21 and 22 are interconnected. The back gate of NMOS 21 is connected to its source. The back gate of NMOS 22 is connected to its source.

[0038] Between the back gate and drain of NMOS 21, there exists a body diode D21 with the back gate side as the anode. Between the back gate and drain of NMOS 22, there exists a body diode D22 with the back gate side as the anode. That is, in the chopper switch Sc1, body diodes D21 and D22 are opposite to each other. The drive signal SCH1_HP output from the level conversion unit 7 is provided to the gates of NMOS 21 and 22. Thus, the turn-on and turn-off of NMOS 21 and 22 are controlled by the drive signal SCH1_HP. The drive signal SCH1_HP functions as the first drive signal for driving the chopper switch S1.

[0039] The chopper switch Sc2 is structured as two NMOS transistors 23 and 24 connected in series. The source of NMOS 23 is connected to the input node Nim, and the source of NMOS 24 is connected to the output node Nom. The drains of NMOS 23 and 24 are interconnected. The gates of NMOS 23 and 24 are interconnected. The back gate of NMOS 23 is connected to its source. The back gate of NMOS 24 is connected to its source.

[0040] Between the back gate and drain of NMOS 23, there is a body diode D23 with the back gate side as the anode. Between the back gate and drain of NMOS 24, there is a body diode D24 with the back gate side as the anode. That is, in the chopper switch Sc2, body diodes D23 and D24 are opposite to each other. The drive signal SCH1_HM output from the level conversion unit 7 is provided to the gates of NMOS 23 and 24. Thus, the turn-on and turn-off of NMOS 23 and 24 are controlled by the drive signal SCH1_HM. The drive signal SCH1_HM functions as the first drive signal for driving the chopper switch Sc2.

[0041] The chopper switch Sc3 is configured as two NMOS25 and 26 connected in series. The source of NMOS25 is connected to the input node Nip, and the source of NMOS26 is connected to the output node Nom. The drains of NMOS25 and 26 are interconnected. The gates of NMOS25 and 26 are interconnected. The back gate of NMOS25 is connected to its source. The back gate of NMOS26 is connected to its source.

[0042] Between the back gate and drain of NMOS 25, there is a body diode D25 with the back gate side as the anode. Between the back gate and drain of NMOS 26, there is a body diode D26 with the back gate side as the anode. That is, in chopper switch Sc3, body diodes D25 and D26 are opposite to each other. The drive signal SCH2_HP output from level conversion unit 7 is provided to the gates of NMOS 25 and 26. Thus, the turn-on and turn-off of NMOS 25 and 26 are controlled by drive signal SCH2_HP. Drive signal SCH2_HP functions as the first drive signal for driving chopper switch Sc3.

[0043] The chopper switch Sc4 is configured as two NMOS27 and 28 connected in series. The source of NMOS27 is connected to the input node Nim, and the source of NMOS28 is connected to the output node Nop. The drains of NMOS27 and 28 are interconnected. The gates of NMOS27 and 28 are interconnected. The back gate of NMOS27 is connected to its source. The back gate of NMOS28 is connected to its source.

[0044] Between the back gate and drain of NMOS 27, there is a body diode D27 with the back gate side as the anode. Between the back gate and drain of NMOS 28, there is a body diode D28 with the back gate side as the anode. That is, in chopper switch Sc4, body diodes D27 and D28 are opposite to each other. The drive signal SCH2_HM output from level conversion unit 7 is provided to the gates of NMOS 27 and 28. Thus, the turn-on and turn-off of NMOS 27 and 28 are controlled by drive signal SCH2_HM. Drive signal SCH2_HM functions as the first drive signal for driving chopper switch Sc4.

[0045] <Specific structure of the input short-circuit section> As a specific structure of the input short-circuit section 4, for example, it can adopt Figure 3 The structure shown. (As illustrated) Figure 3 As shown, in the input short-circuit section 4, the structure corresponding to one of the pair of input nodes Nip and Nim, i.e., input node Nip, and the structure corresponding to the other of the pair of input nodes Nip and Nim, i.e., input node Nim, are symmetrical structures.

[0046] That is, the input short-circuit unit 4 includes two short-circuit switches Ss1 and Ss2 connected between a pair of input nodes Nip and Nim. Short-circuit switches Ss1 and Ss2 can short-circuit the pair of input nodes Nip and Nim. The input short-circuit unit 4 short-circuits the pair of input nodes Nip and Nim by complementary switching of the two short-circuit switches Ss1 and Ss2, as detailed later. Furthermore, the short-circuit switches Ss1 and Ss2 are driven synchronously with the chopper switches S1 to S4 of the chopper unit 3, as detailed later.

[0047] Short-circuit switch Ss1 is configured to open and close between input nodes Nip and Nim. One terminal of short-circuit switch Ss1 is connected to input node Nip, and the other terminal is connected to input node Nim. Short-circuit switch Ss2 is configured to open and close between input nodes Nip and Nim. One terminal of short-circuit switch Ss2 is connected to input node Nip, and the other terminal is connected to input node Nim.

[0048] Both short-circuit switches Ss1 and Ss2 are composed of two MOSFETs whose drains are connected to each other and whose gates are connected to each other. That is, both short-circuit switches Ss1 and Ss2 are back-to-back opposing structures and are composed of two MOSFETs sharing a common drain. In this embodiment, the MOSFETs constituting short-circuit switches Ss1 and Ss2 are both NNMOS.

[0049] The short-circuit switch Ss1 forms a structure where two NMOS transistors 31 and 32 are connected in series. The source of NMOS 31 is connected to the input node Nip, and the source of NMOS 32 is connected to the input node Nim. The drains of NMOS 31 and 32 are interconnected. The gates of NMOS 31 and 32 are interconnected. The back gate of NMOS 31 is connected to its source. The back gate of NMOS 32 is connected to its source.

[0050] Between the back gate and drain of NMOS31, there exists a body diode D31 with the back gate side as the anode. Between the back gate and drain of NMOS32, there exists a body diode D32 with the back gate side as the anode. That is, in the short-circuit switch Ss1, body diodes D31 and D32 are opposite to each other. The drive signal SHORTp_H output from the level conversion unit 7 is provided to the gates of NMOS31 and 32. Thus, the on / off state of NMOS31 and 32 is controlled by the drive signal SHORTp_H. The drive signal SHORTp_H functions as a second drive signal for driving the short-circuit switch S21.

[0051] The short-circuit switch Ss2 forms a structure where two NMOS transistors 33 and 34 are connected in series. The source of NMOS 33 is connected to the input node Nip, and the source of NMOS 34 is connected to the input node Nim. The drains of NMOS 33 and 34 are interconnected. The gates of NMOS 33 and 34 are interconnected. The back gate of NMOS 33 is connected to its source. The back gate of NMOS 34 is connected to its source.

[0052] Between the back gate and drain of NMOS33, there exists a body diode D33 with the back gate side as the anode. Between the back gate and drain of NMOS34, there exists a body diode D34 with the back gate side as the anode. That is, in the short-circuit switch Ss2, body diodes D33 and D34 are opposite to each other. The drive signal SHORTn_H output from the level conversion unit 7 is provided to the gates of NMOS33 and 34. Thus, the on / off state of NMOS33 and 34 is controlled by the drive signal SHORTn_H. The drive signal SHORTn_H functions as a second drive signal for driving the short-circuit switch Ss2.

[0053] <Detailed Structure of the Level Conversion Section> As a specific structure of the level conversion unit 7, for example, it can adopt Figure 3The structure shown. (As illustrated) Figure 3 As shown, in the level conversion unit 7, the structure corresponding to the input node Nip of one of the pair of input nodes Nip and Nim and the structure corresponding to the input node Nim of the other of the pair of input nodes Nip and Nim are symmetrical structures.

[0054] That is, the level conversion unit 7 includes capacitive coupling switches 41, 42, and 43, which are used to convert the levels of externally provided drive signals SCH1, SCH2, SHORTp, and SHORTn. Specifically, the level conversion unit 7 uses capacitive coupling switch 41 to convert the levels of drive signals SCH1 and SCH2 and outputs them as drive signals SCH1_HP and SCH2_HP. The level conversion unit 7 uses capacitive coupling switch 42 to convert the levels of drive signals SCH1 and SCH2 and outputs them as drive signals SCH1_HM and SCH2_HM. The level conversion unit 7 uses capacitive coupling switch 43 to convert the levels of drive signals SHORTp and SHORTn and output them as drive signals SHORTp_H and SHORTn_H.

[0055] Drive signals SCH1 and SCH2 function as the first drive signals. Drive signals SHORTp and SHORTn function as the second drive signals. The level conversion unit 7 controls the operation of chopper switches Sc1~Sc4 and short-circuit switches Ss1 and Ss2 based on drive signals SCH1, SCH2, SHORTp, and SHORTn. Drive signals SCH1, SCH2, SHORTp, and SHORTn are all binary signals, with a high level of +5V and a low level of 0V.

[0056] Capacitively coupled switch 41 performs level switching of drive signals SCH1 and SCH2 based on the voltage Vinp of input node Nip. Capacitively coupled switch 42 performs level switching of drive signals SCH1 and SCH2 based on the voltage Vinm of input node Nim. Capacitively coupled switch 43 performs level switching of drive signals SHORTp and SHORTn based on the reference voltage Vcm output from the reference voltage generation unit 8 (described later).

[0057] The capacitively coupled switch 41 has driving capacitors Cc1 and Cc3 respectively provided corresponding to switches Sc1 and Sc3. The capacitively coupled switch 41 is configured to drive the gates of NMOS 21 and 22 via driving capacitor Cc1 to control the on / off state of chopper switch Sc1, and to drive the gates of NMOS 25 and 26 via driving capacitor Cc3 to control the on / off state of chopper switch Sc3.

[0058] The driving capacitor Cc1 is connected between the input node (node ​​N1) of the driving signal SCH1 and the output node (node ​​N2) of the driving signal SCH1_HP. Node N2 is connected to the gates of NMOS 21 and 22. The driving capacitor Cc3 is connected between the input node (node ​​N3) of the driving signal SCH2 and the output node (node ​​N4) of the driving signal SCH2_HP. Node N4 is connected to the gates of NMOS 25 and 26. In this embodiment, the driving capacitors Cc1 and Cc3 are, for example, composed of comb capacitors.

[0059] The capacitively coupled switch 41 has two NMOS transistors, 51 and 52. The drain of NMOS 51 is connected to node N2, and its source is connected to node N5. The input voltage Vinp from node Nip is supplied to node N5. The back gate of NMOS 51 is connected to its source. The gate of NMOS 51 is connected to node N4. Between the back gate and drain of NMOS 51, there is a body diode D51 with the back gate side as the anode.

[0060] The drain of the NMOS52 is connected to node N4, and its source is connected to node N5. The back gate of the NMOS52 is connected to its source. The gate of the NMOS52 is connected to node N2. Between the back gate and drain of the NMOS52, there is a body diode D52 with the back gate side as the anode.

[0061] The capacitively coupled switch 41 of the above structure uses the voltage Vinp of the input node Nip as a reference potential to generate drive signals SCH1_HP for driving the gates of NMOS 21 and 22, and drive signals SCH2_HP for driving the gates of NMOS 25 and 26. Drive signal SCH1_HP, having the same logic as drive signal SCH1, is supplied from node N2 to the gates of NMOS 21 and 22 of chopper switch Sc1. Drive signal SCH2_HP, having the same logic as drive signal SCH2, is supplied from node N4 to the gates of NMOS 25 and 26 of chopper switch Sc3.

[0062] The capacitively coupled switch 42 has driving capacitors Cc2 and Cc4 respectively provided corresponding to switches Sc2 and Sc4. The capacitively coupled switch 42 is configured to drive the gates of NMOS 23 and 24 via driving capacitor Cc2 to control the on / off state of chopper switch Sc2, and to drive the gates of NMOS 27 and 28 via driving capacitor Cc4 to control the on / off state of chopper switch Sc4.

[0063] The driving capacitor Cc2 is connected between the input node (node ​​N6) of the driving signal SCH1 and the output node (node ​​N7) of the driving signal SCH1_HM. Node N7 is connected to the gates of NMOS 23 and 24. The driving capacitor Cc4 is connected between the input node (node ​​N8) of the driving signal SCH2 and the output node (node ​​N9) of the driving signal SCH2_HM. Node N9 is connected to the gates of NMOS 27 and 28. In this embodiment, the driving capacitors Cc2 and Cc4 are, for example, composed of comb capacitors.

[0064] The capacitively coupled switch 42 has two NMOS transistors, 53 and 54. The drain of NMOS 53 is connected to node N7, and its source is connected to node N10. Node N10 is supplied with the input voltage Vinm from node Nim. The back gate of NMOS 53 is connected to its source. The gate of NMOS 53 is connected to node N9. Between the back gate and drain of NMOS 53, there is a body diode D53 with the back gate side as the anode.

[0065] The drain of the NMOS54 is connected to node N9, and its source is connected to node N10. The back gate of the NMOS54 is connected to its source. The gate of the NMOS54 is connected to node N7. Between the back gate and drain of the NMOS54, there is a body diode D54 with the back gate side as the anode.

[0066] The capacitively coupled switch 42 of the above structure uses the voltage Vinm of the input node Nim as a reference potential to generate drive signals SCH1_HM for driving the gates of NMOS 23 and 24 and drive signals SCH2_HM for driving the gates of NMOS 27 and 28. Drive signal SCH1_HM, having the same logic as drive signal SCH1, is supplied from node N7 to the gates of NMOS 23 and 24 of chopper switch Sc2. Drive signal SCH2_HM, having the same logic as drive signal SCH2, is supplied from node N9 to the gates of NMOS 27 and 28 of chopper switch Sc4.

[0067] The capacitively coupled switch 43 has driving capacitors Cs1 and Cs2 respectively provided corresponding to short-circuit switches Ss1 and Ss2. The capacitively coupled switch 43 is configured to drive the gates of NMOS 31 and 32 via driving capacitor Cs1 to control the on / off state of short-circuit switch Ss1, and to drive the gates of NMOS 33 and 34 via driving capacitor Cs2 to control the on / off state of short-circuit switch Ss2.

[0068] The driving capacitor Cs1 is connected between the input node N11 of the driving signal SHORTp and the output node N12 of the driving signal SHORTp_H. Node N12 is connected to the gates of NMOS 31 and 32. The driving capacitor Cs2 is connected between the input node N13 of the driving signal SHORTn and the output node N14 of the driving signal SHORTn_H. Node N14 is connected to the gates of NMOS 33 and 34. In this embodiment, the driving capacitors Cs1 and Cs2 are, for example, composed of comb capacitors.

[0069] The capacitively coupled switch 43 includes two NMOS transistors 55 and 56. The drain of the NMOS 55 is connected to node N12, and its source is connected to node N15. For node N15, a reference voltage Vcm output from the reference voltage generation unit 8 (described later) is provided. The back gate of the NMOS 55 is connected to its source. The gate of the NMOS 55 is connected to node N14. Between the back gate and drain of the NMOS 55, there is a body diode D55 with the back gate side as the anode.

[0070] The drain of the NMOS56 is connected to node N14, and its source is connected to node N15. The back gate of the NMOS56 is connected to its source. The gate of the NMOS56 is connected to node N12. Between the back gate and drain of the NMOS56, there is a body diode D56 with the back gate side as the anode.

[0071] The capacitively coupled switch 43 of the above structure uses a reference voltage Vcm as a reference potential to generate drive signals SHORTp_H for driving the gates of NMOS 31 and 32, and drive signals SHORTn_H for driving the gates of NMOS 33 and 34. Drive signal SHORTp_H, having the same logic as drive signal SHORTp, is supplied from node N12 to the gates of NMOS 31 and 32 of short-circuit switch Ss1. Drive signal SHORTn_H, having the same logic as drive signal SHORTn, is supplied from node N14 to the gates of NMOS 33 and 34 of short-circuit switch Ss2.

[0072] According to the above structure, capacitively coupled switches 41-43 supply drive signals SCH1_HP, SCH2_HP, SCH1_HM, SCH2_HM, SHORTp_H, and SHORTn_H to the gates of NMOS 21-28 and 31-34 that constitute chopper switches Sc1-Sc4 and short-circuit switches Ss1 and Ss2, respectively. The drive signals SCH1_HP, SCH2_HP, SCH1_HM, SCH2_HM, SHORTp_H, and SHORTn_H are binary signals that represent either the cutoff level (turning off NMOS 21-28 and 31-34) or the turn-on level (turning on NMOS 21-28 and 31-34).

[0073] The above-mentioned turn-on level is the level that satisfies the following equation (1), and the above-mentioned turn-off level is the level that satisfies the following equation (2). Wherein, the gate-source voltage of the NMOS is set to VGS, and the threshold voltage of the NMOS is set to Vt.

[0074] VGS>Vt…(1) VGS≒0…(2) <Detailed Structure of the Reference Voltage Generator> As a specific structure of the reference voltage generation unit 8, for example, it can adopt Figure 3 The structure is shown. The reference voltage generation unit 8 includes resistors Rr1 and Rr2, capacitors Cr1 and Cr2, and four reference voltage switches Sr1, Sr2, Sr3, and Sr4. One terminal of resistor Rr1 is connected to the input node Nip, and the other terminal is connected to node N21. One terminal of resistor Rr2 is connected to node N21, and the other terminal is connected to the input node Nim.

[0075] One terminal of capacitor Cr1 is connected to input node Nip, and the other terminal is connected to node N21. One terminal of capacitor Cr2 is connected to node N22, and the other terminal is connected to input node Nim. Reference voltage switches Sr1 to Sr4 are connected between nodes N21 and N22, respectively. Thus, in the reference voltage generation unit 8, resistors Rr1 and Rr2 and reference voltage switches Sr1 to Sr4 are connected in series between a pair of input nodes Nip and Nim.

[0076] The reference voltage switch Sr1 is driven using the drive signal SCH1_HP used to drive chopper switch Sc1. The reference voltage switch Sr2 is driven using the drive signal SCH1_HM used to drive chopper switch Sc2. The reference voltage switch Sr3 is driven using the drive signal SCH2_HP used to drive chopper switch Sc3. The reference voltage switch Sr4 is driven using the drive signal SCH2_HM used to drive chopper switch Sc4.

[0077] The reference voltage switches Sr1 to Sr4 can each be constructed from two MOSFETs whose sources are connected to each other or whose drains are connected to each other. In this embodiment, the reference voltage switches Sr1 to Sr4 are each constructed from two MOSFETs whose drains are connected to each other. That is, the reference voltage switches Sr1 to Sr4 are all back-to-back opposed structures and are constructed from two MOSFETs sharing a common drain. In this embodiment, the MOSFETs constituting the reference voltage switches Sr1 to Sr4 are all NNMOS.

[0078] The reference voltage switch Sr1 is configured as two NMOS transistors 61 and 62 connected in series. The source of NMOS 61 is connected to node N21, and the source of NMOS 62 is connected to node N22. The drains of NMOS 61 and 62 are interconnected and connected to node N23. Node N23 is the output node for the reference voltage Vcm. The gates of NMOS 61 and 62 are interconnected. The back gate of NMOS 61 is connected to its source. The back gate of NMOS 62 is connected to its source.

[0079] Between the back gate and drain of NMOS61, there is a body diode D61 with the back gate side as the anode. Between the back gate and drain of NMOS62, there is a body diode D62 with the back gate side as the anode. That is, in the reference voltage switch Sr1, body diodes D61 and D62 are opposite to each other. A drive signal SCH1_HP is provided for each gate of NMOS61 and 62. Thus, the turn-on and turn-off of NMOS61 and 62 are controlled by the drive signal SCH1_HP.

[0080] The reference voltage switch Sr2 is configured as two NMOS transistors 63 and 64 connected in series. The source of NMOS 63 is connected to node N21, and the source of NMOS 64 is connected to node N22. The drains of NMOS transistors 61 and 62 are interconnected and connected to node N23. The gates of NMOS transistors 63 and 64 are interconnected. The back gate of NMOS 63 is connected to its source.

[0081] Between the back gate and drain of the NMOS63, there exists a body diode D63 with the back gate side as the anode. That is, in the reference voltage switch Sr2, body diodes D63 and D64 are opposite to each other. The drive signal SCH1_HM is provided to the gates of NMOS63 and 64. Therefore, the turn-on and turn-off of NMOS63 and 64 are controlled by the drive signal SCH1_HM.

[0082] The reference voltage switch Sr3 is configured as two NMOS65 and 66 connected in series. The source of NMOS65 is connected to node N21, and the source of NMOS66 is connected to node N22. The drains of NMOS65 and 66 are interconnected and connected to node N23. The gates of NMOS65 and 66 are interconnected. The back gate of NMOS65 is connected to its source. The back gate of NMOS66 is connected to its source.

[0083] Between the back gate and drain of the NMOS65, there exists a body diode D65 with the back gate side as the anode. Between the back gate and drain of the NMOS66, there exists a body diode D66 with the back gate side as the anode. That is, in the reference voltage switch Sr3, body diodes D65 and D66 are opposite to each other. A drive signal SCH2_HP is provided for each gate of the NMOS65 and 66. Therefore, the turn-on and turn-off of the NMOS65 and 66 are controlled by the drive signal SCH2_HP.

[0084] The reference voltage switch Sr4 is configured as two NMOS67 and 68 connected in series. The source of NMOS67 is connected to node N21, and the source of NMOS68 is connected to node N22. The drains of NMOS67 and 68 are interconnected and connected to node N23. The gates of NMOS67 and 68 are interconnected. The back gate of NMOS67 is connected to its source. The back gate of NMOS68 is connected to its source.

[0085] Between the back gate and drain of NMOS67, there exists a body diode D67 with the back gate side as the anode. Between the back gate and drain of NMOS68, there exists a body diode D68 with the back gate side as the anode. That is, in the reference voltage switch Sr4, body diodes D67 and D68 are opposite to each other. The drive signal SCH2_HM is provided to the gates of NMOS67 and 68. Therefore, the on / off state of NMOS67 and 68 is controlled by the drive signal SCH2_HM.

[0086] According to this structure, the reference voltage generation unit 8 drives the reference voltage switches Sr1 to Sr4 by using the drive signals SCH1_HP, SCH1_HM, SCH2_HP, and SCH2_HM used to drive the chopper switches Sc1 to Sc4, and can generate a reference voltage Vcm that is the intermediate potential of each voltage Vip and Vim of a pair of input nodes Nip and Nim.

[0087] Next, also refer to Figure 4 The function of the above structure will be explained. Figure 4 This is a timing diagram illustrating the action waveforms of each component. Figure 4In this context, the period Ta before time t1 and the period Tc after time t2 represent the aforementioned normal operation, while the period Tb from time t1 to time t2 represents the aforementioned operation stopping or inspection, etc. Figure 4 In the drive signals SHORTp, SHORTn, SCH1, and SCH2, a high level, which is a relatively high level, indicates the level at which the MOSFET of the driven object is turned on, and a low level, which is a relatively low level, indicates the level at which the MOSFET of the driven object is turned off.

[0088] During periods Ta and Tc, drive signals SHORTp and SHORTn are fixed at a low level, therefore the short-circuit operation performed by input short-circuit unit 4 is not executed. During periods Ta and Tc, drive signals SCH1 and SCH2 alternately become high level, thus chopper switches Sc1, Sc2 and Sc3, Sc4 are complementaryly switched on and off. Furthermore, the term "complementarily switched on and off" in this specification does not exclude the possibility of setting the period during which both switches are off, i.e., the so-called dead time.

[0089] Therefore, during periods Ta and Tc, the chopping operation of chopper 3 is performed. Consequently, during periods Ta and Tc, voltages Voutp and Voutm become waveforms that alternate between relatively high and relatively low levels. Furthermore, during periods Ta and Tc, reference voltage generation unit 8 operates by using drive signals SCH1_HP, SCH1_HM, SCH2_HP, and SCH2_HM, which are obtained by level-shifting drive signals SCH1 and SCH2, to generate reference voltage Vcm. Reference voltage Vcm becomes the intermediate voltage between the voltages Vinp and Vinm of input nodes Nip and Nim.

[0090] During period Tb, the drive signals SHORTp and SHORTn alternately become high, thus short-circuit switches Ss1 and Ss2 are complementaryly switched on and off. Therefore, during period Tb, the input short-circuit unit 4 performs a short-circuit operation, short-circuiting the input nodes Nip and Nim. The drive signals SHORTp and SHORTn become synchronized with the drive signals SCH1 and SCH2, thereby driving the short-circuit switches Ss1 and Ss2 synchronously with the chopper switches Sc1 to Sc4. The period of the drive signals SHORTp and SHORTn is, for example, a long period approximately twice the period of the drive signals SCH1 and SCH2.

[0091] According to the embodiment described above, the following effects can be obtained. The voltage detection circuit 1 of this embodiment does not have the selector structure found in the prior art, therefore, the offset is suppressed less compared to the prior art. Furthermore, according to the structure of this embodiment, without activating the input short-circuit section 4 and the reference voltage generation section 8, the impedance of the circuit observed from the input side becomes higher, thus reducing the amount of current flowing in, and consequently, reducing the input offset before correction.

[0092] Furthermore, in this embodiment, the structure corresponding to one of the pair of input nodes Nip and Nim in each of the chopper section 3, the input short-circuit section 4, and the level conversion section 7 is a symmetrical structure. Therefore, in the structure of this embodiment, during normal operation, the amount of current flowing through each of the pair of input nodes Nip and Nim can be balanced, and they will not become the main cause of offset. In this respect, offset can be reduced, thereby improving the accuracy of A / D conversion. Furthermore, according to the structure of this embodiment, offset is suppressed even more by offset correction performed by the offset correction section 9. Therefore, according to this embodiment, the voltage detection accuracy can be improved.

[0093] In this embodiment, the level conversion unit 7 uses capacitive coupling switches 41-43 to convert the levels of drive signals SCH1, SCH2 and drive signals SHORTp, SHORTn. This structure is suitable for applications requiring a common voltage with a relatively high superposition of the voltages Vip and Vim at input nodes Nip and Nim.

[0094] In this embodiment, the chopper switches Sc1~Sc4 of the chopper section 3, the short-circuit switches Ss1 and Ss2 of the input short-circuit section 4, and the reference voltage switches Sr1~Sr4 of the reference voltage generation section 8 are all composed of two MOSFETs with a back-to-back opposing structure. With this structure, reverse current can be prevented in the chopper section 3, the input short-circuit section 4, and the reference voltage generation section 8.

[0095] In this embodiment, the input short-circuit unit 4 includes two short-circuit switches Ss1 and Ss2. By complementary switching of these two short-circuit switches Ss1 and Ss2, a short circuit is formed between a pair of input nodes Nip and Nim. With this structure, the following effect can be achieved: even when short-circuit operation is performed, the short-circuit switches Ss1 and Ss2 cannot be kept constantly connected to address the problem caused by leakage in the level conversion unit 7, and therefore need to be appropriately disconnected.

[0096] While it's possible to use a structure that only provides one of the short-circuit switches Ss1 and Ss2 as the input short-circuit unit 4, this would require a relatively long on-time and a relatively short off-time for one short-circuit switch, which would become a major cause of errors. In contrast, by alternately driving the two short-circuit switches Ss1 and Ss2 as in this embodiment, the on-time and off-time of these short-circuit switches Ss1 and Ss2 can be made equal, thus solving the problem of leakage in the level conversion unit 7 and minimizing errors.

[0097] In this embodiment, short-circuit switches Ss1 and Ss2 are driven synchronously with chopper switches Sc1 to Sc4. This achieves the following effect: if short-circuit switches Ss1 and Ss2 are not driven synchronously with chopper switches Sc1 to Sc4, a short circuit may occur between input nodes Nip and Nim at an undesirable timing.

[0098] In contrast, according to this embodiment, undesirable short circuits between the timing input nodes Nip and Nim can be prevented. As a result, imbalances between the input nodes Nip and Nim can be prevented, thereby minimizing detection errors. Furthermore, the synchronization structure implemented in this embodiment also simplifies the timing design of the drive signals SHORTp and SHORTn for driving the short-circuit switches Ss1 and Ss2, as well as the drive signals SCH1 and SCH2.

[0099] In this embodiment, the MOSFETs constituting the chopper switches Sc1~Sc4, short-circuit switches Ss1, Ss2, reference voltage switches Sr1~Sr4, and capacitively coupled switches 41~43 are all N-channel MOSFETs. With this structure, since there are no different components, it has an advantage in terms of the area of ​​the IC used in the voltage detection circuit 1. That is, according to the above structure, only N-channel MOSFETs are used, and there are no P-channel MOSFETs, so there is no need to form a trench, and correspondingly, the area can be kept relatively small.

[0100] (Second Implementation) The following is for reference Figures 5-7 The second embodiment will be described. For example... Figure 5As shown, the offset correction unit 72 of the voltage detection circuit 71 in this embodiment differs from the offset correction unit 9 of the first embodiment in that it has a correction control unit 73 and a memory 74 instead of a correction control unit 13 and a memory 14, and that a temperature sensor 75 is added. The temperature sensor 75 can detect the temperature of the voltage detection circuit 1, specifically, it can detect the temperature of the semiconductor chip on which the voltage detection circuit 1 is provided. The temperature sensor 75 outputs a temperature detection value, representing the detected temperature, to the correction control unit 73.

[0101] In addition to holding the same information as memory 14, memory 74 also holds the offset value (i.e., the reference offset value) obtained under specified temperature conditions and the temperature value corresponding to that reference offset value. Specifically, memory 74 stores information such as... Figure 6 The calibration table is shown below. In the calibration table, "Offset Value" corresponds to the reference offset value mentioned above, and "Temperature" corresponds to the temperature value mentioned above.

[0102] That is, the calibration table stores, for example, the offset value obtained at 50°C ("high temperature"), i.e., reference offset value A; the offset value obtained at 25°C ("normal temperature"), i.e., reference offset value B; and the offset value obtained at 0°C ("low temperature"), i.e., reference offset value C. These three reference offset values ​​A to C can be measured in advance, for example, at the factory when the product equipped with the voltage detection circuit 71 is shipped. Furthermore, during a predetermined process such as at the factory, a calibration table that associates the reference offset values ​​A to C with their respective corresponding temperature conditions, i.e., "high temperature," "normal temperature," and "low temperature," is written to the memory 74.

[0103] The correction control unit 73 uses the reference offset value and temperature value stored in the memory 74, as well as the temperature detection value detected by the temperature sensor 75, to estimate the offset value under the current temperature conditions. Such estimation can be performed, for example, using a correction formula such as linear interpolation or polynomial interpolation. Specifically, such as... Figure 7 As shown, when the temperature detection value is between "low temperature" and "normal temperature", the offset value under such temperature conditions is based on... Figure 7 The linear interpolation shown by the dashed line becomes O1, according to Figure 7 The polynomial interpolation shown by the double-dotted line becomes O2. Furthermore, this correction formula can be stored in memory 74 beforehand.

[0104] The offset correction unit 72 can use the estimated offset value to correct the offset. That is, during normal operation, the correction control unit 73 estimates the offset value as described above and outputs the estimated offset value to the offset subtraction unit 15. The offset subtraction unit 15 corrects the offset by subtracting the offset value provided by the correction control unit 73 from the detection value detected by the voltage detection unit 12 when the pair of input nodes Nip and Nim are not short-circuited by the input short-circuit unit 4.

[0105] According to the embodiment described above, the following effects can be obtained. The offset correction unit 72 of this embodiment uses the reference offset value and temperature value stored in the memory 74 (which stores the offset value obtained under specified temperature conditions, i.e., the reference offset value and the temperature value corresponding to the reference offset value), and the temperature detection value detected by the temperature sensor 75, to estimate the offset value under the current temperature conditions, and uses this estimated offset value to correct the offset. With this structure, correction corresponding to the temperature dependence of the offset can be performed, and the offset can be suppressed to a small extent regardless of temperature conditions, thereby improving the voltage detection accuracy.

[0106] (Other implementation methods) Furthermore, the present invention is not limited to the embodiments described above and in the accompanying drawings, and can be arbitrarily modified, combined, or extended without departing from its spirit. The numerical values ​​shown in the above embodiments are illustrative and are not intended to limit the invention.

[0107] In the second embodiment, the calibration table stored in the memory 74 stores reference offset values ​​corresponding to three temperature conditions respectively, but it may also store reference offset values ​​corresponding to four or more temperature conditions respectively. For example, if a calibration table storing reference offset values ​​in advance within a hypothetical temperature range at 1°C intervals is stored in the memory 74, the calibration control unit 73 no longer needs to use the calibration formula to estimate the offset value under the current temperature condition, and can directly use the reference offset values ​​stored in the calibration table as offset values.

[0108] Chopper switches Sc1-Sc4 can also be constructed from two MOSFETs whose sources and gates are connected to each other. That is, chopper switches Sc1-Sc4 can also be constructed from two MOSFETs with a back-to-back opposing structure and a shared source. Short-circuit switches Ss1 and Ss2 can also be constructed from two MOSFETs whose sources and gates are connected to each other. That is, short-circuit switches Ss1 and Ss2 can also be constructed from two MOSFETs with a back-to-back opposing structure and a shared source. Reference voltage switches Sr1-Sr4 can also be constructed from two MOSFETs with a back-to-back opposing structure and a shared source.

[0109] In the above embodiments, the MOSFETs constituting the chopper switches Sc1~Sc4, short-circuit switches Ss1, Ss2, reference voltage switches Sr1~Sr4, and capacitively coupled switches 41~43 are all N-channel MOSFETs, but they can also be P-channel MOSFETs. In this case, the area can also be kept relatively small.

[0110] This disclosure is based on embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and variations within the same range. Furthermore, various combinations, forms, and other combinations and forms including only one element, more than one element, or less than one element also fall within the scope and spirit of this disclosure.

Claims

1. A voltage detection circuit for detecting the voltage difference between the voltages of a pair of input nodes, characterized in that, have: The chopper section receives the voltages from the pair of input nodes, reverses the polarity of these voltages, and outputs them from the pair of output nodes, and has a chopper switch connected between the pair of input nodes and the pair of output nodes; The input short-circuit section includes a short-circuit switch connected between the pair of input nodes, which enables a short circuit between the pair of input nodes. The A / D conversion unit performs A / D conversion on the voltage output from the chopper unit; The voltage detection unit calculates the detected value of the differential voltage based on the output signal of the A / D converter; The level conversion unit converts and outputs the levels of the first driving signal used to drive the chopper switch and the second driving signal used to drive the short-circuit switch; A reference voltage generation unit generates the reference voltage in the level conversion unit; as well as The offset correction unit corrects the offset of the detected value. The offset correction unit obtains the detection value detected by the voltage detection unit when the pair of input nodes are short-circuited by the input short-circuit unit as the offset value, and corrects the offset by subtracting the offset value from the detection value detected by the voltage detection unit when the pair of input nodes are not short-circuited by the input short-circuit unit.

2. The voltage detection circuit according to claim 1, characterized in that, The level conversion unit is a structure that uses a capacitively coupled switch to convert the levels of the first drive signal and the second drive signal.

3. The voltage detection circuit according to claim 2, characterized in that, The reference voltage generation unit includes a resistor connected in series between the pair of input nodes and a reference voltage switch. The reference voltage switch consists of two MOSFETs whose sources are connected to each other or whose drains are connected to each other. The reference voltage, which serves as the intermediate potential of the voltages at the pair of input nodes, is generated by driving the reference voltage switch using a drive signal to drive the chopper switch. The level conversion unit performs level conversion of the second drive signal based on the reference voltage.

4. The voltage detection circuit according to any one of claims 1 to 3, characterized in that, In each of the chopper section, the input short-circuit section, and the level conversion section, the structure corresponding to one of the pair of input nodes and the structure corresponding to the other of the pair of input nodes are symmetrical structures.

5. The voltage detection circuit according to any one of claims 1 to 3, characterized in that, The chopper switch and the short-circuit switch are each composed of two MOSFETs whose sources are connected to each other or whose drains are connected to each other and whose gates are connected to each other.

6. The voltage detection circuit according to any one of claims 1 to 3, characterized in that, The offset correction unit also includes: Temperature sensor, used to detect temperature; and The memory stores the offset value (i.e., the reference offset value) and the temperature corresponding to the reference offset value, obtained under specified temperature conditions. The offset correction unit can use the reference offset value and the temperature value stored in the memory, as well as the temperature detection value detected by the temperature sensor, to estimate the offset value under the current temperature conditions, and use the estimated offset value to correct the offset.

7. The voltage detection circuit according to any one of claims 1 to 3, characterized in that, The input short-circuit section includes two short-circuit switches, which are switched on and off complementaryly to short-circuit the pair of input nodes.

8. The voltage detection circuit according to any one of claims 1 to 3, characterized in that, The short-circuit switch is driven synchronously with the chopper switch.

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