Binding impedance detection apparatus and method

Abstract

This application provides a bonding impedance detection device and method, relating to the field of display technology, and solves the technical problem that it is difficult to connect two metal traces at the lower end of the substrate pad for bonding impedance detection as the size of the substrate pad decreases. The bonding impedance detection device includes: a first chip terminal, a second chip terminal, a third chip terminal, a first substrate terminal, a second substrate terminal, a third substrate terminal, a first test line, a second test line, a third test line, a fourth test line, a fifth test line, and a detection module. With this structure, each of the first, second, and third substrate terminals only needs to be connected to one test line for bonding impedance detection. Therefore, even as the size of the first, second, and third substrate terminals decreases with the development of display technology, bonding impedance detection can still be performed using this structure.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a bonding impedance detection device and method. Background Technology

[0002] With the development of display technology, some display modules, such as Organic Light-Emitting Diode (OLED) display modules, have begun to adopt COP (Chip On Pi) packaging technology. Specifically, the COP packaging process involves folding a portion of the display substrate to the back and bonding the integrated circuit (IC) chip to the display substrate. When bonding the driver chip to the display substrate, anisotropic conductive film (ACF) is used for heat and pressure bonding.

[0003] Testing the COP bonding impedance after bonding the driver chip to the display module is crucial. By evaluating whether the COP bonding impedance meets the specifications, the bonding state of the bonding particles can be determined. If the COP bonding impedance is too high, it will lead to display defects such as dark lines.

[0004] In related technologies, when testing COP bonding impedance, it is necessary to connect the lower end of one of the substrate pads (Panel Pad) to two metal traces, and connect the other ends of the two metal traces to their respective test points. However, as the size of the Panel Pad becomes smaller and smaller, it becomes increasingly difficult to connect the lower end of the Panel Pad to the two metal traces. Summary of the Invention

[0005] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a bonding impedance detection device and method.

[0006] In a first aspect, one embodiment of this application provides a bonding impedance detection device, comprising: a first chip terminal disposed on a driver chip; a second chip terminal disposed on the driver chip and electrically connected to the first chip terminal; a third chip terminal disposed on the driver chip and electrically connected to the second chip terminal; a first substrate terminal disposed on a display substrate and bonded to the first chip terminal; a second substrate terminal disposed on the display substrate and bonded to the second chip terminal; a third substrate terminal disposed on the display substrate and bonded to the third chip terminal; and a first test line electrically connected to the first substrate terminal and connected to a first test point on a flexible circuit board. Electrical connections: a second test line electrically connected to a second substrate terminal; a third test line electrically connected to the second test line and to a second test point on the flexible circuit board; a fourth test line electrically connected to the second test line and to a third test point on the flexible circuit board; a fifth test line electrically connected to a third substrate terminal and to a fourth test point on the flexible circuit board; and a detection module electrically connected to the first, second, third, and fourth test points, configured to determine the actual bonding impedance between the driver chip and the display substrate based on current data flowing through the first, second, third, and fourth test points.

[0007] In some embodiments, the first substrate terminal, the second substrate terminal, and the third substrate terminal are arranged sequentially along a first direction; wherein, the bonding impedance detection device further includes: a plurality of fourth substrate terminals disposed on one side of the first substrate terminal, the second substrate terminal, and the third substrate terminal in a second direction, the second direction intersecting the first direction, the plurality of fourth substrate terminals being arranged along the first direction, and a first interval being formed between each pair of adjacent fourth substrate terminals; wherein, a first test line passes through one side of the plurality of fourth substrate terminals in the first direction; and, a second test line passes between a fourth substrate terminal adjacent to the first test line and the first test line, or, the second test line passes through the first interval; and, a fifth test line passes through the first interval.

[0008] In some embodiments, the detection module includes: a detector electrically connected to a first test point, a second test point, a third test point, and a fourth test point, the detector being configured to determine a first resistance of a first branch based on the current flowing through the first test point and the fourth test point and the voltage between the first test point and the fourth test point, the first branch starting from the first test point, passing through a first test line, a first substrate terminal, a first chip terminal, a third chip terminal, a third substrate terminal, a fifth test line, and ending at the fourth test point; and to determine a second resistance of a second branch based on the current flowing through the second test point and the third test point and the voltage between the second test point and the third test point, the second branch starting from the second test point, passing through a third test line and a fourth test line, and ending at the third test point; and a processor communicatively connected to the detector, configured to receive the first resistance and the second resistance sent by the detector, and to determine the actual bonding impedance based on the first resistance and the second resistance.

[0009] In some embodiments, the processor is configured to: receive a first resistor and a second resistor sent by the detector; subtract the first resistor and the second resistor to obtain the difference; and divide the difference by 2 to obtain the actual binding impedance.

[0010] In some embodiments, the sum of the resistances of the first test line and the fifth test line is the same as the sum of the resistances of the third test line and the fourth test line.

[0011] In some embodiments, the processor stores a preset bonding impedance; wherein the processor is further configured to compare the preset bonding impedance with the actual bonding impedance to determine a detection result, the detection result being used to indicate whether the actual bonding impedance conforms to specifications.

[0012] In some embodiments, the detection module further includes: an analog-to-digital converter electrically connected to the detector and communicatively connected to the processor, the analog-to-digital converter being configured to receive analog signals of a first resistor and a second resistor output by the detector, convert the analog signals of the first resistor and the second resistor into digital signals of the first resistor and the second resistor, and send the digital signals of the first resistor and the second resistor to the processor.

[0013] In some embodiments, the bonding impedance detection device further includes an output module, communicatively connected to the processor, configured to receive the actual bonding impedance and / or detection result sent by the processor, and to display the actual bonding impedance and / or detection result.

[0014] Secondly, one embodiment of this application provides a bonding impedance detection method, applied to the bonding impedance detection device of any of the first aspects above. The bonding impedance detection method includes: determining the actual bonding impedance between the driver chip and the display substrate based on the current flowing through the first test point and the fourth test point, the voltage between the first test point and the fourth test point, the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point.

[0015] In some embodiments, determining the actual bonding impedance between the driver chip and the display substrate based on the current flowing through the first test point and the fourth test point, the voltage between the first test point and the fourth test point, the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point includes: determining a first resistance of a first branch based on the current flowing through the first test point and the fourth test point and the voltage between the first test point and the fourth test point, wherein the first branch starts from the first test point, passes through the first test line, the first substrate terminal, the first chip terminal, the third chip terminal, the third substrate terminal, and the fifth test line, and ends at the fourth test point; determining a second resistance of a second branch based on the current flowing through the second test point and the third test point and the voltage between the second test point and the third test point, wherein the second branch starts from the second test point, passes through the third test line and the fourth test line, and ends at the third test point; and determining the actual bonding impedance based on the first resistance and the second resistance.

[0016] The bonding impedance detection device and method proposed in this application embodiment enable each of the first substrate terminal, the second substrate terminal, and the third substrate terminal to be connected to only one test line for bonding impedance detection. Thus, even as the size of the first substrate terminal, the second substrate terminal, and the third substrate terminal becomes smaller with the development of display technology, bonding impedance detection can still be performed through this structure. Attached Figure Description

[0017] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 The diagram shown is a schematic of a binding impedance testing device in related technologies.

[0019] Figure 2 The diagram shows the connection between substrate pads and metal traces in related technologies.

[0020] Figure 3 The diagram shown is a schematic diagram of a bonding impedance detection device provided in an exemplary embodiment of this application.

[0021] Figure 4 The diagram shown is a wiring diagram of the first substrate terminal, the second substrate terminal, and the third substrate terminal provided in an exemplary embodiment of this application.

[0022] Figure 5 The diagram shown is a wiring diagram of the first substrate terminal, the second substrate terminal, and the third substrate terminal provided in another exemplary embodiment of this application.

[0023] Figure 6 The diagram shown is a schematic representation of the detection module and output module provided in an exemplary embodiment of this application.

[0024] Figure 7 The diagram shown is a structural schematic of the detection module and output module provided in another exemplary embodiment of this application.

[0025] Figure 8 The diagram shown is a schematic flowchart of a binding impedance detection method provided in an exemplary embodiment of this application.

[0026] Figure 9 The diagram shown is a flowchart of a binding impedance detection method provided in another exemplary embodiment of this application.

[0027] Figure label:

[0028] 11. First bump; 12. Second bump; 13. Third bump; 21. First substrate pad; 22. Second substrate pad; 23. Third substrate pad; 31. First metal trace; 32. Second metal trace; 33. Third metal trace; 34. Fourth metal trace; 41. First test point; 42. Second test point; 43. Third test point; 44. Fourth test point; 100. Bonding impedance detection device; 101. First chip terminal; 102. Second chip terminal; 103. Third chip terminal; 104. First substrate Terminal; 105, Second substrate terminal; 106, Third substrate terminal; 107, First test line; 108, Second test line; 109, Third test line; 110, Fourth test line; 111, Fifth test line; 112, Detection module; 1121, Detector; 1122, Processor; 1123, Analog-to-digital converter; 113, First test point; 114, Second test point; 115, Third test point; 116, Fourth test point; 117, Fourth substrate terminal; 118, Fifth substrate terminal; 119, Output module. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] Figure 1 The diagram shown is a schematic of a binding impedance testing device in related technologies. Figure 2 The diagram shows the connection between substrate pads and metal traces in related technologies.

[0031] In related technologies, such as Figure 1 As shown, the three bumps (IC bumps) of the driver chip are the first bump 11, the second bump 12, and the third bump 13, which are electrically connected to each other. The three panel pads on the display substrate are the first panel pad 21, the second panel pad 22, and the third panel pad 23. The first bump 11 is bonded to the first panel pad 21, the second bump 12 is bonded to the second panel pad 22, and the third bump 13 is bonded to the third panel pad 23. Figure 1 The area shown within the dashed box is the bonding point where the bump is bonded to the substrate pad via ACF.

[0032] like Figure 1 and Figure 2 As shown, the lower end of the first substrate pad 21 is electrically connected to the first metal trace 31, the lower end of the second substrate pad 22 is electrically connected to the second metal trace 32 and the third metal trace 33, the lower end of the third substrate pad 23 is electrically connected to the fourth metal trace 34, and the other ends of the first metal trace 31, the second metal trace 32, the third metal trace 33 and the fourth metal trace 34 are respectively electrically connected to their corresponding test points. Figure 2 (Not shown in the image), the first test point 41, the second test point 42, the third test point 43 and the fourth test point 44 are electrically connected.

[0033] If the resistance of the first metal trace 31 is R1, the resistance of the second metal trace 32 is R2, the resistance of the third metal trace 33 is R3, and the resistance of the fourth metal trace 34 is R4, then R1 + R4 = R2 + R3. The detection module, through electrical connections to the first test point 41 and the fourth test point 44, and to the second test point 42 and the third test point 43, can detect the impedance of the first branch as RA and the impedance of the second branch as RB. The first branch starts at the first test point 41, passes through the first metal trace 31, the first substrate pad 21, the first bump 11, the third bump 13, the third substrate pad 23, and the fourth metal trace 34, ending at the fourth test point 44. The second branch starts at the second test point 42, passes through the second metal trace 32, the second substrate pad 22, and the third metal trace 33, ending at the third test point 43. Then, the bonding impedance R0 between the driver chip and the display substrate can be calculated using the following formula 1.

[0034] Formula 1:

[0035] However, as the Panel Pad design becomes smaller, it becomes increasingly difficult to connect two metal traces at the lower end of the second substrate pad 22.

[0036] In view of this, this application proposes a bonding impedance detection device and method, which enables each of the first substrate terminal, the second substrate terminal and the third substrate terminal to be connected to only one test line for bonding impedance detection. Thus, even as the size of the first substrate terminal, the second substrate terminal and the third substrate terminal becomes smaller and smaller with the development of display technology, bonding impedance detection can still be performed through this structure.

[0037] Figure 3 The diagram shown is a schematic of a bonding impedance detection device provided in an exemplary embodiment of this application. Figure 4 The diagram shown is a wiring diagram of the first substrate terminal, the second substrate terminal, and the third substrate terminal provided in an exemplary embodiment of this application. Figure 5 The diagram shown is a wiring diagram of the first substrate terminal, the second substrate terminal, and the third substrate terminal provided in another exemplary embodiment of this application.

[0038] like Figures 3-5As shown in the figure, this application embodiment provides a bonding impedance detection device 100, including: a first chip terminal 101, a second chip terminal 102, a third chip terminal 103, a first substrate terminal 104, a second substrate terminal 105, a third substrate terminal 106, a first test line 107, a second test line 108, a third test line 109, a fourth test line 110, a fifth test line 111, a detection module 112, a first test point 113, a second test point 114, a third test point 115, and a fourth test point 116. The first chip terminal 101 is disposed on a driver chip (Integrated Circuit, IC). The second chip terminal 102 is disposed on the driver chip and electrically connected to the first chip terminal 101. The third chip terminal 103 is disposed on the driver chip and electrically connected to the second chip terminal 102. The first substrate terminal 104 is disposed on a display substrate and bonded to the first chip terminal 101. The second substrate terminal 105 is disposed on the display substrate and bonded to the second chip terminal 102. The third substrate terminal 106 is disposed on the display substrate and bonded to the third chip terminal 103. The first test line 107 is electrically connected to the first substrate terminal 104 and to the first test point 113 on the flexible printed circuit (FPC). The second test line 108 is electrically connected to the second substrate terminal 105. The third test line 109 is electrically connected to the second test line 108 and to the second test point 114 on the flexible printed circuit. The fourth test line 110 is electrically connected to the second test line 108 and to the third test point 115 on the flexible printed circuit. The fifth test line 111 is electrically connected to the third substrate terminal 106 and to the fourth test point 116 on the flexible printed circuit. The detection module 112 is electrically connected to the first test point 113, the second test point 114, the third test point 115 and the fourth test point 116, and is configured to determine the actual bonding impedance between the driver chip and the display substrate based on the current data flowing through the first test point 113, the second test point 114, the third test point 115 and the fourth test point 116.

[0039] Among them, the first chip terminal 101, the second chip terminal 102, and the third chip terminal 103 are chip bumps (ICBumps). The first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 are substrate pads (PanelPads). The actual bonding impedance is the bonding impedance between the IC Bump and the PanelPad, such as... Figure 3 The dotted boxes in the figure show the actual bonding impedances between the first chip terminal 101 and the first substrate terminal 104, the second chip terminal 102 and the second substrate terminal 105, and the third chip terminal 103 and the third substrate terminal 106.

[0040] For example, current data includes current and / or voltage.

[0041] For example, the detection module 112 is configured to determine the actual bonding impedance between the driver chip and the display substrate based on the current flowing through the first test point 113 and the fourth test point 116, the voltage between the first test point 113 and the fourth test point 116, the current flowing through the second test point 114 and the third test point 115, and the voltage between the second test point 114 and the third test point 115.

[0042] For example, the second chip terminal 102 is electrically connected to the first chip terminal 101 via a wire, and the third chip terminal 103 is electrically connected to the second chip terminal 102 via a wire.

[0043] For example, the first substrate terminal 104 is bonded to the first chip terminal 101 via an anisotropic conductive film (ACF) (i.e., using COP bonding), the second substrate terminal 105 is bonded to the second chip terminal 102 via anisotropic conductive film (i.e., using COP bonding), and the third substrate terminal 106 is bonded to the third chip terminal 103 via anisotropic conductive film (i.e., using COP bonding).

[0044] For example, the first test line 107, the second test line 108, the third test line 109, the fourth test line 110 and the fifth test line 111 are all metal wires.

[0045] For example, the second test lead 108 is soldered to the third test lead 109 and the fourth test lead 110; alternatively, the second test lead 108 is connected to the third test lead 109 and the fourth test lead 110 via a connector; or, the second test lead 108, the third test lead 109, and the fourth test lead 110 are derived from the same conductor, with the first half of the conductor being the second test lead 108 and the second half being separated to form the third test lead 109 and the fourth test lead 110. The above wiring methods are merely examples, and the embodiments of this application do not limit the wiring methods of the second test lead 108 with the third test lead 109 and the fourth test lead 110.

[0046] For example, the first test line 107 is electrically connected to one end of the first substrate terminal 104, the second test line 108 is electrically connected to one end of the second substrate terminal 105, and the fifth test line 111 is electrically connected to one end of the third substrate terminal 106.

[0047] For example, the flexible circuit board is bonded to the display substrate, such as by using a COP bonding method.

[0048] For example, the length of the second test line 108 can be set arbitrarily. For instance, the second test line 108 can extend from the connection point with the second substrate terminal 105 to outside the bonding area where the Panel Pad is located, and then be electrically connected to the third test line 109 and the fourth test line 110.

[0049] In the above embodiments, each of the first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 only needs to be connected to one test line to perform bonding impedance detection. Thus, even as the size of the first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 becomes smaller with the development of display technology, bonding impedance detection can still be performed through this structure.

[0050] In some embodiments, such as Figure 4 and Figure 5 As shown, the first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 are arranged sequentially along a first direction (as shown by the X direction in the figure). The bonding impedance detection device 100 further includes a plurality of fourth substrate terminals 117. The plurality of fourth substrate terminals 117 are disposed on one side of the first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 in a second direction (as shown by the Y direction in the figure), the second direction intersecting the first direction. The plurality of fourth substrate terminals 117 are arranged along the first direction, and a first interval is formed between each pair of adjacent fourth substrate terminals 117. A first test line 107 passes through one side of the plurality of fourth substrate terminals 117 in the first direction. A second test line 108 passes between a fourth substrate terminal 117 adjacent to the first test line 107 and the first test line 107, or the second test line 108 passes through the first interval. A fifth test line 111 passes through the first interval.

[0051] For example, the second direction is perpendicular to the first direction.

[0052] For example, if the second test line 108 passes between the fourth substrate terminal 117 adjacent to the first test line 107 and the first test line 107, the fifth test line 111 may pass through any of the first intervals; if the second test line 108 passes through one of the first intervals, the first interval through which the fifth test line 111 passes may be the same as or a different one from the first interval through which the second test line 108 passes.

[0053] For example, the first test line 107 is electrically connected to the end of the first substrate terminal 104 near the fourth substrate terminal 117, the second test line 108 is electrically connected to the end of the second substrate terminal 105 near the fourth substrate terminal 117, and the fifth test line 111 is electrically connected to the end of the third substrate terminal 106 near the fourth substrate terminal 117.

[0054] In the above embodiments, this structure allows for a tight and flexible arrangement of the first substrate terminal 104, the second substrate terminal 105, the third substrate terminal 106, the fourth substrate terminal 117, the first test line 107, the second test line 108, and the fifth test line 111. Even as the distance between the various Panel Pads (including the first substrate terminal 104, the second substrate terminal 105, the third substrate terminal 106, and the fourth substrate terminal 117) gets closer and closer, there is still enough space for the first test line 107, the second test line 108, and the fifth test line 111 to be led out from the bonding area where the Panel Pad is located.

[0055] In some embodiments, the first test line 107 passes through the first interval. If other test lines (such as the second test line 108 and / or the fifth test line 111) also pass through the first interval, the first interval through which the first test line 107 passes may be the same as or different from the first interval through which the other test lines pass.

[0056] In some embodiments, the fifth test line 111 passes between the fourth substrate terminal 117 adjacent to the second test line 108 and the second test line 108.

[0057] In some embodiments, such as Figure 4 and Figure 5 As shown, the bonding impedance detection device 100 further includes a plurality of fifth substrate terminals 118. The plurality of fifth substrate terminals 118 are disposed on the side of the fourth substrate terminal 117 away from the first substrate terminal 104, the second substrate terminal 105, and the third substrate terminal 106 in a second direction. The plurality of fifth substrate terminals 118 are arranged along a first direction, and a second interval is formed between each pair of adjacent fifth substrate terminals 118. A fifth test line 111 passes through the second interval, or the fifth test line 111 passes between the fifth substrate terminal 118 adjacent to the second test line 108 and the second test line 108.

[0058] In some embodiments, the first test line 107 passes through one side of a plurality of fifth substrate terminals 118 in a first direction, or the first test line 107 passes through a second interval.

[0059] In some embodiments, the second test line 108 passes between the fifth substrate terminal 118 adjacent to the first test line 107 and the first test line 107, or the second test line 108 passes through the second interval.

[0060] If at least two of the first test line 107, the second test line 108, and the fifth test line 111 pass through the second interval, then the at least two test lines passing through the second interval may pass through the same or different second intervals.

[0061] Figure 6The diagram shown is a schematic representation of the detection module and output module provided in an exemplary embodiment of this application.

[0062] In some embodiments, such as Figure 6 As shown, the detection module 112 includes a detector 1121 and a processor 1122. Detector 1121 is electrically connected to first test point 113, second test point 114, third test point 115, and fourth test point 116. Detector 1121 is configured to determine the first resistance of a first branch based on the current flowing through the first test point 113 and the fourth test point 116 and the voltage between the first test point 113 and the fourth test point 116. The first branch starts from the first test point 113, passes through the first test line 107, the first substrate terminal 104, the first chip terminal 101, the third chip terminal 103, the third substrate terminal 106, and the fifth test line 111, and ends at the fourth test point 116. Detector 1121 also determines the second resistance of a second branch based on the current flowing through the second test point 114 and the third test point 115 and the voltage between the second test point 114 and the third test point 115. The second branch starts from the second test point 114, passes through the third test line 109 and the fourth test line 110, and ends at the third test point 115. The processor 1122 is communicatively connected to the detector 1121 and is configured to receive a first resistor and a second resistor sent by the detector 1121, and determine the actual bonding impedance based on the first resistor and the second resistor.

[0063] For example, the current flowing through the first test point 113 and the fourth test point 116, and the current flowing through the second test point 114 and the third test point 115, can be provided by the detector 1121, that is, the current flowing through the first test point 113 and the fourth test point 116, and the current flowing through the second test point 114 and the third test point 115 are known quantities. By measuring the voltage between the first test point 113 and the fourth test point 116, and dividing the voltage between the first test point 113 and the fourth test point 116 by the current flowing through the first test point 113 and the fourth test point 116, the first resistance of the first branch can be obtained; by measuring the voltage between the second test point 114 and the third test point 115, and dividing the voltage between the second test point 114 and the third test point 115 by the current flowing through the second test point 114 and the third test point 115, the second resistance of the second branch can be obtained.

[0064] For example, detector 1121 can be a multimeter. By electrically connecting the two probes of the multimeter to the first test point 113 and the fourth test point 116 respectively, the first resistance of the first branch can be determined, and by electrically connecting the two probes of the multimeter to the second test point 114 and the third test point 115 respectively, the second resistance of the second branch can be determined.

[0065] For example, the processor 1122 and the detector 1121 may communicate directly or indirectly through other structures, and the transmission method may include wired transmission and / or wireless transmission.

[0066] In the above embodiments, this structure enables precise measurement of the actual bonding impedance between the driver chip and the display substrate.

[0067] In some embodiments, the processor 1122 is configured to receive a first resistor and a second resistor sent by the detector 1121, then subtract the first resistor and the second resistor to obtain a difference, and finally divide the difference by 2 to obtain the actual binding impedance.

[0068] Specifically, such as Figure 3 As shown in Formulas 2, 3, and 4 below, the impedance R1 of the first branch includes: the resistance R107 of the first test line 107, the bonding impedance R3 between the first chip terminal 101 and the first substrate terminal 104, the bonding impedance R3 between the third chip terminal 103 and the third substrate terminal 106, the resistance R111 of the fifth test line 111, and the resistance of the wire between the first chip terminal 101 and the third chip terminal 103. The wire between the first chip terminal 101 and the third chip terminal 103 has a relatively short length, therefore its resistance is negligible. The impedance R2 of the second branch includes: the resistance R109 of the third test line 109 and the resistance R110 of the fourth test line 110. If the sum of R107 and R111 is made approximately equal to the sum of R109 and R110, then Formula 4 can be obtained according to Formulas 2 and 3.

[0069] Formula 2: R1 = R 107 +2·R3+R 111

[0070] Formula 3: R² = R 109 +R 110

[0071] Formula 4:

[0072] In the above embodiments, this calculation method enables the processor 1122 to accurately calculate the actual bonding impedance between the driver chip and the display substrate.

[0073] In some embodiments, the sum of the resistances of the first test line 107 and the fifth test line 111 is the same as the sum of the resistances of the third test line 109 and the fourth test line 110.

[0074] Specifically, the resistance values ​​of the first test line 107, the fifth test line 111, the third test line 109, and the fourth test line 110 can be adjusted by changing their length, thickness, material, etc.

[0075] In the above embodiments, by making the sum of the resistances of the first test line 107 and the fifth test line 111 the same as the sum of the resistances of the third test line 109 and the fourth test line 110, the difference obtained by subtracting the first resistance and the second resistance can be very close to twice the actual binding impedance, so that the actual binding impedance can be accurately calculated according to the above calculation method.

[0076] In some embodiments, the processor 1122 stores a preset bonding impedance; wherein the processor 1122 is further configured to: compare the preset bonding impedance with the actual bonding impedance to determine a detection result, the detection result being used to indicate whether the actual bonding impedance conforms to the specification.

[0077] The test results may include whether the actual bonding impedance meets the specifications or not.

[0078] For example, a preset binding impedance can be used to indicate the maximum value of the binding impedance in the specification. If the actual binding impedance is less than (or equal to) the preset binding impedance, then the actual binding impedance conforms to the specification.

[0079] In the above embodiments, the processor 1122 can automatically detect whether the actual bonding impedance meets the specifications without manual judgment, saving manpower and achieving high detection efficiency.

[0080] Figure 7 The diagram shown is a structural schematic of the detection module and output module provided in another exemplary embodiment of this application.

[0081] In some embodiments, such as Figure 7 As shown, the detection module 112 further includes an analog-to-digital converter 1123. The analog-to-digital converter 1123 is electrically connected to the detector 1121 and communicatively connected to the processor 1122. The analog-to-digital converter 1123 is configured to receive analog signals of the first resistor and the second resistor output by the detector 1121, convert the analog signals of the first resistor and the second resistor into digital signals of the first resistor and the second resistor, and send the digital signals of the first resistor and the second resistor to the processor 1122.

[0082] For example, the transmission between the analog-to-digital converter 1123 and the processor 1122 can be wired or wireless.

[0083] In the above embodiments, by setting the analog-to-digital converter 1123, the processor 1122 can process the analog signals of the first and second resistors detected by the detector 1121.

[0084] In some embodiments, such as Figure 6 and Figure 7 As shown, the bonding impedance detection device 100 further includes an output module 119. The output module 119 is communicatively connected to the processor 1122 and is configured to receive the actual bonding impedance and / or detection results sent by the processor 1122, and display them based on the actual bonding impedance and / or detection results.

[0085] For example, the transmission method between the output module 119 and the processor 1122 can be wired or wireless.

[0086] For example, the output module 119 may include at least one of a display device, an audio playback device, and an indicator light.

[0087] For example, the display device may be a screen that displays the actual bonding impedance and / or test results, such as displaying the text "Bonding impedance is xxx", or the text "Bonding impedance qualified" or "Bonding impedance unqualified". The audio playback device can play the voice of the actual bonding impedance and / or test results, such as playing the voice of "Bonding impedance is xxx", or the voice of "Bonding impedance qualified" or "Bonding impedance unqualified". The indicator light can display different lighting effects according to the test results, such as displaying green light when the actual bonding impedance meets the specifications and red light when the actual bonding impedance does not meet the specifications.

[0088] In the above embodiments, by setting the output module 119, the actual binding impedance and / or test results can be clearly displayed to the staff.

[0089] In some embodiments, the bonding impedance detection device 100 further includes a control module, which is capable of sending a bonding impedance detection signal to the detection module. After receiving the bonding impedance detection signal, the detection module is capable of determining the actual bonding impedance between the driver chip and the display substrate based on the current data flowing through the first test point, the second test point, the third test point, and the fourth test point.

[0090] Figure 8 The diagram shown is a schematic flowchart of a binding impedance detection method provided in an exemplary embodiment of this application.

[0091] Based on the same concept, such as Figure 8 As shown, this application embodiment also provides a binding impedance detection method, applied to the binding impedance detection device 100 in the above embodiment. The binding impedance detection method includes the following steps 201.

[0092] Step 201: Based on the current flowing through the first test point and the fourth test point, the voltage between the first test point and the fourth test point, the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point, determine the actual bonding impedance between the driver chip and the display substrate.

[0093] In the above embodiments, this bonding impedance detection method can accurately detect the actual bonding impedance between the driver chip and the display substrate, and each of the first substrate terminal, the second substrate terminal, and the third substrate terminal only needs to be connected to a single test line to perform bonding impedance detection. Thus, even as the size of the first substrate terminal, the second substrate terminal, and the third substrate terminal becomes smaller with the development of display technology, bonding impedance detection can still be performed using this structure.

[0094] Figure 9 The diagram shown is a flowchart of a binding impedance detection method provided in another exemplary embodiment of this application.

[0095] In some embodiments, such as Figure 9 As shown, when determining the actual bonding impedance between the driver chip and the display substrate based on the current flowing through the first test point and the fourth test point, the voltage between the first test point and the fourth test point, the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point, the following steps 301 to 303 can be performed.

[0096] Step 301: Based on the current flowing through the first test point and the fourth test point, and the voltage between the first test point and the fourth test point, determine the first resistance of the first branch, wherein the first branch starts from the first test point, passes through the first test line, the first substrate terminal, the first chip terminal, the third chip terminal, the third substrate terminal, the fifth test line, and ends at the fourth test point.

[0097] Step 302: Based on the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point, determine the second resistance of the second branch, wherein the second branch starts from the second test point, passes through the third test line and the fourth test line, and ends at the third test point.

[0098] The execution order of steps 301 and 302 is arbitrary. Step 301 can be executed first, followed by step 302, or step 302 can be executed first, followed by step 301.

[0099] Step 303: Determine the actual binding impedance based on the first resistor and the second resistor.

[0100] In the above embodiments, the actual bonding impedance between the driver chip and the display substrate can be accurately detected in this way.

[0101] Since the description of the embodiment of the binding impedance detection method corresponds to the description of the embodiment of the binding impedance detection device 100, the parts of the binding impedance detection method that are not described in detail can be referred to the previous embodiment of the binding impedance detection device 100.

[0102] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0103] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0104] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0105] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0106] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A binding impedance detection device, characterized in that, include: The first chip terminal is located on the driver chip; A second chip terminal is disposed on the driver chip, and the second chip terminal is electrically connected to the first chip terminal. A third chip terminal is disposed on the driver chip, and the third chip terminal is electrically connected to the second chip terminal; The first substrate terminal is disposed on the display substrate and is bonded to the first chip terminal; The second substrate terminal is disposed on the display substrate and is bonded to the second chip terminal; The third substrate terminal is disposed on the display substrate and is bonded to the third chip terminal; The first test line is electrically connected to the first substrate terminal and electrically connected to the first test point on the flexible circuit board. The second test lead is electrically connected to the second substrate terminal; The third test line is electrically connected to the second test line and to the second test point on the flexible circuit board. The fourth test line is electrically connected to the second test line and to the third test point on the flexible circuit board; The fifth test line is electrically connected to the terminal of the third substrate and to the fourth test point on the flexible circuit board; The detection module, electrically connected to the first test point, the second test point, the third test point, and the fourth test point, is configured to determine the actual bonding impedance between the driver chip and the display substrate based on the current data flowing through the first test point, the second test point, the third test point, and the fourth test point.

2. The binding impedance detection device according to claim 1, characterized in that, The first substrate terminal, the second substrate terminal, and the third substrate terminal are arranged sequentially along a first direction; The bonding impedance detection device further includes: A plurality of fourth substrate terminals are disposed on one side of the first substrate terminal, the second substrate terminal and the third substrate terminal in a second direction, the second direction intersecting the first direction, the plurality of fourth substrate terminals are arranged along the first direction, and a first interval is formed between each two adjacent fourth substrate terminals; Wherein, the first test line passes through one side of the plurality of fourth substrate terminals in the first direction; And, the second test line passes between the fourth substrate terminal adjacent to the first test line and the first test line, or the second test line passes through the first interval; And the fifth test line passes through the first interval.

3. The binding impedance detection device according to claim 1 or 2, characterized in that, The detection module includes: A detector is electrically connected to the first test point, the second test point, the third test point, and the fourth test point. The detector is configured to determine a first resistance of a first branch based on the current flowing through the first test point and the fourth test point and the voltage between the first test point and the fourth test point. The first branch starts from the first test point, passes through the first test line, the first substrate terminal, the first chip terminal, the third chip terminal, the third substrate terminal, and the fifth test line, and ends at the fourth test point. The detector also determines a second resistance of a second branch based on the current flowing through the second test point and the third test point and the voltage between the second test point and the third test point. The second branch starts from the second test point, passes through the third test line and the fourth test line, and ends at the third test point. The processor, which is communicatively connected to the detector, is configured to receive the first resistor and the second resistor sent by the detector, and determine the actual bonding impedance based on the first resistor and the second resistor.

4. The binding impedance detection device according to claim 3, characterized in that, The processor is configured to: Receive the first resistor and the second resistor sent by the detector; Subtract the first resistor from the second resistor to obtain the difference; Divide the difference by 2 to obtain the actual binding impedance.

5. The binding impedance detection device according to claim 4, characterized in that, The sum of the resistances of the first test line and the fifth test line is the same as the sum of the resistances of the third test line and the fourth test line.

6. The binding impedance detection device according to claim 3, characterized in that, The processor stores a preset binding impedance; The processor is further configured as follows: The preset bonding impedance is compared with the actual bonding impedance to determine the test result, which is used to indicate whether the actual bonding impedance meets the specifications.

7. The binding impedance detection device according to claim 3, characterized in that, The detection module also includes: An analog-to-digital converter (ADC) is electrically connected to the detector and communicatively connected to the processor. The ADC is configured to receive analog signals of the first resistor and the second resistor output by the detector, convert the analog signals of the first resistor and the second resistor into digital signals of the first resistor and the second resistor, and send the digital signals of the first resistor and the second resistor to the processor.

8. The binding impedance detection device according to claim 6, characterized in that, Also includes: The output module, which is communicatively connected to the processor, is configured to receive the actual binding impedance and / or the detection result sent by the processor, and to display the actual binding impedance and / or the detection result.

9. A method for detecting bound impedance, characterized in that, The bonding impedance detection method, applied to the bonding impedance detection device according to any one of claims 1 to 8, comprises: The actual bonding impedance between the driver chip and the display substrate is determined based on the current flowing through the first and fourth test points, the voltage between the first and fourth test points, the current flowing through the second and third test points, and the voltage between the second and third test points.

10. The binding impedance detection method according to claim 9, characterized in that, The determination of the actual bonding impedance between the driver chip and the display substrate based on the current flowing through the first and fourth test points, the voltage between the first and fourth test points, the current flowing through the second and third test points, and the voltage between the second and third test points includes: Based on the current flowing through the first test point and the fourth test point, and the voltage between the first test point and the fourth test point, the first resistance of the first branch is determined, wherein the first branch starts from the first test point, passes through the first test line, the first substrate terminal, the first chip terminal, the third chip terminal, the third substrate terminal, the fifth test line, and ends at the fourth test point; The second resistance of the second branch is determined based on the current flowing through the second test point and the third test point, and the voltage between the second test point and the third test point. The second branch starts from the second test point, passes through the third test line and the fourth test line, and ends at the third test point. The actual bonding impedance is determined based on the first resistor and the second resistor.

Images