A method for testing the thermal properties of complex three-dimensional micro / nano structures in chips

Abstract

This invention discloses a method for testing the thermal properties of complex three-dimensional micro / nano structures in chips. This method combines FIB (Fiber Optic Injection) step-by-step sample preparation with point-by-point thermal reflection scanning technology. First, FIB technology is used to cut the chip sample into a step-like structure, exposing its internal fine structure layer by layer to ensure that each functional layer is accurately located. Then, pump-probe thermal reflection techniques such as TDTR (Diverter-Temperature Reflectance) are used to scan each step surface point by point, obtaining multi-dimensional parameters such as thermal conductivity and interlayer interface thermal resistance. Furthermore, three-dimensional spatial coordinates are integrated to construct a three-dimensional thermal property distribution map of the chip's internal structure. This method achieves, for the first time, a quantitative mapping of heat transfer characteristics from a single-layer local to a three-dimensional global domain at the nanoscale. It not only fills the gap in thermal property data for three-dimensional stacked chip micro / nano structures but also significantly improves the accuracy of thermal simulation models. It provides high-confidence experimental support for thermal management optimization, interface material design, and reliability assessment of high-density integrated circuits, and has significant scientific and engineering application value.

Description

Technical Field

[0001] This invention relates to thermal property testing technology for micro- and nanostructures, and more specifically to a method for testing the thermal properties of fine micro- and nanostructures inside a three-dimensional stacked chip. Background Technology

[0002] Currently, thermophysical property testing techniques for micro- and nanostructures such as chips are crucial for ensuring the performance and reliability of electronic devices. The mainstream thermophysical property testing techniques mainly include non-contact optical methods such as TDTR (Time-domain Thermoreflectance), FDTR (Frequency Domain Thermal Reflectance), TTR (Transient Thermoreflectance), and SSTR (Steady-state Thermoreflectance). TDTR utilizes the pump-probe mechanism of ultrashort pulse lasers to analyze the transient signal of sample surface reflectivity decaying with temperature, thereby retrieving the material's thermal conductivity, thermal capacity, and interfacial thermal resistance. It is particularly suitable for high-precision characterization of nanofilms and two-dimensional materials. FDTR, on the other hand, heats the sample with sinusoidally modulated lasers and combines frequency domain phase and amplitude signals to analyze thermophysical parameters, making it adept at thermal analysis of multilayer heterostructures and anisotropic materials. TTR broadly encompasses transient heating-probe methods (such as pulsed laser excitation), which calculate the thermal diffusivity through temperature response curves in the nanosecond to millisecond range, and is mostly used for testing bulk materials and thick films; SSTR, on the other hand, is based on the temperature distribution and heat flow relationship under steady-state thermal equilibrium conditions, and calculates thermal conductivity through steady-state heat conduction equations. The equipment is simple but is only suitable for measuring the macroscopic thermal properties of homogeneous materials.

[0003] Existing thermophysical property testing techniques have the following drawbacks:

[0004] (1) Insufficient spatial resolution severely restricts its application in measuring the thermal properties of fine structures inside three-dimensional stacked chips. The vertical spatial resolution of FDTR depends on the thermal wave penetration depth (hundreds of nanometers to micrometers), making it difficult to resolve the thermal resistance distribution of complex interconnect layers, TSVs (Through Silicon Vias), or bonding interfaces at the submicron scale; TTR causes signal ambiguity in the lateral and longitudinal directions due to transient thermal diffusion, making it impossible to locate the local thermal characteristics of nanoscale transistor nodes, and the thermal coupling effect of multi-layer stacking will mask the parameters of a single layer; SSTR has even lower steady-state thermal field resolution (millimeter level), and can only provide macroscopic average thermal conductivity, making it completely unable to distinguish the thermal resistance differences of heterogeneous interfaces inside three-dimensional chips.

[0005] (2) It relies on surface or near-surface thermal signal detection and lacks three-dimensional tomography capability. Embedded structures (such as heat dissipation channels and internal interconnects) will block the heat wave propagation path. Existing models are mostly based on one-dimensional or two-dimensional heat conduction assumptions, which make it difficult to analyze the complex three-dimensional thermal coupling effect, thus limiting their applicability in advanced packaging thermal management.

[0006] In summary, existing technologies have significant limitations in high spatial resolution thermal property characterization of three-dimensional stacked chips. These limitations result in a large gap in thermal property data for structures such as multilayer interconnects, TSVs, and bonding interfaces of three-dimensional stacked chips, necessitating a high-precision and high-efficiency sample preparation and characterization method to address these issues. Summary of the Invention

[0007] The purpose of this invention is to achieve high-precision, high-resolution measurement of the thermal properties of each layer and location inside a three-dimensional stacked chip by innovatively combining FIB (Focused Ion Beam) sample preparation technology with thermal property characterization technology such as TDTR.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A method for testing the thermal properties of complex three-dimensional micro / nano structures in chips is proposed. First, the chip sample is cut into a stepped structure using FIB technology to expose its internal fine structure (such as interconnects between layers, through-silicon vias, bonding interfaces, etc.) layer by layer, ensuring that each layer can be accurately located. Then, pump-probe thermal reflection technology such as TDTR is used to scan each exposed layer point by point, and thermal properties such as local thermal conductivity and thermal capacity are obtained by measuring the thermal reflection signal.

[0010] The technical solution of this invention utilizes the high spatial resolution (planar resolution consistent with the measurement spot, reaching submicron level, and longitudinal resolution reaching nanometer level) and direct measurement capability of material thermal properties of pump-probe thermal reflection technologies such as TDTR. On the other hand, the high precision characteristics of FIB cutting avoid the structural damage that may be caused by CMP (Chemical Mechanical Polishing) and the insufficient precision of manual polishing. It provides an efficient and non-destructive solution for the thermal property characterization of three-dimensional stacked chips, fills the gap in thermal property data of interconnect layers, TSVs and other structures, and provides important technical support for chip thermal management optimization and reliability assessment.

[0011] The technical solution of the present invention can be divided into the following three steps in its specific implementation:

[0012] 1) Pre-processing of 3D stacked chips by dicing. Mechanical dicing is performed along the chip stacking direction to obtain samples with small cross-sectional areas and smooth surfaces, ensuring the test area is located at the edge of the dicing to reduce the time required for subsequent FIB milling to expose the effective portion. This step aims to provide a structurally stable substrate for subsequent processing while avoiding signal interference caused by rough cross-sections or excessively large dimensions. The exposed cross-section after mechanical dicing is perpendicular to the chip plane, and its size is determined according to the requirements of the FIB equipment, typically with a side length of several millimeters.

[0013] 2) Fabrication of FIB three-dimensional stepped structures involves milling the diced sample using FIB technology. By precisely adjusting the spatial orientation of the sample stage, the interface or feature structure to be measured is aligned parallel to the incident direction of the ion beam. Combined with SEM (Scanning Electron Microscope) observation of the sample surface morphology, the beam current is dynamically controlled, and surface material is removed layer by layer to form a high-precision stepped profile. This process, through nanoscale thickness control and directional etching, achieves layer-by-layer non-destructive exposure of each functional layer (such as interconnect layers, dielectric layers, and interface transition regions) within the three-dimensional stacked chip, significantly avoiding material damage or structural deformation problems caused by traditional polishing or mechanical grinding.

[0014] This step involves preparing highly differentiated step structures layer by layer through FIB milling. Preferably, the area of ​​each step is determined by the area to be detected, but it is at least larger than the laser spot size of the thermal reflection technology. The larger the area, the more FIB sample preparation time is required. The height of each step is strictly controlled according to the actual thickness of each functional layer, thereby exposing the structure of each layer.

[0015] Preferably, a combined strategy of high-current rapid roughing and low-current precision milling is adopted when milling each step in FIB. Specifically, a high-current (>6nA) is used for roughing first, and then a low-current (1-6nA) is used for fine milling once the target functional layer is initially exposed, until the target functional layer is fully exposed and the surface roughness reaches Ra<5nm. Further, after the step-by-step FIB milling is completed, an ultra-low current (≤1nA) is used to polish the step surface to eliminate redeposited deposits and microscopic defects. Finally, scanning electron microscopy and energy dispersive spectroscopy are used to verify the interface morphology and chemical composition, ensuring no ion contamination or structural damage.

[0016] 3) Three-dimensional thermophysical characterization: Pump-probe thermal reflection techniques (including TDTR, FDTR, TTR, SSTR, etc.) were used to measure the thermophysical properties of the stepped structure. A non-contact pump-probe optical path was used to scan each step surface point-by-point with sub-micron spatial resolution. By capturing the dynamic decay signal of thermally induced reflectivity, thermophysical data such as thermal conductivity and interlayer thermal resistance of each layer were extracted. Furthermore, the three-dimensional spatial coordinates and thermophysical data were integrated to construct a three-dimensional distribution model of the internal thermophysical parameters of the chip, revealing the coupling influence mechanism of material heterogeneity, interface properties, and geometry on thermal transport behavior at the micro- and nano-scale.

[0017] Furthermore, before scanning, a thin layer of metal is deposited on the surface of the stepped structure as a transducer. This metal layer has high thermal reflectivity at the thermal reflection detection laser wavelength, thereby achieving a higher signal-to-noise ratio. The selected metal is matched with the detection laser wavelength. For lasers of different wavelengths, corresponding metals such as aluminum, gold, and titanium can be selected. The thickness of the metal layer is preferably 70-100 nanometers.

[0018] This step involves fixing the sample to be tested on a precision displacement stage, preferably a two-dimensional precision linear displacement platform with a nanometer-level moving step size, which can be used for scanning path planning in either line-by-line scanning or region-first mode.

[0019] This invention fills the gap in micro- and nanoscale thermal property data for three-dimensional stacked chips by establishing a technical chain of "precision structure fabrication - high-resolution thermal property characterization - multi-parameter three-dimensional reconstruction", laying a methodological foundation for the thermal reliability design and performance improvement of chips.

[0020] The core technology of step 2) above lies in achieving non-destructive exposure and high-precision morphology control of the internal structure of a three-dimensional stacked chip through the lateral bombardment strategy of FIB. Specifically, by rotating the sample, the interface to be tested on the chip is adjusted to be strictly parallel to the incident direction of the ion beam, thereby significantly improving the etching smoothness and processing efficiency. Based on this, a staged beam current control process is adopted: first, a high beam current is used to quickly remove redundant surface material, and then a low beam current is switched for fine trimming, forming a stepped profile layer by layer. This method avoids structural damage caused by traditional mechanical or chemical polishing through ion beam direction optimization and dynamic parameter matching, while ensuring the integrity of the interface morphology and surface smoothness of each layer, providing a high-fidelity test substrate for subsequent thermophysical characterization.

[0021] Step 3) above utilizes thermal reflection technology to scan thermal properties point-by-point. The stepped sample structure design facilitates point-by-point scanning analysis, enabling simultaneous determination of the thermal conductivity of multilayer interconnected structures. During the experiment, a two-dimensional high-precision linear motion platform is used to drive the sample; this device possesses nanometer-level stepping accuracy. Through a computer program control system, the step distance, dwell time, scanning range, and detection path mode can be parameterized, ultimately achieving sub-micron spatial resolution construction of sample surface thermal property maps.

[0022] The beneficial effects of this invention are:

[0023] This invention achieves a significant breakthrough in the nanoscale thermal property characterization of three-dimensional stacked chips by innovatively combining FIB step-by-step sample preparation and thermal reflection point-by-point scanning technology. Specifically, a milling process parallel to the ion beam on the test surface exposes interconnect layers, TSVs, and other micro / nano structures layer by layer with a ±10nm precision, avoiding structural damage caused by traditional mechanical grinding or chemical polishing. This provides a geometrically complete and surface-clean test substrate for analyzing three-dimensional heat transfer characteristics. The thermal reflection technology scans each step surface point by point with sub-micron spatial resolution. By fitting data from picosecond-time-resolved thermal reflection signals, multi-dimensional parameters such as thermal conductivity and interlayer interface thermal resistance are simultaneously obtained, and a three-dimensional thermal property distribution map is constructed. This method achieves, for the first time, a quantitative mapping of heat transfer characteristics from a single-layer local to a three-dimensional global domain at the nanoscale. It not only fills the gap in thermal property data for micro / nano structures of three-dimensional stacked chips but also significantly improves the accuracy of thermal simulation models. This provides high-confidence experimental support for thermal management optimization, interface material design, and reliability assessment of high-density integrated circuits, and has significant scientific and engineering application value.

[0024] This invention addresses the complex heat transfer behavior of micro / nano structures such as interconnect layers, TSVs, and bonding interfaces in three-dimensional stacked chips. Through layer-by-layer exposure and high-resolution thermophysical property measurement, it achieves, for the first time, the precise acquisition of three-dimensional thermal parameters from local to global perspectives. For example, it can quantitatively analyze key parameters such as the thermal resistance at the interface between the TSV and the dielectric layer, and the anisotropic thermal conductivity of the metal interconnect layer, filling the data gap caused by neglecting micro / nano scale effects in traditional bulk material measurements or macroscopic simulations. These measured data can be directly used to correct material properties and boundary conditions (such as interface thermal resistance) in multiphysics simulation models, significantly improving the accuracy of chip temperature field prediction and guiding the optimization of heat dissipation structures and material selection.

[0025] In the field of advanced packaging and integration technology, the method of this invention provides a key tool for assessing the thermal reliability of high-density interconnects and heterogeneous integrated chips (such as 3D ICs and Chiplet). By using three-dimensional thermal property distribution maps, bottleneck regions in the heat flow path (such as high thermal resistance interfaces or low thermal conductivity dielectric layers) can be located, allowing for targeted optimization of TSV filling materials, interface processes, or heat dissipation microstructure design. This reduces localized heat accumulation and improves the long-term stability of the chip. Furthermore, the measured data can be used to establish physical models of heat transfer at the micro- and nano-scale, promoting the development of novel thermally conductive materials and interface engineering technologies.

[0026] In summary, this invention not only provides high-precision experimental data support for chip thermal management, but also accelerates the thermal design iteration in cutting-edge fields such as high-performance computing and artificial intelligence chips through a closed loop of "measurement-simulation-optimization-measurement". It has important engineering significance for breaking through the chip power consumption wall and ensuring the reliability of next-generation electronic devices. Attached Figure Description

[0027] Figure 1 A schematic diagram of the chip sample dicing operation.

[0028] Figure 2 A schematic diagram showing the sample placement direction, ion beam incident direction, and propulsion direction during FIB step sample preparation.

[0029] Figure 3 The example shows a local FIB sample preparation area observed by SEM, which displays a three-step region from left to right.

[0030] Figure 4 A schematic diagram of TDTR point-by-point scanning of a stepped sample. Detailed Implementation

[0031] For ease of understanding, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, the following embodiments are merely individual examples of the present invention and do not represent the scope of protection limited by the present invention. The scope of protection of the present invention shall be defined by the appended claims.

[0032] Step 1: Sample Preparation

[0033] Taking the thermal property analysis of the interconnect layer of a commercial 28nm analog chip as an example, the total thickness of the ten interconnect layers (M1 to M10) is 10μm, the active layer and substrate thickness is approximately 700μm, and the total height is approximately 0.7mm. Controlling the cross-sectional area of ​​the dicing to below 2mm × 1mm is beneficial for stabilizing the sample side on the FIB sample stage. The dicing direction is from top to bottom along the stacking direction. During the diamond dicing process, keep it as vertical as possible and be careful not to scratch the sample surface. Due to the limited bombardment distance of the high-energy Ga ion beam, it is necessary to ensure that the test position is close to the dicing edge, because the closer to the high-energy ion beam emission point, the better the sample cutting quality. The main purpose of dicing is to maintain sample stability when fixing the sample side down on the sample stage and to reduce the height of the sample on the sample stage (i.e., the sample width during dicing). The chip dicing operation is as follows: Figure 1 As shown, the sample obtained from the cleavage is a cuboid, fixed on the FIB sample stage with its side facing down, and has a height of 0.5 mm.

[0034] Step 2: FIB Step Sample Preparation

[0035] The FIB milling process of this invention is implemented as follows: First, the three-dimensional stacked chip sample is rotated 90° so that its side faces down and fixed on the FIB sample stage. The area to be tested is accurately located using SEM, and the tilt angle of the sample stage is adjusted so that the ion beam incident direction is strictly parallel to the plane of the interconnect layer. Then, the working beam voltage is set to 30kV, and a large beam current of 9nA is used for rough milling to quickly remove the surface covering material. The milling depth is monitored in real time using SEM, and rough milling is terminated when the outline of the interconnect layer is initially exposed. After that, the beam current is switched to 0.79nA for fine milling, removing residual material layer by layer until the target interconnect layer is completely exposed and the surface roughness reaches Ra<5nm. The fine milling time for the top layer thick interconnect (2-3μm) is about 10-20 minutes, while the time for the bottom layer ultrathin interconnect (175nm) is shortened to 5-8 minutes. The exposed area of ​​the test surface of each layer is about 40μm×40μm to balance efficiency and processing accuracy.

[0036] After single-layer exposure, the ion beam is moved parallel to the shallow groove formed by the first ion beam bombardment, and the roughing and fine grinding processes are repeated. This process is repeated layer by layer to prepare highly differentiated step structures. The area of ​​each step is maintained at 40μm×40μm, and the step height is strictly controlled according to the actual thickness of the interconnect layer (e.g., 2-3μm for the top layer and 175nm for the bottom layer). The smoothness of the transition region between adjacent steps is optimized by preset ion beam residence time and scanning path to avoid material residue or over-etching. After milling, the step surface is finely polished using an ultra-low beam current to eliminate redeposited materials and micro-defects. Finally, the interface morphology and chemical composition are verified by high-resolution SEM and energy dispersive spectroscopy to ensure no ion contamination or structural damage.

[0037] This process achieves nanometer-level thickness control and interface integrity assurance through a combination of high-current rapid roughing and low-current precision grinding, significantly reducing the risk of interlayer structural collapse caused by traditional mechanical grinding. The stepped, layer-by-layer milling design can adapt to interconnect layers of different heights, supporting spatial analysis of thermal property parameters for complex 3D stacked chip structures. This provides structurally complete and surface-clean test samples for subsequent high-precision measurement of thermal conductivity and interface thermal resistance using TDTR technology, powerfully promoting the optimization of chip thermal management performance. The FIB stepped sample preparation principle is as follows: Figure 2 As shown. Figure 3 The three steps milled by FIB are shown, exposing three different interconnect layer structures.

[0038] Step 3: TDTR point-by-point scanning thermophysical property test

[0039] The basic principle of TDTR is to measure thermal properties, known as thermal reflectivity, by measuring the change in reflectivity with temperature. The sample is typically coated with a thin metal film as a transducer, usually aluminum. An approximately 80nm thick metal film is deposited on the sample surface using electron beam evaporation. The thickness of this metal film can be precisely measured using the TDTR's additional picosecond ultrasound technology (the choice of metal depends on matching the probe laser wavelength to achieve a higher signal-to-noise ratio for easier detection; for an 800nm ​​probe laser, aluminum can be chosen, while for a 488nm probe laser, gold or similar metals are required). The basic setup of TDTR involves splitting the femtosecond laser source into a pump beam and a probe beam. The pump beam heats the sample, while the probe beam detects the change in reflectivity resulting from the pump laser heating. The reflected probe beam is collected by a photodiode detector, converting the optical signal into an electrical signal. By analyzing the reflectivity change curve and fitting the data using a thermal conduction model, parameters such as the thermal conductivity and interfacial thermal conductivity at sample points can be extracted. Since data fitting requires parameters such as the thickness and heat capacity of each layer of the sample, a single-point TDTR needs to be tested before point-by-point scanning to evaluate the reasonableness of the fit.

[0040] After completing multiple single-point tests and verifications, point-by-point scanning is performed. The stepped sample preparation facilitates point-by-point scanning to simultaneously characterize the thermal conductivity of different interconnect layers. Specifically, a two-dimensional precision linear displacement platform (TDTR) is used to move the sample, enabling nanometer-level step-by-step movement. The platform is controlled by software, allowing setting parameters such as displacement step size (minimum accuracy 6 nm), displacement dwell time (sampling time 0.3 s), total displacement distance (maximum range ±13 mm on both horizontal and vertical axes), and measurement sequence (scanning each row from left to right). This achieves high spatial resolution precision scanning of the sample surface, ultimately constructing a three-dimensional thermophysical property map of the sample. The principle of TDTR combined with point-by-point scanning for thermophysical property testing is as follows: Figure 4 As shown.

Claims

1. A method for testing the thermal properties of complex three-dimensional micro / nano structures of chips, comprising the following steps: 1) Mechanically cleave along the chip stacking direction to obtain cleaved samples with a flat cross-section perpendicular to the chip plane; 2) Rotate the diced sample 90° so that its side faces down and fix it on the FIB sample stage. Use FIB to mill the sample, in which each functional layer of the sample is parallel to the incident direction of the ion beam. Combined with scanning electron microscopy observation, dynamically control the FIB beam current, remove the surface covering material layer by layer to form a stepped profile, so that each functional layer inside the three-dimensional stacked chip is exposed layer by layer without damage. 3) The pump-probe thermal reflection technique is used to scan each step surface of the stepped structure obtained in step 2) point by point to obtain the thermal property data of each layer of the structure.

2. The test method as described in claim 1, characterized in that, Step 1) When splitting the sample, make sure the area to be tested is close to the edge of the split.

3. The test method as described in claim 1, characterized in that, In step 2), a large beam current is first used for roughing each layer of the structure. When the target functional layer is initially exposed, a low beam current is used for fine milling until the target functional layer is fully exposed and the surface roughness reaches Ra<5nm.

4. The test method as described in claim 3, characterized in that, After step 2) step-by-step FIB milling is completed, the step surface is finely polished with ultra-low beam current to eliminate redeposit and micro-defects. Finally, the interface morphology and chemical composition are verified by scanning electron microscopy and energy dispersive spectroscopy to ensure that there is no ion contamination or structural damage.

5. The test method as described in claim 1, characterized in that, The pump-probe thermal reflection technology mentioned in step 3) is selected from TDTR, FDTR, TTR, and SSTR.

6. The test method as described in claim 1, characterized in that, Step 3) Before scanning, a thin layer of metal is deposited on the surface of the stepped structure. The metal has a high thermal reflectivity at the thermal reflection detection laser wavelength to improve the signal-to-noise ratio.

7. The test method as described in claim 6, characterized in that, The metals used for plating are selected from aluminum, gold, and titanium, with a thickness of 70-100 nanometers.

8. The test method as described in claim 1, characterized in that, Step 3) Fix the sample to be tested on a two-dimensional precision linear displacement platform with a nanometer-scale moving step.

9. The test method as described in claim 1, characterized in that, Step 3) After obtaining the thermal property data of each layer, integrate them with the three-dimensional spatial coordinates to construct a three-dimensional distribution model of the thermal property parameters inside the chip.

10. The test method as described in claim 9, characterized in that, The thermophysical data include the thermal conductivity of each layer and the interlayer thermal resistance.

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