Test circuit and electronic device comprising same and test method

Abstract

This application relates to test circuits, electronic devices incorporating the same, and test methods. A test circuit includes: a first circuit comprising: a plurality of test input terminals configured to receive a plurality of comparator test signals, wherein each comparator test signal is associated with a threshold voltage of a corresponding test comparator; and a test output terminal, wherein the first circuit is configured to generate a total combined test signal at the test output terminal in response to the plurality of comparator test signals.

Description

Technical Field

[0001] This application generally relates to semiconductor devices, and more specifically to circuits, apparatus, and methods for testing. Background Technology

[0002] Design for Testability (DFT) is a crucial step in the design process of semiconductor devices (such as integrated circuit chips). DFT can include tests targeting various thresholds. Typically, a specific DFT needs to be built for each threshold. In other words, a separate test environment is set up for each threshold to obtain test data specific to that threshold. However, this approach can be inefficient when dealing with a large number of threshold tests. Therefore, a more efficient threshold testing method based on DFT is needed. Summary of the Invention

[0003] According to one aspect of this application, a test circuit is provided, comprising: a first circuit including: a plurality of test input terminals configured to receive a plurality of comparator test signals, wherein each comparator test signal is associated with a threshold voltage of a corresponding test comparator; and a test output terminal, wherein the first circuit is configured to generate a total combined test signal at the test output terminal in response to the plurality of comparator test signals.

[0004] According to another aspect of this application, an electronic device is provided, comprising: a plurality of test comparators, wherein each test comparator is configured to generate a corresponding comparator test signal in response to a test excitation signal, the comparator test signal being associated with a threshold voltage of the test comparator; and a test circuit configured to be coupled to the plurality of test comparators and including a first circuit, the first circuit including: a plurality of test input terminals configured to receive a plurality of comparator test signals from the plurality of test comparators; and a test output terminal, wherein the first circuit is configured to generate a total combined test signal at the test output terminal in response to the plurality of comparator test signals.

[0005] According to another aspect of this application, a testing method is provided, comprising: providing the same test excitation signal to a plurality of test comparators to generate a plurality of comparator test signals, wherein each comparator test signal is associated with a threshold voltage of a corresponding test comparator; generating a total combined test signal in response to the plurality of comparator test signals; and detecting the total combined test signal.

[0006] Details of one or more embodiments of this disclosure are set forth in the following figures and description. Other features, objectives, and advantages will become apparent from the description, the figures, and the claims. Attached Figure Description

[0007] The following figures are mentioned and included in the disclosure in this specification:

[0008] Figure 1 This is a schematic diagram of a test system according to some embodiments of this application.

[0009] Figure 2 This is a schematic diagram of a comparator module according to some embodiments of this application.

[0010] Figures 3A-3C This is a schematic diagram of the first circuit in the test circuit module according to some embodiments of this application.

[0011] Figure 4 This is a schematic diagram of the second circuit in a test circuit module according to some embodiments of this application.

[0012] Figure 5 These are signal waveform diagrams at some nodes in a test system according to some embodiments of this application.

[0013] Figure 6 This is a flowchart of a test method according to some embodiments of this application.

[0014] By convention, the various features illustrated in the figures may not be drawn to scale. Therefore, for clarity, the dimensions of various features may be arbitrarily enlarged or reduced. The shapes of the components illustrated are merely exemplary and do not limit the actual shapes of the components. Furthermore, for clarity, the embodiments illustrated may be simplified. Therefore, the figures may not depict all components of a given device or apparatus. Finally, the same reference numerals may be used throughout the specification and figures to denote the same features. Detailed Implementation

[0015] To better understand the spirit of this application, the following description, in conjunction with some embodiments of this application, will provide further details.

[0016] The terms "in one embodiment" or "according to one embodiment" as used in this specification do not necessarily refer to the same specific embodiment, and the terms "in other (some / some) embodiments" or "according to other (some / some) embodiments" as used in this specification do not necessarily refer to different specific embodiments. The purpose is to, for example, include combinations of all or some of the exemplary specific embodiments. The terms "first," "second," "third," etc., used herein are intended only to distinguish the described objects for the reader's convenience, and these terms are not intended to limit the order or weight of the described objects.

[0017] The terms "connection" or "coupling" as used herein should be understood to encompass both "direct connection" and "connection via one or more intermediate components." The term "coupleable" as used herein should be understood as components being coupled together in some form to achieve certain functions, but not considered coupled when these functions are not being performed. The term "configurable" as used herein should be understood as components being configured to perform corresponding functions when enabled or powered on, and not configured when disabled or not powered on. The names of various components and parts used in this specification are for illustrative purposes only and are not intended to be limiting; different manufacturers may use different names to refer to components and parts with the same function.

[0018] Various embodiments of this application are discussed in detail below. Although specific embodiments are discussed, it should be understood that these embodiments are for illustrative purposes only. Those skilled in the art will recognize that other components and configurations can be used without departing from the spirit and scope of this application. Implementations of this application need not include all components or steps in the embodiments described in the specification, and the execution order of the steps can be adjusted according to the actual application.

[0019] Furthermore, for clarity, detailed descriptions of certain features will not be provided where they are obvious to those skilled in the art, so as not to obscure the description of embodiments of this application. Therefore, the following detailed description should not be construed as limiting.

[0020] As a crucial step in integrated circuit design, DFT can include various threshold tests for the corresponding circuit components. For example, for battery or power management circuits, modules, or chips, threshold tests can include tests for short circuit, recharge, overvoltage protection (OVP) thresholds, etc.

[0021] Threshold testing can be implemented by configuring a test comparator. For example, one input of the test comparator can be coupled to a test node (e.g., an internal node reserved in the circuit), and the other input can receive a test stimulus signal (e.g., a signal from an arbitrary waveform generator (AWG)). By setting an appropriate test stimulus signal, a test signal reflecting the voltage at the test node (also called the "threshold voltage") can be detected at the output of the test comparator. For example, the test stimulus signal can be a ramp voltage signal; when the test stimulus signal rises from a lower voltage to the threshold voltage, the test signal output by the test comparator flips; then the test stimulus signal voltage continues to rise, reaches its maximum value, and begins to fall, during which time the test signal state remains unchanged until the test stimulus signal falls to the threshold voltage, at which point the test signal flips again. Information about the threshold voltage can be obtained by detecting the flipping of the test signal. The test signal output by the test comparator can be digitized for subsequent analysis.

[0022] Typically, threshold testing requires setting separate test stimulus signals and digitization parameters for each test, which makes threshold testing time-consuming, especially when dealing with dozens or even hundreds of thresholds to be tested. To address this, this application provides a solution that can shorten threshold testing time and improve threshold testing efficiency.

[0023] Figure 1 A test system 100 according to some embodiments of this application is illustrated. When enabled or powered on, the test system 100 can be configured to perform various threshold tests. The test system 100 may include a comparator module 110 and a test circuit module 112. In some embodiments, the comparator module 110 and the test circuit module 112 are arranged in the same electronic device. In other embodiments, the comparator module 110 and the test circuit module 112 are arranged in different electronic devices.

[0024] Comparator module 110 may include multiple comparators (also referred to as test comparators) 111-1, ..., 111-N. One input terminal (e.g., positive input terminal) of each comparator may be configured to receive a test excitation signal, and the other input terminal (e.g., negative input terminal) may be coupled to a corresponding test node to receive the corresponding voltage under test (e.g., reference voltage V). REF Based on the test excitation signal and the voltage to be measured, each comparator can be configured to generate a corresponding comparator test signal at its output terminal. Each comparator test signal is associated with the threshold voltage of the corresponding comparator, and the threshold voltage of each comparator is associated with the voltage to be measured it receives. According to some embodiments of this application, comparators 111-1, ..., 111-N can be configured to receive the same test excitation signal, such as a signal from an AWG. In some embodiments of this application, the test excitation signal includes a ramp voltage signal. The AWG can be an external device or a built-in device.

[0025] According to some embodiments of this application, the test circuit module 112 may include a first circuit 120. The first circuit 120 includes a plurality of test input terminals 121-1, ..., 121-N, which are configured to receive a plurality of comparator test signals from the comparator module 110. The first circuit 120 also includes a test output terminal 122. In some embodiments of this application, the first circuit 120 may be configured to generate a total combined test signal at the test output terminal 122 in response to the received plurality of comparator test signals.

[0026] The total combined test signal generated by the first circuit 120 may contain information from the received multiple comparator test signals. For example, the first circuit 120 may be configured to toggle the total combined test signal in response to each of the multiple comparator test signals, i.e., the total combined test signal may toggle once in response to each of the multiple comparator test signals. Therefore, by detecting the total combined test signal, information about multiple voltages under test can be obtained simultaneously by setting only one test excitation signal and digitization parameters, thereby shortening the threshold test time and improving the threshold test efficiency.

[0027] The overall combined test signal can be further transmitted to a display or analysis component for detection. In some embodiments, the display or analysis component may be part of the test system 100. In other embodiments, the display or analysis component may be located outside the test system 100.

[0028] According to some embodiments of this application, the test circuit module 112 may optionally include a second circuit 130. The second circuit 130 includes a plurality of check input terminals 131-1, ..., 131-N, which are configured to receive a plurality of comparator test signals from the comparator module 110. The second circuit 130 also includes selection input terminals 132-1, ..., 132-M, which are configured to receive selection input signals. The second circuit 130 also includes a check output terminal 133. In some embodiments of this application, the second circuit 130 may be configured to selectively output one of the received plurality of comparator test signals at the check output terminal 133 in response to a received selection input signal. In some embodiments, the number of selection input terminals (i.e., the number of bits of the selection input signal) may be determined based on the number of comparator test signals received at the check input terminals. For example, assuming the number of comparator test signals is n, the number of selection input terminals m may be...

[0029] The output signal of the second circuit 130 can be further transmitted to a display or analysis component to check whether the corresponding comparator is functioning correctly. For example, it can be checked whether the output comparator test signal flips as the test stimulus signal rises from a lower voltage to a higher voltage. In some embodiments, the display or analysis component may be part of the test system 100. In other embodiments, the display or analysis component may be located outside the test system 100. The above checks can be performed before the total combined test signal is generated by the first circuit 120 (or before the total combined test signal is detected), thereby avoiding the inability to generate the correct total combined test signal due to a malfunctioning comparator. Therefore, the second circuit 130 can further avoid repeated testing due to a malfunctioning comparator, thereby indirectly improving the overall efficiency of the threshold testing process.

[0030] although Figure 1 Only one comparator module 110 and one test circuit module 112 are shown in the diagram. It should be understood that the test system 100 may include multiple comparator modules 110 and / or multiple test circuit modules 112. Each comparator module 110 may be configured to be coupled to one of the multiple test circuit modules 112. The number of comparators included in each comparator module may be different. Each test circuit module 112 may be dedicated to a particular comparator module 110 or shared by a group of comparator modules 110.

[0031] although Figure 1 Not shown, the test system 100 may further include a control module and a storage module. The control module may be communicatively coupled to each of the comparator module 110 and the test circuit module 112. The control module may include a storage device and a processor. The storage device may store various setting parameters, thereby causing the control module to perform various operations on the comparator module 110 and the test circuit module 112. In some embodiments, the storage device may store setting parameters for test stimulus signals and digitized parameters. In some embodiments, the storage device may include registers.

[0032] The storage module of the test system 100 is communicatively coupled to the control module. The storage module is communicatively coupled to each of the comparator module 110 and the test circuit module 112. The storage module is capable of storing the outputs of the comparator module 110 and / or the test circuit module 112.

[0033] The storage module of the test system 100 may include a non-transitory computer-readable storage medium. The non-transitory computer-readable medium may include (but is not limited to) solid-state memory, optical media, and magnetic media. In other embodiments, the non-transitory computer-readable medium may include read-only memory (“ROM”), random access memory (“RAM”), EPROM, EEPROM, flash memory components, etc. Instructions stored in the non-transitory computer-readable medium can be invoked and executed by the processor of the control module, thereby causing the processor to perform various controls and operations on the comparator module 110 and the test circuit module 112.

[0034] According to some embodiments of this application, the various modules in the test system 100 can be implemented by hardware circuitry, by software, or by a combination of hardware and software.

[0035] Figure 2 A comparator module 210 according to some embodiments of this application is shown. The comparator module 210 may be... Figure 1 One embodiment of comparator module 210. In this embodiment, comparator module 210 includes comparators 201-204. The positive input terminal of comparator 201 is configured to receive a test excitation signal S, and the negative input terminal of comparator 201 is configured to receive a reference voltage V. REF1 Based on the test excitation signal S and the reference voltage V REF1 Comparator 201 can be configured to generate a comparator test signal COMP_OUT1. The positive input terminal of comparator 202 can be configured to receive a test excitation signal S, and the negative input terminal of comparator 202 can be configured to receive a reference voltage V. REF2 Based on the test excitation signal S and the reference voltage V REF2 Comparator 202 can be configured to generate a comparator test signal COMP_OUT2. The positive input terminal of comparator 203 can be configured to receive a test excitation signal S, and the negative input terminal of comparator 203 can be configured to receive a reference voltage V. REF3 Based on the test excitation signal S and the reference voltage V REF3 Comparator 203 can be configured to generate a comparator test signal COMP_OUT3. The positive input terminal of comparator 204 can be configured to receive a test excitation signal S, and the negative input terminal of comparator 204 can be configured to receive a reference voltage V. REF4 Based on the test excitation signal S and the reference voltage V REF4 Comparator 204 can be configured to generate the comparator test signal COMP_OUT4.

[0036] Comparator module 210 may further include inverters 205-208. Inverter 205 may be coupled to the output terminal of comparator 201 and generates its inverted signal COMP_OUT1_Z based on the comparator test signal COMP_OUT1. Inverter 206 may be coupled to the output of comparator 202 and generates its inverted signal COMP_OUT2_Z based on the comparator test signal COMP_OUT2. Inverter 207 may be coupled to the output of comparator 203 and generates its inverted signal COMP_OUT3_Z based on the comparator test signal COMP_OUT3. Inverter 208 may be coupled to the output of comparator 204 and generates its inverted signal COMP_OUT4_Z based on the comparator test signal COMP_OUT4. The inverted signals COMP_OUT1_Z, COMP_OUT2_Z, COMP_OUT3_Z, and COMP_OUT4_Z may also be referred to as comparator test signals. Depending on specific design requirements, COMP_OUT1 or COMP_OUT1_Z can be used as the comparator test signal output by comparator 201, COMP_OUT2 or COMP_OUT2_Z as the comparator test signal output by comparator 202, COMP_OUT3 or COMP_OUT3_Z as the comparator test signal output by comparator 203, and COMP_OUT4 or COMP_OUT4_Z as the comparator test signal output by comparator 204, for use by other circuit modules (e.g., ...). Figure 1 The first circuit 120 or the second circuit 130 shown is used.

[0037] According to some embodiments of this application, comparator test signals COMP_OUT1, COMP_OUT1_Z, COMP_OUT2, COMP_OUT2_Z, COMP_OUT3, COMP_OUT3_Z, COMP_OUT4, and COMP_OUT4_Z are generated in response to the same test stimulus signal S. Each of the above comparator test signals is associated with a threshold voltage of a corresponding one of comparators 201-204. In some embodiments, the test stimulus signal S may include a ramp voltage signal. It should be understood that the comparator module 210 may include any number of comparators to adapt to different test requirements.

[0038] In some embodiments, comparator module 210 may not include inverters 205-208. Alternatively, one or more of inverters 205-208 may be provided independently of comparator module 210. Alternatively, one or more of inverters 205-208 may be provided in subsequent circuitry coupled to comparator module 210 (e.g., Figure 1 In the first circuit 120 or the second circuit 130 shown.

[0039] Figures 3A-3CThe diagram illustrates first circuits 310, 320, and 330 in a test circuit module according to some embodiments of this application. The first circuits 310, 320, and 330 may be... Figure 1 A specific embodiment of the first circuit 120 in the diagram.

[0040] Figure 3A The first circuit 310 shown includes test input terminals 311-1 and 311-2, which can be configured to receive two comparator test signals respectively, for example... Figure 2 The comparator 201 outputs COMP_OUT1, and the comparator 202 outputs COMP_OUT2_Z. The first circuit 310 also includes a test output terminal 312. The first circuit 310 includes a logic gate 313, such as an AND gate. The input terminal 313_1 of logic gate 311 is coupled to the test input terminal 311-1 to receive the comparator test signal COMP_OUT1. The input terminal 313_2 of logic gate 313 is coupled to the test input terminal 311-2 to receive the comparator test signal COMP_OUT2_Z. The output terminal 313_3 of logic gate 313 is coupled to the test output terminal 312. Logic gate 313 can be configured to generate a combined test signal at the output terminal 313_3 in response to the comparator test signals COMP_OUT1 and COMP_OUT2_Z. This combined test signal is the total combined test signal Q output by the first circuit 310. The overall combined test signal Q can be flipped once in response to each of the flips in COMP_OUT1 and COMP_OUT2_Z. Therefore, Figure 3A The total combined test signal Q shown can be used to obtain combined information about the threshold voltages of comparator 201 and comparator 202.

[0041] It should be understood that in other embodiments, the two comparator test signals received by the first circuit 310 may also be COMP_OUT1 and COMP_OUT2, COMP_OUT1_Z and COMP_OUT2, or COMP_OUT1_Z and COMP_OUT2_Z. Different logic gates or combinations of logic gates can be used to generate the desired total combined test signal Q for different combinations of comparator test signals.

[0042] Figure 3B The first circuit 320 shown includes test input terminals 321-1, 321-2, and 321-3, which can be configured to receive three comparator test signals, for example... Figure 2 COMP_OUT1, COMP_OUT2_Z, and COMP_OUT3 are shown. The first circuit 320 also includes a test output terminal 322.

[0043] The first circuit 320 includes a first logic gate 323, such as an AND gate. Input terminals 313_1 and 323_2 of the first logic gate 323 are coupled to test input terminals 321-1 and 321-2, respectively, to receive comparator test signals COMP_OUT1 and COMP_OUT2_Z. The first logic gate 323 is configured to generate a first combined test signal Q1 at its output terminal 323_3 in response to the comparator test signals COMP_OUT1 and COMP_OUT2_Z.

[0044] The first circuit 320 also includes a second logic gate 324, such as an OR gate. The input terminal 324_2 of the second logic gate 324 is coupled to test input terminals 321-3 to receive the comparator test signal COMP_OUT3. The input terminal 324_1 of the second logic gate 324 is coupled to the output terminal 323_3 of the first logic gate 323 to receive the first combined test signal Q1. The output terminal 324_3 of the second logic gate 324 is coupled to the test output terminal 322. The second logic gate 324 is configured to generate a second combined test signal at the output terminal 324_3 in response to the comparator test signal COMP_OUT3 and the first combined test signal Q1. This second combined test signal is the total combined test signal Q output by the first circuit 320. The total combined test signal Q is toggled once in response to each of the toggles of COMP_OUT1, COMP_OUT2_Z, and COMP_OUT3. Therefore, Figure 3B The combined test signal Q shown can be used to obtain combined information about the threshold voltages of comparators 201, 202 and 203.

[0045] According to some embodiments of this application, the threshold voltage associated with the comparator test signal COMP_OUT1 (i.e., the threshold voltage of comparator 201) is less than the threshold voltage associated with the comparator test signal COMP_OUT2_Z (i.e., the threshold voltage of comparator 202), and the threshold voltage associated with the comparator test signal COMP_OUT2_Z is less than the threshold voltage associated with the comparator test signal COMP_OUT3 (i.e., the threshold voltage of comparator 203). The total combined test signal Q can sequentially exhibit transition points corresponding to the threshold voltages of comparator 201, comparator 202, and comparator 203.

[0046] It should be understood that in other embodiments, the three comparator test signals received by the first circuit 320 may also be other combinations of the comparator test signals output by comparator 201, comparator 202, and comparator 203. Different logic gates or combinations of logic gates can be used to generate the desired total combined test signal Q for different combinations of comparator test signals. Furthermore, in some embodiments, the first circuit 320 may be configured to receive only two comparator test signals. In such embodiments, depending on the specific circuit implementation, the first circuit 320 may perform the function of the first circuit 310 described above by grounding, floating, or connecting the test input terminals 321-3 to a high level.

[0047] Figure 3C The first circuit 330 shown includes test input terminals 331-1, 331-2, 331-3, and 331-4, which can be configured to receive four comparator test signals, for example... Figure 2 The COMP_OUT1, COMP_OUT2_Z, COMP_OUT3, and COMP_OUT4_Z are shown. The first circuit 330 also includes a test output terminal 332.

[0048] The first circuit 330 includes a first logic gate 333, such as an AND gate. Input terminals 331_1 and 333_2 of the first logic gate 333 are coupled to test input terminals 331-1 and 331-2, respectively, to receive comparator test signals COMP_OUT1 and COMP_OUT2_Z. The first logic gate 333 is configured to generate a first combined test signal Q1 at its output terminal 333_3 in response to the comparator test signals COMP_OUT1 and COMP_OUT2_Z.

[0049] The first circuit 330 also includes a second logic gate 334, such as an AND gate. The input terminals 334_1 and 334_2 of the second logic gate 334 are coupled to test input terminals 331-3 and 331-4, respectively, to receive comparator test signals COMP_OUT3 and COMP_OUT4_Z. The second logic gate 334 is configured to generate a second combined test signal Q2 at its output terminal 334_3 in response to the comparator test signals COMP_OUT3 and COMP_OUT4_Z.

[0050] The first circuit 330 also includes a third logic gate 335, such as an OR gate. The input terminals 335_1 and 335_2 of the third logic gate 335 are respectively coupled to the output terminal 333_3 of the first logic gate 333 and the output terminal 334_3 of the second logic gate 334 to receive the first combined test signal Q1 and the second combined test signal Q2. The output terminal 335_3 of the third logic gate 335 is coupled to the test output terminal 332. The third logic gate 335 is configured to generate a third combined test signal at the output terminal 335_3 in response to the first combined test signal Q1 and the second combined test signal Q2. This third combined test signal is the total combined test signal Q output by the first circuit 330. The total combined test signal Q is toggled once in response to each of the toggles of COMP_OUT1, COMP_OUT2_Z, COMP_OUT3, and COMP_OUT4_Z. Therefore, Figure 3C The overall combined test signal Q shown can be used to obtain combined information about the threshold voltages of comparators 201, 202, 203 and 204.

[0051] According to some embodiments of this application, the threshold voltage associated with the comparator test signal COMP_OUT1 (i.e., the threshold voltage of comparator 201) is less than the threshold voltage associated with the comparator test signal COMP_OUT2_Z (i.e., the threshold voltage of comparator 202), the threshold voltage associated with the comparator test signal COMP_OUT2_Z is less than the threshold voltage associated with the comparator test signal COMP_OUT3 (i.e., the threshold voltage of comparator 203), and the threshold voltage associated with the comparator test signal COMP_OUT3 is less than the threshold voltage associated with the comparator test signal COMP_OUT4_Z (i.e., the threshold voltage of comparator 204). The total combined test signal Q can sequentially present transition points corresponding to the threshold voltages of comparator 201, comparator 202, comparator 203, and comparator 204.

[0052] It should be understood that in other embodiments, the four comparator test signals received by the first circuit 330 may also be other combinations of the comparator test signals output by comparator 201, comparator 202, comparator 203, and comparator 204. Different logic gates or combinations of logic gates can be used to generate the desired total combined test signal Q for different combinations of comparator test signals. Furthermore, in some embodiments, the first circuit 330 may be configured to receive only two comparator test signals. In this embodiment, depending on the specific circuit implementation, the first circuit 330 may perform the function of the first circuit 310 described above by grounding, floating, or connecting the test input terminals 321-3 and 321-4 to a high level. In some embodiments, the first circuit 330 may be configured to receive only three comparator test signals. In this embodiment, depending on the specific circuit implementation, the first circuit 330 may perform the function of the first circuit 320 described above by grounding, floating, or connecting the test input terminal 321-4 to a high level.

[0053] Figure 1 The number of test input terminals in the first circuit 120 shown may also be more than four. Without departing from the spirit and scope of this application, for example... Figures 3A-3C The first circuits 310, 320, and 330 shown can be appropriately combined, adjusted, or expanded to implement a first circuit 120 containing more than four test input terminals. For example, based on the first circuit 330, the third logic gate 335 can be changed to a three-input OR gate, whose third input terminal can be coupled to the fifth test input terminal to receive the fifth comparator test signal. As another example, based on the first circuit 330, an AND gate can be added, and the third logic gate 335 can be changed to a three-input OR gate, whose third input terminal can be coupled to the output terminal of the added AND gate, and the two input terminals of the added AND gate can be coupled to the fifth and sixth test input terminals, respectively, to receive the fifth and sixth comparator test signals.

[0054] Figure 4 A second circuit 410 in a test circuit module according to some embodiments of this application is shown. The second circuit 410 may be... Figure 1 One embodiment of the second circuit 130. The second circuit 410 may include a first check input terminal, a second check input terminal, a third check input terminal, and a fourth check input terminal. Figure 4 (Not shown in the image), these test input terminals can be configured to receive four comparator test signals respectively, for example... Figure 2 COMP_OUT1, COMP_OUT2, COMP_OUT3, and COMP_OUT4 are shown. The second circuit 410 may include a first selection input terminal and a second selection input terminal (…). Figure 4(Not shown in the diagram), these selection input terminals can be configured to receive two selection input signals, INPUT_PIN1 and INPUT_PIN2, respectively. The second circuit 410 may also include a check output terminal (…). Figure 4 (Not shown in the diagram). The second circuit 410 can select one of the four comparator test signals to output based on the selection input signal received at the selection input terminal, in order to check whether the corresponding comparator is working properly.

[0055] Figure 4 The second circuit 410 shown includes inverters 411 and 412. Inverters 411 and 412 are configured to be coupled to two selection input terminals of the second circuit 410, respectively, to receive selection input signals INPUT_PIN1 and INPUT_PIN2, and output corresponding inverted selection signals INPUT_PIN1_Z and INPUT_PIN2_Z. The second circuit 410 also includes AND gates 413-416 and OR gate 417.

[0056] The input terminal 413_1 of AND gate 413 can be coupled to the first check input terminal of the second circuit 410 to receive the comparator test signal COMP_OUT1. The input terminal 413_2 of AND gate 413 can be coupled to inverter 411 to receive the inverting selection signal INPUT_PIN1_Z. The input terminal 413_3 of AND gate 413 can be coupled to inverter 412 to receive the inverting selection signal INPUT_PIN2_Z. The output terminal 413_4 of AND gate 413 can be coupled to the input terminal 417_1 of OR gate 417.

[0057] The input terminal 414_1 of AND gate 414 can be coupled to the second check input terminal of the second circuit 410 to receive the comparator test signal COMP_OUT2. The input terminal 414_2 of AND gate 414 can be coupled to inverter 411 to receive the inverting selection signal INPUT_PIN1_Z. The input terminal 414_3 of AND gate 414 can be coupled to the second selection input terminal of the second circuit 410 to receive the selection input signal INPUT_PIN2. The output terminal 414_4 of AND gate 414 can be coupled to the input terminal 417_2 of OR gate 417.

[0058] The input terminal 415_1 of AND gate 415 can be coupled to the third check input terminal of the second circuit 410 to receive the comparator test signal COMP_OUT3. The input terminal 415_2 of AND gate 415 can be coupled to the first selection input terminal of the second circuit 410 to receive the selection input signal INPUT_PIN1. The input terminal 415_3 of AND gate 415 can be coupled to inverter 412 to receive the inverted selection signal INPUT_PIN2_Z. The output terminal 415_4 of AND gate 415 can be coupled to the input terminal 417_3 of OR gate 417.

[0059] Input terminal 416_1 of AND gate 416 can be coupled to the fourth check input terminal of the second circuit 410 to receive the comparator test signal COMP_OUT4. Input terminal 416_2 of AND gate 416 can be coupled to the first selection input terminal of the second circuit 410 to receive the selection input signal INPUT_PIN1. Input terminal 416_3 of AND gate 416 can be coupled to the second selection input terminal of the second circuit 410 to receive the selection input signal INPUT_PIN2. Output terminal 416_4 of AND gate 416 can be coupled to input terminal 417_4 of OR gate 417.

[0060] The input terminals 417_1, 417_2, 417_3, and 417_4 of OR gate 417 can be coupled to the output terminals 413_4 of AND gate 413, 414_4 of AND gate 414, 415_4 of AND gate 415, and 416_4 of AND gate 416, respectively. The output terminal 417_5 of OR gate 417 can be coupled to the check output terminal of the second circuit 410. The signal OUTPUT on the output terminal 417_5 of OR gate 417 is the comparator test signal selectively output in response to the selection input signals INPUT_PIN1 and INPUT_PIN2. For example, when both INPUT_PIN1 and INPUT_PIN2 are 0 (low level), OR gate 417 outputs COMP_OUT1; when INPUT_PIN1 is 0 (low level) and both INPUT_PIN2 are 1 (high level), OR gate 417 outputs COMP_OUT2.

[0061] In some embodiments, the second circuit 410 may be configured to receive only the two comparator test signals. In this embodiment, only one select input signal (e.g., INPUT_PIN1) may be received. Accordingly, only one inverter (e.g., inverter 411) and two AND gates (e.g., AND gates 413 and 415) may be used. The other inverter and two AND gates may be disabled. Depending on the specific circuit implementation, unused check input terminals and select input terminals may be grounded, left floating, or connected to a high level.

[0062] Figure 1 The number of check input terminals in the second circuit 130 shown may be less than or more than four. Without departing from the spirit and scope of this application, for example... Figure 4 The second circuit 410 shown can be appropriately adjusted, reduced, or expanded to implement a second circuit 130 containing fewer or more than four check input terminals. For example, a second circuit 130 containing two check input terminals may include an inverter, two AND gates, and a two-input OR gate; a second circuit 130 containing five check input terminals may include three inverters, five AND gates, and a five-input OR gate.

[0063] In other embodiments, Figure 1 The second circuit 130 shown may include a multiplexer. Specifically, the multiplexer may have multiple input terminals configured to receive multiple comparator test signals, and a selection terminal configured to receive a selection input signal.

[0064] Figure 5 The following is an exemplary illustration of the waveforms of signals changing over time at some nodes in a test system according to some embodiments of this application. In this example, the test system (e.g., Figure 1 The comparator module of the test system 100 shown may include four comparators (e.g., Figure 2 Comparators 201-204 are shown. The test excitation signal S is a ramp voltage signal that gradually increases from a minimum voltage to a maximum voltage, and then gradually decreases back to the aforementioned minimum voltage. The test excitation signal S can be simultaneously transmitted to each of the four comparators, thereby starting four threshold tests simultaneously. At time T1, the rising threshold R associated with comparator 201... vth1 Triggered (i.e., the voltage of the test excitation signal S reaches R) vth1 This causes the comparator test signal COMP_OUT1 output by comparator 201 to flip from low to high, a state that remains until time T8. At time T2, the rising threshold R associated with comparator 202... vth2 This is triggered, causing the comparator test signal COMP_OUT2 output by comparator 202 to toggle from low to high, a state maintained until time T7. At time T3, the rising threshold R associated with comparator 203... vth3 This is triggered, causing the comparator test signal COMP_OUT3 output by comparator 203 to toggle from low to high, a state that remains until time T6. At time T4, the rising threshold R associated with comparator 204... vth4 When triggered, the comparator test signal COMP_OUT4 output by comparator 204 flips from low to high, and this state is maintained until time T5.

[0065] At time T5, the falling threshold F associated with comparator 204 vth4 This is triggered, causing the comparator test signal COMP_OUT4 output by comparator 204 to toggle from high to low. At time T6, the falling threshold F associated with comparator 203... vth3 This is triggered, causing the comparator test signal COMP_OUT3 output by comparator 203 to toggle from high to low. At time T7, the falling threshold F associated with comparator 202... vth2This is triggered, causing the comparator test signal COMP_OUT2 output by comparator 202 to toggle from high to low. At time T8, the falling threshold F associated with comparator 201... vth1 When triggered, the comparator test signal COMP_OUT1 output by comparator 201 flips from high level to low level.

[0066] like Figure 5 As shown, the total combined test signal Q (e.g., via such as...) Figure 3C The Q generated by the first circuit 330 shown can combine the test results of the above four threshold tests together, that is, a flip occurs in response to each flip of the comparator test signal.

[0067] According to some embodiments of this application, comparators for combined testing can be selected based on associated threshold voltages. For example, comparators that meet the following condition can be selected for combined testing: the difference between the threshold voltages of any two comparators is greater than a first predetermined value and less than a second predetermined value. The first predetermined value is set to ensure that the total combined test signal can be correctly triggered and toggled by the voltage threshold of each comparator. The second predetermined value is set to avoid an excessively large voltage range for the test excitation signal, and also to avoid excessively long scan (test) times.

[0068] It should be understood that the various circuits, modules, and functions described in this application can also be implemented using programmable logic devices. For example, Figure 1 The first circuit 120 may include a programmable logic device. The programmable logic device may include a plurality of inputs, each of which is configurable to be coupled to a corresponding of a plurality of test input terminals 121-1, ..., 121-N to receive a corresponding comparator test signal. The programmable logic device may also include an output, which is configurable to be coupled to a test output terminal 122 to output a total combined test signal generated by the programmable logic device to the test output terminal 122. The programmable logic device may be configured to toggle the total combined test signal in response to each toggle of the received plurality of comparator test signals.

[0069] Figure 6 A flowchart of a test method according to some embodiments of this application is shown. At step 610, the same test excitation signal can be provided to multiple test comparators to generate multiple comparator test signals, wherein each comparator test signal is associated with a threshold voltage of the corresponding test comparator. Prior to step 610, the test system (e.g., Figure 1The test system 100 shown is initialized. During initialization, the threshold of each of the plurality of test comparators can be set, for example, by coupling each of the plurality of test comparators to a corresponding test node. Furthermore, parameters of the AWG can be set to generate the desired test excitation signal. In some embodiments, the test excitation signal is a ramp voltage signal.

[0070] At step 620, a total combined test signal can be generated in response to multiple comparator test signals. For example, this can be achieved through... Figure 1 The first circuit 120 shown generates a total combined test signal. In some embodiments, the total combined test signal may be flipped once in response to each of the plurality of comparator test signals.

[0071] At step 630, the generated total combined test signal can be detected.

[0072] In some embodiments, after step 610 and before step 620, one of a plurality of comparator test signals may be selected for output in response to a selection input signal to check whether the corresponding test comparator is working properly.

[0073] According to some embodiments of this application, Figure 6 The test method shown can be executed by the processor executing instructions stored on a non-transitory computer-readable storage medium.

[0074] The description in this specification is provided to enable those skilled in the art to make or use the invention. Various modifications to the invention will readily be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the invention. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test circuit, comprising: The first circuit includes: Multiple test input terminals, configurable to receive multiple comparator test signals, wherein each comparator test signal is associated with a threshold voltage of a corresponding test comparator; and A test output terminal, wherein the first circuitry is configured to generate a total combined test signal at the test output terminal in response to the plurality of comparator test signals.

2. The test circuit according to claim 1, wherein the plurality of comparator test signals are generated by a plurality of test comparators in response to the same test excitation signal.

3. The test circuit of claim 1, wherein the first circuit is configured to flip the total combined test signal in response to each flip of the plurality of comparator test signals.

4. The test circuit according to claim 1, wherein the first circuit further comprises: The first logic gate, which includes: A first input terminal is coupled to a first test input terminal among the plurality of test input terminals to receive a first comparator test signal among the plurality of comparator test signals; A second input terminal, coupled to a second test input terminal among the plurality of test input terminals, to receive a second comparator test signal among the plurality of comparator test signals; and A first output terminal, wherein the first logic gate is configured to generate a first combined test signal at the first output terminal in response to the first comparator test signal and the second comparator test signal.

5. The test circuit according to claim 4, wherein the first circuit further comprises: The second logic gate includes: A third input terminal is coupled to a third test input terminal among the plurality of test input terminals to receive a third comparator test signal among the plurality of comparator test signals; A fourth input terminal, coupled to the first output terminal, is used to receive the first combined test signal; and A second output terminal is coupled to the test output terminal, wherein the second logic gate is configured to generate the total combined test signal at the second output terminal in response to at least the third comparator test signal and the first combined test signal.

6. The test circuit of claim 5, wherein the threshold voltage of the first test comparator associated with the first comparator test signal is less than the threshold voltage of the second test comparator associated with the second comparator test signal, and the threshold voltage of the second test comparator is less than the threshold voltage of the third test comparator associated with the third comparator test signal.

7. The test circuit according to claim 4, wherein the first circuit further comprises: The second logic gate includes: A third input terminal is coupled to a third test input terminal among the plurality of test input terminals to receive a third comparator test signal among the plurality of comparator test signals; A fourth input terminal, coupled to the fourth test input terminal of the plurality of test input terminals, to receive a fourth comparator test signal of the plurality of comparator test signals; and A second output terminal, wherein the second logic gate is configured to generate a second combined test signal at the second output terminal in response to the third comparator test signal and the fourth comparator test signal; and The third logic gate includes: The fifth input terminal is coupled to the first output terminal to receive the first combined test signal; A sixth input terminal, coupled to the second output terminal, is used to receive the second combined test signal; and A third output terminal is coupled to the test output terminal, wherein the third logic gate is configured to generate the total combined test signal at the third output terminal in response to at least the first combined test signal and the second combined test signal.

8. The test circuit of claim 7, wherein the threshold voltage of the first test comparator associated with the first comparator test signal is less than the threshold voltage of the second test comparator associated with the second comparator test signal, the threshold voltage of the second test comparator is less than the threshold voltage of the third test comparator associated with the third comparator test signal, and the threshold voltage of the third test comparator is less than the threshold voltage of the fourth test comparator associated with the fourth comparator test signal.

9. The test circuit according to claim 1, further comprising: The second circuit includes: Multiple test input terminals are configured to receive the multiple comparator test signals; The selection input terminal is configurable to receive a selection input signal; and Check the output terminal, wherein the second circuit is configured to selectively output one of the plurality of comparator test signals at the check output terminal in response to the selection input signal.

10. The test circuit according to claim 9, wherein the second circuit further comprises: An inverter coupled to the selection input terminal and configured to receive the selection input signal and output an inverted selection signal; The first AND gate, which includes: A first input terminal, which is coupled to a first check input terminal among the plurality of check input terminals to receive a first comparator test signal among the plurality of comparator test signals; A second input terminal, coupled to the inverter to receive the inverting selection signal; and First output terminal; The second AND gate includes: A third input terminal is coupled to a second check input terminal among the plurality of check input terminals to receive a second comparator test signal among the plurality of comparator test signals; A fourth input terminal, coupled to the selection input terminal to receive the selection input signal; and Second output terminal; and OR gates, which include: The fifth input terminal is coupled to the first output terminal; The sixth input terminal is coupled to the second output terminal; and The third output terminal is coupled to the inspection output terminal.

11. The test circuit of claim 9, wherein the second circuit includes a multiplexer.

12. The test circuit according to claim 2, wherein the test excitation signal includes a ramp voltage signal.

13. The test circuit according to claim 1, wherein the first circuit includes a programmable logic device, the programmable logic device comprising: Multiple inputs, coupled to the multiple test input terminals, to receive the multiple comparator test signals; as well as The output is coupled to the test output terminal to output the total combined test signal generated by the programmable logic device to the test output terminal. The programmable logic device is configured to toggle the total combined test signal in response to each toggle of the plurality of comparator test signals.

14. An electronic device comprising: Multiple test comparators, wherein each test comparator is configured to generate a corresponding comparator test signal in response to a test stimulus signal, the comparator test signal being associated with a threshold voltage of the test comparator; as well as A test circuit, configurable to be coupled to the plurality of test comparators and including a first circuit, the first circuit comprising: Multiple test input terminals, which can be configured to receive multiple comparator test signals from the multiple test comparators; as well as A test output terminal, wherein the first circuitry is configured to generate a total combined test signal at the test output terminal in response to the plurality of comparator test signals.

15. The electronic device of claim 14, wherein the plurality of comparator test signals are generated by the plurality of test comparators in response to the same test excitation signal.

16. The electronic device of claim 14, wherein the first circuitry is configured to flip the total combined test signal in response to each flip of the plurality of comparator test signals.

17. The electronic device of claim 14, wherein the first circuit further comprises: The first logic gate, which includes: A first input terminal is coupled to a first test input terminal among the plurality of test input terminals to receive a first comparator test signal among the plurality of comparator test signals; A second input terminal, coupled to a second test input terminal among the plurality of test input terminals, to receive a second comparator test signal among the plurality of comparator test signals; and A first output terminal, wherein the first logic gate is configured to generate a first combined test signal at the first output terminal in response to the first comparator test signal and the second comparator test signal.

18. The electronic device of claim 17, wherein the first circuit further comprises: The second logic gate includes: A third input terminal is coupled to a third test input terminal among the plurality of test input terminals to receive a third comparator test signal among the plurality of comparator test signals; A fourth input terminal, coupled to the first output terminal, is used to receive the first combined test signal; and A second output terminal is coupled to the test output terminal, wherein the second logic gate is configured to generate the total combined test signal at the second output terminal in response to at least the third comparator test signal and the first combined test signal.

19. The electronic device of claim 18, wherein the threshold voltage of the first test comparator associated with the first comparator test signal is less than the threshold voltage of the second test comparator associated with the second comparator test signal, and the threshold voltage of the second test comparator is less than the threshold voltage of the third test comparator associated with the third comparator test signal.

20. The electronic device of claim 17, wherein the first circuit further comprises: The second logic gate includes: A third input terminal is coupled to a third test input terminal among the plurality of test input terminals to receive a third comparator test signal among the plurality of comparator test signals; A fourth input terminal, coupled to the fourth test input terminal of the plurality of test input terminals, to receive a fourth comparator test signal of the plurality of comparator test signals; and A second output terminal, wherein the second logic gate is configured to generate a second combined test signal at the second output terminal in response to the third comparator test signal and the fourth comparator test signal; and The third logic gate includes: The fifth input terminal is coupled to the first output terminal to receive the first combined test signal; A sixth input terminal, coupled to the second output terminal, is used to receive the second combined test signal; and A third output terminal is coupled to the test output terminal, wherein the third logic gate is configured to generate the total combined test signal at the third output terminal in response to at least the first combined test signal and the second combined test signal.

21. The electronic device of claim 20, wherein the threshold voltage of the first test comparator associated with the first comparator test signal is less than the threshold voltage of the second test comparator associated with the second comparator test signal, the threshold voltage of the second test comparator is less than the threshold voltage of the third test comparator associated with the third comparator test signal, and the threshold voltage of the third test comparator is less than the threshold voltage of the fourth test comparator associated with the fourth comparator test signal.

22. The electronic device of claim 14, wherein the test circuit further comprises a second circuit, the second circuit comprising: Multiple test input terminals are configured to receive the multiple comparator test signals; Select input terminal, which can be configured to receive select input signal; as well as Check the output terminal, wherein the second circuit is configured to selectively output one of the plurality of comparator test signals at the check output terminal in response to the selection input signal.

23. The electronic device of claim 15, wherein the same test excitation signal comprises a ramp voltage signal.

24. A testing method, comprising: The same test excitation signal is provided to multiple test comparators to generate multiple comparator test signals, wherein each comparator test signal is associated with the threshold voltage of the corresponding test comparator. A total combined test signal is generated in response to the test signals of the plurality of comparators; as well as The overall combined test signal is detected.

25. The method of claim 24, wherein generating the total combined test signal in response to the plurality of comparator test signals comprises flipping the total combined test signal in response to each flip of the plurality of comparator test signals.

26. The method of claim 24, wherein the test excitation signal is a ramp voltage signal.

27. The method of claim 24, further comprising: Before generating the total combined test signal, one of the plurality of comparator test signals is selected from the input signal and output to check whether the corresponding test comparator is working properly.

28. A non-transitory computer-readable storage medium having instructions stored thereon that, when executed by a processor, cause the processor to perform the method according to any one of claims 24-27.

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