A dual-channel ultra-low temperature drift operational amplifier testing method

Abstract

This invention discloses a testing method for dual-channel cryogenic operational amplifiers. Relying on a testing system and a high-low temperature airflow temperature shock system, the testing adaptation system consists of an independent test bench adapter board, an L-shaped fixture adapter board, and a sealed insulation box. Physical isolation separates the ambient temperature testing system area from the high-low temperature testing area, avoiding extreme temperature drift and damage to components on the test bench. The L-shaped fixture structure isolates the mechanical and airflow stresses of the heat flow shroud of the temperature shock equipment, eliminating offset voltage testing errors caused by the chip piezoresistive effect. Pluggable flexible cables achieve flexible signal interconnection, balancing testing accuracy with batch replacement testing efficiency. This invention solves the technical problems of stress interference, uneven temperature field, system temperature drift, and poor test repeatability in traditional high-low temperature testing of cryogenic operational amplifiers. It can accurately calculate the offset voltage temperature drift coefficient of dual-channel operational amplifiers and is suitable for the industrial precision testing of high-precision cryogenic analog devices.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and specifically to a testing method for a dual-channel ultra-low temperature drift operational amplifier. Background Technology

[0002] Operational amplifiers are core components of analog integrated circuits, widely used in fields with stringent requirements for analog signal acquisition accuracy, operational stability, and temperature adaptability, such as industrial automation control, precision medical testing equipment, high-precision data acquisition systems, and aerospace electronic devices. As high-end electronic systems continue to iterate towards higher precision, ultra-stability, and wide-temperature-range operation, the application scenarios of ultra-low temperature drift operational amplifiers continue to expand. The core characteristic of this type of device is its extremely low offset voltage drift across its entire rated operating temperature range, enabling stable acquisition and accurate processing of weak analog signals. Its offset voltage temperature drift coefficient is a core indicator for evaluating the performance level of the device.

[0003] The temperature drift parameter of ultra-low temperature operational amplifiers is extremely small, making them highly sensitive to the uniformity of ambient temperature, mechanical stress state, and stability of the test system during the testing process. Existing general-purpose integrated circuit test systems can perform tests on conventional parameters such as offset voltage, open-loop gain, common-mode rejection ratio, and power supply rejection ratio of dual-channel operational amplifiers. However, they suffer from several inherent technical limitations in high- and low-temperature extreme environment precision testing scenarios: First, the test system host and onboard precision components are not resistant to extreme high- and low-temperature environments. Direct exposure to temperature variations will cause inherent temperature drift, introducing system testing errors and easily damaging components, reducing test consistency and equipment lifespan. Second, silicon-based semiconductor chips exhibit significant piezoresistive effects. In traditional test structures, temperature shock equipment requires a preloaded heat flow shroud and high-speed... Airflow impact loads can cause micro-deformation of the chip at the micrometer level, disrupting the internal stress balance of the silicon crystal, changing the carrier mobility, and introducing additional offset voltage. This error magnitude far exceeds the temperature drift value of the ultra-low temperature drift device itself, leading to distorted test results. Third, traditional test structures lack dedicated sealed heat insulation chambers, and heat exchange occurs between the chip test area and the external environment, easily forming local temperature gradients and poor temperature field uniformity, resulting in insufficient repeatability and stability of test data. Fourth, traditional manual test solutions have cumbersome operation procedures and are difficult to control environmental parameters, making them only suitable for laboratory sampling verification and unable to meet the needs of industrialized batch standardized testing.

[0004] In summary, existing technologies lack a high and low temperature precision testing method for dual-channel ultra-low temperature drift operational amplifiers that can isolate system temperature drift, eliminate mechanical stress interference, ensure uniform and stable temperature field, and be suitable for mass production. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a testing method for dual-channel ultra-low temperature drift operational amplifiers. This method solves the technical problems in existing testing technologies, such as temperature drift interference in the testing system, poor adaptability to extreme temperatures, offset errors introduced by mechanical stress, non-uniform testing temperature field, low testing efficiency, and inability to conduct standardized batch testing. It achieves high-precision, high-repeatability, and batch testing of the offset voltage temperature drift parameters of dual-channel ultra-low temperature drift operational amplifiers.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A testing method for a dual-channel cryogenic operational amplifier includes using an integrated circuit testing system and a high-low temperature airflow temperature shock system to perform high-low temperature tests on the offset voltage temperature drift parameters of the dual-channel cryogenic operational amplifier. The method is characterized by the following steps: S1. Based on the pin definitions and interface layout of the integrated circuit test bench, customize a matching test bench adapter board to standardize the connection of all test signal ports of the operational amplifier chip. S2. A custom L-shaped fixture adapter board is designed according to the operational amplifier chip fixture package. It is used to extend the chip fixture and operational amplifier chip to one side, so that the chip fixture and operational amplifier chip can be placed in the high and low temperature test environment, and to achieve physical isolation between the room temperature area of ​​the test bench and the high and low temperature test area. S3. Based on the external dimensions of the heat flow meter, a customized sealed insulation box is used to realize the high and low temperature test environment. The chip fixture and operational amplifier chip connected to one side of the L-shaped fixture adapter board are arranged in the center of the insulation box cavity to construct a sealed high and low temperature test cavity. S4. Set corresponding flexible flat cable sockets at the corresponding positions of the test bench adapter board and the L-shaped fixture adapter board, and realize the flexible interconnection of all test signals of the two adapter boards through pluggable flexible flat cables. S5. Start the high and low temperature airflow temperature shock system, set the high and low temperature limit test temperatures respectively, and after the temperature field inside the insulation box reaches a stable and balanced state, collect the low temperature offset voltage data and high temperature offset voltage data of the dual channels of the operational amplifier chip under test, substitute them into the temperature drift calculation formula to solve the offset voltage temperature drift coefficient, and complete the ultra-low temperature drift performance test of the device.

[0007] Based on the above technical solutions, the following further technical solutions are proposed: The test bench adapter board uses 1mm standard pin spacing for pads and flexible flat cable sockets, and fixedly leads out nine test ports, namely the positive and negative power supply terminals of the operational amplifier, the output terminal of channel A, the output terminal of channel B, the inverting input terminal of channel A, the inverting input terminal of channel B, the non-inverting input terminal of channel A, the non-inverting input terminal of channel B, and the ground terminal; the test bench adapter board uses a large area of ​​copper plating to build a solid surface, and is connected to the AGND interface of the test bench.

[0008] The sealed heat preservation box uses a hard stainless steel plate as the overall support frame. Thickened silicone heat insulation pads are pasted on the outer side, bottom and upper bonding surface of the heat preservation box, and the inner side of the heat preservation box is fully covered with aluminum foil heat insulation board. The side wall of the sealed heat preservation box has an assembly opening that matches the width of the L-shaped clamp adapter plate, and the assembly opening is equipped with a removable sealing plug.

[0009] The test parameters in step S5 are configured as follows: low temperature limit test temperature -55℃, high temperature limit test temperature 125℃, operational amplifier chip power supply voltage V+=2.5V, V-=-2.5V, common mode input level VCM=0V; during the test, the temperature sensor is attached to the surface of the chip under test, and the airflow intensity is adjusted until the cavity temperature is stable and undisturbed.

[0010] The formula for calculating the offset voltage temperature drift coefficient in step S5 is as follows: (1) Where: ΔV OS This is the offset voltage temperature drift coefficient, expressed in nV / ℃. V OS2 The offset voltage at the extreme high temperature is expressed in μV. V OS1 The offset voltage at the low-temperature limit temperature is expressed in μV. T max This refers to the high-temperature limit test temperature, expressed in °C. T min This is the low-temperature limit test temperature, in °C.

[0011] The pins at both ends of the pluggable flexible flat cable correspond one-to-one with the socket ports of the two adapter boards, enabling detachable signal conduction between the two adapter boards for rapid changeover testing of the chip under test.

[0012] The present invention has the following advantages over the prior art: 1. This invention adopts a split physical isolation architecture, which completely separates the room temperature area of ​​the test bench from the high and low temperature test area of ​​the chip, thus completely avoiding the temperature drift error and damage risk caused by the contact of precision components of the test system with extreme temperatures, eliminating system-level test interference from the source, and greatly improving the stability of the test benchmark.

[0013] 2. The present invention adopts an L-shaped suspended fixture structure, which completely removes the chip under test from the pressure load of the heat flow shroud and the impact range of airflow, eliminating the micro-deformation and additional offset voltage error caused by the piezoresistive effect of silicon chips, solving the core problem of low accuracy in ultra-low temperature drift parameter testing, and can accurately capture the true temperature drift characteristics of the device.

[0014] 3. The present invention adopts a stainless steel pressure-bearing frame with a double-layer heat-insulated and sealed cavity structure, which can fully withstand the pressure of the heat flow shroud pressing, while isolating internal and external heat exchange, ensuring that the temperature field of the chip in the cavity is uniform, gradient-free, and undisturbed, greatly improving the repeatability and accuracy of high and low temperature test data.

[0015] 4. This invention adopts a pluggable flexible interconnect structure with a flexible flat cable, which is convenient to install and remove and allows for fast chip replacement. It eliminates the cumbersome operation of traditional manual testing, and while ensuring high-precision testing, it adapts to the needs of industrialized batch standardized testing, taking into account both testing accuracy and production efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall testing system structure of the present invention; Figure 2 This is a PCB simulation diagram of the adapter board for the test bench of this invention; Figure 3 This is a PCB simulation diagram of the L-shaped clamp adapter board of the present invention; Figure 4 This is a schematic diagram of the high and low temperature drift test results of the present invention. Detailed Implementation

[0017] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. This embodiment is based on the technical solution of the present invention and provides a detailed operation process and parameter configuration, but the scope of protection of the present invention is not limited to the following embodiment.

[0018] The present invention is based on the Huafeng Measurement and Control STS8200 series test system and the high and low temperature airflow temperature shock system to build a test platform. The overall test adapter structure includes a test bench adapter plate, an L-shaped fixture adapter plate, and a double-layer heat-insulating and sealed insulation box.

[0019] First, see Figure 1 , Figure 2 Based on the high and low temperature test chamber space, the external dimensions of the heat flow meter, and the interface parameters of the test bench, the overall size and layout of the adapter board PCB structure were determined. According to the standard pin layout of the test bench, a customized test bench adapter board 1 was designed. The board features 1mm standard pin pitch pads and flexible flat cable sockets, providing complete access to nine test ports: positive and negative power supplies for the operational amplifier chip, A / B dual-channel non-inverting inputs, A / B dual-channel inverting inputs, A / B dual-channel outputs, and ground. A large area of ​​copper plating was used to construct a physical interface that connects to the test bench's AGND interface, ensuring stable test signals and reliable grounding.

[0020] Also see Figure 3A custom-designed, elongated L-shaped clamp adapter board 4 extends the operational amplifier chip mounting area into an independent high and low temperature test chamber, completely physically isolating it from the ambient temperature test bench. The chip clamp is positioned on the bottom layer of the adapter board's PCB, avoiding direct impact from the vertical airflow of the heat shroud. Simultaneously, pre-installed filter capacitor pads are provided around the chip's power pads. The inclusion of filter capacitors effectively suppresses power ripple interference caused by long-distance traces, reducing transmission errors. The L-shaped corner structure allows for stress-free, suspended chip placement, completely avoiding the mechanical preload generated by the heat shroud and eliminating piezoresistive misalignment errors caused by micro-deformation of the chip.

[0021] Furthermore, the customized integrated sealed insulation box 5 uses a hard stainless steel plate as the core support frame to fully bear the pressure of the heat flow hood pressing, avoiding stress transmission to the fixture and chip; thickened silicone heat insulation pads are pasted on the outer side, bottom and upper bonding surface of the insulation box, and the inner side is fully covered with aluminum foil heat insulation board to form a double-layer heat insulation and sealing structure to maximize the isolation of internal and external heat exchange; the side wall of the insulation box has an assembly opening for adapting to the irregularly shaped fixture adapter plate. After the test assembly is completed, the opening is completely sealed with sealing plugs to ensure the airtightness of the cavity, so that the internal temperature field is uniform and stable, without temperature gradient and airflow disturbance.

[0022] The test bench adapter board 2 and the L-shaped fixture adapter board 4 are interconnected one-to-one via a two-end matched pluggable flexible flat cable 3. This allows for convenient assembly and disassembly, stable conduction, and rapid chip replacement, enabling batch testing. The dual-channel ultra-low temperature drift operational amplifier chip under test is fixed in the center mounting position of the fixture, ensuring that the chip is completely within the constant temperature zone in the center of the insulation box cavity.

[0023] The test parameters are configured as follows: operational amplifier chip supply voltage V+=2.5V, V-=-2.5V, common-mode input level VCM=0V; the low-temperature limit test temperature is set to -55℃, and the high-temperature limit test temperature is set to 125℃. During testing, the temperature sensor is placed in close contact with the surface of the chip under test, the airflow intensity of the heat flow meter is finely adjusted, and after the internal temperature of the cavity remains stable without fluctuation, dual-channel offset voltage test data are collected under low-temperature and high-temperature conditions.

[0024] The offset voltage temperature drift coefficient is calculated using the industry-standard temperature drift calculation formula: (1) Taking the measured data of the chip under test in this embodiment as an example: T Amin =-55℃, the dual-channel offset voltages are respectively V OS1 =-0.17μV and -1.07μV; T Amax =125℃, the dual-channel offset voltages are respectively VOS2 =0.74μV and 0.70μV, substituting into formula (1), we can calculate that the temperature drift coefficient of the offset voltage of channel A is 5nV / ℃ and the temperature drift coefficient of the offset voltage of channel B is 9.8nV / ℃, which accurately characterizes the ultra-low temperature drift performance of the device under test.

[0025] This invention fundamentally solves the technical drawbacks of traditional testing schemes, such as system temperature drift, mechanical stress interference, uneven temperature field, and low testing efficiency, through a collaborative design that integrates room temperature / high and low temperature physical isolation, stress-free suspended fixture design, double-layer constant temperature sealed cavity, and flexible rapid interconnection. It achieves high-precision, high-stability, and standardized batch testing of temperature drift parameters of dual-channel ultra-low temperature drift operational amplifiers.

[0026] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the technical concept and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A testing method for a dual-channel cryogenic operational amplifier, comprising using an integrated circuit testing system and a high-low temperature airflow temperature shock system to perform high-low temperature tests on the offset voltage temperature drift parameters of the dual-channel cryogenic operational amplifier, characterized in that, Includes the following steps: S1. Based on the pin definitions and interface layout of the integrated circuit test bench, customize a matching test bench adapter board to standardize the connection of all test signal ports of the operational amplifier chip. S2. A custom L-shaped fixture adapter board is designed according to the operational amplifier chip fixture package to extend the chip fixture and operational amplifier chip to one side, so that the chip fixture and operational amplifier chip can be placed in the high and low temperature test environment, and the normal temperature circuit area of ​​the test bench can be physically isolated from the high and low temperature test area. S3. Based on the external dimensions of the heat flow meter, a customized sealed insulation box is used to realize the high and low temperature test environment. The chip fixture and operational amplifier chip connected to one side of the L-shaped fixture adapter board are arranged in the center of the insulation box cavity to construct a sealed high and low temperature test cavity. S4. Set corresponding flexible flat cable sockets at the corresponding positions of the test bench adapter board and the L-shaped fixture adapter board, and realize the flexible interconnection of all test signals of the two adapter boards through pluggable flexible flat cables. S5. Start the high and low temperature airflow temperature shock system, set the high and low temperature limit test temperatures respectively, and after the temperature field inside the insulation box reaches a stable and balanced state, collect the low temperature offset voltage data and high temperature offset voltage data of the dual channels of the operational amplifier chip under test, substitute them into the temperature drift calculation formula to solve the offset voltage temperature drift coefficient, and complete the ultra-low temperature drift performance test of the device.

2. The test method for a dual-channel cryogenic operational amplifier according to claim 1, characterized in that, The test bench adapter board uses 1mm standard pin spacing for pads and flexible flat cable sockets, and fixedly leads out nine test ports, namely the positive and negative power supply terminals of the operational amplifier, the output terminal of channel A, the output terminal of channel B, the inverting input terminal of channel A, the inverting input terminal of channel B, the non-inverting input terminal of channel A, the non-inverting input terminal of channel B, and the ground terminal; the test bench adapter board uses a large area of ​​copper plating to build a solid surface, and is connected to the AGND interface of the test bench.

3. The test method for a dual-channel cryogenic operational amplifier according to claim 1, characterized in that, The sealed heat preservation box uses a hard stainless steel plate as the overall support frame. Thickened silicone heat insulation pads are pasted on the outer side, bottom and upper bonding surface of the heat preservation box, and the inner side of the heat preservation box is fully covered with aluminum foil heat insulation board. The side wall of the sealed heat preservation box has an assembly opening that matches the width of the L-shaped clamp adapter plate, and the assembly opening is equipped with a removable sealing plug.

4. The test method for a dual-channel cryogenic operational amplifier according to claim 1, characterized in that, The test parameters in step S5 are configured as follows: low temperature limit test temperature -55℃, high temperature limit test temperature 125℃, operational amplifier chip power supply voltage V+=2.5V, V-=-2.5V, common mode input level VCM=0V; during the test, the temperature sensor is attached to the surface of the chip under test, and the airflow intensity is adjusted until the cavity temperature is stable and undisturbed.

5. The test method for a dual-channel cryogenic operational amplifier according to claim 1 or 4, characterized in that, The formula for calculating the offset voltage temperature drift coefficient in step S5 is as follows: （1） Where: ΔV OS This is the offset voltage temperature drift coefficient, expressed in nV / ℃. V OS2 The offset voltage at the extreme high temperature is expressed in μV. V OS1 The offset voltage at the low-temperature limit temperature is expressed in μV. T max This refers to the high-temperature limit test temperature, expressed in °C. T min This is the low-temperature limit test temperature, in °C.

6. The test method for a dual-channel cryogenic operational amplifier according to claim 1, characterized in that, The pins at both ends of the pluggable flexible flat cable correspond one-to-one with the socket ports of the two adapter boards, enabling detachable signal conduction between the two adapter boards for rapid changeover testing of the chip under test.

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