Chip testing method, testing machine and program product

Abstract

This application discloses a chip testing method, a testing machine, and a program product. The chip testing method includes assigning a corresponding address to any chip according to a preset address allocation rule, so that after multiple chips are activated, each chip is assigned a corresponding address; after each chip is assigned a corresponding address, an FT test program is written to each chip based on the address assigned to each chip; after each chip is written with the FT test program, each chip executes the FT test program based on the address assigned to each chip, until all chips are running the FT test program to complete the testing of multiple chips. The chips on the test board can complete the FT test without disassembly. Therefore, after completing the reliability test, the FT test can be performed directly, improving testing efficiency. Furthermore, the absence of disassembly avoids mechanical damage to the chips, improving both product yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a chip testing method, testing machine, and program product. Background Technology

[0002] Before mass production, automotive-grade MCUs must pass reliability tests such as High Temperature Operating Life (HTOL), Endurance, High Temperature Bias Accelerated Test (BHAST), and Early Failure Rate (ELFR). Each test typically requires 240 samples to run continuously under high temperature and electrical conditions. After the reliability test is completed, the Financial Time Test (FT) is performed.

[0003] In existing testing solutions, the chip is installed in a removable manner on the chip socket. After the reliability test is completed, the chip is removed from the chip socket and transferred to the FT testing equipment for FT testing. This results in a lengthy and inefficient testing process. In addition, the chip is prone to mechanical damage during repeated insertion and removal, which affects the product yield and reliability. Summary of the Invention

[0004] The main technical problem solved by this invention is that after reliability testing is completed, the chip needs to be removed from the chip socket and transferred to the FT testing equipment for FT testing. This results in a lengthy and inefficient testing process, and the chip is prone to mechanical damage during repeated insertion and removal, which affects product yield and reliability.

[0005] According to a first aspect, one embodiment provides a chip testing method applied to a testing machine, the testing machine being used to test chips on a testing board, the testing board having multiple chips fixedly disposed thereon, the multiple chips being connected in series to form a daisy chain, the chip testing method comprising:

[0006] When all the chips are in the chained boot code loading complete state, a first activation signal is output to the input of the daisy chain so that the chips are activated in sequence. When any one of the chips is activated and no corresponding address is assigned, a corresponding address is assigned to the chip according to a preset address allocation rule so that after all the chips are activated, each chip is assigned a corresponding address.

[0007] After each of the plurality of chips is assigned a corresponding address, a first selection signal corresponding to the address of each chip is generated and broadcast sequentially based on the address assigned to each chip, so as to select the corresponding chip using the first selection signal, and write the FT test program into the program storage area of ​​each selected chip, until the FT test program is written into each of the plurality of chips.

[0008] After the FT test program is written to each of the plurality of chips, a second selection signal corresponding to the address of each chip is generated and broadcast sequentially based on the address assigned to each chip, so as to select the corresponding chip using the second selection signal, and to issue a test command to the selected chip each time, so that the selected chip executes the FT test program, until all the plurality of chips run the FT test program to complete the test of the plurality of chips.

[0009] In one embodiment, the step of outputting a first activation signal to the input of the daisy chain to sequentially activate the plurality of chips, and when any one of the plurality of chips is activated and has not been assigned a corresponding address, assigning a corresponding address to that chip according to a preset address allocation rule, so that after all the plurality of chips are activated, each chip is assigned a corresponding address, includes:

[0010] The first activation signal is sent to the first-level chip among the plurality of chips, and a corresponding address is assigned to the first-level chip according to the preset address allocation rule. Any one of the plurality of chips, after receiving the corresponding address, sends a second activation signal to the next connected chip and sends an indication signal to the test machine. The second activation signal is used to activate the next connected chip.

[0011] In response to the indication signal, the address corresponding to the next connected chip is assigned to the next connected chip according to the preset address allocation rule, until each chip is assigned a corresponding address.

[0012] In one embodiment, the preset address allocation rule is that multiple addresses are pre-stored, and the multiple chips correspond one-to-one with the multiple addresses, and one address is allocated sequentially from the multiple addresses each time.

[0013] In one embodiment, the step of sequentially generating and broadcasting a first selection signal corresponding to each chip address based on the address assigned to each chip, so as to select the corresponding chip using the first selection signal, and writing an FT test program into the program storage area of ​​each selected chip, until the FT test program is written to each of the plurality of chips, includes:

[0014] Based on the address assigned to each chip, the addresses assigned to each chip are traversed. When any address is reached, a first selection signal corresponding to that address is generated and broadcast to select the corresponding chip using the first selection signal corresponding to that address. The FT test program is then written into the program storage area of ​​the selected chip, so that the FT test program is written into each of the plurality of chips.

[0015] In one embodiment, writing the FT test program to the program memory area of ​​the selected chip includes:

[0016] When the program storage area of ​​the chip selected by the first selection signal stores an initial program, an erase command is output to the chip selected by the first selection signal so that the chip selected by the first selection signal erases its stored initial program; and after erasing its stored initial program, the FT test program is written into the program storage area of ​​the chip selected by the first selection signal.

[0017] When the program storage area of ​​the chip selected by the first selection signal does not contain an initial program, the FT test program is written into the chip selected by the first selection signal.

[0018] In one embodiment, after the FT test program is written to each of the plurality of chips, a second selection signal corresponding to the address of each chip is sequentially generated and broadcast based on the address assigned to each chip, so as to select the corresponding chip using the second selection signal, and to issue a test command to the selected chip each time, so that the selected chip executes the FT test program, until all the plurality of chips have run the FT test program to complete the test of the plurality of chips, including:

[0019] Based on the address assigned to each of the chips, the addresses assigned to each of the chips are traversed. When any address is reached, a second selection signal corresponding to that address is generated and broadcast to select the corresponding chip using the second selection signal corresponding to that address. A test instruction is output to the selected chip to make the selected chip run the FT test program to complete the test of the multiple chips.

[0020] In one embodiment, the plurality of chips are soldered onto the test board.

[0021] In one embodiment, when all the multiple chips are in the chained boot code loading completion state, a first activation signal is output to the input of the daisy chain to activate the multiple chips sequentially. Furthermore, when any one of the multiple chips is activated but has not been assigned a corresponding address, a corresponding address is assigned to that chip according to a preset address allocation rule, so that after all the multiple chips are activated, each chip is assigned a corresponding address. This process includes:

[0022] The test board is placed in a test chamber to perform reliability testing on the chips on the test board.

[0023] According to a second aspect, one embodiment provides a test machine, including: a processor for performing the chip testing method as described above.

[0024] According to a third aspect, one embodiment provides a program product including a computer program / instructions that, when executed by a processor, implement the chip testing method as described above.

[0025] According to the chip testing method, testing machine, and program product described in the above embodiments, multiple chips on the test board are arranged in a daisy chain. When all chips have completed the chain-style boot code loading, the testing machine outputs a first activation signal to the input of the daisy chain, activating the chips sequentially. During the activation process, an address is assigned to each chip. After address allocation, a first selection signal corresponding to each chip is broadcast sequentially based on the assigned address, and an FT test program is written to each chip. After the FT test program is written to each chip, a second selection signal corresponding to each chip is broadcast sequentially based on the assigned address. When a chip is selected by the second selection signal, a test command is sent to the selected chip to execute the FT test program. This process continues until all chips are running the FT test program, thus completing the FT test for multiple chips. Therefore, the chips on the test board can complete the FT test without disassembly. Thus, after reliability testing, FT testing can be performed directly without disassembly, improving testing efficiency. Furthermore, the absence of disassembly avoids mechanical damage to the chips, improving both product yield and reliability. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the installation of existing technology chips on a test board;

[0027] Figure 2 This is a flowchart illustrating a chip testing method according to one embodiment;

[0028] Figure 3 This is a schematic diagram of a chip mounted on a test board according to one embodiment. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0030] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0031] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0032] Those skilled in the art will know that automotive-grade MCUs (Microcontroller Units) must undergo reliability testing and Fourier Transmission Test (FT) before mass production. Specifically, the testing process includes... Figure 1 As shown, the chip is detachably mounted on the test board via a chip socket for initial reliability testing. Because the chip socket occupies a large area, only a small number of chips can be mounted on a single test board. If the four reliability tests are performed simultaneously, a large number of test boards and chip sockets are required, further increasing the number of environmental test chambers needed. Therefore, to save costs, reliability testing is conducted in a serial experimental manner. This involves setting up a group of chips, first performing a high-temperature operating life (HTOL) test, then performing an endurance test on the same group of chips after the HTOL test, and so on, sequentially completing the HTOL, endurance, high-temperature bias accelerated testing (BHAST), and early failure rate (ELFR) tests. After the reliability test is completed, the chip is removed from the chip socket and sent to a testing facility for final tests (FT tests) at room temperature, high temperature, and low temperature. While this method can complete reliability testing and FT testing, the testing process is lengthy and inefficient. The chip is prone to mechanical damage during repeated insertion and removal, which affects product yield and reliability. In addition, the chip socket is relatively expensive, which increases the cost.

[0033] Based on this, this application provides a chip testing method in which the chip 12 on the test board can complete the FT test without disassembly, which improves the testing efficiency and avoids mechanical damage to the chip 12 without disassembly, thus improving product yield and reliability.

[0034] This chip testing method is applied to a tester 11, which is used to test chips 12 on a test board. Multiple chips 12 are fixedly mounted on the test board and are connected in series to form a daisy chain. Specifically, as shown... Figure 3 As shown, multiple chips 12 are soldered onto the test board. Each chip 12 includes a test pin, a data receive pin (RX pin), a data transmit pin (TX pin), a boot mode switch pin (Boot0 pin), an enable signal receive pin (PA1 pin), an enable signal transmit pin (PB13 pin), and a test pin. When multiple chips 12 are connected, they are cascaded sequentially. The enable signal receive pin of the next-stage chip 12 is connected to the enable signal transmit pin of the previous-stage chip 12, and the enable signal receive pin of the first-stage chip 12 is connected to the test machine 11, forming a daisy chain. Multiple chips 12 have data receive pins connected to the data transmit pins of the UART port of the test machine 11, and their data transmit pins are also connected to the data receive pins of the UART port of the test machine 11. The boot mode switching pins of the multiple chips 12 are connected to the power supply terminal via a first switch 13, and to the ground terminal via a second switch 14. When the first switch 13 is on, the boot mode switching pins of the multiple chips 12 are connected to the power supply terminal; when the second switch 14 is on, they are connected to the ground terminal. Of course, the UART port can also be either an I2C interface or an SPI interface.

[0035] In some embodiments, the testing method includes the following steps:

[0036] S100. Place the test board in the test chamber to perform reliability testing on the chip 12 on the test board.

[0037] Specifically, all the chips 12 required for reliability testing are divided into four test groups. The chips 12 in each group are soldered onto a corresponding test board, and the chips 12 on each test board are connected in the daisy-chain manner described above. After soldering, a chain-type bootloader and reliability test code are programmed onto each chip 12. When programming the reliability test code, the chips 12 on each of the four test boards are programmed with the codes corresponding to HTOL (High Temperature Operating Life), Endurance (durability / durability life), BHAST (Biased Highly Accelerated Temperature and Humidity Stress Test), and ELFR (Early Life Failure Rate). The chips 12 on the same test board are programmed with the same test code.

[0038] Since the chip 12 is directly soldered onto the test board, there is no need to set up a socket, which reduces the cost. Compared with the method of mounting the chip 12 onto the test board through a socket, the soldering method allows more chips 12 to be soldered onto the same area of ​​the test board. Therefore, compared with the method of mounting the chip 12 onto the test board through a socket, the same number of chips 12 greatly reduces the number of test boards used. With the same number of test chambers, more chips 12 can be tested for reliability at the same time, which improves the testing efficiency.

[0039] In one embodiment, 20 chips 12 can be mounted on the test board using the chip socket mounting method, and 120 chips 12 can be mounted on the test board using the direct soldering method. Assuming that each test requires 240 chips 12, the chip socket mounting method requires 48 test boards for four tests. The test chamber can hold a maximum of 12 test boards at a time. Therefore, during reliability testing, each test is completed before proceeding to the next test. In contrast, the direct soldering method requires only 2 test boards for each test, and a total of 8 test boards are needed for four tests. Since the test chamber can hold a maximum of 12 test boards, all 8 test boards can be placed in the test chamber at the same time, and the four tests (HTOL, Endurance, BHAST, and ELFR) can be performed in parallel, significantly improving testing efficiency. During the reliability test of the chip 12, the first switch 13 is turned off and the second switch 14 is turned on, so that the boot mode switching pin of the chip 12 is connected to the ground terminal through the second switch 14.

[0040] In some embodiments, such as Figure 2 As shown, the chip testing method also includes the following steps:

[0041] S101. Assign a corresponding address to any chip 12 according to the preset address allocation rules, so that after multiple chips 12 are activated, each chip 12 is assigned a corresponding address.

[0042] In this step, before assigning the corresponding address to chip 12, the test machine 11 can control the first switch 13 on each chip 12 to close and the second switch 14 to open, so that the boot mode switching pin of chip 12 is connected to the power supply terminal through the first switch 13. Multiple chips 12 on the test board are in the chain boot loading completed state (that is, the chain bootloader placed in Flash (non-volatile memory) has been completed). In other words, each chip 12 on the test board is in the chain boot loading completed state.

[0043] After all the chips 12 on the test board are in the chain-driven boot loading state, the test machine 11 outputs a first activation signal to the input of the daisy chain, so that the chips 12 are activated sequentially. When any one of the chips 12 is activated and has not been assigned a corresponding address, the test machine 11 assigns a corresponding address to the chip 12 according to a preset address allocation rule. Thus, after all the chips 12 are activated, each chip 12 is assigned a corresponding address. The enable signal input of the first-level chip 12 is the input of the daisy chain, and different chips 12 have different addresses.

[0044] For any one of the multiple chips 12, after the chip 12 is written, it outputs an indication signal to the test machine 11, and at the same time outputs a second activation signal to the next-level chip 12 through its enable signal output pin (the second activation signal is output to the next-level chip 12 through its enable signal output pin is a pull-high enable signal output pin). When the next-level chip 12 is connected, the second activation signal activates the next-level chip 12. In response to the indication signal, the test machine 11 assigns the address of the next connected chip 12 according to the preset address allocation rule, until each chip 12 is assigned a corresponding address.

[0045] Specifically, during address allocation, the test machine 11 sends a first activation signal to the first-level chip 12 in the daisy chain, activating the first-level chip 12. That is, the test machine 11 sends the first activation signal to the enable signal receiving pin of the first-level chip 12 via a pin connected to the enable signal receiving pin of the first-level chip 12, thus activating the first-level chip 12. Simultaneously, the test machine 11 broadcasts a blank device discovery command. Since the first-level chip 12 is activated and has not been written with an address, it responds to the blank device discovery command broadcast by the test machine 11, causing the test machine 11 to issue an address through its data transmission pin according to a preset address allocation rule. The first-level chip 12 receives this address through its data reception pin and uses it as its own address. After the address of the first-level chip 12 is written, the first-level chip 12 sends a second activation signal to activate the second-level chip 12 and sends an indication signal to the test machine 11, causing the test machine 11 to continue broadcasting the blank device discovery command. The second-level chip 12 responds to the blank device discovery command broadcast by the test machine 11. The test machine 11 sends an address through its data transmission pin according to the preset address allocation rule. The second-level chip 12 receives this address through its data reception pin and uses it as its own address. After the second-level chip 12 writes the address, it sends a second activation signal to activate the third-level chip 12 and sends an indication signal to the test machine 11, causing the test machine 11 to continue broadcasting the blank device discovery command and begin writing the address to the third-level chip 12. In this way, the test machine 11 writes the corresponding address to each of the multiple chips 12 according to the preset address allocation rule.

[0046] Therefore, it can be seen that the chip testing method can assign a corresponding address to each chip 12 when multiple chips 12 are connected in parallel. In contrast, conventional buses have address conflicts or competition when multiple chips 12 are connected in parallel, making it difficult to implement independent programming and testing of each chip 12 on a single board.

[0047] In some embodiments, the preset allocation rule is that multiple addresses are pre-stored, and multiple chips 12 correspond one-to-one with multiple addresses. One address is allocated sequentially from the multiple addresses each time. Specifically, the test machine 11 pre-stores multiple addresses, and multiple chips 12 correspond one-to-one with multiple addresses. For example, when there are 120 chips 12, when writing addresses to the multiple chips 12 on the test board, the test machine 11 can pre-store 120 addresses (000-119). Starting with 000 as the first address issued, the corresponding address is written sequentially to each of the 120 chips 12. Specifically, the address written to the first-level chip 12 is 000, the address written to the second-level chip 12 is 001, the address written to the third-level chip 12 is 002, ..., and the address written to the last-level chip 12 is 119.

[0048] S102. After each chip 12 is assigned a corresponding address, the FT test program is written to each chip 12 based on the address assigned to each chip 12.

[0049] In this step, after each of the multiple chips 12 is assigned a corresponding address, a first selection signal corresponding to the address of each chip 12 is generated and broadcast sequentially based on the address assigned to each chip 12, so as to select the corresponding chip 12 using the first selection signal, and write the FT test program into the program storage area of ​​each selected chip 12, until the FT test program is written into each of the multiple chips 12.

[0050] In some embodiments, after address allocation is completed, based on the address allocated to each chip 12, the addresses allocated to each chip 12 are traversed. When any address is reached, a first selection signal corresponding to that address is generated and broadcast. This first selection signal is used to select the corresponding chip 12, and an FT test program is written to the program storage area of ​​the selected chip 12, so that each of the multiple chips 12 has an FT test program. Specifically, after each of the multiple chips 12 has its corresponding address allocated, an FT test program is further written to the program storage area of ​​each chip 12. In this embodiment, the test machine 11 can sequentially traverse one address at a time, starting from 000, according to a pre-stored set of addresses (i.e., based on the address allocated to each chip 12). When any address is reached, the test machine 11 generates and broadcasts the first selection signal corresponding to that address via a data transmission pin. The chip 12 corresponding to that address can match the first selection signal and select the corresponding chip 12 through the first selection signal. After the first selection signal selects chip 12 (target chip 12), it checks whether there is an initial program in the main program area of ​​the Flash of the target chip 12 (the initial program can be reliability test code). If there is an initial program in the main program area, the target chip 12 replies with ACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port and jumps to the main program area, erases the previously burned initial program, and writes the FT test program into the target chip 12. If there is no initial program in the main program area, the target chip 12 replies with NACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port but does not jump to the main program area. The test machine 11 writes the FT test program into the target chip 12.

[0051] For example, when the test machine 11 reaches address 000, it generates and broadcasts the first selection signal corresponding to address 000 to select the first-level chip 12. It checks whether there is code in the main program area of ​​the Flash memory of the first-level chip 12. If there is code in the main program area, the first-level chip 12 replies with ACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port and jumps to the main program area, erases the reliability test code previously burned into the first-level chip 12, and writes the FT test program into the first-level chip 12. If there is no code in the main program area, the first-level chip 12 replies with NACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port but does not jump to the main program area. The test machine 11 writes the FT test program into the first-level chip 12. After the first-level chip 12 is written with the FT test program, the test machine 11 traverses to address 001. The test machine 11 generates and broadcasts the first selection signal corresponding to address 001 to select the second-level chip 12. It checks whether there is code in the main program area of ​​the Flash of the second-level chip 12. If there is code in the main program area, the second-level chip 12 replies with ACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port and jumps to the main program area, erases the reliability test code previously burned into the second-level chip 12, and writes the FT test program into the second-level chip 12. If there is no code in the main program area, the second-level chip 12 replies with NACK through the data transmission pin. The test machine 11 switches the UART port to the SWD port but does not jump to the main program area. The test machine 11 writes the FT test program into the second-level chip 12. In this manner, until traversing to 119, the test machine 11 generates and broadcasts the first selection signal corresponding to address 119 to select the last stage chip 12, and writes the FT test program into the chip 12 corresponding to address 119, so as to write the FT test program into each of the multiple chips 12.

[0052] In some embodiments, when writing the FT program, the chip 12 that is not selected by the first selection signal directly enters sleep mode to save power consumption.

[0053] S103. After writing the FT test program to each of the multiple chips 12, each chip 12 executes the FT test program based on the address assigned to each chip 12, until all multiple chips 12 run the FT test program to complete the test of the multiple chips 12.

[0054] In this step, after the FT test program is written to each of the multiple chips 12, a second selection signal corresponding to the address of each chip 12 is generated and broadcast sequentially based on the address assigned to each chip 12, so as to select the corresponding chip 12 using the second selection signal, and to issue a test command to the selected chip 12 each time, so that the selected chip 12 executes the FT test program, until all the multiple chips 12 run the FT test program to complete the test of the multiple chips 12.

[0055] In some embodiments, after the FT test program is written to each chip 12, based on the address assigned to each chip 12, the addresses assigned to each chip 12 are traversed. When any address is traversed, a second selection signal corresponding to any address is generated and broadcast, so as to select the corresponding chip 12 using the second selection signal corresponding to any address; and a test instruction is output to the selected chip 12 so that the selected chip 12 runs the FT test program to complete the test of multiple chips 12. Specifically, the test machine 11 can sequentially traverse one address at a time, starting from 000, according to a pre-stored set of addresses (i.e., based on the address assigned to each chip 12). When traversing to any address, the test machine 11 generates and broadcasts a second selection signal corresponding to that address via its data transmission pin. The chip 12 corresponding to that address can match the second selection signal, select the corresponding chip 12 through the second selection signal, and send a test command to the selected chip 12 via its data transmission pin, causing the selected chip 12 to run the FT test program. After the selected chip 12 completes the FT test program, it can return the test result to the test machine 11. In response to the test result, the test machine 11 can continue to traverse to the next address, and so on, to complete the testing of multiple chips 12.

[0056] For example, the test machine 11 iterates to 000, generates and broadcasts the second selection signal corresponding to address 000 to select the first-level chip 12, sends a test command to the first-level chip 12, and the first-level chip 12 starts running the FT test program. After the first-level chip 12 finishes running the FT test program, it returns the test result to the test machine 11. In response to the returned test result, the test machine 11 iterates to 001, generates and broadcasts the second selection signal corresponding to address 001 to select the second-level chip 12, sends a test command to the second-level chip 12, and the second-level chip 12 starts running the FT test program. After the second-level chip 12 finishes running the FT test program, it returns the test result to the test machine 11. In response to the returned test result, the test machine 11 iterates to 002 and starts testing the third-level chip 12. In this manner, until traversing to 119, the test machine 11 generates and broadcasts the second selection signal corresponding to address 119 to select the last-stage chip 12, causing the chip 12 corresponding to address 119 to run the FT test program, thereby enabling multiple chips 12 to complete the test.

[0057] In some embodiments, when chip 12 runs the FT test program, chip 12 that is not selected by the second selection signal directly enters sleep mode to save power consumption.

[0058] In some embodiments, this application also provides a test machine 11, including a processor for executing the chip testing method described above. Specific details are as described in the detailed embodiment of the chip testing method above, and will not be repeated here.

[0059] In some embodiments, this application also provides a program product, including a computer program / instructions, which, when executed by a processor, implement the chip testing method described above. Specific details are as described in the detailed embodiment of the chip testing method above, and will not be repeated here.

[0060] In summary, this application provides a chip testing method, a testing machine 11, and a program product, which have the following beneficial effects:

[0061] When installing the test board on chip 12, there is no need to set up chip sockets, which reduces costs and the number of test boards. With a limited number of test chambers, more chips 12 can be tested for reliability at the same time.

[0062] After the reliability test is completed, the FT test can be performed without disassembling the chip 12, which improves the testing efficiency. Moreover, the absence of disassembly avoids mechanical damage to the chip 12, thus improving both product yield and reliability.

[0063] Achieving a seamless connection between reliability testing and FT testing reduces manual intervention and thus lowers labor costs;

[0064] The daisy-chain connection method ensures the integrity of the link signal. The test machine 11 can dynamically discover and assign addresses to all chips 12. As long as the test board can continue to install chips 12, it can support the expansion of any number of chips 12.

[0065] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0066] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0067] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A chip testing method, characterized in that, The method is applied to a testing machine used to test chips on a testing board. The testing board has multiple chips fixedly mounted on it, and these chips are connected in series to form a daisy chain. The chip testing method includes: When all the chips are in the chained boot code loading complete state, a first activation signal is output to the input of the daisy chain so that the chips are activated in sequence. When any one of the chips is activated and no corresponding address is assigned, a corresponding address is assigned to the chip according to a preset address allocation rule so that after all the chips are activated, each chip is assigned a corresponding address. After each of the plurality of chips is assigned a corresponding address, a first selection signal corresponding to the address of each chip is generated and broadcast sequentially based on the address assigned to each chip, so as to select the corresponding chip using the first selection signal, and write the FT test program into the program storage area of ​​each selected chip, until the FT test program is written into each of the plurality of chips. After the FT test program is written to each of the plurality of chips, a second selection signal corresponding to the address of each chip is generated and broadcast sequentially based on the address assigned to each chip, so as to select the corresponding chip using the second selection signal, and to issue a test command to the selected chip each time, so that the selected chip executes the FT test program, until all the plurality of chips run the FT test program to complete the test of the plurality of chips.

2. The chip testing method as described in claim 1, characterized in that, The first activation signal is output to the input of the daisy chain to activate the plurality of chips sequentially. When any one of the chips is activated but has not been assigned a corresponding address, a corresponding address is assigned to that chip according to a preset address allocation rule, so that after all the chips are activated, each chip is assigned a corresponding address. This includes: The first activation signal is sent to the first-level chip among the plurality of chips, and a corresponding address is assigned to the first-level chip according to the preset address allocation rule. Any one of the plurality of chips, after receiving the corresponding address, sends a second activation signal to the next connected chip and sends an indication signal to the test machine. The second activation signal is used to activate the next connected chip. In response to the indication signal, the address corresponding to the next connected chip is assigned to the next connected chip according to the preset address allocation rule, until each chip is assigned a corresponding address.

3. The chip testing method as described in claim 1 or 2, characterized in that, The preset address allocation rule is that multiple addresses are pre-stored, and the multiple chips correspond one-to-one with the multiple addresses. One of the multiple addresses is allocated sequentially each time.

4. The chip testing method as described in claim 1 or 2, characterized in that, Based on the address assigned to each chip, a first selection signal corresponding to each chip address is sequentially generated and broadcast to select the corresponding chip using the first selection signal, and an FT test program is written into the program storage area of ​​each selected chip, until the FT test program is written into each of the plurality of chips, including: Based on the address assigned to each chip, the addresses assigned to each chip are traversed. When any address is reached, a first selection signal corresponding to that address is generated and broadcast to select the corresponding chip using the first selection signal corresponding to that address. The FT test program is then written into the program storage area of ​​the selected chip, so that the FT test program is written into each of the plurality of chips.

5. The chip testing method as described in claim 4, characterized in that, Writing the FT test program to the program memory area of ​​the selected chip includes: When the program storage area of ​​the chip selected by the first selection signal stores an initial program, an erase command is output to the chip selected by the first selection signal so that the chip selected by the first selection signal erases its stored initial program; and after erasing its stored initial program, the FT test program is written into the program storage area of ​​the chip selected by the first selection signal. When the program storage area of ​​the chip selected by the first selection signal does not contain an initial program, the FT test program is written into the chip selected by the first selection signal.

6. The chip testing method as described in claim 1 or 2, characterized in that, After the FT test program is written to each of the plurality of chips, a second selection signal corresponding to the address of each chip is sequentially generated and broadcast based on the address assigned to each chip. This second selection signal is used to select the corresponding chip, and a test command is issued to each selected chip to execute the FT test program. This process continues until all the plurality of chips have run the FT test program, thus completing the test of the plurality of chips. The process includes: Based on the address assigned to each of the chips, the addresses assigned to each of the chips are traversed. When any address is reached, a second selection signal corresponding to that address is generated and broadcast to select the corresponding chip using the second selection signal corresponding to that address. A test instruction is output to the selected chip to make the selected chip run the FT test program to complete the test of the multiple chips.

7. The chip testing method as described in claim 1 or 2, characterized in that, The multiple chips are soldered onto the test board.

8. The chip testing method as described in claim 7, characterized in that, When all the chips are in the chained boot code loading complete state, a first activation signal is output to the input of the daisy chain to activate the chips sequentially. Furthermore, when any one of the chips is activated but has not been assigned a corresponding address, a corresponding address is assigned to that chip according to a preset address allocation rule, so that after all the chips are activated, each chip has a corresponding address. This process includes: The test board is placed in a test chamber to perform reliability testing on the chips on the test board.

9. A testing machine, characterized in that, include: A processor for executing the chip testing method as described in any one of claims 1 to 6.

10. A program product, characterized in that, It includes a computer program / instruction, characterized in that, when the computer program / instruction is executed by a processor, it implements the chip testing method as described in any one of claims 1 to 6.

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