A multi-channel adaptive closed-loop detection method and system for automotive-grade chips

Abstract

This invention relates to a multi-channel adaptive closed-loop testing method and system for automotive-grade chips, belonging to the field of automotive-grade chip testing technology. The method includes: analyzing the packaging structure characteristics of the automotive-grade chip under test; reconstructing the mapping relationship between acquisition channels and pins, range matching relationship, and sampling rate adaptation parameters based on the packaging structure characteristics; performing spatiotemporal aligned sampling on each test channel to acquire electrical test data; extracting features from the electrical test data, including transient overcurrent, leakage drift, and timing jitter features, and comparing them with preset judgment thresholds to identify latent fault characteristics; when a latent fault characteristic is identified, mapping its type to the corresponding chip failure physical mechanism, determining the test excitation adjustment strategy and reconstructing the test excitation parameters, and returning to re-acquisition; looping until the convergence condition is met, terminating, and outputting the test results. This invention effectively captures latent faults such as transient overcurrent, leakage drift, and timing jitter in automotive-grade chips, improving detection accuracy and efficiency.

Description

Technical Field

[0001] This invention belongs to the field of automotive-grade chip testing technology, specifically relating to a multi-channel adaptive closed-loop testing method and system for automotive-grade chips. Background Technology

[0002] With the development of intelligent and electric automotive electronic systems, the market demand for automotive-grade chips continues to grow. Automotive-grade chips must meet stringent reliability standards such as AEC-Q100, and their testing directly affects the safety and lifespan of the entire vehicle. Currently, automotive-grade chip testing mainly relies on automated test equipment (ATE) to complete electrical parameter testing. While existing ATE equipment is relatively mature in routine steady-state parameter testing, it still faces the following prominent problems when dealing with the increasingly complex testing requirements of automotive-grade chips: First, there is insufficient packaging compatibility. Automotive-grade chips come in various packaging forms, including QFN (Quad Flat No-lead), BGA (Ball Grid Array), and die, with significant differences in pin count, spacing, and signal characteristics. Existing ATE equipment typically uses fixed channel configurations and fixed range designs. When dealing with chips in different packages, manual replacement of test fixtures or rewiring is required, resulting in low configuration efficiency and susceptibility to human errors such as poor contact, making it difficult to achieve efficient compatibility testing for chips in various packages.

[0003] Second, the accuracy of multi-channel synchronous detection is limited. The high-speed interface of automotive-grade chips has extremely high requirements for the timing consistency between multiple channels. Existing equipment often suffers from clock deviation or triggering asynchrony issues in multi-channel acquisition, which leads to distortion of timing correlation analysis between channels and makes it impossible to accurately identify cross-channel coupling faults.

[0004] Third, the detection mode is open-loop analysis, resulting in a high rate of missed detection for latent faults. Traditional detection methods employ an open-loop mode of "one-time excitation, single-acquisition," where the test excitation parameters remain constant throughout the detection process, and only static threshold judgments are performed on the acquired data. This mode cannot capture the progressive and transient latent faults unique to automotive-grade chips, such as transient overcurrent, leakage drift, and timing jitter. For example, timing degradation caused by hot carrier effects and leakage current drift caused by gate oxide defects exhibit abnormal characteristics only under specific excitation conditions or during dynamic changes. Fixed-excitation open-loop detection is difficult to effectively identify these faults, leading to early-failure chips flowing into downstream processes.

[0005] Fourth, there is a lack of a closed-loop adjustment mechanism that correlates with the physical mechanisms of failure. While existing ATE equipment possesses basic data feedback capabilities, its feedback logic remains at the level of "abnormal alarm - manual intervention," failing to establish a mapping relationship between abnormality types and chip failure physical mechanisms. This prevents the adaptive adjustment of test excitation parameters based on abnormal characteristics to approximate the fault threshold. This non-adaptive detection method struggles to distinguish between different failure mechanisms (such as electromigration and hot carrier injection, both of which manifest as timing anomalies) and cannot verify the reproducibility of the fault through excitation adjustment, resulting in insufficient detection depth.

[0006] In summary, existing automotive-grade chip testing technologies have significant shortcomings in terms of package compatibility, multi-channel synchronization accuracy, open-loop detection misses, and failure physics-driven closed-loop adjustment. There is an urgent need for an automotive-grade chip testing method and system that can dynamically adapt to various packages, has high-precision multi-channel synchronous acquisition capabilities, and drives adaptive closed-loop adjustment based on failure physics mechanisms. Summary of the Invention

[0007] To address the aforementioned problems in the existing technology, this invention provides a multi-channel adaptive closed-loop detection method and system for automotive-grade chips. The objective of this invention can be achieved through the following technical solutions: A method for multi-channel adaptive closed-loop detection of automotive-grade chips includes the following steps: S1: Analyze the packaging structure characteristics of the automotive-grade chip under test, reconstruct the mapping relationship between the acquisition channel and the pin, the range matching relationship and the sampling rate adaptation parameters based on the packaging structure characteristics; and perform spatiotemporal aligned sampling of each test channel through a global synchronous clock reference to obtain electrical test data. S2: Extract features from the electrical test data, extract transient overcurrent feature values, leakage drift feature values, and timing jitter feature values, and compare each feature value with a preset judgment threshold set based on automotive standards to identify hidden fault features; S3: When a latent fault feature is identified, the type of the latent fault feature is mapped to the corresponding chip failure physical mechanism. Based on the failure physical mechanism, a test stimulus adjustment strategy is determined. The test stimulus parameters are reconstructed according to the adjustment strategy, and the process returns to step S1 for re-acquisition. S4: The closed-loop detection loop is formed by steps S1 to S3. The loop is executed until the preset convergence condition is met and then the detection result is output.

[0008] Specifically, the failure physical mechanism mapping relationship includes at least one of the following correspondences: The transient overcurrent anomaly corresponds to the failure physical mechanism of electromigration effect or hot carrier effect, and the test excitation adjustment strategy corresponding to this anomaly is to reduce the test voltage or limit the test current. The leakage drift anomaly corresponds to the physical mechanism of gate oxide layer defects or interface state trap failure, and the test excitation adjustment strategy corresponding to this anomaly is to adjust the bias voltage or change the test frequency. Timing jitter anomalies correspond to physical mechanisms of power integrity or clock distribution path defects, and the corresponding test stimulus adjustment strategies are to adjust the position of the test timing edge or change the load conditions.

[0009] Specifically, the package type corresponding to the package structure features includes at least one of QFN package, BGA package, and bare die; the mapping relationship between the acquisition channel and the pins is different for different package types: For QFN packages, the mapping relationship is that the acquisition channel is connected to the corresponding peripheral pins of the QFN package; For BGA packages, the mapping relationship is that the acquisition channel is connected to the corresponding ball grid array pin of the BGA package; For bare dies, the mapping relationship is that the acquisition channel is connected to the corresponding probe test point of the bare die.

[0010] Specifically, the electrical test data includes transient current parameters, static leakage current sequence, and edge transition time parameters for each test channel; The transient current parameter is a current timing signal continuously acquired at a set sampling rate within a preset detection time window; the static leakage current sequence is a sequence of steady-state leakage current values ​​acquired continuously for a preset number of detection cycles under static bias conditions; the edge transition time parameter is the moment when the rising or falling edge of the voltage signal of each test channel crosses the reference level.

[0011] Specifically, the transient overcurrent characteristic values ​​include the current spike amplitude and the current change rate. The current spike amplitude is the maximum instantaneous value of the transient current parameter within the detection time window, and the current change rate is the amount of change of the transient current parameter per unit time. When the current spike amplitude exceeds a preset transient overcurrent threshold and / or the current change rate exceeds a preset current change rate threshold, a transient overcurrent anomaly is determined to exist.

[0012] Specifically, the leakage current drift characteristic value is the drift amount of the static leakage current sequence within a consecutive preset number of detection cycles. The drift amount is the absolute value of the difference between the last cycle value and the first cycle value in the static leakage current sequence. When the absolute value of the difference exceeds the preset leakage current drift threshold, it is determined that there is a leakage current drift anomaly.

[0013] Specifically, the timing jitter characteristic value is the absolute value of the time deviation of the edge transition time between adjacent detection cycles; the absolute value of the time deviation is the absolute value of the difference between the edge transition time in the current detection cycle and the corresponding edge transition time in the previous detection cycle; when the absolute value of the time deviation exceeds the preset timing jitter threshold, it is determined that there is a timing jitter abnormality.

[0014] Specifically, the preset judgment thresholds based on automotive-grade standards include transient overcurrent thresholds, leakage drift thresholds, and timing jitter thresholds; the transient overcurrent thresholds include current spike amplitude thresholds and current change rate thresholds; the leakage drift thresholds are static leakage current drift thresholds; and the timing jitter thresholds are edge transition time deviation thresholds. Each threshold is set according to automotive-grade chip reliability testing specifications, and different threshold values ​​correspond to different models and / or different application levels of automotive-grade chips.

[0015] Specifically, the test excitation parameters include at least one of the following: test voltage amplitude, test current limit, and test timing edge position; The test voltage amplitude includes the test power supply voltage and / or the test signal voltage amplitude, the test current limit is the maximum output current limit of the test excitation source, and the test timing edge position is the delay time of the rising edge and / or falling edge of the test excitation signal relative to the reference clock. When reconstructing the test voltage amplitude, the reconstruction amplitude shall not exceed the preset voltage safety margin range; when reconstructing the test current limit, the reconstruction amplitude shall not exceed the preset current safety margin range; and when reconstructing the test timing edge position, the reconstruction step size shall not exceed the preset step size upper limit.

[0016] Specifically, the preset convergence condition is at least one of the following conditions: No abnormality was detected in any of the closed-loop detection cycles that were performed for a preset number of consecutive times; The closed-loop detection loop has reached its preset maximum number of iterations. The rate of change of each feature value between two consecutive closed-loop detection cycles is lower than the preset rate of change threshold.

[0017] Specifically, a waiting interval is provided between two adjacent cycles of the closed-loop detection loop, and the length of the waiting interval is negatively correlated with the degree of abnormality: the higher the degree of abnormality, the shorter the waiting interval; the lower the degree of abnormality, the longer the waiting interval.

[0018] Specifically, an automotive-grade chip multi-channel adaptive closed-loop detection system includes a processor for performing the method as described in any one of claims 1 to 11.

[0019] The beneficial effects of this invention are as follows: This invention achieves adaptive topology reconstruction for data acquisition, improving compatibility across multiple packages and synchronization accuracy across multiple channels. By analyzing package structure characteristics, it reconstructs the mapping relationship between acquisition channels and pins, range matching relationships, and sampling rate adaptation parameters. Differentiated mapping strategies are adopted for different packages such as QFN, BGA, and bare die, eliminating the need for manual fixture replacement or rewiring and significantly reducing test switching time. Simultaneously, a global synchronous clock reference is used to perform spatiotemporally aligned sampling of each test channel, effectively avoiding timing correlation analysis distortion caused by clock deviations or trigger asynchrony, and accurately identifying cross-channel coupling faults.

[0020] This invention extracts features from three types of automotive-grade latent faults, significantly reducing the missed detection rate of early failures. Specifically, it defines detailed calculation methods and judgment logic for three types of automotive-grade latent faults: transient overcurrent, leakage drift, and timing jitter. Transient overcurrent is judged using a dual-condition joint determination of current peak amplitude and current change rate; leakage drift is determined using the endpoint difference method of the static leakage current sequence within a continuously preset detection cycle; and timing jitter is detected by the cycle-by-cycle deviation at the edge transition times of adjacent cycles. This solution effectively solves the problem of high missed detection rate of latent faults in traditional ATE equipment operating in open-loop mode.

[0021] This invention establishes an excitation reconstruction mechanism driven by failure physics mechanisms to achieve intelligent detection and fault reproducibility. It constructs a complete mapping library of "anomaly type - failure physics mechanism - adjustment strategy": transient overcurrent is mapped to electromigration or hot carrier effects, corresponding to reducing test voltage or limiting test current; leakage drift is mapped to gate oxide defects or interface state traps, corresponding to adjusting bias voltage or changing test frequency; timing jitter is mapped to power integrity or clock distribution defects, corresponding to adjusting test timing edge positions or changing load conditions. When a latent fault characteristic is identified, the system maps it to the failure physics mechanism, determines the adjustment strategy accordingly, and reconstructs the test excitation parameters, forming a closed-loop detection cycle. Compared to the static "anomaly alarm - manual intervention" mode of existing ATE equipment, this invention can dynamically approach the fault critical point and verify fault reproducibility, significantly improving detection depth.

[0022] This invention establishes an automotive-grade standard threshold system and safety constraints to ensure the reliability of automotive-grade testing. Based on the AEC-Q100 standard, this invention sets various thresholds, with different threshold values ​​corresponding to different models and application levels, achieving differentiated testing. During the test stimulus reconstruction process, multiple safety constraints are set, including voltage safety margin, current safety margin, and step size upper limit, to avoid chip damage caused by excessive reconstruction. Simultaneously, multiple convergence conditions are preset, such as multiple consecutive anomalies, reaching the upper limit of the number of cycles, and the characteristic value change rate being lower than the threshold, balancing comprehensive testing with efficiency to meet the "zero defect" quality target of automotive-grade chips. Attached Figure Description

[0023] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0024] Figure 1 This is an overall flowchart of the method of the present invention; Figure 2 This is a diagram showing the mapping relationship between the failure physical mechanisms of the present invention; Figure 3 This is a schematic diagram of the multi-package adaptive configuration of the present invention; Figure 4 This is a flowchart of the three types of automotive-grade feature extraction and determination process of the present invention. Detailed Implementation

[0025] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided.

[0026] Example 1: Joint Detection of Transient Overcurrent and Timing Jitter in BGA-Packaged Automotive-Grade MCU Chips See Figure 1 , Figure 2 , Figure 3 and Figure 4 This embodiment uses the mass production electrical testing of a BGA-packaged automotive-grade MCU chip (model XC-32F427, operating temperature grade 1, -40℃ to 125℃) as an application scenario to explain in detail the complete execution process of the method of the present invention.

[0027] Step S1: Encapsulate feature parsing, acquire topology reconstruction and multi-channel spatiotemporal alignment sampling Before testing begins, the operator places the chip to be tested into the test socket on the testing platform. The package identification module obtains the chip's package structure characteristics through one of the following methods: (1) The operator selects the “BGA package” option through the host computer interface; (2) The system automatically reads chip packaging information through optical recognition or RFID tags.

[0028] In this embodiment, the system obtains the package structure characteristic as "BGA-256", which is 256 ball grid array pins. The acquisition configuration module performs acquisition topology reconstruction according to the preset package-channel mapping table: Mapping relationship between acquisition channels and pins: The BGA-256 package has a total of 256 pins, including 32 power pins, 48 ​​ground pins, and 176 signal pins. The system connects the 176 acquisition channels one-to-one with the 176 signal ball grid pins of the BGA package, and the 32 power pins and 48 ground pins are grouped and connected to the auxiliary channels according to preset rules.

[0029] Range matching relationship: According to the datasheet of this chip model, the signal pin voltage range is 0~3.6V, and the system configures the range of each signal channel to 0~5V (with margin); the power supply pin voltage is 3.3V, and is configured to a range of 0~10V.

[0030] Sampling rate adaptation parameters: The main frequency of this MCU is 120MHz. In order to accurately capture the timing jitter of high-speed signal edges, the system is configured with a sampling rate of 1GSa / s (billions of samples per second).

[0031] After the topology reconstruction is completed, the multi-channel acquisition system applies a global synchronization clock reference to all 176 signal test channels and simultaneously sends acquisition start signals through clock synchronization triggers to establish a spatiotemporal alignment relationship of sampling time between each test channel, ensuring that each channel starts data acquisition at the same time.

[0032] Within a complete detection cycle (100μs), the system performs correlated sampling, collecting the following three types of electrical test data from each test channel: Transient current parameters: The current timing signals of each signal pin are continuously acquired at a sampling rate of 1GSa / s within a 100μs time window; Static leakage current sequence: Under static bias conditions (all input pins connected to fixed level, output pins floating), the steady-state leakage current value is continuously collected for 5 detection cycles (100μs per cycle, 500μs interval between cycles). Edge transition time parameter: Collect the time when the rising and falling edges of the voltage signal of each signal pin cross the reference level (1.8V) during the output transition.

[0033] Step S2: Identification of Latent Fault Characteristics The feature analysis module performs three types of latent fault feature identification on the spatiotemporally aligned electrical test data: (1) Transient overcurrent feature identification For test channel 37 (which is the chip's PWM output pin), the system extracts the following two sub-features: Current spike amplitude: Within a 100μs time window, the maximum instantaneous value of the transient current parameter is 45mA; Rate of change of current: During the process of the current rising from 0mA to 45mA, the change in current per unit time (1ns) is 45mA / ns.

[0034] The system compares the current spike amplitude of 45mA with the preset transient overcurrent amplitude threshold (set to 35mA according to the AEC-Q100 specification for this chip model)—45mA > 35mA, the amplitude condition meets the anomaly judgment; the current change rate of 45mA / ns is compared with the preset current change rate threshold (set to 40mA / ns)—45mA / ns > 40mA / ns, the change rate condition also meets the anomaly judgment. Using an AND / OR dual-condition joint judgment logic (amplitude exceeding the threshold and / or change rate exceeding the threshold determines an anomaly), the system identifies a latent transient overcurrent fault characteristic in test channel 37. If only the amplitude exceeds the threshold but the change rate does not, or only the change rate exceeds the threshold but the amplitude does not, it is also identified as a latent transient overcurrent fault characteristic.

[0035] (2) Leakage drift characteristic identification For test channel 89 (the output detection pin of the chip's analog power management unit), the system continuously collected the static leakage current value for five detection cycles under static bias conditions: cycle 1 was 2.1nA, cycle 2 was 2.3nA, cycle 3 was 2.8nA, cycle 4 was 3.5nA, and cycle 5 was 4.2nA. ​​The system calculated the difference between the first and last endpoints: |4.2nA - 2.1nA| = 2.1nA. The preset leakage drift threshold (set to 1.5nA according to the AEC-Q100 Grade 1 requirements for this type of chip) -- 2.1nA > 1.5nA, therefore the system identified a latent leakage drift fault characteristic in test channel 89.

[0036] (3) Timing jitter feature recognition For test channel 37 (the same channel as the aforementioned transient overcurrent, exhibiting a related anomaly), the system compares the rising edge transition times of the channel's output signal in two adjacent detection cycles: the rising edge transition time in cycle 1 is 10.02ns (relative to the reference clock), and the rising edge transition time in cycle 2 is 10.15ns, with an absolute time deviation of 0.13ns. The preset timing jitter threshold (set to 0.10ns based on AEC-Q100 timing requirements for this chip model) is 0.13ns > 0.10ns, thus the system identifies a latent timing jitter fault characteristic in test channel 37.

[0037] Based on the identification results of the above three types of features, the system confirmed that test channel 37 has both transient overcurrent latent fault features and timing jitter latent fault features, and test channel 89 has leakage drift latent fault features.

[0038] Step S3: Excitation Reconfiguration Driven by Failure Physical Mechanism After receiving the latent fault characteristic identification results, the closed-loop feedback control module performs excitation reconstruction based on the failure physical mechanism: For the transient overcurrent latent fault characteristic of test channel 37: the system maps "transient overcurrent" to the failure physical mechanism of electromigration effect and / or hot carrier effect. Based on this failure physical mechanism, the corresponding test excitation adjustment strategy is determined to be reducing the test voltage and limiting the test current. The system reduces the test voltage applied to test channel 37 from 3.3V to 2.8V (reconstruction amplitude 0.5V, not exceeding the preset voltage safety margin range of 0.8V), and at the same time reduces the test current limit from 50mA to 35mA (reconstruction amplitude 15mA, not exceeding the preset current safety margin range of 20mA).

[0039] Regarding the latent timing jitter fault characteristic of test channel 37: the system maps "timing jitter" to the physical mechanism of power integrity and / or clock distribution path defects. Based on this physical mechanism, the corresponding test stimulus adjustment strategy is determined to be adjusting the test timing edge position and changing the load conditions. The system adjusts the delay time of the rising edge of the test stimulus signal relative to the reference clock from 10.00ns to 10.20ns (reconstruction step size 0.20ns, not exceeding the preset step size upper limit of 0.50ns), and at the same time adjusts the output load from 15pF to 10pF.

[0040] For the latent fault characteristic of leakage drift in test channel 89: the system maps "leakage drift" to the failure physical mechanism of gate oxide layer defects and / or interface state traps. Based on this failure physical mechanism, the corresponding test excitation adjustment strategy is determined to be adjusting the bias voltage and changing the test frequency. The system adjusts the bias voltage of test channel 89 from 1.2V to 0.9V (reconstruction amplitude of 0.3V, not exceeding the preset voltage safety margin range of 0.4V), while reducing the test frequency from 1MHz to 100kHz.

[0041] After the stimulus reconstruction is completed, the system returns to step S1 to collect data again.

[0042] Step S4: Closed-loop cycle and convergence determination The system consists of a closed-loop detection cycle consisting of steps S1 (encapsulated feature parsing, acquisition topology reconstruction and multi-channel spatiotemporal alignment sampling) → S2 (latent fault feature identification) → S3 (excitation reconstruction driven by failure physical mechanism and return to reacquisition).

[0043] Severity Quantification Definition: In this embodiment, the severity of the anomaly is defined as the percentage by which the current feature value deviates from a preset threshold, i.e.: Severity = (Current feature value - Preset threshold) / Preset threshold × 100%.

[0044] A positive severity value indicates the presence of a latent fault, with a larger positive value indicating a more severe deviation; a negative value indicates that the threshold has not been exceeded. Based on this quantification, the system has a preset waiting interval mapping rule: wait 100ms when severity ≤ 20%; wait 50ms when severity > 20% and ≤ 50%; and wait 30ms when severity > 50%.

[0045] The severity of the current spike amplitude of 45mA in test channel 37 is approximately 28.6% (45-35) / 35×100% (>20% and ≤50%), and the severity of the timing jitter of 0.13ns is approximately 30% (0.13-0.10) / 0.10×100% (>20% and ≤50%). Both fall into the medium severity range, and the system sets the waiting interval to 50ms. The severity of the leakage drift of 2.1nA in test channel 89 is approximately 40% (2.1-1.5) / 1.5×100% (>20% and ≤50%), also falling into the medium range, and the waiting interval is set to 50ms. Since multiple test channels exhibit latent fault characteristics, the system uses the shortest waiting interval required for each test channel as the global waiting interval, which is 50ms.

[0046] After the second cycle of data acquisition, the current spike amplitude of test channel 37 decreased to 32mA (below the 35mA threshold), and the timing jitter decreased to 0.08ns (below the 0.10ns threshold); the leakage drift of test channel 89 decreased to 1.2nA (below the 1.5nA threshold). All three characteristic values ​​returned to the normal range.

[0047] The system continues with the third loop, confirming that no latent fault characteristics have been identified in two consecutive loops (N=2), thus satisfying the preset convergence condition of "no latent fault characteristics have been identified in N consecutive closed-loop detection loops". The value of N is selected based on the historical test data statistics of this chip model. Two consecutive loops without abnormalities indicate that the latent fault has been eliminated and the chip state has returned to stability. For Grade 0 chips with higher safety levels, N can be set to 3 to provide higher confidence. The system terminates the loop and outputs the "Detection passed" result. The entire detection process takes approximately 350ms (including 3 loops and waiting intervals).

[0048] Example 2: Testing of QFN-packaged automotive-grade power management chips This embodiment uses the testing of a QFN-32 packaged automotive-grade power management chip (model PM-208, Grade 2, -40℃ to 105℃) as an application scenario to illustrate the differentiated acquisition topology reconstruction strategy under different package types.

[0049] Step S1: Encapsulate feature parsing, acquire topology reconstruction and multi-channel spatiotemporal alignment sampling The system identifies the package structure as "QFN-32" (32 peripheral pins distributed around the chip's perimeter). The acquisition configuration module then performs acquisition topology reconstruction. Mapping relationship between acquisition channels and pins: The system connects the 32 acquisition channels one-to-one with the 32 peripheral pins. Unlike BGA packages, QFN packages do not require configuring all channels (BGA has 176 signal channels), only the number of channels needs to be configured to match the number of peripheral pins.

[0050] Range matching relationship: The I / O voltage of this power management chip is 5V, and the system configures the range of each test channel to 0~10V.

[0051] Sampling rate adaptation parameters: This chip is a low-frequency power management chip and does not require high-speed sampling. The system will configure the sampling rate to 100MSa / s.

[0052] The pins of the QFN package are distributed around the perimeter of the chip. When sampling multi-channel spatiotemporal alignment, there is no need to deal with the cross-region clock deviation problem caused by the ball grid array layout in the BGA package, and the acquisition accuracy is easier to guarantee.

[0053] After the topology reconstruction is completed, the multi-channel acquisition system applies a global synchronization clock reference to all 32 test channels, establishes a spatiotemporal alignment relationship between the sampling times of each test channel, performs associated sampling, and acquires the spatiotemporally aligned electrical test data of each test channel.

[0054] Step S2: Identification of Latent Fault Characteristics The feature analysis module performs three types of latent fault feature identification on the electrical test data obtained in step S1: transient overcurrent, leakage drift, and timing jitter. The feature extraction method and judgment logic are the same as in Example 1: the amplitude of the current spike and the rate of change of the current are extracted as transient overcurrent feature values ​​and compared with a preset transient overcurrent threshold; the difference between the first and last endpoints of the static leakage current sequence within a preset number of consecutive detection cycles is extracted as leakage drift feature values ​​and compared with a preset leakage drift threshold; the absolute value of the time deviation between the edge transition times of two adjacent detection cycles is extracted as timing jitter feature values ​​and compared with a preset timing jitter threshold. When any feature value exceeds the corresponding preset threshold, a latent fault feature is determined to exist.

[0055] Step S3: Excitation Reconfiguration Driven by Failure Physical Mechanism When a latent fault characteristic is identified, the closed-loop feedback control module maps the type of the latent fault characteristic to the corresponding chip failure physical mechanism, determines the test stimulus adjustment strategy based on the failure physical mechanism, reconstructs the test stimulus parameters according to the adjustment strategy, and then returns to step S1 for re-acquisition. The specific mapping relationship and adjustment strategy are the same as in Example 1.

[0056] Step S4: Closed-loop cycle and convergence determination The system uses steps S1 to S3 to form a closed-loop detection cycle, which is executed repeatedly until a preset convergence condition is met, at which point the system terminates and outputs the detection result. The convergence condition and waiting interval rules are the same as in Example 1.

[0057] Example 3: Inspection of bare wafers (wafer level) This embodiment uses the die inspection during the wafer testing stage (CP testing, Chip Probe) as an application scenario to illustrate the application of the present invention in die packaging types.

[0058] Step S1: Encapsulate feature parsing, acquire topology reconstruction and multi-channel spatiotemporal alignment sampling The system identifies the package structure as a bare die. This die has 48 pads, and the probe card is configured with 48 parallel probes. The nominal probe contact resistance is 100mΩ. The acquisition configuration module performs acquisition topology reconstruction: Mapping relationship between acquisition channels and pins: The system connects the 48 acquisition channels to the 48 solder pad test points on the bare die one by one according to the probe layout of the probe card.

[0059] Range matching relationship and sampling rate adaptation parameters: Configure the corresponding voltage range (0~5V) and sampling rate parameters (500MSa / s) according to the design specifications of the bare chip.

[0060] After the topology reconstruction is completed, the multi-channel acquisition system applies a global synchronization clock reference to all 48 test channels, establishes a spatiotemporal alignment relationship between the sampling times of each test channel, performs associated sampling, and acquires the spatiotemporally aligned electrical test data of each test channel.

[0061] Step S2: Identification of Latent Fault Characteristics The feature analysis module performs three types of latent fault feature identification on the electrical test data obtained in step S1: transient overcurrent, leakage drift, and timing jitter. The identification process is the same as in Example 1.

[0062] False Fault Differentiation Mechanism in the Detection Process During die inspection, the contact condition between the probe and the pad directly affects the accuracy of electrical test data. Poor probe contact (abnormally high contact resistance) may lead to abnormally high transient current readings, which can easily be misdiagnosed as chip-on-chip failure.

[0063] In this embodiment, the system extracts transient overcurrent characteristic values ​​from the 12th test channel (which is the power pad of the bare die) in a certain detection cycle and finds that the current spike amplitude is 80mA, which exceeds the preset transient overcurrent threshold (50mA), thus identifying the transient overcurrent hidden fault characteristics.

[0064] Step S3: Excitation Reconfiguration Driven by Failure Physical Mechanism The closed-loop feedback control module maps transient overcurrent to the failure physical mechanism of electromigration and / or hot carrier effects. Based on this failure physical mechanism, the test excitation adjustment strategy is determined to reduce the test current, decreasing it from the nominal value of 10mA to 8mA (reconstruction amplitude 2mA, not exceeding the preset current safety margin range of 5mA). Then, it returns to step S1 for re-acquisition. After re-acquisition, the current peak amplitude of test channel 12 synchronously decreases to 64mA (a decrease roughly proportional to the 20% reconstruction amplitude), indicating that the latent fault characteristic changes in the same direction as the reconstruction of the test excitation. That is, the anomaly originates from the test contact rather than the chip itself—excessive probe contact resistance causes the current reading to rise, rather than electromigration or hot carrier effects inside the chip. At this time, the system marks the test channel as "contact abnormality, not chip failure," adjusts the probe contact state, and restarts the test.

[0065] If the current spike amplitude does not decrease synchronously after re-collection (i.e., the abnormal reading remains basically unchanged after reconstructing the test current), it is confirmed that there is an overcurrent abnormality in the chip itself. The system continues to execute the excitation reconstruction process driven by the failure physical mechanism (mapping the transient overcurrent to the failure physical mechanism of electromigration effect and / or hot carrier effect, and determining the test excitation adjustment strategy based on the failure physical mechanism as reducing the test voltage and limiting the test current).

[0066] Step S4: Closed-loop cycle and convergence determination After confirming that the contact status is normal, the system forms a closed-loop detection cycle with steps S1 to S3, and executes the cycle until the preset convergence condition is met and then terminates, outputting the detection result and distinguishing between two conclusions: "chip failure" and "test contact failure".

[0067] Example 4: Power Device Leakage Drift Detection and Dynamic Waiting Interval Application This embodiment uses leakage drift detection of an automotive-grade power drive chip (model PWR-612, used for motor drive control in new energy vehicles, Grade 0, -40℃ to 150℃) as an application scenario, and focuses on illustrating the typical detection process of latent leakage drift fault characteristics in power devices and the setting logic of dynamic waiting interval.

[0068] Scene background This power driver chip has multiple high-voltage analog input pins (used to acquire motor phase current). Under high-temperature operating conditions, leakage drift caused by gate oxide defects or interface state traps is one of its typical failure modes. Under the high-temperature operating conditions of Grade 0 (junction temperature can reach 150°C), the impact of gate oxide defects on leakage current is significantly amplified, making leakage drift detection particularly critical.

[0069] Step S1: Encapsulate feature parsing, acquire topology reconstruction and multi-channel spatiotemporal alignment sampling The system identifies the package structure as "HSSOP-24" (a small package with 24 pins on both sides). The acquisition configuration module performs acquisition topology reconstruction: connecting the 24 acquisition channels one-to-one with the 24 pins of the package, configuring the range to 0~20V (the driving voltage of this power chip is relatively high), and configuring the sampling rate to 200MSa / s.

[0070] After topology reconstruction, the multi-channel acquisition system applies a global synchronization clock reference to all 24 test channels, establishing a spatiotemporal alignment relationship for sampling times among the test channels. Under static bias conditions (drive pins connected to a fixed off level, output pins left floating), the system performs correlated sampling, continuously acquiring a steady-state leakage current value sequence for 8 detection cycles (each cycle 200μs, cycle interval 1ms).

[0071] Step S2: Identification of Latent Fault Characteristics The system extracts a sequence of steady-state leakage current values ​​for eight detection cycles: cycle 1 is 5.2nA, cycle 2 is 5.8nA, cycle 3 is 6.5nA, cycle 4 is 8.1nA, cycle 5 is 10.5nA, cycle 6 is 13.2nA, cycle 7 is 16.8nA, and cycle 8 is 21.0nA. The system calculates the difference between the first and last endpoints: |21.0nA - 5.2nA| = 15.8nA. A preset leakage drift threshold (set to 10.0nA based on the high-temperature leakage requirement of AEC-Q100 Grade 0 for this type of power chip) is applied. Since 15.8nA > 10.0nA, the system identifies a latent leakage drift fault.

[0072] Severity quantification: Severity = (15.8-10.0) / 10.0×100% = 58%, which exceeds the 50% threshold and is mapped to high severity.

[0073] Step S3: Excitation Reconfiguration Driven by Failure Physical Mechanism The system maps leakage drift to the failure physics mechanism of gate oxide layer defects and / or interface state traps. Based on this failure physics mechanism, the test excitation adjustment strategy is determined to be adjusting the bias voltage and changing the test frequency. The system adjusts the bias voltage from 1.5V to 1.0V (reconstruction amplitude of 0.5V, not exceeding the preset voltage safety margin range of 0.6V), while reducing the test frequency from 500kHz to 100kHz. After the excitation reconstruction is completed, the system automatically returns to step S1 for re-acquisition.

[0074] Step S4: Closed-loop cycle and convergence determination The system forms a closed-loop detection cycle with steps S1 to S3. Since the severity of this latent fault feature is 58% (>50%), the system sets the waiting interval between two adjacent cycles to 30ms according to the preset waiting interval mapping rule (the waiting interval is 30ms when the severity is >50%), in order to accelerate convergence.

[0075] After the second cycle of data acquisition, the leakage drift decreased to 11.2 nA (still above the 10.0 nA threshold), and the severity decreased to 12% (≤20%). Based on the waiting interval mapping rule, the system extended the waiting interval between the second and third cycles to 100 ms to allow the chip to fully stabilize under the reconstructed bias conditions.

[0076] After the system performed the third cycle of data acquisition, the leakage current drift decreased to 8.5 nA (below the 10.0 nA threshold). The system continued to execute the fourth cycle, confirming that no latent fault characteristics were identified in two consecutive cycles (N=2), thus meeting the convergence condition. The cycle was then terminated and a "detection passed" result was output.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A multi-channel adaptive closed-loop detection method for automotive-grade chips, characterized in that, Includes the following steps: S1: Analyze the packaging structure characteristics of the automotive-grade chip under test, reconstruct the mapping relationship between the acquisition channel and the pin, the range matching relationship and the sampling rate adaptation parameters based on the packaging structure characteristics; and perform spatiotemporal aligned sampling of each test channel through a global synchronous clock reference to obtain electrical test data. S2: Extract features from the electrical test data, extract transient overcurrent feature values, leakage drift feature values, and timing jitter feature values, and compare each feature value with a preset judgment threshold set based on automotive standards to identify hidden fault features; S3: When a latent fault feature is identified, the type of the latent fault feature is mapped to the corresponding chip failure physical mechanism. Based on the failure physical mechanism, a test stimulus adjustment strategy is determined. The test stimulus parameters are reconstructed according to the adjustment strategy, and the process returns to step S1 for re-acquisition. S4: The closed-loop detection loop is formed by steps S1 to S3. The loop is executed until the preset convergence condition is met and then the detection result is output.

2. The method according to claim 1, characterized in that, The failure physical mechanism mapping relationship includes at least one of the following correspondences: The transient overcurrent anomaly corresponds to the failure physical mechanism of electromigration effect or hot carrier effect, and the test excitation adjustment strategy corresponding to this anomaly is to reduce the test voltage or limit the test current. The leakage drift anomaly corresponds to the physical mechanism of gate oxide layer defects or interface state trap failure, and the test excitation adjustment strategy corresponding to this anomaly is to adjust the bias voltage or change the test frequency. Timing jitter anomalies correspond to physical mechanisms of power integrity or clock distribution path defects, and the corresponding test stimulus adjustment strategies are to adjust the position of the test timing edge or change the load conditions.

3. The method according to claim 1, characterized in that, The package type corresponding to the package structure features includes at least one of QFN package, BGA package, and bare die; the mapping relationship between the acquisition channel and the pins is different for different package types: For QFN packages, the mapping relationship is that the acquisition channel is connected to the corresponding peripheral pins of the QFN package; For BGA packages, the mapping relationship is that the acquisition channel is connected to the corresponding ball grid array pin of the BGA package; For bare dies, the mapping relationship is that the acquisition channel is connected to the corresponding probe test point of the bare die.

4. The method according to claim 1, characterized in that, The electrical test data includes transient current parameters, static leakage current sequence, and edge transition time parameters for each test channel. The transient current parameter is a current timing signal continuously acquired at a set sampling rate within a preset detection time window; the static leakage current sequence is a sequence of steady-state leakage current values ​​acquired continuously for a preset number of detection cycles under static bias conditions; the edge transition time parameter is the moment when the rising or falling edge of the voltage signal of each test channel crosses the reference level.

5. The method according to claim 1, characterized in that, The transient overcurrent characteristic values ​​include the current spike amplitude and the current change rate. The current spike amplitude is the maximum instantaneous value of the transient current parameter within the detection time window, and the current change rate is the amount of change of the transient current parameter per unit time. When the current spike amplitude exceeds a preset transient overcurrent threshold and / or the current change rate exceeds a preset current change rate threshold, a transient overcurrent anomaly is determined to exist.

6. The method according to claim 1, characterized in that, The leakage drift characteristic value is the drift amount of the static leakage current sequence within a consecutive preset number of detection cycles. The drift amount is the absolute value of the difference between the last cycle value and the first cycle value in the static leakage current sequence. When the absolute value of the difference exceeds the preset leakage drift threshold, it is determined that there is a leakage drift anomaly.

7. The method according to claim 1, characterized in that, The timing jitter characteristic value is the absolute value of the time deviation of the edge transition time between adjacent detection cycles; the absolute value of the time deviation is the absolute value of the difference between the edge transition time in the current detection cycle and the corresponding edge transition time in the previous detection cycle; when the absolute value of the time deviation exceeds the preset timing jitter threshold, it is determined that there is a timing jitter abnormality.

8. The method according to claim 1, characterized in that, The preset judgment thresholds based on automotive-grade standards include transient overcurrent threshold, leakage drift threshold, and timing jitter threshold. The transient overcurrent threshold includes current spike amplitude threshold and current change rate threshold. The leakage drift threshold is a static leakage current drift threshold, and the timing jitter threshold is an edge transition time deviation threshold. Each threshold is set according to the automotive-grade chip reliability test specifications, and different threshold values ​​correspond to different models and / or different application levels of automotive-grade chips.

9. The method according to claim 1, characterized in that, The test excitation parameters include at least one of the following: test voltage amplitude, test current limit, and test timing edge position; The test voltage amplitude includes the test power supply voltage and / or the test signal voltage amplitude, the test current limit is the maximum output current limit of the test excitation source, and the test timing edge position is the delay time of the rising edge and / or falling edge of the test excitation signal relative to the reference clock. When reconstructing the test voltage amplitude, the reconstruction amplitude shall not exceed the preset voltage safety margin range; when reconstructing the test current limit, the reconstruction amplitude shall not exceed the preset current safety margin range; and when reconstructing the test timing edge position, the reconstruction step size shall not exceed the preset step size upper limit.

10. The method according to claim 1, characterized in that, The preset convergence condition is at least one of the following conditions: No abnormality was detected in any of the closed-loop detection cycles that were performed for a preset number of consecutive times; The closed-loop detection loop has reached its preset maximum number of iterations. The rate of change of each feature value between two consecutive closed-loop detection cycles is lower than the preset rate of change threshold.

11. The method according to claim 1, characterized in that, The closed-loop detection cycle has a waiting interval between two adjacent cycles. The length of the waiting interval is negatively correlated with the degree of abnormality: the higher the degree of abnormality, the shorter the waiting interval; the lower the degree of abnormality, the longer the waiting interval.

12. A multi-channel adaptive closed-loop detection system for automotive-grade chips, comprising a processor for performing the method as described in any one of claims 1 to 11.

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