A pin-level electrical- timing co-compensation method and system in high-parallel ATE testing

Abstract

This invention relates to a pin-level electrical-timing collaborative compensation method and system for high-parallel ATE testing, belonging to the technical field of semiconductor automatic test equipment. The method includes: acquiring pin voltage offset and timing offset; loading a benchmark test vector; determining the type of deviation; acquiring initial compensation parameters; fusing load capacitance and real-time temperature for feedforward correction; outputting the first-round feedforward compensation amount; loading this first-round feedforward compensation amount into a voltage-time delay sensitivity matrix; iteratively optimizing using an alternating constraint successive approximation algorithm; outputting the final voltage compensation amount and timing compensation amount; synchronously sending the final compensation amount to the pin drive link and sampling back the actual offset; injecting an attenuation factor to compress the iteration step size; cyclically executing the test and compensation process until the actual offset continuously converges within a preset threshold; and solidifying the compensation parameters. This achieves collaborative compensation of electrical and timing parameters, improving compensation accuracy and mass production consistency in high-parallel testing scenarios.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor automatic test equipment technology, specifically relating to a pin-level electrical-timing collaborative compensation method and system in high-parallel ATE testing. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve towards smaller sizes, chip integration and operating frequencies continue to increase, placing higher demands on the testing capabilities of semiconductor automated test equipment. Currently, the new generation of VLSI test systems can support high-parallel testing of up to 512 stations, that is, testing 512 chips under test simultaneously through 512 test channels. While this high-parallel test architecture significantly improves mass production testing efficiency, it also brings unprecedented technical challenges.

[0003] In high-parallel testing scenarios, the physical wiring lengths from different test channels to each chip under test vary, resulting in different signal transmission path delays. At the same time, when multiple stations simultaneously drive high-speed signals, the local temperature rise inside the test head is uneven. Temperature differences at different locations can cause inconsistencies in the delay drift of the drive circuit. In addition, the load capacitance driven by different pins also varies, affecting the charging and discharging time constants of the signal rising and falling edges, further exacerbating the inconsistency of the edge positions of the output signals from each pin. The superposition and cross-influence of these factors result in significant differences in signal quality and timing accuracy between different test stations. These differences in signal quality may lead to test vector retries, increasing test time and even directly affecting test yield.

[0004] To address the aforementioned issues, existing automated test equipment typically employs separate level calibration and timing calibration schemes. For level calibration, the output voltage accuracy of the driver is calibrated by adjusting the gain and bias of the digital-to-analog converter (DAC) of the pin electronics. For timing calibration, the transmission delay from the channel driver output to the pin of the chip under test is calibrated using time-domain reflectometry (TDAR) technology. However, existing level and timing calibrations are performed independently. Level calibration only adjusts voltage parameters without considering the impact of voltage changes on signal propagation delay, while timing calibration only adjusts delay parameters without considering the impact of timing adjustments on the driver stage load. There is a lack of effective coordination between the two, failing to resolve the cross-coupling problem between voltage and timing adjustments. Furthermore, existing calibration schemes are mostly one-time factory calibrations or periodic offline calibrations, which are open-loop calibrations and cannot compensate for dynamic deviations caused by factors such as temperature drift and changes in contact resistance during mass production testing. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a pin-level electrical-timing collaborative compensation method and system for high-parallel ATE testing. The objective of this invention can be achieved through the following technical solutions: Includes the following steps: Obtain the pin voltage offset and timing offset, load the benchmark test vector from the preset calibration vector library, and determine the type of deviation by voltage-delay drift ratio; The initial compensation parameters are obtained based on the deviation type index, and the load capacitance and real-time temperature are fused for feedforward correction to output the first round of feedforward compensation. The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the final voltage compensation and timing compensation are output through iterative optimization by the successive approximation algorithm with alternating constraints. The final voltage compensation and timing compensation are simultaneously sent to the pin drive link and the actual offset is sampled back. An attenuation factor is injected to compress the iteration step size. The testing and compensation process is repeated until the actual offset continuously converges within the preset threshold, and the compensation parameters are then fixed.

[0006] Specifically, the process of obtaining the pin voltage offset and timing offset is as follows: The output voltage of the pin is sampled at the rising edge of the system clock after the test vector is loaded, and the sampled value is compared with the preset reference value to obtain the voltage offset. The timing offset is obtained by capturing the signal transition edge time within the same period and comparing it with the expected edge time. Multiple sample values ​​are read continuously, and the median is taken as the effective voltage offset and effective timing offset of the current period.

[0007] Specifically, the process of loading the benchmark test vector is as follows: The reference test vector sequence of the corresponding pin channel is read from the preset calibration vector library. The reference test vector sequence contains multiple data states arranged in succession, including a preset high-level segment and a low-level segment. The low-level segment is used to measure the voltage reference when driving a low level, and the high-level segment is used to measure the voltage reference when driving a high level. During the loading process, the test vector sequence is shifted into the input buffer of the pin driver one by one. After a complete vector cycle is completed to allow the signal to enter the preset stable state, the voltage offset and timing offset sampling operations are performed.

[0008] Specifically, the process for determining the type of deviation is as follows: Multiply the voltage offset by the preset voltage delay coupling conversion factor to obtain the converted delay, and calculate the percentage of the total timing offset. If the total offset is less than the preset micro-time threshold, it is directly determined to be a timing-dominant deviation; otherwise, if the percentage is lower than the preset first threshold, it is determined to be timing-dominant; if it is higher than the preset second threshold, it is determined to be voltage-dominant; and if it is between the preset first threshold and the preset second threshold, it is determined to be a coupling deviation.

[0009] Specifically, the process of obtaining the initial compensation parameters is as follows: Generate an index vector based on the determined deviation type and access the preset compensation parameter register group; If the deviation type is voltage-dominant, then look up the corresponding voltage step value according to the direction and amplitude level of the voltage offset as the initial voltage compensation parameter. If the deviation type is timing-dominant, then look up the corresponding delay step value according to the direction and amplitude level of the timing offset as the initial timing compensation parameter; If the deviation type is coupled, then both the voltage step value and the delay step value are queried simultaneously, and the obtained voltage step value and delay step value are output together as a set of paired parameters.

[0010] Specifically, the process of outputting the first round of feedforward compensation is as follows: Read the value of the pin load capacitance, calculate the correction amount of the charging and discharging time constant, and add it to the voltage compensation amount to obtain the voltage feedforward correction value; Read the current ambient temperature and compare it with the reference temperature. Calculate the delay drift correction amount according to the unit temperature drift coefficient and add it to the delay compensation amount to obtain the timing feedforward correction value. The voltage feedforward correction value and the timing feedforward correction value are used as the first round of feedforward compensation output.

[0011] Specifically, the process of loading the voltage-delay sensitivity matrix is ​​as follows: Read the two-dimensional matrix in memory. The first row of elements is the edge displacement corresponding to each voltage level, and the second row of elements is the output impedance change corresponding to each delay level. During loading, the voltage and timing components of the feedforward compensation are mapped to the corresponding row index, the cross-influence coefficient sub-block at the operating point is extracted, and the coupling compensation increment is obtained by multiplying it with the compensation amount.

[0012] Specifically, the process for the final output voltage compensation and timing compensation is as follows: The coupling compensation increment is fed into the alternating approximation loop. In the first iteration, the fixed timing compensation amount is adjusted only to minimize the deviation, and in the second iteration, the fixed voltage compensation amount is adjusted only to minimize the deviation. After completion, the total deviation is calculated. If the reduction compared to the previous round is less than the preset proportional threshold, the iteration is terminated, and the current voltage and timing compensation amount are output as the final value.

[0013] The specific process of sending the final voltage compensation and timing compensation to the pin drive link and sampling the actual offset is as follows: The final voltage compensation amount is converted into the configuration code value of the driver-level digital-to-analog converter, and the final timing compensation amount is converted into the delay configuration value of the edge adjustment unit, and synchronously written into the driver link register of the corresponding pin. Waiting for the preset signal establishment period, sampling is triggered at the rising edge of the system clock. The current actual output voltage and the actual transition edge time of the pin are collected and compared with the preset reference voltage and the expected edge time, respectively. The actual residual voltage offset and the actual residual timing offset are calculated. Multiple sampling operations are performed continuously, and the median of the multiple sampling results is taken as the effective actual offset of the current round and sent back.

[0014] Specifically, the process of reducing the iteration step size by injecting the attenuation factor is as follows: When the actual offset exceeds the preset tolerance threshold, the iteration round is read. In the first iteration, the current compensation amount is multiplied by the initial attenuation factor as the initial value of the next round. In the second round and thereafter, the difference between the compensation amount of the previous round and the compensation amount of the current round is multiplied by the corresponding attenuation factor and then added to the compensation amount of the previous round as the initial value of the next round. The attenuation factor decreases with the iteration round and remains at the preset lower limit.

[0015] Specifically, the process for obtaining the curing compensation parameters is as follows: Convergence is defined as the actual offset being less than the preset error threshold multiple times consecutively and the fluctuation value not exceeding a preset proportion of the preset error threshold. The final voltage compensation, final timing compensation, and pin channel number at convergence are summarized into a parameter record and written into a fixed parameter table for the corresponding pin address in the non-volatile memory area. When testing the same type of chip in the future, the parameters in the fixed parameter table are read first as the reference compensation value and loaded directly.

[0016] Specifically, a pin-level electrical-timing co-compensation system for high-parallel ATE testing includes: Deviation perception classification unit: acquires pin voltage offset and timing offset, loads benchmark test vector from preset calibration vector library, and determines the deviation type by voltage-delay drift ratio; Feedforward correction unit: Based on the deviation type index, the initial compensation parameters are obtained, the load capacitance and real-time temperature are fused for feedforward correction, and the first round of feedforward compensation is output; Coupled Iteration Unit: The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the successive approximation algorithm with alternating constraints is used to iteratively optimize the final voltage compensation and timing compensation. Closed-loop convergence and solidification unit: synchronously sends the final voltage compensation amount and timing compensation amount to the pin drive link and samples back the actual offset, injects the attenuation factor to compress the iteration step size; cyclically executes the test and compensation process until the actual offset continuously converges within the preset threshold, and solidifies the compensation parameters.

[0017] The beneficial effects of this invention are as follows: (1) By calculating the proportion of voltage-delay drift, the deviation is quantitatively classified into voltage-dominant, time-dominant, or coupled types, so as to achieve accurate identification of deviation types and implement corresponding measures, avoid invalid iteration caused by uniform processing, and reduce the computational overhead in high-parallel testing; at the same time, the dual feedforward strategies of load capacitance correction and real-time temperature drift correction are integrated to suppress the interference caused by capacitive load differences and environmental temperature drift in advance before iteration, reduce the number of iteration optimizations, and improve the compensation response speed. (2) The voltage compensation amount and timing compensation amount are coupled and iteratively optimized by the successive approximation algorithm of voltage-time delay sensitivity matrix and alternating constraint, which overcomes the defects of the traditional scheme where level calibration and timing calibration are independent and ignore the cross-coupling effect. In the closed-loop sampling, the attenuation factor is introduced to dynamically compress the iteration step size to prevent oscillation caused by alternating adjustment, ensure stable convergence of iteration, and solidify and reuse the convergence parameters to realize continuous availability from single compensation to parameter reusability, thereby improving the test yield and mass production consistency in high parallel test scenarios. Attached Figure Description

[0018] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0019] Figure 1 This is a data flow diagram of a pin-level electrical-timing collaborative compensation method in a high-parallel ATE test according to the present invention; Figure 2 This is a system architecture diagram of a pin-level electrical-timing collaborative compensation system for high-parallel ATE testing according to the present invention; Figure 3 This is a schematic diagram of the overall structure of the high-parallel ATE test system in this invention. Detailed Implementation

[0020] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided.

[0021] Please see Figures 1-3 A pin-level electrical-timing collaborative compensation method and system for high-parallel ATE testing; Includes the following steps: Obtain the pin voltage offset and timing offset, load the benchmark test vector from the preset calibration vector library, and determine the type of deviation by voltage-delay drift ratio; The initial compensation parameters are obtained based on the deviation type index, and the load capacitance and real-time temperature are fused for feedforward correction to output the first round of feedforward compensation. The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the final voltage compensation and timing compensation are output through iterative optimization by the successive approximation algorithm with alternating constraints. The final voltage compensation and timing compensation are simultaneously sent to the pin drive link and the actual offset is sampled back. An attenuation factor is injected to compress the iteration step size. The testing and compensation process is repeated until the actual offset continuously converges within the preset threshold, and the compensation parameters are then fixed.

[0022] In this embodiment, the voltage offset refers to the difference between the actual output voltage of the pin and the preset reference voltage. The difference includes positive and negative direction information. A positive value means that the actual output voltage is higher than the preset reference voltage, and a negative value means that the actual output voltage is lower than the preset reference voltage. The difference also includes amplitude level information, which is determined by the range of the absolute value of the difference. Timing offset refers to the time difference between the transition time of the pin output signal and the expected edge time of the system. This difference contains information on whether it is ahead or behind. A positive value indicates that the signal transition is later than the expected time, i.e., the lag direction, and a negative value indicates that the signal transition is earlier than the expected time, i.e., the lead direction. This difference also contains amplitude level information, which is determined by the time interval in which the absolute value of the difference is located. The deviation type refers to the dominant category of pin deviations based on the conversion relationship between voltage deviation and timing deviation. Specifically, it includes voltage-dominant deviation, timing-dominant deviation, and coupling deviation. Voltage-dominant deviation indicates that the equivalent delay after voltage deviation conversion accounts for the main proportion of the total timing deviation. Timing-dominant deviation indicates that the timing deviation itself accounts for the main proportion of the total timing deviation. Coupling deviation indicates that the contributions of both voltage deviation and timing deviation to the total deviation are not negligible. The initial compensation parameter refers to the first compensation adjustment amount obtained from the preset compensation parameter register group according to the deviation type. Specifically, it includes the initial voltage compensation parameter and the initial timing compensation parameter. The initial voltage compensation parameter includes adjustment direction information and adjustment amplitude level information, and the initial timing compensation parameter includes lead or lag direction information and adjustment amplitude level information. The first-round feedforward compensation amount refers to the first-round compensation amount output after load capacitance correction and temperature drift correction. Specifically, it includes voltage feedforward correction value and timing feedforward correction value. The voltage feedforward correction value is the result of superimposing the charge and discharge characteristic correction caused by the load capacitance on the initial voltage compensation parameters. The timing feedforward correction value is the result of superimposing the delay drift correction caused by the ambient temperature deviating from the reference temperature on the initial timing compensation parameters. The coupling compensation increment refers to the compensation correction value obtained by matrix operation after loading the feedforward compensation amount into the voltage-time delay sensitivity matrix. Specifically, it includes voltage coupling correction amount and timing coupling correction amount. The final voltage compensation amount refers to the voltage compensation value output to the pin drive link after iterative optimization by the alternating constraint successive approximation algorithm. This value includes adjustment direction and amplitude information. The final timing compensation value refers to the delay compensation value output to the pin drive link after iterative optimization by the alternating constraint successive approximation algorithm. This value includes information on the lead or lag direction and magnitude. The actual offset refers to the actual residual deviation value of the pin obtained by retrieval after the final compensation amount is issued. Specifically, it includes the actual residual voltage offset and the actual residual timing offset. The actual residual voltage offset is the difference between the actual output voltage and the preset reference voltage after the compensation is issued. The actual residual timing offset is the time difference between the actual transition edge time and the system's expected edge time after the compensation is issued. The decay factor is a dynamic adjustment coefficient used to compress the iteration step size. This coefficient is a positive number between zero and one, which decreases with the increase of the iteration rounds and remains at a preset lower limit.

[0023] Specifically, the process of obtaining the pin voltage offset and timing offset is as follows: The output voltage of the pin is sampled at the rising edge of the system clock after the test vector is loaded, and the sampled value is compared with the preset reference value to obtain the voltage offset. The timing offset is obtained by capturing the signal transition edge time within the same period and comparing it with the expected edge time. Multiple sample values ​​are read continuously, and the median is taken as the effective voltage offset and effective timing offset of the current period.

[0024] Specifically, the process of loading the benchmark test vector is as follows: The reference test vector sequence of the corresponding pin channel is read from the preset calibration vector library. The reference test vector sequence contains multiple data states arranged in succession, including a preset high-level segment and a low-level segment. The low-level segment is used to measure the voltage reference when driving a low level, and the high-level segment is used to measure the voltage reference when driving a high level. During the loading process, the test vector sequence is shifted into the input buffer of the pin driver one by one. After a complete vector cycle is completed to allow the signal to enter the preset stable state, the voltage offset and timing offset sampling operations are performed.

[0025] Specifically, the process for determining the type of deviation is as follows: Multiply the voltage offset by the preset voltage delay coupling conversion factor to obtain the converted delay, and calculate the percentage of the total timing offset. If the total offset is less than the preset micro-time threshold, it is directly determined to be a timing-dominant deviation; otherwise, if the percentage is lower than the preset first threshold, it is determined to be timing-dominant; if it is higher than the preset second threshold, it is determined to be voltage-dominant; and if it is between the preset first threshold and the preset second threshold, it is determined to be a coupling deviation.

[0026] Specifically, the process of obtaining the initial compensation parameters is as follows: Generate an index vector based on the determined deviation type and access the preset compensation parameter register group; If the deviation type is voltage-dominant, then look up the corresponding voltage step value according to the direction and amplitude level of the voltage offset as the initial voltage compensation parameter. If the deviation type is timing-dominant, then look up the corresponding delay step value according to the direction and amplitude level of the timing offset as the initial timing compensation parameter; If the deviation type is coupled, then both the voltage step value and the delay step value are queried simultaneously, and the obtained voltage step value and delay step value are output together as a set of paired parameters.

[0027] Specifically, the process of outputting the first round of feedforward compensation is as follows: Read the value of the pin load capacitance, calculate the correction amount of the charging and discharging time constant, and add it to the voltage compensation amount to obtain the voltage feedforward correction value; Read the current ambient temperature and compare it with the reference temperature. Calculate the delay drift correction amount according to the unit temperature drift coefficient and add it to the delay compensation amount to obtain the timing feedforward correction value. The voltage feedforward correction value and the timing feedforward correction value are used as the first round of feedforward compensation output.

[0028] Specifically, the process of loading the voltage-delay sensitivity matrix is ​​as follows: Read the two-dimensional matrix in memory. The first row of elements is the edge displacement corresponding to each voltage level, and the second row of elements is the output impedance change corresponding to each delay level. During loading, the voltage and timing components of the feedforward compensation are mapped to the corresponding row index, the cross-influence coefficient sub-block at the operating point is extracted, and the coupling compensation increment is obtained by multiplying it with the compensation amount.

[0029] Specifically, the process for the final output voltage compensation and timing compensation is as follows: The coupling compensation increment is fed into the alternating approximation loop. In the first iteration, the fixed timing compensation amount is adjusted only to minimize the deviation, and in the second iteration, the fixed voltage compensation amount is adjusted only to minimize the deviation. After completion, the total deviation is calculated. If the reduction compared to the previous round is less than the preset proportional threshold, the iteration is terminated, and the current voltage and timing compensation amount are output as the final value.

[0030] The specific process of sending the final voltage compensation and timing compensation to the pin drive link and sampling the actual offset is as follows: The final voltage compensation amount is converted into the configuration code value of the driver-level digital-to-analog converter, and the final timing compensation amount is converted into the delay configuration value of the edge adjustment unit, and synchronously written into the driver link register of the corresponding pin. Waiting for the preset signal establishment period, sampling is triggered at the rising edge of the system clock. The current actual output voltage and the actual transition edge time of the pin are collected and compared with the preset reference voltage and the expected edge time, respectively. The actual residual voltage offset and the actual residual timing offset are calculated. Multiple sampling operations are performed continuously, and the median of the multiple sampling results is taken as the effective actual offset of the current round and sent back.

[0031] Specifically, the process of reducing the iteration step size by injecting the attenuation factor is as follows: When the actual offset exceeds the preset tolerance threshold, the iteration round is read. In the first iteration, the current compensation amount is multiplied by the initial attenuation factor as the initial value of the next round. In the second round and thereafter, the difference between the compensation amount of the previous round and the compensation amount of the current round is multiplied by the corresponding attenuation factor and then added to the compensation amount of the previous round as the initial value of the next round. The attenuation factor decreases with the iteration round and remains at the preset lower limit.

[0032] Specifically, the process for obtaining the curing compensation parameters is as follows: Convergence is defined as the actual offset being less than the preset error threshold multiple times consecutively and the fluctuation value not exceeding a preset proportion of the preset error threshold. The final voltage compensation, final timing compensation, and pin channel number at convergence are summarized into a parameter record and written into a fixed parameter table for the corresponding pin address in the non-volatile memory area. When testing the same type of chip in the future, the parameters in the fixed parameter table are read first as the reference compensation value and loaded directly.

[0033] Specifically, a pin-level electrical-timing co-compensation system for high-parallel ATE testing includes: Deviation perception classification unit: acquires pin voltage offset and timing offset, loads benchmark test vector from preset calibration vector library, and determines the deviation type by voltage-delay drift ratio; Feedforward correction unit: Based on the deviation type index, the initial compensation parameters are obtained, the load capacitance and real-time temperature are fused for feedforward correction, and the first round of feedforward compensation is output; Coupled Iteration Unit: The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the successive approximation algorithm with alternating constraints is used to iteratively optimize the final voltage compensation and timing compensation. Closed-loop convergence and solidification unit: synchronously sends the final voltage compensation amount and timing compensation amount to the pin drive link and samples back the actual offset, injects the attenuation factor to compress the iteration step size; cyclically executes the test and compensation process until the actual offset continuously converges within the preset threshold, and solidifies the compensation parameters.

[0034] In this embodiment, the specific process for obtaining the pin voltage offset and timing offset is as follows: Figure 3 As shown, the pin output voltage is sampled at the rising edge of the 50MHz system clock. The sample-and-hold circuit locks the pin output voltage to the sampling capacitor during the high level of the clock. The analog-to-digital converter converts the voltage value on the sampling capacitor into a 12-bit digital code and compares it with the corresponding digital code of the preset reference voltage to obtain the voltage offset. Within the same system clock cycle, the edge trigger in the timing frequency test unit captures the transition edge of the pin output signal. The edge trigger outputs the clock cycle count value corresponding to the transition edge. This count value is compared with the count value corresponding to the expected edge moment of the system to obtain the timing offset. To eliminate random noise interference that may be introduced by a single sampling, three sample values ​​are read continuously, and the median is taken as the effective voltage offset and effective timing offset of the current cycle. The time interval between the three samples is 20 ns, corresponding to a complete vector cycle at the 50 MHz test frequency.

[0035] The specific process for determining the type of deviation is as follows: multiply the voltage offset by the voltage delay conversion factor to obtain the converted delay. This conversion factor is obtained by measuring the corresponding edge drift after applying step voltage to each pin during the factory calibration stage and performing least squares linear fitting. The value range is from 0.5 ps per mV to 2.0 ps per mV. Calculate the percentage of the converted delay to the total timing offset. When the total timing offset is less than 50 ps, ​​it is directly determined as a timing-dominant deviation. Otherwise, when the percentage is less than 30%, it is determined as a timing-dominant deviation; when it is greater than 70%, it is determined as a voltage-dominant deviation; and when it is between 30% and 70%, it is determined as a coupling deviation.

[0036] The specific process of outputting the first round of feedforward compensation is as follows: Read the capacitance value of the pin load capacitor. This capacitance value is obtained by applying an AC test signal to the pin output terminal by the test system and back-calculating by measuring the charge and discharge time constant. The value range is from 10 pF to 100 pF. Calculate the charge and discharge time constant correction amount for the rising and falling edges of the signal based on the capacitance value and add it to the voltage compensation amount to obtain the voltage feedforward correction value. At the same time, read the current temperature value by temperature sensors deployed in multiple locations inside the test head. Take the average of the multiple temperatures and compare it with the reference temperature of 25 ℃ during calibration. Calculate the temperature drift correction amount according to the corresponding delay drift coefficient for each degree Celsius deviation and add it to the delay compensation amount to obtain the timing feedforward correction value. The temperature drift coefficient is calibrated point by point by the test system in the temperature test chamber within the range of 0 ℃ to 60 ℃, with a value range of 1 ps to 5 ps per ℃.

[0037] The specific process of loading the voltage-delay sensitivity matrix is ​​as follows: A two-dimensional matrix stored in system memory is read. The first row of the matrix contains the edge displacement corresponding to each voltage adjustment level. The voltage adjustment range is -2 V to +6 V, totaling 32 levels, with a step interval of 0.25 V. The second row contains the output impedance change of the driver stage corresponding to each delay adjustment level. The delay adjustment range is -500 ps to +500 ps, ​​totaling 32 levels, with a step interval of approximately 32.3 ps. The values ​​of each element in the matrix are obtained by fitting the response data measured after applying step voltage and step delay to each pin during the calibration phase using cubic spline interpolation. The voltage and timing components of the feedforward compensation are mapped to the corresponding row index positions of the matrix. A 2×2 cross-influence coefficient sub-block is extracted at the current operating point. This sub-block is then multiplied with the feedforward compensation vector to obtain the coupling compensation increment.

[0038] The specific process for outputting the final voltage compensation and timing compensation is as follows: The coupling compensation increment is used as the initial iteration value and fed into the alternating approximation loop. In each iteration, the timing compensation is kept unchanged and only the voltage compensation is adjusted. The voltage adjustment step size is one-third of the current voltage deviation. After the adjustment is completed, the current total deviation is measured again. Then, the voltage compensation is kept unchanged and only the timing compensation is adjusted. The timing adjustment step size is one-third of the current timing deviation. After the adjustment is completed, the current total deviation is measured again, completing a set of alternating voltage and timing adjustments. The total deviation value after this complete alternation is compared with the total deviation value after the previous complete alternation. If the decrease in the total deviation value is less than five percent of the current total deviation value, the iteration is determined to have converged. The iteration is terminated and the current voltage compensation and timing compensation are output as the final values. The processing time for each iteration does not exceed 1 μs.

[0039] The specific process of injecting attenuation factors to compress the iteration step size is as follows: After obtaining the actual offset through closed-loop sampling, if the actual offset exceeds the preset tolerance threshold, the current iteration round is read. The tolerance threshold is set according to the test specifications as voltage deviation ±5 mV to ±10 mV and timing deviation ±50 ps to ±100 ps. In the first iteration, the current compensation amount is multiplied by the initial attenuation factor 0.8 as the initial value of the next round. In the second round and thereafter, the difference between the compensation amount of the previous round and the compensation amount of the current round is multiplied by the attenuation factor corresponding to the current round and added to the compensation amount of the previous round as the initial value of the next round. The attenuation factor decreases by 0.1 round by round starting from 0.8, and remains unchanged after decreasing to 0.3, so that the iteration step size gradually shrinks with the increase of the round, preventing the voltage and timing from diverging and oscillating during the alternating adjustment.

[0040] The specific process of solidifying the compensation parameters is as follows: when the actual offset is less than the preset error threshold for three consecutive detections and the offset fluctuation value between the three consecutive detections does not exceed one-fifth of the error threshold, iterative convergence is considered achieved. The preset error thresholds are voltage deviation ±5 mV and timing deviation ±50 ps. The final voltage compensation value, the final timing compensation value, and the corresponding pin channel number used during convergence are summarized into a parameter record and written into the solidified parameter table of the corresponding pin address in the non-volatile memory area via the system bus. Each parameter record occupies 32 bytes of storage space. When testing the same model of chip in the future, the test master program will first read the corresponding parameter from the solidified parameter table as the reference compensation value and directly load it into the digital-to-analog converter and programmable delay unit of the pin driver, without having to re-execute the deviation judgment and iterative optimization process.

[0041] Example: A multi-site parallel testing scenario for mixed-signal chips in mass production testing; After the test starts, a reference test vector sequence is applied to each pin. The pin output voltage is sampled at the rising edge of the system clock and compared with a preset reference value to obtain the voltage offset. Simultaneously, the timing frequency test unit captures the signal transition edge time and compares it with the expected edge time to obtain the timing offset. Multiple consecutive samples are taken, and the median is used as the effective offset. The voltage offset is multiplied by the voltage delay conversion factor to obtain the converted delay. The percentage of this delay relative to the total timing offset is calculated, and the deviation type is determined based on the comparison of this percentage with a preset threshold. Based on the determined deviation type, an index vector is generated to access the compensation parameter register group. The initial voltage compensation parameters and initial timing compensation parameters are obtained by querying according to the direction and magnitude of the offset. The capacitance value of the pin load is read to calculate the charge / discharge time constant correction and superimposed on the voltage compensation to obtain the voltage feedforward correction value. The current ambient temperature is read and compared with the reference temperature to calculate the temperature drift correction and superimposed on the timing compensation to obtain the timing feedforward correction value. The voltage feedforward correction value and the timing feedforward correction value are combined to form the first round of feedforward compensation. The voltage and timing components of the first-round feedforward compensation are mapped to the corresponding row index positions of the voltage-delay sensitivity matrix. The cross-influence coefficient sub-block at the current operating point is extracted and matrix multiplication is performed to obtain the coupling compensation increment. The coupling compensation increment is fed into an alternating approximation loop. In each iteration, the timing compensation is first fixed and the voltage compensation is adjusted with a set ratio of the voltage deviation as the step size. Then, the voltage compensation is fixed and the timing compensation is adjusted with a set ratio of the timing deviation as the step size. After completing a set of alternations, the current total deviation value is calculated and compared with the total deviation value of the previous round. If the reduction is lower than the preset ratio threshold, the iteration is terminated and the final voltage compensation and final timing compensation are output. The final voltage compensation and timing compensation are simultaneously sent to the pin driver link. After the signal stabilizes, the actual residual offset is sampled. If it exceeds the preset tolerance threshold, the current iteration is read. In the first iteration, the current compensation is multiplied by the initial attenuation factor as the initial value for the next iteration. In subsequent iterations, the difference between the compensations of the previous and next iterations is multiplied by the corresponding attenuation factor and added to the compensation of the previous iteration as the initial value for the next iteration. The attenuation factor increases and decreases with each iteration until it reaches a preset lower limit and is then maintained. The test and compensation process is repeated until the actual offset is continuously detected to be less than the tolerance threshold multiple times and the fluctuation value does not exceed the set proportion of the tolerance threshold. At this point, convergence is considered achieved, and the current compensation parameters are solidified for direct reuse in subsequent tests of the same model of chip.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A pin-level electrical-timing co-compensation method for high-parallel ATE testing, characterized in that, Includes the following steps: Obtain the pin voltage offset and timing offset, load the benchmark test vector from the preset calibration vector library, and determine the type of deviation by voltage-delay drift ratio; The initial compensation parameters are obtained based on the deviation type index, and the load capacitance and real-time temperature are fused for feedforward correction to output the first round of feedforward compensation. The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the final voltage compensation and timing compensation are output through iterative optimization by the successive approximation algorithm with alternating constraints. The final voltage compensation and timing compensation are simultaneously sent to the pin drive link and the actual offset is sampled back. An attenuation factor is injected to compress the iteration step size. The testing and compensation process is repeated until the actual offset continuously converges within the preset threshold, and the compensation parameters are then fixed.

2. The method according to claim 1, characterized in that, The specific process for obtaining the pin voltage offset and timing offset is as follows: The output voltage of the pin is sampled at the rising edge of the system clock after the test vector is loaded, and the sampled value is compared with the preset reference value to obtain the voltage offset. The timing offset is obtained by capturing the signal transition edge time within the same period and comparing it with the expected edge time. Multiple sample values ​​are read continuously, and the median is taken as the effective voltage offset and effective timing offset of the current period.

3. The method according to claim 1, characterized in that, The specific process of loading the benchmark test vector is as follows: The reference test vector sequence of the corresponding pin channel is read from the preset calibration vector library. The reference test vector sequence contains multiple data states arranged in succession, including a preset high-level segment and a low-level segment. The low-level segment is used to measure the voltage reference when driving a low level, and the high-level segment is used to measure the voltage reference when driving a high level. During the loading process, the test vector sequence is shifted into the input buffer of the pin driver one by one. After a complete vector cycle is completed to allow the signal to enter the preset stable state, the voltage offset and timing offset sampling operations are performed.

4. The method according to claim 1, characterized in that, The specific process for determining the type of deviation is as follows: Multiply the voltage offset by the preset voltage delay coupling conversion factor to obtain the converted delay, and calculate the percentage of the total timing offset. If the total offset is less than the preset micro-time threshold, it is directly determined to be a timing-dominant deviation; otherwise, if the percentage is lower than the preset first threshold, it is determined to be timing-dominant; if it is higher than the preset second threshold, it is determined to be voltage-dominant; and if it is between the preset first threshold and the preset second threshold, it is determined to be a coupling deviation.

5. The method according to claim 1, characterized in that, The specific process for obtaining the initial compensation parameters is as follows: Generate an index vector based on the determined deviation type and access the preset compensation parameter register group; If the deviation type is voltage-dominant, then look up the corresponding voltage step value according to the direction and amplitude level of the voltage offset as the initial voltage compensation parameter. If the deviation type is timing-dominant, then look up the corresponding delay step value according to the direction and amplitude level of the timing offset as the initial timing compensation parameter; If the deviation type is coupled, then both the voltage step value and the delay step value are queried simultaneously, and the obtained voltage step value and delay step value are output together as a set of paired parameters.

6. The method according to claim 1, characterized in that, The specific process of outputting the first round of feedforward compensation is as follows: Read the value of the pin load capacitance, calculate the correction amount of the charging and discharging time constant, and add it to the voltage compensation amount to obtain the voltage feedforward correction value; Read the current ambient temperature and compare it with the reference temperature. Calculate the delay drift correction amount according to the unit temperature drift coefficient and add it to the delay compensation amount to obtain the timing feedforward correction value. The voltage feedforward correction value and the timing feedforward correction value are used as the first round of feedforward compensation output.

7. The method according to claim 1, characterized in that, The specific process of loading the voltage-delay sensitivity matrix is ​​as follows: Read the two-dimensional matrix in memory. The first row of elements is the edge displacement corresponding to each voltage level, and the second row of elements is the output impedance change corresponding to each delay level. During loading, the voltage and timing components of the feedforward compensation are mapped to the corresponding row index, the cross-influence coefficient sub-block at the operating point is extracted, and the coupling compensation increment is obtained by multiplying it with the compensation amount.

8. The method according to claim 1, characterized in that, The specific process for the final output voltage compensation and timing compensation is as follows: The coupling compensation increment is fed into the alternating approximation loop. In the first iteration, the fixed timing compensation amount is adjusted only to minimize the deviation, and in the second iteration, the fixed voltage compensation amount is adjusted only to minimize the deviation. After completion, the total deviation is calculated. If the reduction compared to the previous round is less than the preset proportional threshold, the iteration is terminated, and the current voltage compensation amount and timing compensation amount are output as the final value.

9. The method according to claim 1, characterized in that, The specific process of sending the final voltage compensation and timing compensation to the pin drive link and sampling the actual offset is as follows: The final voltage compensation amount is converted into the configuration code value of the driver-level digital-to-analog converter, and the final timing compensation amount is converted into the delay configuration value of the edge adjustment unit, and synchronously written into the driver link register of the corresponding pin. Waiting for the preset signal establishment period, sampling is triggered at the rising edge of the system clock. The current actual output voltage and the actual transition edge time of the pin are collected and compared with the preset reference voltage and the expected edge time, respectively. The actual residual voltage offset and the actual residual timing offset are calculated. Multiple sampling operations are performed continuously, and the median of the multiple sampling results is taken as the effective actual offset of the current round and sent back.

10. The method according to claim 1, characterized in that, The specific process of compressing the iteration step size using the injection attenuation factor is as follows: When the actual offset exceeds the preset tolerance threshold, the iteration round is read. In the first iteration, the current compensation amount is multiplied by the initial attenuation factor as the initial value of the next round. In the second round and thereafter, the difference between the compensation amount of the previous round and the compensation amount of the current round is multiplied by the corresponding attenuation factor and then added to the compensation amount of the previous round as the initial value of the next round. The attenuation factor decreases with the iteration round and remains at the preset lower limit.

11. The method according to claim 1, characterized in that, The specific process for obtaining the curing compensation parameters is as follows: Convergence is defined as the actual offset being less than the preset error threshold multiple times consecutively and the fluctuation value not exceeding a preset proportion of the preset error threshold. The final voltage compensation, final timing compensation, and pin channel number at convergence are summarized into a parameter record and written into a fixed parameter table for the corresponding pin address in the non-volatile memory area. When testing the same type of chip in the future, the parameters in the fixed parameter table are read first as the reference compensation value and loaded directly.

12. A pin-level electrical-timing co-compensation system for high-parallel ATE testing, characterized in that, include: Deviation perception classification unit: acquires pin voltage offset and timing offset, loads benchmark test vector from preset calibration vector library, and determines the deviation type by voltage-delay drift ratio; Feedforward correction unit: Based on the deviation type index, the initial compensation parameters are obtained, the load capacitance and real-time temperature are fused for feedforward correction, and the first round of feedforward compensation is output; Coupled Iteration Unit: The first round of feedforward compensation is loaded into the voltage-time delay sensitivity matrix, and the successive approximation algorithm with alternating constraints is used to iteratively optimize the final voltage compensation and timing compensation. Closed-loop convergence and solidification unit: synchronously sends the final voltage compensation amount and timing compensation amount to the pin drive link and samples back the actual offset, injects the attenuation factor to compress the iteration step size; cyclically executes the test and compensation process until the actual offset continuously converges within the preset threshold, and solidifies the compensation parameters.

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