Circuit testing methods and circuit testing systems

Abstract

A circuit testing method includes: acquiring test data of an integrated circuit, wherein the test data is used to record at least one test characteristic during scan testing of multiple logic circuits and multiple memory circuits; analyzing the test data to classify each of the multiple memory circuits into one of multiple test groups, wherein multiple first memory circuits of the multiple memory circuits are classified into a first test group of the multiple test groups; and generating test signals and multiple control signals based on the classification results of the multiple memory circuits and the test data. The test signals are used to perform scan testing on the integrated circuit. The multiple control signals are used to control the multiple first memory circuits so that, during scan testing, the number of multiple first memory circuits simultaneously enabled is limited to below a first enable upper limit.

Description

Technical Field

[0001] This disclosure relates to the testing of integrated circuits, and in particular to a circuit testing method and a circuit testing system. Background Technology

[0002] Scan testing is a testing technique applied to integrated circuits (ICs) to detect the presence of abnormal or damaged logic circuits within the IC. As chip design complexity increases, the detection process of identifying potential defects within integrated circuits through scan testing has become increasingly important, serving as a necessary step to ensure circuit reliability and performance. Summary of the Invention

[0003] This disclosure relates to a circuit testing method, comprising: acquiring test data of an integrated circuit, wherein the integrated circuit includes multiple logic circuits and multiple memory circuits, and the test data is used to record at least one test feature of the multiple logic circuits and the multiple memory circuits during scan testing; analyzing the test data to classify each of the multiple memory circuits into one of multiple test groups, wherein multiple first memory circuits of the multiple memory circuits are classified into a first test group of the multiple test groups; and generating test signals and multiple control signals based on the classification results of the multiple memory circuits and the test data. The test signals are used to perform scan testing on the integrated circuit. The multiple control signals are used to control the multiple first memory circuits so that, during scan testing, the number of multiple first memory circuits simultaneously enabled is limited to below a first enable upper limit.

[0004] In one embodiment, the method of analyzing test data to classify each of the plurality of memory circuits into one of the plurality of test groups further includes: classifying each of the plurality of memory circuits into one of the plurality of test groups based on a plurality of physical locations of the plurality of memory circuits.

[0005] In one embodiment, the method of analyzing test data to classify each of the plurality of memory circuits into one of the plurality of test groups further includes: analyzing a plurality of time domains or a plurality of test modes corresponding to the plurality of memory circuits based on netlist data or constraint data.

[0006] In one embodiment, the method of analyzing test data to classify each of the plurality of memory circuits into one of the plurality of test groups further includes classifying a portion of the plurality of memory circuits belonging to the same of the plurality of time domains into the same of the plurality of test categories.

[0007] In one embodiment, the method of analyzing test data to classify each of the plurality of memory circuits into one of the plurality of test groups further includes: classifying another portion of the plurality of memory circuits belonging to different time domains into the same portion of the plurality of test groups according to the plurality of test categories.

[0008] In one embodiment, a method for obtaining test data of an integrated circuit includes: obtaining one or more of the following: netlist data, constraint data, cell library data, and format data of the integrated circuit; wherein the netlist data is used to record the connection relationships between the plurality of logic circuits and the plurality of memory circuits; wherein the constraint data is used to record the clock of the integrated circuit; wherein the cell library data is used to record the logic characteristics or power consumption of the plurality of memory circuits; and wherein the format data is used to record the layout structure of the integrated circuit.

[0009] In one embodiment, the circuit testing method further includes: analyzing multiple memory enable limits of the multiple test groups based on multiple physical regions corresponding to the multiple test groups, wherein the multiple memory enable limits include a first enable limit; and generating restriction data based on the multiple memory enable limits, classification results, and test data to generate the multiple control signals.

[0010] In one embodiment, the circuit testing method further includes: disabling the plurality of memory circuits according to a plurality of clock signals corresponding to the plurality of memory circuits in the displacement mode of the scan test; and enabling the plurality of memory circuits according to the plurality of clock signals corresponding to the plurality of memory circuits in the acquisition mode of the scan test.

[0011] This disclosure also relates to a circuit testing system comprising multiple memory circuits, multiple logic circuits, and multiple control circuits. The multiple memory circuits are categorized into one of multiple test groups, wherein multiple first memory circuits of the multiple memory circuits are categorized into a first test group within the multiple test groups. The multiple logic circuits are coupled to the multiple memory circuits. The multiple control circuits are coupled to the multiple memory circuits, wherein each of the multiple control circuits selectively enables or disables a corresponding one of the multiple memory circuits. During a scan test, the multiple control circuits are used to receive multiple control signals to control the number of simultaneously enabled first memory circuits to be below a first enable limit.

[0012] In one embodiment, the circuit testing system further includes processing circuitry. The processing circuitry generates the plurality of control signals based on the plurality of physical locations of the plurality of memory circuits.

[0013] In one embodiment, the circuit testing system further includes a processing circuit for generating the plurality of control signals and for analyzing, based on netlist data or constraint data, a plurality of time-domain or multiple test modes corresponding to the plurality of memory circuits.

[0014] In one embodiment, the processing circuitry is further configured to classify a portion of the plurality of memory circuits belonging to the same entity in the plurality of time domains into the same entity in the plurality of test categories.

[0015] In one embodiment, the processing circuitry is further configured to: classify another portion of the plurality of memory circuits belonging to different time domains into the same portion of the plurality of test groups, based on the plurality of test categories.

[0016] In one embodiment, the circuit testing system further includes a processing circuit for: analyzing multiple memory enable limits of the multiple test groups based on multiple physical regions corresponding to the multiple test groups, wherein the multiple memory enable limits include a first enable limit; and generating restriction data based on the multiple memory enable limits to generate the multiple control signals.

[0017] In one embodiment, the circuit testing system further includes processing circuitry. The processing circuitry acquires one or more of the netlist data, constraint data, cell library data, and format data of the plurality of logic circuits and memory circuits to generate the plurality of control signals. The netlist data records the connection relationships between the plurality of logic circuits and memory circuits. The constraint data records the clock speeds of the plurality of logic circuits and memory circuits. The cell library data records the logic characteristics or power consumption of the plurality of memory circuits. The format data records the layout structure of the plurality of logic circuits and memory circuits.

[0018] In one embodiment, during the displacement mode of the scan test, the control circuit disables the plurality of memory circuits according to the plurality of clock signals corresponding to the plurality of memory circuits; during the acquisition mode of the scan test, the control circuit enables the plurality of memory circuits according to the plurality of clock signals corresponding to the plurality of memory circuits.

[0019] In one embodiment, each of the plurality of control circuits includes an enable control circuit and a mode control circuit. The enable control circuit is coupled to a corresponding one of the plurality of memory circuits for selectively enabling or disabling the corresponding one of the plurality of memory circuits. The mode control circuit is coupled to a corresponding one of the plurality of memory circuits for selectively setting the corresponding one of the plurality of memory circuits to a read mode or a write mode.

[0020] This disclosure also relates to a circuit testing method, comprising: acquiring test data of an integrated circuit, wherein the integrated circuit includes a plurality of logic circuits and a plurality of memory circuits, and the test data is used to record at least one test feature of the integrated circuit during scan testing; classifying each of the plurality of memory circuits into one of a plurality of test categories based on the test data, wherein a portion of the plurality of memory circuits belonging to the same time domain is classified into the same category; classifying each of the plurality of memory circuits into one of a plurality of test groups based on the test data and the plurality of test categories; and generating control signals corresponding to the plurality of memory circuits based on the test data and the plurality of test groups, so as to selectively control the operating state of the plurality of memory circuits according to the plurality of control signals during scan testing.

[0021] In one embodiment, a method for classifying each of the plurality of memory circuits into one of the plurality of test categories includes classifying each of the plurality of memory circuits into one of the plurality of test categories based on a plurality of clock signals or a plurality of test modes of the plurality of memory circuits.

[0022] In one embodiment, a method for classifying each of the plurality of memory circuits into one of the plurality of test groups includes classifying each of the plurality of memory circuits into one of the plurality of test groups based on a plurality of physical locations of the plurality of memory circuits.

[0023] Therefore, by analyzing the test characteristics of integrated circuits and scanning tests, and classifying memory circuits to control the number of memory circuits that can be enabled simultaneously, the test results can be retrieved using the existing memory circuits within the integrated circuit. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an integrated circuit according to some embodiments of the present disclosure;

[0025] Figure 2 This is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure;

[0026] Figure 3 The diagram shown is a flowchart of a circuit testing method according to some embodiments of the present disclosure;

[0027] Figure 4A The diagram shown is a schematic representation of the operation of a processing circuit according to a partial embodiment of the present disclosure.

[0028] Figure 4B The diagram shown is a classification and grouping method according to some embodiments of the present disclosure;

[0029] Figure 5 This is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure.

[0030] [Symbol Explanation]

[0031] 100: Integrated Circuits

[0032] 110A: Logic Circuit

[0033] 110B: Logic Circuits

[0034] 110C: Logic Circuits

[0035] 110D: Logic Circuit

[0036] 110E: Logic Circuits

[0037] 120: Memory Circuit

[0038] 130: Control Circuit

[0039] 140: Processing Circuit

[0040] 200: Circuit Testing System

[0041] 211: Setting Circuit

[0042] 220: Memory Circuit

[0043] 230: Control Circuit

[0044] 231: Temporary Register

[0045] 240: Processing Circuit

[0046] 400: Processing Circuit

[0047] 410: Data Creation Program

[0048] 411: Clock Analysis

[0049] 412: Memory Feature Analysis

[0050] 420: Memory Classification Program

[0051] 421: Memory Classification

[0052] 422: Memory Clustering

[0053] 423: Restrict Data Generation

[0054] 500: Circuit Test System

[0055] 510: Logic Circuits

[0056] 520: Memory Circuit

[0057] 530: Control Circuit

[0058] 530A: Mode Control Circuit

[0059] 530B: Enable control circuit

[0060] 531: Temporary Register

[0061] 532: Logic element

[0062] 533: Multiplexer

[0063] C41-C43: Test Categories

[0064] CK: Clock signal

[0065] CE: Enable Control Terminal

[0066] D: Input terminal

[0067] Dde: Netlist data

[0068] Dsdc: Constraint Data

[0069] Dlib: Unit library data

[0070] Ddef: Formatted data

[0071] DB: Database

[0072] G41: Test Group

[0073] G42: Test Group

[0074] LG21: Logic Gate

[0075] LG22: Logic Gate

[0076] LG23: Logic Gates

[0077] M41-M45: Memory Circuit

[0078] MUX21: Multiplexer

[0079] MUX22: Multiplexer

[0080] RWM: Read / Write Control Terminal

[0081] RM: Regression Model

[0082] RG11: Temporary Register

[0083] RG12: Temporary Register

[0084] RG13: Temporary Register

[0085] RG14: Bypass Logic

[0086] S301-S306: Steps

[0087] Spt: Test signal

[0088] Sctr: Control signal

[0089] Scon: Data Restriction

[0090] Scen: Enable signal

[0091] Sm1: Mode signal

[0092] Sm2: Mode signal

[0093] Smd: Scan mode signal

[0094] SI: Input signal

[0095] SE: Enable signal

[0096] WE: Input end Detailed Implementation

[0097] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0098] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0099] This disclosure relates to a circuit testing system and method for integrated circuits, used to perform scan tests on integrated circuits. To facilitate understanding of the application of this disclosure, we will first introduce... Figure 1 Taking the integrated circuit 100 shown as an example, the operation of the scan test is explained below.

[0100] Please see Figure 1 Integrated circuit 100 includes multiple logic circuits and multiple memory circuits. The logic circuits are as follows: Figure 1The 110A to 110D shown contain one or more logic elements. Depending on the function of different circuits, the composition and circuit architecture of the logic circuits will also be different. Since those skilled in the art can understand the meaning of the logic circuits here, they will not be described in detail here.

[0101] Memory circuits such as Figure 1 RG11 to RG13 and 120 shown can be implemented by flip-flops (such as D-type flip-flops). For the purpose of describing the implementation of this disclosure in subsequent paragraphs, they are referred to by different numbers here. Taking memory circuit 120 as an example, it has an input terminal D, an input terminal WE, an enable control terminal CE, and a read / write control terminal RWM (Read / Write Margin). The input terminal D, the input terminal WE, and the read / write control terminal RWM are coupled to logic circuits 110A, 110C, and 110D, respectively, and the output terminal of memory circuit 120 is coupled to logic circuit 110B.

[0102] Scan testing is a technique used to test integrated circuits for circuit anomalies. In one embodiment, a test signal Spt (Pattern) is generated by processing circuitry 140 as input data during the scan test. Processing circuitry 140 can generate the test signal Spt using Automatic Test Pattern Generation (ATPG) technology. Here, "processing circuitry" can be a test bench, a signal processor, or a computer device used to generate signals; this disclosure is not limiting.

[0103] For ease of understanding, the scanning test process is explained below. Figure 1 For example, if the target of the scan test is logic circuit 110A, when performing the scan test, a corresponding bypass logic RG14 (such as a temporary register) needs to be configured between logic circuit 110A and memory circuit 120 to read the scan test results.

[0104] The scanning test process includes shift mode and capture mode. In shift mode, the test signal Spt is input to logic circuit 110A one by one through a register according to the clock signal. This process of inputting data with pulses is called "shift". In capture mode, the clock signal is stopped, and after logic circuit 110A completes the corresponding logic operation, the clock signal is restored so that the operation result of logic circuit 110A is output to bypass logic RG14. This process of outputting the result to bypass logic RG14 after operation is called "capture".

[0105] However, in some integrated circuit products, due to design limitations (such as insufficient space), bypass logic may not be possible, preventing successful scan testing. Please refer to [link / reference]. Figure 1 As shown, although there is a memory circuit 120 between logic circuits 110A and 110B that is not used during the scan test, the memory circuit 120 is not suitable for recording the results of the scan test. This is because if multiple memory circuits 120 within integrated circuit 100 are simultaneously enabled to record test results during the scan test, the current will increase significantly, leading to a corresponding increase in the voltage across the electronic components within integrated circuit 100. This instability in the power supply may cause some electronic components to malfunction or become abnormal, a phenomenon known as the "IR-drop problem."

[0106] This disclosure describes configuring a control circuit 130 (e.g., an enable control terminal CE coupled to the memory circuit 120) in the integrated circuit 100 to control the memory circuit 120. By controlling the enable or disable time of the memory circuit 120, the memory circuit 120 can be used to record the results of scan tests. Accordingly, not only is there no need to configure additional bypass logic, but there is also no need to worry about IR-drop problems.

[0107] Specifically, when generating the test signal Spt, the processing circuit 140 also generates a corresponding control signal Sctr for each control circuit 130 based on the limitation data Scon, so as to set the operating state (i.e., enable or disable) of the memory circuit 120 by changing the logic level of the enable control terminal CE. The definition and generation method of the limitation data Scon will be described in detail in subsequent paragraphs.

[0108] Figure 2 This is a schematic diagram of a circuit testing system 200 according to a portion of the embodiments of this disclosure. The circuit testing system 200 can be applied to... Figure 1 The integrated circuit shown, due to Figure 2 The embodiments described have not changed. Figure 1 The operation of "logic circuits 110A and 110C receiving the test signal Spt for scanning test" is described in the accompanying diagram. Therefore, to maintain brevity for illustration, the diagram is omitted here. Figure 2 The middle part is omitted Figure 1 The intermediate coupling is connected to input terminal D, input terminal WE, and the corresponding logic circuit. Memory circuit 220 can be... Figure 1 The memory circuit 120 is shown. The control circuit 230 can be... Figure 1 The control circuit 130 shown is shown.

[0109] The circuit test system 200 includes multiple logic circuits ( Figure 2 Only 110D and 110E are shown in the diagram, along with the memory circuit. Figure 2Only 220 and the control circuit are shown in the figure. Figure 2 (Only 230 is shown in the figure). In this embodiment, the read / write control terminal RWM of the memory circuit 220 is coupled to the logic circuit 110D and the setting circuit 211 through the multiplexer MUX21. The setting circuit 211 is used to provide read / write setting signals to set the speed at which the memory circuit 220 operates in the read or write state.

[0110] The control circuit 230 includes a temporary register 231, a multiplexer MUX22, and multiple logic gates LG21 to LG23 (e.g., ...). Figure 2 (The AND gate and inverter are shown). Logic gates LG21 to LG23 are used to receive the enable signal Scan (scan_enable) and the mode signals Sm1 / Sm2 respectively, so as to selectively change the level of the output signal of the control circuit 230, thereby controlling the enable or disable of the memory circuit 220. The "enable signal Scan" and the "mode signals Sm1 / Sm2" can be the aforementioned "control signal Sctr" or at least a part thereof.

[0111] Please refer to the table below, which shows the signal status of the circuit test system 200 in different modes ("X" represents "irrelevant condition"). The "functional mode" refers to the operating state of the integrated circuit when it is operating normally, rather than when it is performing a scan test.

[0112] model Signal Sm1 signal Sm2 Signal Scen Functional mode X 0 0 Displacement mode X 1 1 Extraction mode 1 1 0

[0113] As shown in the table above, in functional mode, the multiplexer MUX22 selects the signal from logic circuit 110E as its output signal; therefore, the circuit test system 200 is not performing a scan test at this time. In shift mode, since the enable signal Scen is "1", after inversion by logic gate LG21, the output signal of logic gate LG22 is "0", and the memory circuit 220 will be disabled. On the other hand, in capture mode, the output signal of logic gate LG22 is "1", and the memory circuit 220 will be enabled. It is important to note that the control circuit 230 is not limited to these limitations. Figure 2 The circuit shown is only one embodiment.

[0114] This disclosure generates a test signal Spt and multiple control signals Sctr corresponding to multiple memory circuits based on the test data of the integrated circuit. The control circuit 230 selectively controls the operating state of the memory circuit 220 during scan testing based on the corresponding control signals Sctr, such as: read / write disabled, read state, or write state. The aforementioned "test data" includes at least one test characteristic recorded during scan testing, which reflects the circuit characteristics or configuration of the integrated circuit (e.g., logic circuit or memory circuit). In some embodiments, the "test data" may include one or more of the following four:

[0115] (1) Netlist data: Netlist data is used to record the connection relationships between multiple logic circuits and multiple memory circuits in an integrated circuit. Specifically, netlist data records the electrical connection relationships between circuit elements in a specific format, such as including the identifiers of electronic components.

[0116] (2) Constraint Data (Synopsys Design Constraints, SDC): Constraint data is used to record the clock speed of the integrated circuit. Specifically, constraint data uses a special data format to record the operating characteristics of each logic circuit within the integrated circuit to ensure that the circuit can achieve the expected performance during operation.

[0117] (3) Library data: The library data is used to record the logic characteristics and / or power consumption of these memory circuits and various logic circuits, such as the circuit composition and operating characteristics of a variety of different logic elements.

[0118] (4) Design Exchange Format (DEF): This data is used to record the layout structure of the integrated circuit. Specifically, the DEF uses a special format to describe the physical design of the integrated circuit, recording the layout design, component locations, connection paths, etc.

[0119] In this embodiment, the circuit testing system 200 includes a processing circuit 240 for acquiring test data (e.g., coupled to an integrated circuit for detection, or entered by a tester), and classifying each memory circuit 220 into one of a plurality of "test categories" and / or grouping it into one of a plurality of "test groups" based on the test data. Based on the analysis results of the classification and grouping, the processing circuit 240 first generates constraint data Scon, and then generates the test signal Spt required for the scan test, as well as the control signal Sctr provided to each control circuit 230. In other embodiments, the test data can be acquired and constraint data Scon can be generated by another processor first, and then the constraint data Scon can be input to the processing circuit 240 to generate the test signal Spt and the control signal Sctr.

[0120] As mentioned above, the "classification" and "grouping" actions are based on whether multiple memory circuits need to operate simultaneously during scan testing. For example, it determines whether the logic circuits corresponding to multiple memory circuits are interconnected, belong to the same scan chain, or use the same clock domain signal. Therefore, memory cells that need to operate simultaneously during scan testing (e.g., belonging to the same clock domain) to record test results will be assigned to the same test category.

[0121] Conversely, memory cells that do not need to operate simultaneously to record test results during scan testing will be grouped into the same test group. It should be noted that, in one embodiment, the same test group may contain a certain number of memory circuits that "operate simultaneously," this number is referred to herein as the "enabling limit." In other words, the number of memory circuits simultaneously enabled in the same test group will be controlled to be below the enabling limit. For example, the first test group contains 30 first memory circuits, and the first enabling limit for the first test group is "2." During scan testing, the control circuit will control that at most two of these first memory circuits will be enabled simultaneously according to the control signal STr. The "enabling limit" will be determined based on the power supply capacity or power consumption limitations in the integrated circuit, for example, it may be one, two, or five, but this disclosure is not limited to these numbers.

[0122] The control signal generated in the aforementioned manner can control the number of memory circuits simultaneously enabled during scan testing, thus avoiding the IR-drop problem caused by the current increase due to multiple memory circuits being enabled at the same time. Accordingly, the memory already configured in the integrated circuit can be used as a temporary register during scan testing without the need to configure bypass logic separately.

[0123] Figure 3The diagram shown is a flowchart of a circuit testing method according to some embodiments of this disclosure, which can be applied to... Figure 1 Integrated circuit 100 or Figure 2 The circuit test system 200 is shown. The operational concept of this disclosure is illustrated using a flowchart as an example. In step S301, the processing circuit 240 first acquires the test data of the integrated circuit. As previously mentioned, the test data may include one or more of the following: netlist data, constraint data, cell library data, and format data of the integrated circuit.

[0124] In step S302, the processing circuit 240 analyzes the test characteristics in the test data to classify the multiple memory circuits into one of multiple test categories. As mentioned earlier, memory cells that need to operate simultaneously during the scan test (e.g., belonging to the same time domain) to record test results will be assigned to the same test category.

[0125] In step S303, the processing circuit 240 analyzes the test characteristics in the test data and, based on the classification results in step S302, further groups the multiple memory circuits into one of the multiple test groups. In one embodiment, the memory circuits in the same test group may all be "not required to operate simultaneously during scan testing," for example, multiple memory circuits belonging to different time domains (i.e., a portion of all memory circuits) may be grouped into the same test group. In another embodiment, the memory circuits in the same test group must meet the requirement that "the number of circuits simultaneously enabled during scan testing is less than the enable limit."

[0126] In step S304, based on the test data and analysis results (i.e., classification results and / or clustering results), the processing circuit 240 will generate the limitation data Scon. Specifically, the processing circuit 240 can analyze the memory enable limit of each test group according to the physical region corresponding to the test group (i.e., the placement location in the integrated circuit), and then generate the limitation data Scon based on the test data, analysis results, and / or memory enable limit.

[0127] In step S305, the processing circuit 240 generates a test signal Spt for performing a scan test and a control signal Sctr provided to each control circuit based on the constraint data Scon.

[0128] In step S306, the integrated circuit performs a scan test based on the test signal Spt and the control signal Str. For example, the test signal Spt is provided to... Figure 1 The logic circuit 110A and control signal Sctr shown are provided to Figure 1The control circuit 130 is shown. Specifically, in the displacement mode of the scan test, the control circuit disables the corresponding memory circuit according to the clock signal corresponding to each memory circuit. In the acquisition mode of the scan test, the control circuit enables the corresponding memory circuit according to the clock signal corresponding to each memory circuit to obtain the scan test result.

[0129] It is worth mentioning here that... Figure 3 In the flowchart, the actions performed by the processing circuit can be executed by different devices; that is, the processing circuit 140 is not limited to a single circuit device. For example, the processing circuit 140 includes a first device and a second device. The first device generates limit data Scon, and the second device generates a test signal Spt and a control signal Sctr based on the limit data Scon.

[0130] This section explains how the contents of this disclosure work from different perspectives. Please refer to [link / reference]. Figure 4A This is a schematic diagram illustrating the operation of a processing circuit 400 according to a partial embodiment of the present disclosure. The processing circuit 400 can be applied to implement... Figure 1 Processing circuit 140 or Figure 2 The processing circuit 240. The processing circuit 400 is used to execute the data creation program 410 to generate analysis results, and to execute the memory classification program 420 to generate the restriction data Scon.

[0131] like Figure 4A As shown, the data creation program 410 includes clock analysis 411 and memory feature analysis 412. During clock analysis 411, the processing circuit 400 receives netlist data Dde and constraint data Dsdc to analyze the test modes corresponding to multiple memory circuits, or to analyze the time domain of multiple clock signals corresponding to memory circuits.

[0132] During memory feature analysis 412, processing circuit 400 receives cell library data Dlib and format data Ddef to obtain the circuit characteristics of the integrated circuit. Specifically, processing circuit 400 can analyze the layout design, component locations, and connection paths of the integrated circuit as a basis for subsequent classification or grouping. Processing circuit 400 records the analysis data generated by clock analysis 411 and memory feature analysis 412 into database DB.

[0133] The memory classification program 420 includes memory classification 421, memory grouping 422, and restricted data generation 423. During memory classification 421, the processing circuit 400 classifies the memory circuits based on the analysis data obtained by the data creation program 410. Specifically, the processing circuit 400 classifies the memory circuits into various test categories based on the time domain or test mode of the clock signal corresponding to the memory circuit. For example, memory circuits belonging to the same time domain (i.e., a subset of memory circuits) are classified into the same test category.

[0134] During memory clustering 422, processing circuit 400 clusters the memory circuits based on test data, analysis data obtained by data creation program 410, and classification results. Specifically, in one embodiment, processing circuit 400 classifies memory circuits into various test groups based on their physical location within the integrated circuit. In another embodiment, processing circuit 400 classifies memory circuits belonging to different time domains (i.e., another portion of memory circuits) into the same test group based on the classification results (i.e., test categories) from memory classification 421. The aforementioned classification and clustering results can be recorded in the regression model RM in processing circuit 400 to record and update the analysis results each time.

[0135] During the restriction data generation 423, the processing circuit 400 generates restriction data based on the aforementioned classification and grouping results. This restriction data will then be used to generate test signals and control signals. In other words, the test signals and control signals used in the scan test can be generated based on characteristics such as the physical location, time domain, or test mode of the memory circuit.

[0136] For ease of understanding, here we will use Figure 4B The schematic diagram illustrates the classification and grouping methods. In one embodiment, the integrated circuit includes multiple memory circuits M41 to M45. During the aforementioned "memory classification 421," the processing circuit 400 classifies the memory circuits M41 to M45 into multiple test categories C41 to C43 based on the time domain or test mode of the clock signal. For example, the clock signals corresponding to memory circuits M41 and M42 are in the same time domain, and therefore will be classified into the same test category C41.

[0137] Continuing from the above, during the "memory grouping 422" process, the processing circuit 400 further groups the memory circuits M41 to M45 based on the classification results. That is, it controls the number of memory circuits simultaneously enabled within the same test group. For example... Figure 4B As shown, memory circuits M41 to M45 will be grouped into multiple test groups G41 to G42, and in each test group, no multiple memory circuits will be enabled at the same time.

[0138] The control circuit disclosed herein can be adjusted according to design requirements and is not limited to the aforementioned. Figure 2 For details regarding the circuit architecture, please refer to [link / reference]. Figure 5 The diagram shown illustrates a circuit testing system 500 according to another embodiment of this disclosure. The circuit testing system 500 includes a logic circuit 510, a memory circuit 520, and a control circuit 530. The logic circuit and the control circuit 530 are respectively coupled to different input terminals or control terminals of the memory circuit 520. Figure 2 resemblance, Figure 5 The 500 circuit testing system can be applied to Figure 1 The integrated circuit shown, and because Figure 5 The embodiment does not change the operation mode and circuit of "the logic circuit under test 110A receiving the test signal Spt", therefore Figure 5 The text omits some circuits and focuses on the relative relationship between the enable control terminals CE of the control circuit 530 and the memory circuit 520.

[0139] like Figure 5 As shown, the control circuit 530 includes a mode control circuit 530A and an enable control circuit 530B. The mode control circuit 530A is coupled to the enable control terminal CE of the memory circuit via the enable control circuit 530B, and is used to selectively enable or disable a corresponding memory circuit (i.e., memory circuit 520). Specifically, the mode control circuit 530A includes at least one logic element (e.g., an AND gate) and is used to receive multiple control signals, such as mode signals Sm1 / Sm2 and enable signals Scen, to generate an enable control signal.

[0140] The enable control circuit 530B is coupled to the enable control terminal CE of the mode control circuit 530A and the memory circuit 520, and includes a register 531, a logic element 532, and a multiplexer 533. The register 531 receives the input signal SI and the enable signal SE, and outputs the stored data according to the clock signal CK. The logic element 532 receives the stored data output by the register 531 and the enable control signal generated by the mode control circuit 530A. The multiplexer 533 is coupled to the logic circuit 510 and the logic element 532, and outputs the signal provided by the logic circuit 510 or the logic element 532 according to the scan mode signal Smd, to selectively set the memory circuit 520 to read mode or write mode.

[0141] In one embodiment, the logic circuit architecture within the control circuit can be determined based on the type of memory circuit, for example, the logic elements required for the control circuit can be determined based on the analysis results of the aforementioned data creation program 410.

[0142] In some embodiments, by using existing memory circuitry within the integrated circuit as the memory for reading the test results of the scan test, the coverage of the scan test can be improved, and the impact of voltage drop (IR-drop) on circuit performance can be effectively avoided. Accordingly, not only can the coverage of the scan test be improved, but the circuit layout cost during scan testing can also be reduced.

[0143] The components, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of textual description or the order of presentation of the drawings in this disclosure.

[0144] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A circuit testing method, characterized in that, Include: Obtain test data for an integrated circuit, wherein the integrated circuit includes multiple logic circuits and multiple memory circuits, and the test data is used to record at least one test feature when the multiple logic circuits and the multiple memory circuits are subjected to a scan test. The test data is analyzed to classify each of the plurality of memory circuits into one of the plurality of test groups, wherein the plurality of first memory circuits of the plurality of memory circuits are classified into a first test group of the plurality of test groups; as well as Based on the classification result of the plurality of memory circuits and the test data, a test signal and a plurality of control signals are generated, wherein the test signal is used to perform the scan test on the integrated circuit, and the plurality of control signals are used to control the plurality of first memory circuits so that, during the scan test, the number of the plurality of first memory circuits that are simultaneously enabled is limited to below a first enable limit.

2. The circuit testing method as described in claim 1, characterized in that, The method of analyzing the test data to classify each of the plurality of memory circuits into one of the plurality of test groups further comprises: Based on the multiple physical locations of the multiple memory circuits, each of the multiple memory circuits is classified into one of the multiple test groups.

3. The circuit testing method as described in claim 1, characterized in that, The method of analyzing the test data to classify each of the plurality of memory circuits into one of the plurality of test groups further comprises: Based on a netlist or a constraint, analyze the multiple time domains or multiple test modes corresponding to the multiple memory circuits.

4. The circuit testing method as described in claim 3, characterized in that, The method of analyzing the test data to classify each of the plurality of memory circuits into one of the plurality of test groups further comprises: The multiple memory circuits that belong to the same group in the multiple time domains are classified into the same group in multiple test categories.

5. The circuit testing method as described in claim 4, characterized in that, The method of analyzing the test data to classify each of the plurality of memory circuits into one of the plurality of test groups further comprises: Based on the multiple test categories, another portion of the multiple memory circuits belonging to different time domains are classified into the same one in the multiple test groups.

6. The circuit testing method as described in claim 1, characterized in that, The method for obtaining the test data of the integrated circuit includes: Obtain one or more of the following: a netlist data, a constraint data, a cell library data, and a format data of the integrated circuit; The netlist data is used to record the connection relationships between the plurality of logic circuits and the plurality of memory circuits; The constraint data is used to record the clock speed of the integrated circuit; The cell library data is used to record the logic characteristics or power consumption of the multiple memory circuits; and This data format is used to record the layout structure of the integrated circuit.

7. The circuit testing method as described in claim 1, characterized in that, Also includes: Based on the multiple physical regions corresponding to the multiple test groups, the multiple memory enable limits of the multiple test groups are analyzed, wherein the multiple memory enable limits include the first enable limit; as well as Based on the multiple memory enable limits, the classification results, and the test data, a limit data is generated to generate the multiple control signals.

8. The circuit testing method as described in claim 1, characterized in that, Also includes: During a shift mode of the scan test, the plurality of memory circuits are disabled according to the plurality of clock signals corresponding to the plurality of memory circuits; and In one acquisition mode of the scan test, the plurality of memory circuits are enabled according to the plurality of clock signals corresponding to the plurality of memory circuits.

9. A circuit testing system, characterized in that, Include: Multiple memory circuits are classified into one of multiple test groups, wherein multiple first memory circuits of the multiple memory circuits are classified into a first test group of the multiple test groups. Multiple logic circuits are coupled to the multiple memory circuits; as well as Multiple control circuits are coupled to the multiple memory circuits, wherein each of the multiple control circuits selectively enables or disables a corresponding one of the multiple memory circuits; During a scan test, the plurality of control circuits are used to receive a plurality of control signals to control the number of the plurality of first memory circuits that are simultaneously enabled to be less than a first enable limit.

10. The circuit testing system as described in claim 9, characterized in that, The circuit testing system also includes a processing circuit, which generates the plurality of control signals based on the plurality of physical locations of the plurality of memory circuits.

11. The circuit testing system as described in claim 9, characterized in that, The circuit testing system also includes a processing circuit for generating the plurality of control signals, and further for: Based on a netlist or a constraint, analyze the multiple time domains or multiple test modes corresponding to the multiple memory circuits.

12. The circuit testing system as described in claim 11, characterized in that, This processing circuit is also used for: The multiple memory circuits that belong to the same group in the multiple time domains are classified into the same group in multiple test categories.

13. The circuit testing system as described in claim 12, characterized in that, This processing circuit is also used for: Based on the multiple test categories, another portion of the multiple memory circuits belonging to different time domains are classified into the same one in the multiple test groups.

14. The circuit testing system as described in claim 9, characterized in that, The circuit testing system also includes a processing circuit, which is used to: Based on the multiple physical regions corresponding to the multiple test groups, the multiple memory enable limits of the multiple test groups are analyzed, wherein the multiple memory enable limits include the first enable limit; as well as Based on the multiple memory enable limits, a limit data is generated to generate the multiple control signals.

15. The circuit testing system as described in claim 9, characterized in that, The circuit testing system also includes: A processing circuit is used to obtain one or more of a netlist data, a constraint data, a cell library data, and a format data from the plurality of logic circuits and the plurality of memory circuits, so as to generate the plurality of control signals. The netlist data is used to record the connection relationships between the plurality of logic circuits and the plurality of memory circuits; The constraint data is used to record the clock speeds of the plurality of logic circuits and the plurality of memory circuits; The cell library data is used to record the logic characteristics or power consumption of the multiple memory circuits; and This data format is used to record the layout structure of the plurality of logic circuits and the plurality of memory circuits.

16. The circuit testing system as described in claim 9, characterized in that, In a displacement mode of the scan test, the control circuit is used to disable the plurality of memory circuits according to the plurality of clock signals corresponding to the plurality of memory circuits; in a capture mode of the scan test, the control circuit is used to enable the plurality of memory circuits according to the plurality of clock signals corresponding to the plurality of memory circuits.

17. The circuit testing system as described in claim 9, characterized in that, Each of the plurality of control circuits includes: An enable control circuit, coupled to a corresponding one of the plurality of memory circuits, is used to selectively enable or disable a corresponding one of the plurality of memory circuits; and A mode control circuit, coupled to a corresponding one of the plurality of memory circuits, is used to selectively set the corresponding one of the plurality of memory circuits to a read mode or a write mode.

18. A circuit testing method, characterized in that, Include: Obtain test data for an integrated circuit, wherein the integrated circuit includes multiple logic circuits and multiple memory circuits, and the test data is used to record at least one test feature of the integrated circuit during a scan test. Based on the test data, each of the plurality of memory circuits is classified into one of the plurality of test categories, wherein the plurality of memory circuits belonging to the same time domain are the same ones classified into the plurality of test categories; Based on the test data and the multiple test categories, each of the multiple memory circuits is classified into one of the multiple test groups; as well as Based on the test data and the plurality of test groups, a plurality of control signals corresponding to the plurality of memory circuits are generated, so that during the scan test, the operating state of the plurality of memory circuits can be selectively controlled according to the plurality of control signals.

19. The circuit testing method as described in claim 18, characterized in that, The method of classifying each of the plurality of memory circuits into one of the plurality of test categories includes: Based on multiple clock signals or multiple test modes of the multiple memory circuits, each of the multiple memory circuits is classified into one of the multiple test categories.

20. The circuit testing method as described in claim 18, characterized in that, The method of classifying each of the plurality of memory circuits into one of the plurality of test groups includes: Based on the multiple physical locations of the multiple memory circuits, each of the multiple memory circuits is classified into one of the multiple test groups.

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