A short-circuit resistance test method for power devices based on overcurrent fast response protection

Abstract

This invention discloses a short-circuit withstand test method for power devices based on overcurrent fast response protection, belonging to the field of device testing and processing technology. By defining a characteristic time window and simultaneously extracting two coupled electrical characteristic quantities—gate charge and drain-source voltage drop—it provides a refined characterization of the device's turn-on transient from the dual-dimensional coupling perspective of gate drive energy and drain-source voltage response. By actively opening an effective detection interval within the blanking time window, it fundamentally breaks the inherent constraint that the blanking time must be fully shielded. By performing a coupling ratio calculation of gate charge and drain-source voltage drop and generating a short-circuit prediction factor, it achieves advanced judgment of short-circuit faults within the desaturation detection blanking time window. Utilizing the gate charge and drain-source voltage coupling characteristics that can be extracted within a few nanoseconds to tens of nanoseconds in the initial stage of the turn-on transient, the decision-making time for short-circuit judgment is significantly advanced, compressing the protection blind zone caused by traditional blanking time.

Description

Technical Field

[0001] This invention belongs to the field of device testing and processing technology, specifically a short-circuit withstand test method for power devices based on overcurrent fast response protection. Background Technology

[0002] The core of short-circuit withstand testing for power devices based on overcurrent fast response protection is to verify, under real short-circuit conditions, whether ultra-fast overcurrent detection combined with fast shutdown protection can safely operate before the device burns out, and to accurately determine the effective short-circuit withstand time / energy of the device under this protection mechanism. Desaturation (DESAT) detection must be set with a blanking time of 200-800ns to shield the instantaneous device turn-on. The process from the bus voltage drop to the conduction voltage drop is crucial; otherwise, it will be falsely triggered. However, the short-circuit withstand time of SiC MOSFET is only 2-3μs, and the blanking time accounts for 1 / 3 to 1 / 2, which severely compresses the effective protection window. Under extreme conditions, such as a junction temperature of 150°C and a bus voltage of 1200V, the device is close to the edge of thermal runaway when the blanking time ends, resulting in the blanking time paradox and the defect of detection blind zone in desaturation detection. Summary of the Invention

[0003] To address the problems existing in the above solutions, this invention provides a short-circuit withstand test method for power devices based on overcurrent fast response protection, which solves the technical problems existing in the background art.

[0004] The objective of this invention can be achieved through the following technical solutions: A short-circuit withstand test method for power devices based on overcurrent fast response protection, comprising: S1. Synchronous acquisition of turn-on transient waveform: In the SiC MOSFET short-circuit withstand test circuit, a turn-on gate pulse is applied to the SiC MOSFET under test, and the gate voltage signal, gate current signal and drain-source voltage signal of the SiC MOSFET under test are acquired at high speed simultaneously. S2. Gate charge-drain-source voltage coupling feature extraction: Within the desaturation detection blanking time window, based on the gate voltage signal, a characteristic time window from the threshold voltage moment to the preset reference voltage moment before the Miller plateau is determined, and the amount of gate charge injected within the characteristic time window is calculated using the gate current signal. At the same time, the amount of drain-source voltage drop corresponding to the end of the characteristic time window is obtained using the drain-source voltage signal. S3. Short-circuit prediction factor generation and protection trigger: The gate charge and the drain-source voltage drop are coupled and calculated to generate a short-circuit prediction factor. When the short-circuit prediction factor is less than the preset short-circuit determination threshold, the SiC MOSFET under test is determined to be in a short-circuit state, and an overcurrent protection trigger signal is output before the end of the desaturation detection blanking time window.

[0005] Furthermore, in step S1, the short-circuit withstand test circuit includes a DC bus power supply, a bus capacitor, a load inductor, and the SiC MOSFET under test. The output voltage of the DC bus power supply is the nominal blocking voltage of the SiC MOSFET under test. The gate current signal is acquired in real time through a current sensing resistor or an integrated current sensor connected in series in the gate drive circuit.

[0006] Furthermore, in step S2, the characteristic time window is determined by identifying the first moment when the gate voltage signal first rises to the threshold voltage. And the second moment before the gate voltage signal first rises to the reference voltage before the Miller plateau. Then As a characteristic time window; wherein, the reference voltage before the Miller plateau is set to be higher than the threshold voltage and lower than the typical Miller plateau start voltage.

[0007] Furthermore, the amount of gate charge injected within the characteristic time window The calculation expression is: ;in, This is the gate current signal acquired in real time. and They are respectively and The corresponding sampling point index, The sampling interval; This is the gate current signal; It is a discrete sequence of gate current signals.

[0008] Furthermore, the drain-source voltage drop The calculation expression is: ;in, This is the DC bus voltage; This represents the instantaneous drain-source voltage value corresponding to the discrete drain-source voltage signal sequence.

[0009] Furthermore, short-circuit predictor The expression is: ;in, The reference gate charge is the amount measured within the same characteristic time window under pre-calibrated normal turn-on conditions.

[0010] Furthermore, the pre-calibration method for the reference gate charge is as follows: before each short-circuit withstand test, under non-short-circuit conditions, a turn-on pulse is applied to the SiC MOSFET under test, and the gate charge obtained within the corresponding characteristic time window is used as the reference gate charge.

[0011] Furthermore, the generated short-circuit predictor factors Compared with the preset short circuit detection threshold When comparing, When the test is initiated, the SiC MOSFET under test is determined to be in a short-circuit state.

[0012] Furthermore, the current junction temperature of the SiC MOSFET under test is obtained using a temperature sensor or thermistor method. The short-circuit judgment threshold is determined based on the junction temperature correction function. Adaptive adjustment is performed so that the threshold is appropriately reduced as the junction temperature increases, in order to match the physical characteristics of the device being more prone to thermal runaway at high temperatures.

[0013] Furthermore, the function for junction temperature correction is: ;in, For junction temperature The short-circuit detection threshold is below; This is the baseline value for short-circuit detection at a junction temperature of 25℃. γ is the current junction temperature; γ is the temperature coefficient.

[0014] Compared to existing solutions, the beneficial effects achieved by this invention are: This invention provides high-time-resolution raw data on device switching characteristics by simultaneously and rapidly acquiring three transient signals—gate voltage, gate current, and drain-source voltage—in a short-circuit withstand test circuit. By introducing synchronous acquisition of the gate current signal, it reveals whether the device enters an abnormal overcurrent state during the initial turn-on phase from the perspective of gate drive energy flow, overcoming the inherent limitation of relying solely on delayed detection of drain-source voltage signals. By defining a characteristic time window and simultaneously extracting two coupled electrical characteristics—gate charge and drain-source voltage drop—it provides a refined characterization of the device turn-on transient from the dual-dimensional coupling perspective of gate drive energy and drain-source voltage response. By actively creating an effective detection interval within the blanking time window, it fundamentally breaks the inherent constraint that the blanking time must be completely shielded. Furthermore, by controlling the gate current... The coupling ratio of charge and drain-source voltage drop is calculated to generate a short-circuit prediction factor with clear physical meaning, enabling advanced judgment of short-circuit faults within the desaturation detection blanking time window. Utilizing the coupling characteristics of gate charge and drain-source voltage that can be extracted within a few to tens of nanoseconds in the initial stage of turn-on transients, the decision-making time for short-circuit judgment is significantly advanced, fundamentally compressing the protection blind zone caused by traditional blanking time. The construction of the normalized ratio automatically offsets bus voltage fluctuations and device parameter dispersion, improving the universality and consistency of the criterion. The design of online calibration of the reference gate charge enables the system to adapt to different temperatures, driving conditions, and aging states. The addition of junction temperature compensation function further improves the timeliness of protection under high-temperature extreme conditions, solving the protection problem of devices approaching the edge of thermal runaway at a junction temperature of 150℃. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a short-circuit withstand test method for power devices based on overcurrent fast response protection according to the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] like Figure 1As shown, a short-circuit withstand test method for power devices based on overcurrent fast response protection includes: S1. Synchronous acquisition of turn-on transient waveform: In the SiC MOSFET short-circuit withstand test circuit, a turn-on gate pulse is applied to the SiC MOSFET under test, and the gate voltage signal, gate current signal and drain-source voltage signal of the SiC MOSFET under test are acquired at high speed simultaneously. This step constructs a short-circuit withstand test circuit for SiC MOSFETs and performs synchronous high-speed acquisition of key waveforms during device turn-on transients; the short-circuit withstand test circuit is powered by a DC bus power supply. Low-inductance bus capacitor Load inductance It consists of a SiC MOSFET under test, and the host computer controls the application of a single or repeated turn-on gate pulse to the device under test, while recording the transient waveform in real time.

[0019] During the acquisition process, the applied gate turn-on pulse is generated by a high-speed gate driver, and the driving voltage starts from the turn-off negative voltage. Jump to conduction positive voltage To simulate the hard-switching process under actual operating conditions; the three signals acquired synchronously are: gate voltage signal Gate current signal and drain-source voltage signal ; Specifically, the gate voltage signal is extracted directly at the gate-source pin of the device by a high-bandwidth differential voltage probe; the gate current signal is obtained through a non-inductive shunt or integrated current sensor connected in series in the gate circuit; and the drain-source voltage signal is extracted at the drain-source pin by a high-voltage passive probe or an optically isolated voltage probe. All three signals are connected to the same multi-channel high-speed digital storage oscilloscope or synchronous data acquisition system, using the rising edge of the gate pulse as a unified trigger source to achieve sub-nanosecond-level inter-channel synchronization.

[0020] To ensure effective capture of the extremely short turn-on transient of the SiC MOSFET, the system sampling rate must be no less than 2 GS / s, with a corresponding sampling interval Δt ≤ 0.5 ns, which can be specifically represented as a sampling time series: ; ;in, For the time corresponding to the nth sampling point, Where n is the sampling interval, n is the sampling point index, and N is the number of sampling points recorded in a single trigger. The collected discrete signal sequences are as follows: , and It fully preserves the complete transition process from the initial rise of the gate voltage to the complete drop of the drain-source voltage to the on-state voltage drop at the moment of turn-on; simultaneously, the DC bus voltage... Static measurements are performed using a separate digital multimeter or oscilloscope channel and used as a reference value for subsequent calculations.

[0021] In this embodiment of the invention, by synchronously and rapidly acquiring three transient signals—gate voltage, gate current, and drain-source voltage—in the short-circuit withstand test circuit, high-time-resolution raw data of the device's switching characteristics are provided for subsequent steps. Traditional short-circuit detection relies solely on the drain-source voltage desaturation phenomenon, resulting in a single acquisition dimension and being limited by the forced blind zone of the blanking time. This step introduces the synchronous acquisition of the gate current signal, which can reveal whether the device has entered an abnormal overcurrent state in the initial stage of turn-on from the perspective of gate drive energy flow, breaking the limitation of relying solely on... The inherent limitations of delayed detection; the design with a sampling rate of no less than 2GS / s enables precise digitization of the sub-nanosecond gate charge injection process, providing a measurement basis for defining the characteristic time window and calculating the integral of the gate charge in step S2; through unified triggering and synchronous acquisition, the time delay error between different channels is eliminated, ensuring the strictness of timing alignment in subsequent delay time calculation and short-circuit prediction factor generation. This is the core data guarantee for the entire method to achieve early warning and overcome the blanking time paradox within the 2~3μs short-circuit tolerance time window.

[0022] S2. Gate charge-drain-source voltage coupling feature extraction: Within the desaturation detection blanking time window, based on the gate voltage signal, a characteristic time window from the threshold voltage moment to the preset reference voltage moment before the Miller plateau is determined, and the amount of gate charge injected within the characteristic time window is calculated using the gate current signal. At the same time, the amount of drain-source voltage drop corresponding to the end of the characteristic time window is obtained using the drain-source voltage signal. Step S2 is based on the gate voltage signal synchronously acquired in step S1. Gate current signal and drain-source voltage signal Within the desaturation detection blanking time window, key parameters reflecting the dynamic characteristics of the device in the early stage of turn-on are extracted, specifically including the definition of the characteristic time window and the gate charge. Calculation and drain-source voltage drop The acquisition of.

[0023] When defining the characteristic time window, the determination of the characteristic time window is based on the gate voltage signal. The transition process between two characteristic voltage points; the discrete gate voltage signal sequence acquired in step S1. The gate voltage was first identified as rising to the threshold voltage of the SiC MOSFET under test. The first moment That is, satisfying: ;in, This represents the gate voltage sample value at the corresponding moment. The threshold voltage of the SiC MOSFET under test is given by the device datasheet or obtained through pre-testing; min{} is the minimum value function; Gate voltage signal The reference voltage before its first rise to the preset Miller plateau is identified. The second moment That is, satisfying: ;in, The reference voltage before the Miller platform must be set to meet the following requirements. , This is the starting voltage for the gate voltage to enter the Miller plateau under normal turn-on conditions; under short-circuit conditions, because the drain-source voltage remains high, the gate-drain capacitance... The reverse transport effect causes the gate voltage to reach The subsequent rise rate was significantly slower than normal startup, and the Miller plateau was significantly delayed or even absent; therefore... Set as a middle The midpoint between this value and the typical Miller plateau onset voltage allows the characteristic time window to fully capture the abnormal rise in gate voltage under short-circuit conditions. value ratio 1V to 2V higher; Based on the two calculated moments, the feature time window Defined as: Implement gate charge quantity During the calculation, in the characteristic time window Internally, the gate drive circuit supplies the gate-source capacitance of the SiC MOSFET under test. Continuous charge injection, the amount of which directly reflects the cumulative effect of driving energy input to the device; utilizing the gate current signal acquired in step S1 discrete sequence The amount of gate charge injected within the characteristic time window is calculated by numerical integration. The expression is: ;in, This is the gate current signal acquired in real time. and They are respectively and The corresponding sampling point index, The sampling interval in step S1; The unit is coulomb or nanocoulomb; It needs to be explained that, under normal turn-on conditions, due to the drain-source voltage... From bus voltage Rapidly drops to the on-state voltage drop, gate-drain capacitance After undergoing significant charge and discharge cycles, almost all of the gate current during the Miller plateau phase is used for... The discharge occurs, therefore the gate voltage reaches... Later rose to Required gate charge Relatively small; however, under short-circuit conditions, the drain-source voltage is... Always maintained at a high level, gate-drain capacitance Without undergoing a significant discharge, almost all of the gate current is used for... During charging, the gate voltage rises at a faster rate, resulting in a smaller amount of gate charge injected within the same characteristic time window. Significantly greater than the baseline value under normal operating conditions This difference constitutes the key physical basis for distinguishing between a short circuit and normal operation. In addition, gate-source capacitance , which is the parasitic capacitance between the gate and the source. Connected directly in parallel to the output of the driver, when the driver applies a positive voltage, the gate current... First of all, Charging, causing the gate voltage to... Increase; therefore, Decision made Rise from 0 to the threshold voltage speed; Gate-drain capacitance The parasitic capacitance between the gate and drain. It is the most critical capacitor in a MOSFET switch, connecting the input (gate) and output (drain) circuits, and generating the Miller effect; when the drain voltage... When things change rapidly, it will be through Injecting or extracting current into or from the gate significantly affects The waveform.

[0024] Implement drain-source voltage drop When acquiring the signal, at the end of the characteristic time window, the discrete signal sequence of drain-source voltage acquired in step S1 is used. Obtain the corresponding instantaneous drain-source voltage value. And combined with the DC bus voltage measured in step S1 Calculate the drain-source voltage drop at the end of the characteristic time window. The expression is: It needs to be explained that, This characterizes the actual decrease in drain-source voltage from the bus voltage level within a characteristic time window; under normal turn-on conditions, exist The time has dropped significantly. Larger; under short-circuit conditions, The bus voltage level was maintained almost throughout the entire desaturation detection blanking time window. Approaching zero or extremely small; therefore, It is another key electrical parameter for determining whether a device has entered a short-circuit state.

[0025] In this embodiment of the invention, by defining a characteristic time window and simultaneously extracting two coupled electrical characteristic quantities—gate charge and drain-source voltage drop—a refined characterization of the device turn-on transient is achieved from the dual-dimensional coupling perspective of gate drive energy and drain-source voltage response. Unlike existing desaturation detection methods that are completely blind within the blanking time window, this step utilizes the gate voltage from... arrive During the transition phase, an effective detection interval is actively opened up within the blanking time window, fundamentally breaking the inherent constraint that the blanking time must be completely shielded; the integrated charge of the gate current is introduced as a criterion, utilizing the gate-drain capacitance under short-circuit conditions. The gate charge injection effect, which does not require discharge, manifests within nanoseconds after turn-on, far exceeding the time required for desaturation. Simultaneously, the drain-source voltage drop serves as an auxiliary criterion, enhancing the robustness of the criterion. Through the synergistic extraction of these two physical quantities, step S2 provides a high-dimensional input feature with clear physical meaning and extremely fast response for the generation of the short-circuit prediction factor in step S3. This is the core step in achieving advanced early warning judgment within the desaturation detection blanking time window.

[0026] S3. Short-circuit prediction factor generation and protection trigger: The gate charge and the drain-source voltage drop are coupled and calculated to generate a short-circuit prediction factor. When the short-circuit prediction factor is less than the preset short-circuit determination threshold, the SiC MOSFET under test is determined to be in a short-circuit state, and an overcurrent protection trigger signal is output before the end of the desaturation detection blanking time window.

[0027] Step S3 is based on the gate charge extracted in step S2. With drain-source voltage drop The system generates a short-circuit prediction factor through coupling operations and determines the short-circuit state in advance within the desaturation detection blanking time window, and outputs an overcurrent protection trigger signal.

[0028] The short-circuit predictor aims to integrate the abnormal characteristics of two dimensions: gate drive energy injection and drain-source voltage response. By normalizing the ratio, it eliminates the influence of individual device differences and bus voltage fluctuations, and constructs a discriminant index that is highly sensitive to short-circuit conditions and robust to normal turn-on.

[0029] Short circuit predictor The expression is: ; It should be noted that the numerator of this expression The normalized drain-source voltage drop ratio characterizes the actual decrease in drain-source voltage from the bus voltage level at the end of the characteristic time window; during normal turn-on, The decrease is significant, and the ratio is close to 1; under short-circuit conditions, With almost no decrease, the ratio approaches 0; the denominator term The gate charge normalization ratio characterizes the ratio of the current gate charge injection amount to the normal turn-on reference value; under short-circuit conditions, due to the gate-drain capacitance... Without the need for discharge, gate charge injection is faster, and this ratio is significantly greater than 1; during normal turn-on, this ratio is around 1; therefore, under short-circuit conditions, the numerator is small and the denominator is large, resulting in a high short-circuit predictor factor. Much less than 1; Short-circuit prediction factor during normal commissioning Approximately equal to 1; this coupling ratio amplifies the difference between short circuit and normal state, improving the sensitivity and reliability of the discrimination.

[0030] In addition, the reference gate charge The calibration method is as follows: Before each short-circuit withstand test, under non-short-circuit conditions, such as disconnecting the load circuit or ensuring that the load inductor is not saturated, apply a turn-on pulse to the SiC MOSFET under test, and obtain the gate charge within the corresponding characteristic time window according to the method in step S2, as a reference value under the current temperature and bus voltage. This online calibration method can automatically eliminate the effects of temperature drift, device batch differences, and gate drive circuit parameters.

[0031] The generated short-circuit prediction factor Compared with the preset short circuit detection threshold When comparing, When the test SiC MOSFET is in a short-circuit state, it is determined that the MOSFET under test has entered a short-circuit state; among which, The value is a fixed value between 0.15 and 0.35; this threshold is obtained through statistical analysis of a large number of normal turn-on and short-circuit turn-on waveforms to ensure sufficient safety margin. In a preferred embodiment, The value is 0.25.

[0032] The decision logic is executed in real time within the desaturation detection blanking time window, which is a forced shielding period after the gate pulse is applied, typically set to 200ns to 800ns. In this embodiment, the decision can be completed at the end of the characteristic time window. The calculation and comparison are performed to actively output a short-circuit fault flag before the blanking time window has ended; Once a short circuit is detected, the short circuit fault flag is immediately set, and an overcurrent protection trigger signal is output. This trigger signal is issued before the end of the blanking time window and is used to directly block the gate drive pulse, causing the gate voltage to drop rapidly to the turn-off negative voltage, or to trigger the active clamping circuit to achieve soft turn-off protection for the SiC MOSFET under test. As a result, the effective protection window is significantly moved forward from after the blanking time of traditional desaturation detection, significantly shortening the duration of the short circuit current.

[0033] To maintain accuracy over a wide temperature range, this implementation also provides a junction temperature compensation function: the current junction temperature of the SiC MOSFET under test is obtained via a temperature sensor or thermistor parameter method. The short-circuit judgment threshold is determined based on the junction temperature correction function. Adaptive adjustment is performed so that the threshold is appropriately reduced as the junction temperature increases, in order to match the physical characteristics of the device being more prone to thermal runaway at high temperatures; The function for junction temperature correction is: ;in, For junction temperature The short-circuit detection threshold is below; The threshold value for short circuit determination at a junction temperature of 25℃ is 0.25, and a recommended value is 0.25. The current junction temperature is expressed in °C; γ is the temperature coefficient, ranging from 0.003 / ℃ to 0.008 / ℃, with a typical value of 0.005 / ℃. For example, when the junction temperature rises to 150°C, the temperature-compensated threshold drops to about 62% of that at 25°C, making short-circuit detection more sensitive at high temperatures and effectively avoiding high-temperature protection delays caused by fixed thresholds. It should be noted that the calculations involved in this embodiment all involve standardization of the data before the calculation, including but not limited to extracting the numerical values ​​of the calculation data and normalization processing. These are all existing conventional technical solutions, and the specific implementation steps will not be described in detail here.

[0034] In this embodiment of the invention, a short-circuit prediction factor with clear physical meaning is generated by coupling the gate charge and the drain-source voltage drop ratio, thereby achieving advanced determination of short-circuit faults within the desaturation detection blanking time window; this differs from existing technologies that rely entirely on the end of the blanking time. Unlike desaturation voltage detection, this step utilizes the gate charge and drain-source voltage coupling characteristics that can be extracted within a few to tens of nanoseconds during the initial turn-on transient, significantly advancing the decision-making time for short circuit detection and fundamentally compressing the protection blind zone caused by traditional blanking time. The construction of the normalized ratio automatically offsets bus voltage fluctuations and device parameter dispersion, improving the universality and consistency of the criterion. The design of online calibration of the reference gate charge enables the system to adapt to different temperatures, driving conditions, and aging states. The addition of junction temperature compensation further enhances the timeliness of protection under extreme high-temperature conditions, solving the protection problem of devices approaching the edge of thermal runaway at a junction temperature of 150°C.

[0035] In summary, step S3 achieves highly reliable short-circuit warning with extremely low delay, solves the serious compression of the effective protection window of SiC MOSFET by the blanking time paradox in desaturation detection, and provides key technical support for power devices to achieve safe turn-off within the short-circuit tolerance limit.

[0036] In the several embodiments provided by this invention, it should be understood that the disclosed methods can be implemented in other ways. For example, the embodiments of the invention described above are merely illustrative; for instance, the division of modules is only a logical functional division, and there may be other division methods in actual implementation.

[0037] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0038] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the essential characteristics of the present invention.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A short-circuit withstand test method for power devices based on overcurrent fast response protection, characterized in that, include: S1. Synchronous acquisition of turn-on transient waveform: In the SiC MOSFET short-circuit withstand test circuit, a turn-on gate pulse is applied to the SiC MOSFET under test, and the gate voltage signal, gate current signal and drain-source voltage signal of the SiC MOSFET under test are acquired at high speed simultaneously. S2. Gate charge-drain-source voltage coupling feature extraction: Within the desaturation detection blanking time window, based on the gate voltage signal, a characteristic time window from the threshold voltage moment to the preset reference voltage moment before the Miller plateau is determined, and the amount of gate charge injected within the characteristic time window is calculated using the gate current signal. At the same time, the amount of drain-source voltage drop corresponding to the end of the characteristic time window is obtained using the drain-source voltage signal. S3. Short-circuit prediction factor generation and protection trigger: The gate charge and the drain-source voltage drop are coupled and calculated to generate a short-circuit prediction factor. When the short-circuit prediction factor is less than the preset short-circuit determination threshold, the SiC MOSFET under test is determined to be in a short-circuit state, and an overcurrent protection trigger signal is output before the end of the desaturation detection blanking time window.

2. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 1, characterized in that, In step S1, the short-circuit withstand test circuit includes a DC bus power supply, a bus capacitor, a load inductor, and the SiC MOSFET under test. The output voltage of the DC bus power supply is the nominal blocking voltage of the SiC MOSFET under test. The gate current signal is acquired in real time through a current sensing resistor or an integrated current sensor connected in series in the gate drive circuit.

3. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 1, characterized in that, In step S2, the characteristic time window is determined by identifying the first moment when the gate voltage signal first rises to the threshold voltage. And the second moment before the gate voltage signal first rises to the reference voltage before the Miller plateau. Then As a characteristic time window; wherein, the reference voltage before the Miller plateau is set to be higher than the threshold voltage and lower than the typical Miller plateau start voltage.

4. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 1, characterized in that, Gate charge injected within the characteristic time window The calculation expression is: ;in, This is the gate current signal acquired in real time. and They are respectively and The corresponding sampling point index, The sampling interval; This is the gate current signal; It is a discrete sequence of gate current signals.

5. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 4, characterized in that, Drain-source voltage drop The calculation expression is: ;in, This is the DC bus voltage; This represents the instantaneous drain-source voltage value corresponding to the discrete drain-source voltage signal sequence.

6. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 5, characterized in that, Short circuit predictor The expression is: ;in, The reference gate charge is the amount measured within the same characteristic time window under pre-calibrated normal turn-on conditions.

7. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 6, characterized in that, The pre-calibration method for the reference gate charge is as follows: before each short-circuit withstand test, under non-short-circuit conditions, a turn-on pulse is applied to the SiC MOSFET under test, and the gate charge obtained within the corresponding characteristic time window is used as the reference gate charge.

8. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 6, characterized in that, The generated short-circuit prediction factor Compared with the preset short circuit detection threshold When comparing, When the test is initiated, the SiC MOSFET under test is determined to be in a short-circuit state.

9. The short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 8, characterized in that, The current junction temperature of the SiC MOSFET under test is obtained using a temperature sensor or thermistor method. The short-circuit judgment threshold is determined based on the junction temperature correction function. Adaptive adjustment is performed so that the threshold is appropriately reduced as the junction temperature increases, in order to match the physical characteristics of the device being more prone to thermal runaway at high temperatures.

10. A short-circuit withstand test method for power devices based on overcurrent fast response protection according to claim 9, characterized in that, The function for junction temperature correction is: ;in, For junction temperature The short-circuit detection threshold is below; This is the baseline value for short-circuit detection at a junction temperature of 25℃. γ is the current junction temperature; γ is the temperature coefficient.

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