A distributed control high-power converter synchronous fault recording system and method

Abstract

This invention relates to a distributed control high-power converter synchronous fault recording system and method, comprising: S1, high-precision clock synchronization communication; S2, establishment of a unified synchronous time base; S3, high-speed synchronous sampling and cyclic pre-buffering of slave controllers; S4, fault detection and uploading of slave controllers; S5, global fault distribution; S6, recording control of slave controllers; and S7, data storage and retrieval. This invention uses the control cycle count value as a unified time base, achieving nanosecond-level alignment accuracy at the sampling trigger times of each slave controller, ensuring strict alignment of recorded data on the time axis; enabling global coordinated triggering and synchronous stopping of recording by multiple slave controllers, completely recording the propagation process of faults in a multi-node system; and generating synchronous fault waveforms of all slave controllers under the same time base after recording is completed.

Description

Technical Field

[0001] This invention belongs to the field of fault monitoring and diagnosis technology for power electronic converters, specifically relating to a distributed control high-power converter synchronous fault recording system and method. Background Technology

[0002] High-power converters are core equipment in heavy-duty drive and power conversion scenarios in industries such as metallurgy, petrochemicals, power, and coal. To overcome the capacity limitations of a single unit or achieve high-voltage, high-capacity output, multiple converters of the same model are typically connected in parallel or cascaded with multi-level topology units (such as cascaded H-bridges). The system mostly adopts a distributed control architecture with one master and multiple slaves. In such systems, there are complex electromagnetic interactions and couplings between power units and between units and the control system. Once a unit fails (such as power device breakdown, overcurrent, abnormal circulating current, or submodule capacitor voltage imbalance), it can easily trigger a chain reaction within microseconds to milliseconds, causing the fault to expand or even the entire system to shut down.

[0003] When performing fault analysis on the aforementioned distributed control system, it is not only necessary to acquire high-sampling-rate waveform data of individual units / modules, but more importantly, it is necessary to obtain synchronous waveform data of all power units under the same time base to reconstruct the precise timing relationship of parameters such as voltage, current, circulating current, switching status, and fault flags of each unit at the time of the fault. Therefore, such distributed control systems have an urgent need for synchronous fault recording among multiple modules, requiring strict synchronization of the sampling clocks of each slave control unit and global coordinated triggering at the time of the fault.

[0004] Currently, most solutions are designed for single-machine setups, and even those involving parallel systems lack a global synchronization triggering mechanism from the control unit. A search of existing published patent literature revealed the following similar patent documents: 1. Chinese Patent No. CN119881476A discloses a fault recording method for low-voltage frequency converters. This method dynamically adjusts the sampling interval by detecting the zero-crossing point of the voltage and adopts a dual recording mode that combines effective value recording and real-time value recording, taking into account both high-resolution waveform capture at the moment of fault and long-term trend recording.

[0005] However, this solution is only applicable to a single low-voltage frequency converter and does not address the clock synchronization and synchronization triggering issues in scenarios involving high-power multi-machine parallel connection or multi-module cascading.

[0006] 2. Chinese Patent Publication No. CN119125698A discloses a fault recording system and method for a high-power frequency converter. The system includes a cloud server, a gateway, and a high-power frequency converter using multiple frequency converters of the same model connected in parallel. The main control adopts an FPGA+ARM+DSP chip architecture, and the slave control adopts an FPGA chip. The method is as follows: different fault types are identified and encoded through fault classification and recognition, and different types of fault data are collected and uploaded through optical fiber communication. Finally, the data is handed over to the cloud server for centralized processing and storage.

[0007] However, this scheme has the following drawbacks: In terms of clock synchronization, it uses a cascaded time synchronization method that forwards data from the cloud server through the main control ARM and the main control FPGA to the slave control FPGA. The time synchronization link is relatively long. If the time message of a certain period is delayed or lost due to network jitter or instantaneous high processor load, it will introduce millisecond-level jitter or cause the synchronization error to accumulate continuously over time, resulting in poor synchronization reliability. Furthermore, it lacks a timestamp anomaly detection and error correction recovery mechanism. In terms of the triggering mechanism, the fault triggering of this scheme relies on the local criteria of each slave control and lacks a global synchronization triggering mechanism for multiple machines in a distributed system. When a slave control fails, other slave controls cannot start recording waveforms accurately at the same time, making it difficult to fully record and accurately analyze the propagation process of the fault among multiple machines / modules.

[0008] The applicant of this patent application filed a Chinese patent application in 2025, publication number CN119995764A, entitled "A High-Precision Clock Synchronization Device and Method for Parallel Control of High-Power Devices," which proposes a systematic solution to the synchronization defects of existing cascaded time synchronization paths. The patent discloses a high-precision clock synchronization device and method based on an FPGA main control chip and 50MHz high-speed optical fiber communication. The main controller is connected to multiple slave controllers in a parallel topology, employing a bidirectional timestamp mechanism (the master station records the transmission time T_Z1 and the reception time T_Z4, and the slave stations record the reception time T_S2 and the transmission time T_S3). The average optical fiber line delay is calculated through multiple communication transmissions, and random errors caused by protocol parsing time fluctuations are suppressed based on a proportional feedback closed-loop method. Simultaneously, a damping feedback coefficient k is introduced to eliminate system oscillations caused by long-period integration of the clock error compensation amount offset. Finally, a large-inertia filter is used to obtain the compensation clock TC, enabling the slave control clock TSC (slave communication clock TS + compensation clock TC) to achieve a high-precision, low-fluctuation synchronization effect. This scheme employs a 200MHz counting clock (5ns per unit time) to calibrate the slave communication clock every 0.5ms. Furthermore, the crystal oscillator offset can be obtained via offset to achieve crystal chip consistency screening, further improving crystal drift at the hardware level. This fundamentally solves the millisecond-level jitter and synchronization error accumulation problems caused by cascaded time synchronization, providing a nanosecond-level accurate time reference for distributed control systems.

[0009] However, the patent's technical solution primarily focuses on the clock synchronization device itself and the implementation of the synchronization method. Its direct purpose is to ensure the real-time performance and control consistency of the parallel control system for high-power devices. It does not address how to construct a high-speed fault recording system based on this high-precision synchronization architecture, nor does it disclose key technologies such as the global synchronization triggering strategy required for fault recording, the multi-node recording control method at fault moments, and fault propagation characteristic analysis. In other words, high-precision clock synchronization is a necessary prerequisite for achieving high-speed synchronous fault recording, but nanosecond-level clock synchronization alone is insufficient to meet the comprehensive requirements of distributed control systems for fault recording in terms of trigger synchronization, data integrity, timing accuracy, and fault traceability.

[0010] In summary, although the applicant's prior patent application has solved the fundamental problem of nanosecond-level high-precision clock synchronization in distributed control systems, existing technologies still lack a high-speed synchronous fault recording system specifically designed for high-power power electronic converters employing distributed control architectures, based on this high-precision synchronization architecture. Existing solutions either only apply to single-machine scenarios, or while involving multiple machines / modules, lack sufficient synchronization accuracy and a global collaborative triggering mechanism, or while possessing high-precision synchronization, they do not extend to waveform recording applications. All these solutions suffer from deficiencies such as insufficient time alignment accuracy of multi-node waveform recording data, difficulty in triggering global synchronization at the moment of fault, and difficulty in fully reconstructing the fault propagation process among multiple nodes. Consequently, they cannot meet the high-speed, accurate, and comprehensive fault recording requirements of high-power distributed power electronic converters. Summary of the Invention

[0011] The purpose of this application is to overcome the shortcomings of the prior art and provide a distributed control high-power converter synchronous fault recording system and method, which aims to solve the following three problems: first, the fault triggering is not synchronized; second, it is difficult to accurately align the multi-machine recording data; and third, the fault propagation process cannot be completely restored.

[0012] The technical problem solved by this application is achieved through the following technical solution: A distributed control high-power converter synchronous fault recording system is provided. The system is applicable to high-power power electronic converters with a distributed control architecture. The above devices all adopt a master-slave control architecture, including one master controller and N slave controllers. The master controller and each slave controller form a star topology communication network through independent optical fiber links. The main controller consists of a main control FPGA and a main control ARM processor. The main control FPGA integrates a high-precision clock synchronization 50MHz fiber optic communication main module and a global fault distribution module. The 50MHz fiber optic communication module is used to realize the high-precision synchronization clock, generate a global control cycle count value for each slave station to synchronize and record waveforms, and also undertake data interaction and transmission. The main control ARM processor is responsible for data storage management and human-machine interaction. The slave controller includes a slave FPGA and a high-speed analog-to-digital converter (AD chip). The slave FPGA has a built-in high-precision clock synchronization 50MHz fiber optic communication slave module, a high-speed synchronous sampling module, a cyclic pre-buffering module, a fault detection module, and a waveform recording control module. Each master FPGA establishes independent point-to-point bidirectional 50MHz fiber optic communication with each slave FPGA for transmitting high-precision synchronous clock stamps, control cycle count values, fault flag signals, global trigger signals, waveform recording control words, waveform recording status words, and waveform recording data frames.

[0013] Furthermore, the master controller and slave controller obtain a high-precision, low-fluctuation slave controller clock TSC through bidirectional timestamp recording, average fiber optic line delay calculation, proportional feedback closed-loop damping compensation, and large inertia filtering.

[0014] A distributed control high-power converter synchronous fault recording method is applied to the recording system described above. The steps of the method are as follows: S1. High-precision clock synchronization communication: The high-precision clock synchronization 50MHz fiber optic communication master module and slave module are responsible for the interaction and transmission of control cycle count values ​​(i.e., the time base for synchronous waveform recording), fault flag signals, global fault trigger signals, waveform recording control words, waveform recording status words, and waveform recording data frames. The master controller sends data to the slave controller multiple times at fixed time intervals within a control cycle, with the timing of each data transmission recorded sequentially as T1, T2, T3…T… x The timing of sending the corresponding data after receiving data from the controller is denoted as TS. x ; S2. Establish a unified time base: The master controller generates a global time base and distributes it to each slave controller. Each slave controller uses a high-precision synchronous clock aligned with the master controller to achieve local time synchronization under a unified clock base. S3. High-speed synchronous sampling and cyclic pre-buffering from the controller: Each slave controller, according to the requirements of the high-speed synchronous fault recording acquisition rate, synchronously acquires two types of signals and writes them into the FIFO with a fixed acquisition period of 0.5 to 2 μs: one is the electrical analog signal acquired by the high-speed AD chip, including DC bus voltage, AC port voltage / current, submodule capacitor voltage and bridge arm current; the other is the switching status signal of power devices or submodules and the digital signal of overvoltage, overcurrent, short circuit, over-temperature, and capacitor voltage imbalance fault protection; the analog signal is converted into a 16-bit digital signal by the high-speed analog-to-digital converter, and the digital signal is integrated into a 16-bit status word to achieve a uniform bit width for all signals to be recorded; S4. Fault detection and uploading from the controller: The signal that triggers high-speed fault recording is a serious fault signal that affects the safe operation of a high-power distributed system. The specific fault type is determined according to the device protection strategy: in parallel frequency converters, it includes overvoltage, overcurrent, circulating current faults, power module drive faults, and power module short circuits; in the H-bridge system, it also includes submodule capacitor voltage over-limit and power unit bypass failure, but its control logic for triggering recording is consistent with the above process. The slave FPGA monitors the local operating status in real time. When a major fault signal is detected, the control cycle count value at the time of the fault is recorded. When the current control cycle count value is determined When the fault signal to be uploaded is set to 1, the slave controller will inform the master controller FPGA of the fault information through the uplink fiber optic cable in the next control cycle, regardless of whether the fault occurs before or after the slave controller uploads the fault signal. S5, Global Fault Distribution: Within each control cycle, the T1 timing sequence of the master controller and the TS1 timing sequence of the slave controller are used to exchange fault information, waveform recording control words, waveform recording status words, and fault data, regardless of whether the fault occurs in the slave controller cycle. Before or after TS1, the controller is in a cycle. Then, upload the fault marker at position 1 at time TS1; After the master controller captures N fault signals from the slave controllers, it generates N global fault trigger signals corresponding to each slave controller. S6. Slave controller waveform recording control: The slave FPGA uses the local control cycle count value when a fault trigger signal is generated or received as the trigger timestamp; the timestamp is recorded when a fault trigger signal is generated locally. Record the timestamp when a global trigger signal is received. The global trigger signal issued by the fault source controller will eventually inform all slave controllers, so each slave controller holds at least one... or The controller determines the fault timeline of each slave controller based on the fault source identifier and trigger timestamp; and precisely controls the recording stop time of all slave controllers based on the fault timeline. S7. Data storage and retrieval: The slave FPGA uploads the status word containing the trigger stop signal to the master FPGA through an independent fiber optic link and stores it in the dual-port RAM shared by the master and ARM. The ARM uses the parallel bus to periodically read the dual-port RAM. Once the trigger stop signal is detected, it broadcasts the control word for retrieving the fault waveform to each slave controller through the dual-port RAM and the fiber optic link. After receiving the command from the controller, the waveform data is uploaded in batches according to the channel group. Each time, one group is selected and N_data data and a status word containing channel group and channel type information are transmitted. N_data is determined by the amount of data in a single communication. After receiving the waveform data, the ARM stores it in the local SD card according to the channel group and type. When the host computer retrieves the fault waveform, the ARM uploads the selected waveform data to the host computer, which then draws the fault waveform.

[0015] Furthermore, the master controller and slave controller of S1 exchange multiple sets of data within one control cycle. The master controller sends one set of data at fixed intervals, and can send it continuously n times. The timing sequence of sending and receiving each set of data is as follows: the master controller in T x Data is constantly sent to the slave controller, and after the slave controller receives the data, it is processed in TS. x The corresponding data group is sent to the master controller at each time point, and the master controller receives the data from the slave controller at the time point T of the master controller's transmission sequence. x+1 Time and T x+2 Between moments.

[0016] Furthermore, S2 specifically involves: the main controller generating a global synchronization clock based on a 200MHz counting clock. To improve resolution accuracy, the synchronization clock value is incremented by 8 every 5ns, with a control cycle of 0.5ms. The counting range is 0~800k. The main controller cyclically accumulates the global control cycle count value at the start of the synchronization clock, recorded as... And it is synchronously distributed to each slave controller through communication data frames. The maximum value of the control cycle count is determined by the duration of the fault recording waveform. The controller time synchronization mechanism employs the following synchronization strategy: (1) Normal synchronization: When the data frame is verified to be correct, the slave controller loads the received global count value into the local control cycle counter at the start of the synchronization clock to achieve precise synchronization with the master controller; (2) Abnormal retention: If the data frame verification fails, the local counter will automatically accumulate based on its own crystal oscillator to maintain the continuity of the time base and avoid synchronization interruption; (3) Automatic correction: When communication returns to normal and the data frame is verified to be correct again, the local counter will automatically correct and synchronize with the global counter value at the start of the next synchronization clock, and the accurate synchronization state can be restored without manual intervention.

[0017] Moreover, the method for achieving high-speed synchronous sampling in S3 is as follows: the AD sampling trigger signal of each slave controller is generated by the TSC clock counter which has achieved high-precision synchronization. When the TSC counter accumulates to the count value corresponding to one sampling cycle, it automatically outputs a trigger pulse to start the AD conversion. Meanwhile, to suppress the impact of local crystal oscillator phase difference on AD drive timing, the high-speed synchronous sampling module applies periodic synchronous reset to the frequency divider counter inside each slave station AD driver based on the slave controller clock TSC, eliminating the phase offset of the SPI communication clock of each station; the digital status word is synchronously latched at the same trigger moment to ensure the time consistency between analog and digital quantities. Based on the high-precision synchronous slave controller clock TSC, each slave controller has nanosecond-level alignment accuracy in the acquisition trigger moment, and the waveform data is strictly aligned on the time axis. Each controller allocates A+B independent 16-bit FIFOs based on the number of analog channels A and digital channels B to be recorded. It uses a cyclic overlay mode to continuously store the sampled data of the most recent period. When a recording stop signal is detected, the write pointer is frozen to retain the complete recording window before and after the fault for uploading and analysis.

[0018] Furthermore, in step S5, after the master controller captures N fault signals from slave controllers, it generates N global fault trigger signals corresponding to each slave controller. Specifically, the rule is: when any slave controller other than itself uploads a fault flag bit of 1, the global trigger signal of that slave controller is triggered periodically. T3 and period Set between time T2 and the period Reset between T2 and T3; the main controller in cycle At time T1, N global fault trigger signals are broadcast to each slave controller via independent parallel optical fibers.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. In response to the millisecond-level jitter and synchronization error accumulation problems caused by cascaded timing paths in existing technologies, this invention relies on the nanosecond-level high-precision clock synchronization architecture already implemented in the prior patent application. It uses the control cycle count value as a unified time reference to achieve nanosecond-level alignment accuracy of the sampling trigger time of each slave controller. The waveform data is strictly aligned on the time axis, fundamentally solving the defect that it is difficult to accurately align the waveform data of multiple nodes.

[0020] 2. To address the problem in existing technologies where fault triggering relies on local criteria of each slave controller and lacks a global synchronization triggering mechanism, this invention proposes a global fault distribution module and a fault timing sorting algorithm: After the master controller aggregates the fault flags of all slave controllers, it broadcasts a global fault triggering signal through independent parallel optical fibers, with an end-to-end delay deterministically defined as 2 control cycles; each slave controller, based on the fault source identifier (local / non-local) and trigger timestamp (…),… The system performs fault sequencing, accurately calculates the waveform recording stop time, and realizes global coordinated triggering and synchronous stopping of waveform recording by multiple slave controllers. It fully records the propagation process of faults in the multi-node system. After waveform recording is completed, it can generate synchronous fault waveforms of all slave controllers under the same time reference.

[0021] 3. The present invention has the ability to maintain and automatically correct communication in case of communication failure: When data frame verification fails, the local counter of each slave controller automatically accumulates based on its own crystal oscillator to maintain the continuity of the time base; after communication is restored to normal, it automatically corrects and synchronizes with the global count value without manual intervention, ensuring the synchronization reliability under long-term operation.

[0022] 4. The scope of protection of this invention covers various high-power converters that adopt a distributed control architecture, including but not limited to converters that adopt multi-level topologies such as NPC three-level, ANPC three-level, T-type three-level, flying capacitor type, and cascaded H-bridge. Its distributed control architecture and synchronous fault recording method remain consistent under different topologies. Only the number of analog channels A and the number of digital status words B are flexibly configured according to the specific topology, which has strong versatility. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the system architecture and data flow of the present invention; Figure 2 This is a diagram illustrating the optical fiber communication data interaction of the present invention. Figure 3 This is a waveform diagram of the clock and control cycle count values ​​of the present invention; Figure 4 This is a timing diagram for global fault distribution in this invention; Figure 5 This is a fault sequencing timing diagram for a single fault source scenario according to the present invention; Figure 6 This is a timing diagram for fault sequencing in a multi-fault-source scenario according to the present invention; Figure 7 The waveform diagram is for the high-speed synchronous fault recording data of this invention. Detailed Implementation

[0024] The present application will be further described in detail below through specific embodiments. The following embodiments are merely descriptive and not limiting, and should not be used to limit the scope of protection of the present application.

[0025] An innovative distributed control system for synchronous fault recording of high-power frequency converters is described below: This embodiment applies to a system of three high-power parallel frequency converters, including one master controller and three slave controllers. The master controller adopts an FPGA+ARM architecture, and the three slave FPGAs control the power units of the three frequency converters respectively. The master controller and each slave controller form a star topology communication network through independent optical fiber links.

[0026] The main controller consists of a main control FPGA and a main control ARM processor. The main control FPGA integrates a high-precision clock synchronization 50MHz fiber optic communication main module and a global fault distribution module. The 50MHz fiber optic communication module is used to realize the high-precision synchronization clock, generate a global control cycle count value for each slave station to synchronize waveform recording, and also undertake data interaction and transmission. The main control ARM processor is responsible for data storage management and human-machine interaction.

[0027] The controller corresponds to each power unit (or power unit group), but the specific correspondence does not affect the waveform recording architecture of this invention. Each slave controller includes a slave FPGA and a high-speed analog-to-digital converter (ADC) chip. The slave FPGA integrates a high-precision clock synchronization 50MHz fiber optic communication slave module, a high-speed synchronous sampling module, a cyclic pre-buffering module, a fault detection module, and a waveform recording control module.

[0028] In terms of communication links, an independent point-to-point bidirectional 50MHz optical fiber communication is established between the master FPGA and each slave FPGA to transmit key information such as high-precision synchronous clock stamps, control cycle count values, fault flag signals, global trigger signals, waveform recording control words, waveform recording status words, and waveform recording data frames.

[0029] A distributed control high-power converter synchronous fault recording method is applied to the recording system described above. The steps of the method are as follows: (1) High-precision clock synchronization communication The high-precision clock synchronization adopts the synchronization architecture based on FPGA and 50MHz high-speed optical fiber communication disclosed in the applicant's prior application. The master controller and slave controller obtain a high-precision, low-fluctuation slave controller clock TSC through bidirectional timestamp recording, average optical fiber line delay calculation, proportional feedback closed-loop damping compensation, and large inertia filtering. The implementation method will not be described in detail here.

[0030] Based on this architecture, in addition to implementing the clock synchronization function in the prior patent, the high-precision clock synchronization 50MHz fiber optic communication master module and slave module also undertake the following data interaction and transmission: control cycle count value (i.e., the time base for synchronous waveform recording), fault flag signal, global fault trigger signal, waveform recording control word, waveform recording status word, and waveform recording data frame.

[0031] like Figure 2As shown, the master controller and slave controller exchange multiple sets of data within one control cycle. The master controller sends a set of data at fixed intervals (e.g., 10µs), and can send n sets of data consecutively. The timing of sending and receiving each set of data is as follows: the master controller sends data to the slave controller at time Tx, and after receiving the data, the slave controller sends the corresponding data set back to the master controller at time TSx. The moment when the master controller receives the data from the slave controller falls between the master controller's sending timings T2 and T3.

[0032] (2) Establish a synchronized and unified time base like Figure 3 As shown, to achieve synchronized waveform recording among slave controllers that have no physical connection, a unified time base needs to be established. In a master-slave architecture, the master controller generates a global time base and distributes it to each slave controller. Each slave controller uses a high-precision synchronous clock aligned with the master controller to achieve local time synchronization under the unified clock base.

[0033] Global Time Base Generation and Distribution: The main controller generates a global synchronization clock based on a 200MHz counting clock (5ns resolution). To improve resolution accuracy, the synchronization clock value is incremented by 8 every 5ns. A control cycle is defined as 0.5ms, with a counting range of 0~800k. The main controller cyclically accumulates the global control cycle count value (denoted as ) at the beginning of the synchronization clock. The data is synchronously distributed to each slave controller via communication data frames. The maximum value of the control cycle count is determined by the duration of the fault recording waveform.

[0034] Time synchronization mechanism from the controller: Due to communication timing issues, there is a certain lag in receiving the count value from the controller. To address this problem, the following synchronization strategy is adopted: (1) Normal synchronization: When the data frame is verified to be correct, the controller loads the received global count value into the local control cycle counter at the starting point of the synchronization clock to achieve precise synchronization with the main controller.

[0035] (2) Abnormal retention: If the data frame verification fails, the local counter will automatically accumulate based on its own crystal oscillator to maintain the continuity of the time base and avoid synchronization interruption.

[0036] (3) Automatic correction: When communication returns to normal and the data frame is verified to be correct again, the local counter will automatically correct and synchronize with the global counter value at the start of the next synchronization clock, and the accurate synchronization state can be restored without manual intervention.

[0037] This mechanism relies on a high-precision synchronous clock aligned with the master controller and a global control cycle count value to ensure the continuity and reliability of the time reference of each slave controller in the event of communication transient anomalies, providing a stable and unified time coordinate for synchronous waveform recording.

[0038] (3) High-speed synchronous sampling and cyclic pre-buffering module from the controller Each slave controller, based on the high-speed synchronous fault recording acquisition rate requirement, synchronously acquires two types of signals and writes them into the FIFO with a fixed acquisition period of 0.5–2 μs: one is the local electrical analog signals acquired by the high-speed AD chip (including but not limited to DC bus voltage, AC port voltage / current, submodule capacitor voltage, bridge arm current, etc., the specific channel configuration is determined according to the device topology); the other is the switching status signals of power devices or submodules, as well as digital signals for fault protection such as overvoltage, overcurrent, short circuit, over-temperature, and capacitor voltage imbalance. The analog signals are converted into 16-bit digital signals by a high-speed analog-to-digital converter, and the digital signals are integrated into a 16-bit status word, achieving a uniform bit width for all signals to be recorded.

[0039] The method for achieving high-speed synchronous sampling is as follows: The AD sampling trigger signal of each slave controller is generated by a TSC clock counter that has achieved high-precision synchronization. The TSC counter automatically outputs a trigger pulse to start the AD conversion when it accumulates to the count value corresponding to one sampling cycle. Simultaneously, to suppress the influence of local crystal oscillator phase difference on the AD drive timing, the high-speed synchronous sampling module applies a periodic synchronous reset to the frequency divider counter inside each slave station's AD driver based on the slave controller clock TSC, eliminating the phase offset of the SPI communication clock at each station. Digital status words are synchronously latched at the same trigger moment, ensuring the time consistency between analog and digital quantities. Based on the high-precision synchronized slave controller clock TSC, the acquisition trigger moment of each slave controller has nanosecond-level alignment accuracy, and the recorded waveform data is strictly aligned on the time axis.

[0040] Each slave controller allocates A+B independent 16-bit FIFOs based on the number of analog channels (A) and digital channels (B) to be recorded. These FIFOs use a cyclic overlay mode to continuously store the most recently sampled data. When a recording stop signal is detected, the write pointer is frozen, preserving the complete recording window before and after the fault for upload and analysis. It should be noted that the correspondence between slave controllers and controlled power units (or power unit groups) can be flexibly configured according to the topology, but the system architecture and synchronous recording method remain unchanged.

[0041] (4) From controller fault detection and uploading The signals that trigger high-speed fault recording are usually serious fault signals that affect the safe operation of high-power distributed systems. The specific fault type is determined according to the device protection strategy: in parallel frequency converters, these include overvoltage, overcurrent, circulating current faults, power module drive faults, power module short circuits, etc.; in H-bridge systems, these also include submodule capacitor voltage over-limit, power unit bypass failure, etc., but the control logic for triggering the recording is the same as the above process.

[0042] The controller FPGA monitors the local operating status in real time. When a major fault signal is detected, the control cycle count value at the time of the fault is recorded. When the current control cycle count value is determined At this time, it is allowed to set the critical fault signal to be uploaded to 1, that is, regardless of whether the fault occurs before or after the time when the fault signal is uploaded by the slave controller, the slave controller will inform the master controller FPGA of the critical fault information through the uplink optical fiber in the next control cycle.

[0043] (5) Global fault distribution like Figure 4 As shown, within each control cycle, the T1 timing of the master controller and the TS1 timing of the slave controller are specifically used for exchanging fault information, waveform recording control words, waveform recording status words, and fault data. This applies regardless of whether the fault occurs during the slave controller cycle. Before or after TS1, the controller is in a cycle. Then, mark the fault as position 1 and upload it at time TS1.

[0044] One master controller corresponds to N slave controllers. When the master controller captures fault signals from N slave controllers, it generates N global fault trigger signals, each corresponding to a different slave controller. The specific rules are as follows: when any slave controller other than itself uploads a fault flag bit of 1, that slave controller's global trigger signal is activated periodically. T3 and period Set between time T2 and the period The main controller resets between T2 and T3. At time T1, N global fault trigger signals are broadcast to each slave controller via independent parallel optical fibers. In summary, the end-to-end delay of global fault distribution is 2 control cycles, meaning that the time window from the occurrence of a fault in any slave controller to the receipt of global trigger signals by all slave controllers is deterministic.

[0045] (6) Control from the waveform recording of the controller Distributed control system fault sequencing timing, such as Figure 5 and Figure 6 As shown. All controllers operate under strictly synchronized control cycles, and in each control cycle, they perform a fixed "receive (RX) first, then transmit (TX)" communication action. Furthermore, the transmission of the global fault trigger signal between controllers has a fixed delay of 2 control cycles.

[0046] The FPGA controller uses the local control cycle count value (strictly synchronized across all slave controllers) at the time of generating or receiving a fault trigger signal as the trigger timestamp: the timestamp is recorded when the fault trigger signal is generated locally. Record the timestamp when a global trigger signal is received. The global trigger signal issued by the fault source controller will eventually inform all slave controllers (excluding itself), therefore each slave controller holds at least one trigger signal. or . Figure 5 and Figure 6 The fault sequencing timeline is shown in single-fault-source and multi-fault-source scenarios respectively. The fault timeline of each slave controller is determined by the fault source identifier and trigger timestamp.

[0047] by Figure 5 Taking controller 1 as an example, if there is only a local trigger signal, then the source of the fault is the local controller; by Figure 5 Taking controller 2 as an example, if there is only a global trigger signal, the source of the fault is other slave controllers; If both local and global trigger signals exist simultaneously: by Figure 6 Taking controller 1 as an example, when ,and This indicates that the local fault source occurred earlier than other slave controller fault sources. by Figure 6 Taking controller 2 as an example, when ,and This indicates that other fault sources from the controller and local fault sources occur within the same control cycle; by Figure 6 controller For example, when ,and This indicates that other controller fault sources occurred earlier than the local fault source; by Figure 6 controller Taking fault point 4 as an example, when This indicates that other controller fault sources occurred earlier than the local fault source; Based on the aforementioned fault timeline, the recording stop time of all slave controllers can be precisely controlled. This allows for precise control of the recording stop time before triggering. Each control cycle and after triggering Taking one control cycle as an example (the total number of recorded control cycles is...), , ): If the first fault source is the local controller, or another fault source from the slave controller is in the same control cycle as the local fault source, then when the control cycle count reaches... A recording stop signal is generated at certain times, controlling the FIFO to stop writing data; If the first fault source is another slave controller, or the fault source of another slave controller is earlier than the local fault source, then when the control cycle count reaches... A recording stop signal is generated at certain times to control the FIFO to stop writing data.

[0048] To facilitate the analysis of waveform characteristics before and after a fault, the fault recording period is usually divided into... , ,or The proportions are allocated accordingly.

[0049] (7) Data storage and retrieval Each slave controller's FPGA uploads a status word containing a trigger stop signal to the master controller's FPGA via an independent fiber optic link and stores it in its shared dual-port RAM with the ARM. The ARM periodically reads the dual-port RAM using a parallel bus. Once a trigger stop signal is detected, it broadcasts a control word for retrieving the fault waveform to each slave controller via the dual-port RAM and fiber optic link. Upon receiving the command, the slave controller uploads the waveform data in batches according to channel groups. Each time, it selects one group and transmits N_data data points and a status word containing channel group and channel type information. N_data is determined by the amount of data in a single communication. After receiving the data, the ARM stores the waveform data into its local SD card according to the channel group and type. When the host computer retrieves the fault waveform, the ARM uploads the selected waveform data to the host computer, which then plots it as shown in the image. Figure 7 The fault recording waveform is shown.

[0050] It should be noted that for different topologies, the number of analog channels A and the number of digital status words B can be flexibly adjusted according to actual needs, while the above data storage, group upload and read processes remain unchanged. The waveform recording system architecture and method of this invention have wide topology adaptability.

[0051] Example 1: High-speed synchronous fault recording of three parallel frequency converters like Figure 1 As shown, this embodiment is applied to a system with three high-power parallel frequency converters. The main controller adopts an FPGA+ARM architecture, and the three slave FPGAs control the power units of the three frequency converters respectively.

[0052] The specific parameter configurations are as follows: Control cycle: 0.5ms; Acquisition cycle: 1us; Number of analog channels A=7 (DC voltage, three-phase AC voltage, three-phase AC current); Number of digital status words B=2 (1 switch status word + 1 fault flag); Recording window: M=7 control cycles before triggering, K=8 control cycles after triggering, ratio M+1:K=1:1; Single communication data volume N_data=8.

[0053] Work process: Step 1: The three slave FPGAs achieve nanosecond-level clock synchronization based on prior application. The master controller generates a global control cycle count value and distributes it to each slave controller. Step 2: Each slave controller synchronously acquires 7 analog signals and 8 digital signals at a 1µs cycle, and writes them cyclically into the FIFO; Step 3: When controller 1 is in a cycle When an overcurrent fault is detected, record. In the next control cycle Set the fault flag to 1 and upload it to the main control FPGA; Step 4: After receiving fault flags from the three slave controllers, the master FPGA generates three global fault trigger signals, which are executed periodically. The T1 time is broadcast in parallel to each slave controller; Step 5: Each control unit based on and The fault timeline shows that controller 1 (locally launched) is in... +9 stops recording; controller 2 / 3 is in... +7 Stop recording; Step Six: After waveform recording stops, each slave controller uploads the FIFO data to the main controller ARM according to the channel group. The ARM stores the data for the host computer to retrieve and analyze.

[0054] Example 2: Autonomous Maintenance and Automatic Correction under Communication Anomalies Suppose that in Example 1, controller 2 experiences a fiber optic communication frame verification failure during a certain control cycle: Abnormal state: The local counter of controller 2 accumulates autonomously based on its own crystal oscillator, maintains the continuity of the time base, and continues to perform high-speed sampling and FIFO cyclic writing. The fault detection function is unaffected. Recovery process: Once communication is restored, controller 2 will automatically align the local counter with the global control cycle count value at the start of the next synchronization clock, without requiring manual intervention. Effect: The timeline of the recorded waveform data remains continuous throughout the entire abnormal period, without any time jumps or data breaks.

[0055] Example 3: Recording Stop Control in Concurrent Fault Source Scenarios Assume that in Example 1, the three frequency converters fail sequentially: Controller 1 experiences an overcurrent fault when the control cycle count value N1=2; Controller 2 triggers overcurrent protection when N2=4 due to the circulating current caused by the fault in Controller 1; Controller 3 is normal.

[0056] Timing: Each slave controller records its own fault and global fault timestamps, and controller 1 records... , Controller 2 records , Controller 3 records .

[0057] Waveform recording stop judgment: Controller 1 determines the local start and stops the count value = Controller 2 makes a judgment = If other controllers are determined to be the initial fault, stop the counter value = Controller 3 determines that the initial local fault signal is not the first one received, and stops counting based on the first global fault signal received. The timelines of the waveform recordings from the three controllers are strictly aligned, allowing for a complete reconstruction of the fault propagation path.

[0058] Although embodiments and drawings of the present invention have been disclosed for illustrative purposes, those skilled in the art will understand that various substitutions, variations and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the scope of the present invention is not limited to the contents disclosed in the embodiments and drawings.

Claims

1. A distributed control high-power converter synchronous fault recording system, characterized in that: The system is applicable to high-power power electronic conversion devices with a distributed control architecture. The devices all adopt a master-slave control architecture, including one master controller and N slave controllers. The master controller and each slave controller form a star topology communication network through independent optical fiber links. The main controller consists of a main control FPGA and a main control ARM processor. The main control FPGA integrates a high-precision clock synchronization 50MHz fiber optic communication main module and a global fault distribution module. The 50MHz fiber optic communication module is used to realize the high-precision synchronization clock, generate a global control cycle count value for each slave station to synchronize and record waveforms, and also undertake data interaction and transmission. The main control ARM processor is responsible for data storage management and human-machine interaction. The slave controller includes a slave FPGA and a high-speed analog-to-digital converter (AD chip). The slave FPGA has a built-in high-precision clock synchronization 50MHz fiber optic communication slave module, a high-speed synchronous sampling module, a cyclic pre-buffering module, a fault detection module, and a waveform recording control module. Each master FPGA establishes independent point-to-point bidirectional 50MHz fiber optic communication with each slave FPGA for transmitting high-precision synchronous clock stamps, control cycle count values, fault flag signals, global trigger signals, waveform recording control words, waveform recording status words, and waveform recording data frames.

2. The distributed control high-power converter synchronous fault recording system according to claim 1, characterized in that: The master controller and slave controller obtain a high-precision, low-fluctuation slave controller clock (TSC) through bidirectional timestamp recording, average fiber optic line delay calculation, proportional feedback closed-loop damping compensation, and large inertia filtering.

3. A method for synchronous fault recording in a distributed control high-power converter, characterized in that: Applied to the waveform recording system as described in any one of claims 1 and 2, the method comprises the following steps: S1. High-precision clock synchronization communication: The high-precision clock synchronization 50MHz fiber optic communication master module and slave module are responsible for the interaction and transmission of control cycle count values ​​(i.e., the time base for synchronous waveform recording), fault flag signals, global fault trigger signals, waveform recording control words, waveform recording status words, and waveform recording data frames. The master controller sends data to the slave controller multiple times at fixed time intervals within a control cycle, with the timing of each data transmission recorded sequentially as T1, T2, T3…T… x The timing of sending the corresponding data after receiving data from the controller is denoted as TS. x ; S2. Establish a unified time base: The master controller generates a global time base and distributes it to each slave controller. Each slave controller uses a high-precision synchronous clock aligned with the master controller to achieve local time synchronization under a unified clock base. S3. High-speed synchronous sampling and cyclic pre-buffering from the controller: Each slave controller, according to the requirements of the high-speed synchronous fault recording acquisition rate, synchronously acquires two types of signals and writes them into the FIFO with a fixed acquisition period of 0.5 to 2 μs: one is the electrical analog signal acquired by the high-speed AD chip, including DC bus voltage, AC port voltage / current, submodule capacitor voltage and bridge arm current; the other is the switching status signal of power devices or submodules and the digital signal of overvoltage, overcurrent, short circuit, over-temperature, and capacitor voltage imbalance fault protection; the analog signal is converted into a 16-bit digital signal by the high-speed analog-to-digital converter, and the digital signal is integrated into a 16-bit status word to achieve a uniform bit width for all signals to be recorded; S4. Fault detection and uploading from the controller: The signal that triggers high-speed fault recording is a serious fault signal that affects the safe operation of a high-power distributed system. The specific fault type is determined according to the device protection strategy: in parallel frequency converters, it includes overvoltage, overcurrent, circulating current faults, power module drive faults, and power module short circuits; in the H-bridge system, it also includes submodule capacitor voltage over-limit and power unit bypass failure, but its control logic for triggering recording is consistent with the above process. The slave FPGA monitors the local operating status in real time. When a major fault signal is detected, the control cycle count value at the time of the fault is recorded. When the current control cycle count value is determined to be... When the fault signal to be uploaded is set to 1, the slave controller will inform the master controller FPGA of the fault information through the uplink fiber optic cable in the next control cycle, regardless of whether the fault occurs before or after the slave controller uploads the fault signal. S5, Global Fault Distribution: Within each control cycle, the T1 timing sequence of the master controller and the TS1 timing sequence of the slave controller are used to exchange fault information, waveform recording control words, waveform recording status words, and fault data, regardless of whether the fault occurs in the slave controller cycle. Before or after TS1, the controller is in a cycle. Then, upload the fault marker at position 1 at time TS1; After the master controller captures N fault signals from the slave controllers, it generates N global fault trigger signals corresponding to each slave controller. S6. Slave controller waveform recording control: The slave FPGA uses the local control cycle count value when a fault trigger signal is generated or received as the trigger timestamp; the timestamp is recorded when a fault trigger signal is generated locally. Record the timestamp when a global trigger signal is received. The global trigger signal issued by the fault source controller will eventually inform all slave controllers, so each slave controller holds at least one trigger signal. or The controller determines the fault timeline of each slave controller based on the fault source identifier and trigger timestamp; and precisely controls the recording stop time of all slave controllers based on the fault timeline. S7. Data storage and retrieval: The slave FPGA uploads the status word containing the trigger stop signal to the master FPGA through an independent fiber optic link and stores it in the dual-port RAM shared by the master and ARM. The ARM uses the parallel bus to periodically read the dual-port RAM. Once the trigger stop signal is detected, it broadcasts the control word for retrieving the fault waveform to each slave controller through the dual-port RAM and the fiber optic link. After receiving the command from the controller, the waveform data is uploaded in batches according to the channel group. Each time, one group is selected and N_data data and a status word containing channel group and channel type information are transmitted. N_data is determined by the amount of data in a single communication. After receiving the waveform data, the ARM stores it in the local SD card according to the channel group and type. When the host computer retrieves the fault waveform, the ARM uploads the selected waveform data to the host computer, which then draws the fault waveform.

4. The distributed control high-power converter synchronous fault recording method according to claim 3, characterized in that: The master controller and slave controller of S1 exchange multiple sets of data within one control cycle. The master controller sends a set of data at fixed intervals, and can send it continuously n times. The timing sequence of sending and receiving each set of data is as follows: the master controller in T x Data is constantly sent to the slave controller, and after the slave controller receives the data, it is processed in TS. x The corresponding data group is sent to the master controller at each time point, and the master controller receives the data from the slave controller at the time point T of the master controller's transmission sequence. x+1 Time and T x+2 Between moments.

5. The distributed control high-power converter synchronous fault recording method according to claim 3, characterized in that: Specifically, S2 involves the main controller generating a global synchronization clock based on a 200MHz counting clock. To improve resolution, the synchronization clock value is incremented by 8 every 5ns, with a control cycle of 0.5ms. The counting range is 0~800k. The main controller cyclically accumulates the global control cycle count value at the start of the synchronization clock, recorded as follows: And it is synchronously distributed to each slave controller through communication data frames. The maximum value of the control cycle count is determined by the duration of the fault recording waveform. The controller time synchronization mechanism employs the following synchronization strategy: (1) Normal synchronization: When the data frame is verified to be correct, the slave controller loads the received global count value into the local control cycle counter at the start of the synchronization clock to achieve precise synchronization with the master controller; (2) Abnormal retention: If the data frame verification fails, the local counter will automatically accumulate based on its own crystal oscillator to maintain the continuity of the time base and avoid synchronization interruption; (3) Automatic correction: When communication returns to normal and the data frame is verified to be correct again, the local counter will automatically correct and synchronize with the global counter value at the start of the next synchronization clock, and the accurate synchronization state can be restored without manual intervention.

6. The distributed control high-power converter synchronous fault recording method according to claim 3, characterized in that: The method for achieving high-speed synchronous sampling in S3 is as follows: the AD sampling trigger signal of each slave controller is generated by the TSC clock counter that has achieved high-precision synchronization. When the TSC counter accumulates to the count value corresponding to one sampling cycle, it automatically outputs a trigger pulse to start the AD conversion. Meanwhile, in order to suppress the impact of local crystal oscillator phase difference on AD drive timing, the high-speed synchronous sampling module applies periodic synchronous reset to the frequency divider counter inside each slave station AD driver based on the slave controller clock TSC, thereby eliminating the phase offset of the SPI communication clock of each station. Digital status words are synchronously latched at the same trigger moment to ensure the time consistency between analog and digital quantities. Based on the high-precision synchronous slave controller clock TSC, each slave controller has nanosecond-level alignment accuracy in acquiring trigger moments, and the waveform data is strictly aligned on the time axis. Each controller allocates A+B independent 16-bit FIFOs based on the number of analog channels A and digital channels B to be recorded. It uses a cyclic overlay mode to continuously store the sampled data of the most recent period. When a recording stop signal is detected, the write pointer is frozen to retain the complete recording window before and after the fault for uploading and analysis.

7. The distributed control high-power converter synchronous fault recording method according to claim 3, characterized in that: In step S5, after the master controller captures N fault signals from slave controllers, it generates N global fault trigger signals corresponding to each slave controller. Specifically, when any slave controller other than itself uploads a fault flag bit of 1, the global trigger signal of that slave controller is triggered periodically. T3 and period Set between time T2 and time T2, during the period Reset between T2 and T3; the main controller in cycle At time T1, N global fault trigger signals are broadcast to each slave controller via independent parallel optical fibers.

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