A cell average constant false alarm rate detection based on hardware-algorithm collaborative design

Abstract

This invention provides a unit-averaged constant false alarm rate (CFAR) detection based on hardware-algorithm co-design, belonging to the field of integrated circuit and radar signal processing technology. Addressing the technical pain points of traditional automotive radar CA-CFAR hardware implementations, which rely on DSP slicing, hardware dividers, and BRAM storage resources, resulting in high processing latency, high power consumption, high resource consumption, poor operational stability, and inability to adapt to the real-time lightweight deployment of automotive edge radar, this invention constructs a novel lightweight CA-CFAR hardware architecture. This invention completely eliminates the three core hardware resources—DSP slicing, hardware dividers, and BRAM—significantly reducing chip area and hardware cost, effectively eliminating critical path latency, storage bandwidth conflicts, and wiring congestion problems. With a maximum operating frequency of 340MHz, it combines high real-time performance, low power consumption, and high robustness, adaptable to different specifications of passenger and commercial vehicle millimeter-wave radars, meeting the millisecond-level target detection requirements of ADAS systems, and suitable for large-scale deployment of automotive edge devices.

Description

Technical Field

[0001] This invention provides a unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design, belonging to the field of integrated circuit and radar signal processing technology. Background Technology

[0002] In autonomous driving and advanced driver assistance systems (ADAS), millimeter-wave radar has become a core perception device due to its all-weather detection capabilities and ability to directly calculate target distance and velocity. Constant false alarm rate (CFAR) detection algorithms are a key technology for radar to accurately extract targets from complex clutter. As vehicle-mounted radar gradually develops towards distributed deployment, edge integration, and high-resolution imaging, the data volume of range-Doppler images (RDM) has increased significantly, placing stringent requirements on signal processing systems for high real-time performance, high throughput, small hardware area, low power consumption, and low cost.

[0003] Currently, mainstream CFAR implementation solutions in the industry have many inherent defects and cannot adapt to the application scenarios of automotive edge radar. They can be divided into the following four categories: The software implementation scheme based on DSP / MCU relies on the processor's serial instruction pipeline to perform operations such as modulus calculation, accumulation, and threshold comparison pixel by pixel. The serial execution mode results in extremely high data processing latency, which cannot meet the millisecond-level response requirements of ADAS and makes it difficult to achieve zero-pause data stream processing.

[0004] The OS-CFAR hardware architecture based on sorting logic requires the construction of logical structures such as bitone sorting networks and bubble sorting trees to complete the sorting of reference cells. The consumption of logic resources increases exponentially with the size of the sliding window, which can easily cause chip wiring congestion and high dynamic power consumption, making it unsuitable for low-cost edge FPGAs.

[0005] CFAR architecture based on complex algorithms or deep learning relies on large-scale multiply-accumulate arrays, deep pipelines, and massive on-chip storage units. The hardware cost and thermal design power exceed the budget of automotive edge devices, making it difficult to implement.

[0006] Traditional CA-CFAR hardware acceleration architecture: As the most widely used solution in the industry, its technical shortcomings are the most prominent: complex amplitude calculation relies on multiplication and square root IP cores, which consume a large number of scarce DSP slices in FPGA; the number of sliding window reference cells is an arbitrary integer, and the calculation of background mean must use a hardware divider, which lengthens the critical path and limits the system frequency; the use of BRAM to cache high bit width data has problems such as read and write port conflicts, storage bandwidth shortage, and wiring congestion; at the same time, the high bit width data flow and uncontrolled clock flips lead to high power consumption, and when the ambient noise is close to zero, it is also prone to division by zero errors and abnormal false alarm rates, requiring additional complex anti-interference logic.

[0007] In summary, existing technologies cannot simultaneously address resource consumption, processing latency, power consumption, and operational robustness, thus hindering the large-scale application of automotive edge millimeter-wave radar. This invention addresses these pain points by proposing a novel CA-CFAR hardware architecture and implementation method through collaborative optimization of hardware and algorithms. Summary of the Invention

[0008] This invention aims to overcome the problems of high latency, high power consumption, high resource consumption, and poor operational stability in existing CA-CFAR hardware accelerators that rely excessively on DSP slices, hardware dividers, and BRAM storage units. It provides a unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design. Through integrated design including topological constraints, equivalent computational substitution, data bit width compression, and clock gating, this invention achieves zero DSP usage, zero BRAM usage, and no hardware divider. While reducing hardware cost and power consumption, it improves the system's operating frequency and data processing real-time performance, making it fully adaptable to automotive edge millimeter-wave radars of different specifications and application scenarios.

[0009] To address the aforementioned problems, the present invention proposes the following technical solution: a unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design, comprising a finite state machine power consumption control unit, a decoding and accumulation module, a row accumulation module, and a comparison module; the finite state machine power consumption control unit is connected to the decoding and accumulation module, the row accumulation module, and the comparison module respectively, and outputs a clock enable signal; an external 32-bit complex data stream is transmitted sequentially through the decoding and accumulation module and the row accumulation module to the comparison module, and the comparison module combines the threshold coefficient to output the target detection result; The decoding and accumulation module includes a parallel floating-point decoding unit, a multiplier-free amplitude approximation calculation unit, and a noise-gated dynamic quantization unit. The parallel floating-point decoding unit is used to decompose the real part, imaginary part, and exponent part of 32-bit complex data. The multiplier-free amplitude approximation calculation unit adopts the Alpha-Max-Beta-Min algorithm, selects the maximum and minimum values ​​of the absolute values ​​of the real and imaginary parts through a comparator, sets the minimum value branch to a 1-bit hardware logic right shift connection, and connects it to an adder to complete the amplitude calculation. The noise-gated dynamic quantization unit is an 8-bit nonlinear quantization circuit that saturates and truncates data greater than a preset upper limit, while forcibly clamping noise data less than a preset lower limit to a fixed noise floor value, and outputs 8-bit quantized data. The row accumulation module includes a distributed line-buffer chain constructed based on the cascading of shift register lookup table (SRL) primitives and an asymmetric row accumulator array. The line-buffer chain consists of a two-dimensional sliding window composed of multiple shift registers. The two-dimensional sliding window adopts a topology of 5×5 outer window with 3×3 guard window, so that the total number of effective reference cells is fixed at 16. The asymmetric row accumulator array includes two types of row accumulation circuits: a sliding accumulation circuit with a trigger feedback loop is set for rows without guard cells, and a skip-type point-to-point addition circuit is set for rows with guard cells. The output of the row accumulator array is connected to a two-stage multi-input addition tree, and a 4-bit hardware logic right shift network is configured at the end of the addition tree to complete the calculation of the average background noise power. The comparison module includes a lookup table, a threshold generation circuit, and a digital comparator. The lookup table maps a preset scaling factor to a shift-add combination network to replace the hardware multiplier to generate a decision threshold. The digital comparator compares the decision threshold with the data to be detected and outputs a detection flag. The finite state machine power consumption control unit tracks the timing of radar physical frames, and pulls down the clock enable signal in the idle state and data empty state to shut down the clock flip of the downstream module to achieve clock gating.

[0010] Furthermore, the multiplier-free amplitude approximation calculation unit completely abandons the square operation and square root operation circuits, and uses only comparators, multiplexers and adders to form a pure logic gate data path throughout the process, without calling DSP slice resources.

[0011] Furthermore, the preset upper limit of the noise-gated dynamic quantization unit is 255, and the preset lower limit is 2. This clamps weak thermal noise below 2 to a value of 2, forming a noise-gated filtering effect at the hardware level, while avoiding division by zero errors in subsequent calculations.

[0012] Furthermore, the Line-Buffer chain completely abandons Block Random Access Memory (BRAM) and relies solely on the cascading of SRL primitives built into the FPGA to achieve two-dimensional radar data caching. The BRAM resource occupancy rate is zero, and all pixel data within the window is output in parallel in a single clock cycle.

[0013] Furthermore, the two-dimensional sliding window has 16 effective reference cells after topological constraints, corresponding to 2 to the power of 4. The normalization operation of dividing by 16 is equivalently achieved through a 4-bit hardware logic right shift network, and the hardware divider IP core is removed.

[0014] Furthermore, the sliding accumulator circuit is configured according to the formula Newsum = Oldsum + Datain. Dataout completes the single-cycle row data portion and update; the jump-type point-to-point addition circuit physically spans the detection unit and protection unit at the center of the window, and only performs summation operations on the valid reference unit.

[0015] Furthermore, the lookup table pre-quantizes the scaling factor α and synthesizes it into a shift and addition basic circuit through combinational logic, replacing the hardware multiplier to complete the threshold scaling operation without occupying any DSP slices.

[0016] Furthermore, this includes the following steps: S1. After the system is powered on, the finite state machine power consumption control unit outputs a clock enable signal according to the radar frame timing to control the working state of each module; the external 32-bit complex radar data input decoding and accumulation module, and the parallel floating-point decoding unit decompose the real part, imaginary part and exponent information of the data. S2, the multiplier-free amplitude approximation calculation unit extracts the absolute values ​​of the real and imaginary parts, distinguishes the maximum and minimum values ​​through a comparator, and adds the minimum value branch to the maximum value after a 1-bit logic right shift to complete the complex amplitude approximation calculation; S3. The amplitude data is accumulated along the antenna dimension and then sent to the noise-gated dynamic quantization unit. Data greater than 255 is saturated and truncated, and data less than 2 is clamped to 2. The data is then uniformly converted into 8-bit quantized data and output. The S4, 8-bit quantized data input row accumulation module is constructed by a 5×5 two-dimensional sliding window built by a cascaded SRL primitive line-buffer chain. Based on the window topology, 16 effective reference cells are obtained. The effective cells of each row are summed by two types of asymmetric row accumulators. The row accumulation results are summarized by a two-level addition tree and then the average power of the background noise is obtained by a 4-bit logical right shift. S5, the background noise average power input comparison module, generates a decision threshold by performing scaling operations through a lookup table, compares the decision threshold with the data to be detected in the window, and outputs a valid target detection flag if the data to be detected is greater than the threshold. S6. When the radar is in the inter-frame blanking period, idle state, or data emptying state, the finite state machine power consumption control unit pulls down the clock enable signal, freezes the logic flipping of the entire data path, and reduces dynamic power consumption.

[0017] Furthermore, in step S2, the amplitude calculation uses the formula abs=max(∣Re∣,∣Im∣)+0.5×min(∣Re∣,∣Im∣), which equates the 0.5 multiplication operation in the formula to a hardware 1-bit logical right shift operation.

[0018] Furthermore, in step S4, the two-dimensional sliding window includes a central unit to be detected and a 3×3 protection unit. During the row accumulation process, the protection unit and the unit to be detected are automatically skipped, and the summation operation is only performed on the edge valid reference units. The entire data processing flow does not use DSP slicing, hardware dividers, or block random access memory (BRAM). The core logic consists only of logic gates, flip-flops, shift registers, and lookup tables.

[0019] Due to the adoption of the above technical solution, the beneficial effects of the unit average constant false alarm rate detection based on hardware-algorithm co-design of the present invention are as follows: 1. Zero DSP resource consumption and lower hardware cost: This invention replaces multiplication with hardware logic right shift and threshold scaling multiplication with lookup table shift addition logic, completely eliminating DSP slicing and square / square root IP cores. The core logic only occupies a small number of LUTs and registers, which can be mounted on low-end, low-cost FPGAs, greatly reducing the hardware cost and chip area of ​​the device.

[0020] 2. No hardware divider, significantly improving system frequency and real-time performance: By fixing the effective reference unit to 16 (24) through window topology constraints, and replacing the hardware divider with a 4-bit logical right shift, the long-delay critical path is eliminated, the system's maximum operating frequency can reach 340MHz, and it only takes 12.4ms to process a 2048×2048 distance-Doppler image, which meets the millisecond-level real-time processing requirements of ADAS.

[0021] 3. Zero BRAM usage, completely solving storage bandwidth and routing bottlenecks: 8-bit quantization compresses the data bit width, reducing storage bandwidth by 75%; the SRL primitive is used to build a distributed row cache chain, completely eliminating the use of BRAM, avoiding read / write port conflicts and routing congestion problems, while releasing BRAM resources to other functional modules of the radar system, improving the overall resource utilization of the chip.

[0022] 4. Fine-grained clock gating and extremely low dynamic power consumption: Based on a finite state machine, time-domain clock control is implemented, and the logic flipping is frozen during the inter-frame blanking period. The core dynamic power consumption is only 17mW at a 100MHz main frequency, which is suitable for the low power consumption and low heat dissipation requirements of automotive equipment.

[0023] 5. Hardware-level noise suppression and strong system robustness: The quantization circuit has built-in noise floor clamping logic, which can achieve noise filtering without additional algorithms, effectively preventing division-by-zero errors and false alarm rate changes caused by the noise floor approaching zero, and improving radar detection stability. Attached Figure Description

[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1This is a scenario application diagram of the unit average constant false alarm rate detection based on hardware-algorithm co-design of the present invention; Figure 2 This is a hardware architecture diagram of a unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to the present invention. Figure 3 This is a schematic diagram of the parallel floating-point decoding and multiplier-free amplitude approximation principle of a unit average constant false alarm rate detection based on hardware-algorithm co-design of the present invention. Figure 4 This is a diagram of a distributed line-buffered cache architecture for unit average constant false alarm rate detection based on hardware-algorithm co-design according to the present invention; Figure 5 This invention presents a window topology constraint and asymmetric row accumulator array diagram for a unit average constant false alarm rate (CFAR) detection based on hardware-algorithm co-design. Figure 6 This is a diagram illustrating the threshold generation and target decision deployment for a unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to the present invention. Detailed Implementation

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Example 1: Low-frequency basic example for adapting to short-range vehicle-mounted forward-facing radar 1. Application Scenarios This embodiment applies to a short-range forward-facing millimeter-wave radar for passenger vehicles, primarily used for detecting nearby obstacles, pedestrians, and non-motorized vehicles in front of the vehicle. It belongs to the basic ADAS perception equipment category. The hardware platform uses an entry-level, low-cost FPGA, with a rated operating frequency of 100MHz. The radar outputs a 32-bit complex data stream, and the range-Doppler image specification is 1024×1024. It has stringent requirements for hardware resources and power consumption, and does not have excessively high requirements for maximum operating frequency.

[0027] 2. Device Hardware Configuration and Parameter Settings (1) Global control unit: The finite state machine power consumption control unit is divided into four states: IDLE, FILL, PROCESS, and DRAIN. The duration of the inter-frame blanking period of the radar is fixed. During the blanking period, the clock enable signal is continuously pulled low to shut down the clock of all data paths.

[0028] (2) Decoding and accumulation module: The parallel floating-point decoding unit natively parses the real part, imaginary part and exponent of a 32-bit floating-point complex number; the multiplier-free amplitude approximation calculation unit is built with pure logic gates, and a 1-bit logic right shift circuit realizes the 0.5 times coefficient operation, with zero DSP occupation throughout the process; the noise-gated dynamic quantization unit has fixed parameters: upper limit 255, lower limit 2, and thermal noise below 2 is uniformly clamped to 2, outputting 8-bit fixed-point data.

[0029] (3) Row accumulation module: Five groups of line buffer chains are constructed by cascading the built-in SRL16 primitives of the FPGA to form a standard 5×5 outer window + 3×3 guard window topology, with a strict number of effective reference cells of 16; the first and fifth rows are configured with sliding accumulation circuits with flip-flops, and the second, third and fourth rows are configured with jump-type point-to-point addition circuits; the two-level addition tree completes the data aggregation, and the end is configured with a 4-bit fixed logic right shift network, which is equivalent to the division by 16 operation without using any BRAM and hardware divider.

[0030] (4) Comparison module: look up the prequantization scaling factor α in the table, decompose the multiplication operation into a shift + addition combination logic; the digital comparator synchronously compares the threshold with the data to be detected, and outputs the target detection level signal.

[0031] 3. Workflow and Operational Results After the system powers on, the finite state machine continuously outputs a high-level clock enable signal. The 32-bit complex data from the radar sequentially enters the decoding unit to complete field splitting. After amplitude approximation, antenna accumulation, and 8-bit quantization, the data is sent to the line-buffer chain to form a two-dimensional sliding window. The asymmetric line accumulator sums 16 valid reference cells, and the average background noise is obtained by summing through a two-level addition tree and a 4-bit logical right shift. The average is used to generate a decision threshold through a lookup table, and the detection result is output after being compared with the data to be detected at the center of the window.

[0032] When the radar enters the inter-frame blanking period, the finite state machine pulls the clock low to enable, and all registers and combinational logic stop toggling. In this embodiment, at a 100MHz main frequency, the core dynamic power consumption is only 17mW, the FPGA's internal DSP and BRAM resource utilization is 0%, and the number of logic units (LUTs) is less than 1000. Processing one frame of 1024×1024 range-Doppler image takes approximately 3.2ms, fully meeting the real-time detection requirements of short-range radar. The maximum relative amplitude error is 11.8%, within the allowable error range of short-range radar, and the target detection accuracy is on par with traditional CA-CFAR hardware solutions.

[0033] Example 2: High-frequency, high-performance example of adapting to mid-range vehicle-mounted surround-view radar 1. Application Scenarios This embodiment applies to a mid-range surround-view millimeter-wave radar for passenger vehicles. Multiple radars are installed throughout the vehicle to form a surround-view perception network for monitoring vehicles to the side and rear, as well as obstacles. It is a core sensor for automatic parking and lane change assist functions. The hardware platform uses a mid-range FPGA, with the system's rated operating frequency increased to 340MHz. The distance-Doppler image specification is 2048×2048, requiring extremely low data processing latency, high throughput, and extremely high real-time performance.

[0034] 2. Device Hardware Configuration and Parameter Settings The overall architecture and core circuit of the invention remain unchanged, with optimizations only made to timing, pipeline, and data throughput. (1) Finite state machine power consumption control unit: optimizes state transition timing, shortens FILL and DRAIN state switching delay, and matches high-speed data flow under high main frequency; retains clock gating function, and shuts down the clock during blanking period to control power consumption.

[0035] (2) Decoding and accumulation module: The parallel floating-point decoding unit and amplitude approximation calculation unit are pipelined to adapt to the timing constraints of 340MHz high main frequency; the quantization parameters are kept unchanged with an upper limit of 255 and a lower limit of 2 to ensure noise suppression effect.

[0036] (3) Line Accumulation Module: The Line-Buffer chain of SRL primitive cascade adds a local pipeline register to eliminate setup time violations under high clock frequency; the window topology, two types of asymmetric accumulation circuits, and 4-bit logic right shift network structure remain unchanged, still achieving zero BRAM and zero divider design.

[0037] (4) Comparison module: The lookup table circuit is optimized for timing, shortens the combinational logic delay, and matches the highest main frequency of the system; the threshold comparison logic runs in pipeline throughout the process, and realizes the decision in a single clock cycle.

[0038] 3. Workflow and Operational Results The data processing flow is consistent with Example 1. Relying on pipeline optimization and high clock frequency configuration, the system throughput is greatly improved. At the rated clock frequency of 340MHz, it only takes 12.4ms to process a frame of 2048×2048 ultra-large range-Doppler image, achieving zero-stop pipeline processing and fully meeting the high-speed data processing requirements of surround-view radar.

[0039] In this embodiment, the DSP and BRAM resource utilization remains at 0%, with the core logic occupying approximately 1490 LUTs and 726 registers. Dynamic power consumption increases slightly at high clock frequencies, with a full-load operating power consumption of 29mW, significantly lower than the traditional CA-CFAR hardware architecture. In a multi-radar networked surround-view system, this device exhibits no resource conflicts, stable timing, and both the false alarm rate and missed detection rate meet automotive radar industry standards.

[0040] Example 3: Wide-Temperature-Range Hardening Example for Commercial Vehicle Radar 1. Application Scenarios This embodiment is applied to vehicle-mounted millimeter-wave radar for commercial vehicles such as freight trucks and buses. Commercial vehicles operate in complex environments with wide temperature ranges and strong electromagnetic interference. The space for radar installation is limited, requiring the detection device to have strong anti-interference capabilities, a simplified hardware structure, and stable operation over a wide temperature range. The hardware platform uses an industrial-grade FPGA, with a system operating frequency of 200MHz and a range-Doppler image specification of 1536×1536, balancing real-time performance, stability, and low power consumption.

[0041] 2. Device Hardware Configuration and Parameter Settings Based on the core architecture of this invention, we have made reinforcements and anti-interference optimizations for industrial environments, while keeping the core computing, storage, and control logic unchanged: (1) Finite state machine power consumption control unit: Add state debouncing logic to suppress false state jumps caused by electromagnetic interference in industrial environment; Add timing buffer circuit to clock enable signal to ensure clock signal integrity in wide temperature range.

[0042] (2) Decoding and accumulation module: A simple signal buffer register is added to the back end of the 8-bit noise-gated dynamic quantization unit to resist electromagnetic interference; the quantization parameters (upper limit 255, lower limit 2) and amplitude approximation circuit structure remain unchanged, continuously realizing hardware noise gating and zero-removal protection.

[0043] (3) Line Accumulation Module: The Line-Buffer line buffer chain adopts industrial-grade SRL primitive configuration to enhance timing stability under high and low temperature environments; the 5×5 window topology, asymmetric accumulation circuit, and 4-bit logic right shift network are completely based on the basic design, and the characteristics of zero BRAM and zero hardware divider remain unchanged.

[0044] (4) Comparison module: The digital comparator adds an output latch register to avoid electromagnetic interference causing the detection signal to jump; the lookup table circuit is reinforced with redundancy to ensure normal logic function under wide temperature range.

[0045] 3. Workflow and Operational Results The data processing flow is consistent with the aforementioned embodiment. The 32-bit complex radar data undergoes decoding, amplitude calculation, quantization, window summation, and threshold comparison before outputting the detection result. This embodiment operates within the full industrial temperature range of -40℃ to +85℃, and exhibits no logic failures or timing errors during high and low temperature cycling tests.

[0046] Operating at a 200MHz clock frequency, the system processes a 1536×1536 range-Doppler image in approximately 6.8ms, meeting the real-time detection requirements of commercial vehicle radar. With zero DSP and BRAM resource usage, it is easy to deploy within the confined radar hardware cavity. Utilizing a hardware noise floor clamping design, the system exhibits a significantly lower false alarm rate than traditional hardware solutions in complex road clutter and strong electromagnetic interference environments, resulting in a substantial improvement in operational robustness. Its full-load dynamic power consumption is 22mW, suitable for the power supply and heat dissipation requirements of commercial vehicles.

[0047] The present invention and its embodiments have been described above. This description is not restrictive. In short, if a person skilled in the art is inspired by this description and designs a similar structure and embodiment without departing from the spirit of the present invention, such design should fall within the protection scope of the present invention.

Claims

1. A unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design, characterized in that, It includes a finite state machine power consumption control unit, a decoding and accumulation module, a row accumulation module, and a comparison module; the finite state machine power consumption control unit is connected to the decoding and accumulation module, the row accumulation module, and the comparison module respectively and outputs a clock enable signal; an external 32-bit complex data stream is transmitted to the comparison module in sequence through the decoding and accumulation module and the row accumulation module, and the comparison module outputs the target detection result by combining the threshold coefficient; The decoding and accumulation module includes a parallel floating-point decoding unit, a multiplier-free amplitude approximation calculation unit, and a noise-gated dynamic quantization unit. The parallel floating-point decoding unit is used to decompose the real part, imaginary part, and exponent part of 32-bit complex data. The multiplier-free amplitude approximation calculation unit adopts the Alpha-Max-Beta-Min algorithm, selects the maximum and minimum values ​​of the absolute values ​​of the real and imaginary parts through a comparator, sets the minimum value branch to a 1-bit hardware logic right shift connection, and connects it to an adder to complete the amplitude calculation. The noise-gated dynamic quantization unit is an 8-bit nonlinear quantization circuit that saturates and truncates data greater than a preset upper limit, while forcibly clamping noise data less than a preset lower limit to a fixed noise floor value, and outputs 8-bit quantized data. The row accumulation module includes a distributed line-buffer chain constructed based on the cascading of shift register lookup table (SRL) primitives and an asymmetric row accumulator array. The line-buffer chain consists of a two-dimensional sliding window composed of multiple shift registers. The two-dimensional sliding window adopts a topology of 5×5 outer window with 3×3 guard window, so that the total number of effective reference cells is fixed at 16. The asymmetric row accumulator array includes two types of row accumulation circuits: a sliding accumulation circuit with a trigger feedback loop is set for rows without guard cells, and a skip-type point-to-point addition circuit is set for rows with guard cells. The output of the row accumulator array is connected to a two-stage multi-input addition tree, and a 4-bit hardware logic right shift network is configured at the end of the addition tree to complete the calculation of the average background noise power. The comparison module includes a lookup table, a threshold generation circuit, and a digital comparator. The lookup table maps a preset scaling factor to a shift-add combination network to replace the hardware multiplier to generate a decision threshold. The digital comparator compares the decision threshold with the data to be detected and outputs a detection flag. The finite state machine power consumption control unit tracks the timing of radar physical frames, and pulls down the clock enable signal in the idle state and data empty state to shut down the clock flip of the downstream module to achieve clock gating.

2. The unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The multiplier-free amplitude approximation calculation unit completely abandons the square operation and square root operation circuits, and uses only comparators, multiplexers and adders to form a pure logic gate data path throughout the process, without calling DSP slice resources.

3. The unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The preset upper limit of the noise-gated dynamic quantization unit is 255, and the preset lower limit is 2. It clamps weak thermal noise below 2 to a value of 2, forming a noise-gated filtering effect at the hardware level, while avoiding division by zero errors in subsequent calculations.

4. The unit average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The Line-Buffer chain completely abandons Block Random Access Memory (BRAM) and relies solely on the cascading of SRL primitives built into the FPGA to achieve two-dimensional radar data caching. The BRAM resource occupancy rate is zero, and all pixel data within the window are output in parallel in a single clock cycle.

5. The unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The two-dimensional sliding window has 16 effective reference cells after topological constraints, corresponding to 2 to the power of 4. The normalization operation of dividing by 16 is equivalently achieved by a 4-bit hardware logic right shift network, and the hardware divider IP core is removed.

6. The unit average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The sliding accumulator circuit follows the formula Newsum = Oldsum + Datain Dataout completes the single-cycle row data portion and update; the skip-type point-to-point addition circuit physically spans the detection unit and protection unit at the center of the window, and only performs summation operations on the valid reference unit.

7. The unit average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that: The lookup table pre-quantizes the scaling factor α and synthesizes it into a shift and addition basic circuit through combinational logic, replacing the hardware multiplier to complete the threshold scaling operation without occupying any DSP slices.

8. The unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 1, characterized in that, Includes the following steps: S1. After the system is powered on, the finite state machine power consumption control unit outputs a clock enable signal according to the radar frame timing to control the working state of each module; the external 32-bit complex radar data input decoding and accumulation module, and the parallel floating-point decoding unit decompose the real part, imaginary part and exponent information of the data. S2, the multiplier-free amplitude approximation calculation unit extracts the absolute values ​​of the real and imaginary parts, distinguishes the maximum and minimum values ​​through a comparator, and adds the minimum value branch to the maximum value after a 1-bit logic right shift to complete the complex amplitude approximation calculation; S3. The amplitude data is accumulated along the antenna dimension and then sent to the noise-gated dynamic quantization unit. Data greater than 255 is saturated and truncated, and data less than 2 is clamped to 2. The data is then uniformly converted into 8-bit quantized data and output. The S4, 8-bit quantized data input row accumulation module is constructed by a 5×5 two-dimensional sliding window built by a cascaded SRL primitive line-buffer chain. Based on the window topology, 16 effective reference cells are obtained. The effective cells of each row are summed by two types of asymmetric row accumulators. The row accumulation results are summarized by a two-level addition tree and then the average power of the background noise is obtained by a 4-bit logical right shift. S5, the background noise average power input comparison module, generates a decision threshold by performing scaling operations through a lookup table, compares the decision threshold with the data to be detected in the window, and outputs a valid target detection flag if the data to be detected is greater than the threshold. S6. When the radar is in the inter-frame blanking period, idle state, or data emptying state, the finite state machine power consumption control unit pulls down the clock enable signal, freezes the logic flipping of the entire data path, and reduces dynamic power consumption.

9. A unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 8, characterized in that: In step S2, the amplitude is calculated using the formula abs=max(∣Re∣,∣Im∣)+0.5×min(∣Re∣,∣Im∣), which equates the 0.5 multiplication operation in the formula to a 1-bit logical right shift operation in hardware.

10. A unit-average constant false alarm rate (CFAR) detection method based on hardware-algorithm co-design according to claim 8, characterized in that: In step S4, the two-dimensional sliding window includes a central unit to be detected and a 3×3 protection unit. During the row accumulation process, the protection unit and the unit to be detected are automatically skipped, and the summation operation is only performed on the edge valid reference units. The entire data processing flow does not use DSP slicing, hardware dividers, or block random access memory (BRAM). The core logic consists only of logic gates, flip-flops, shift registers, and lookup tables.

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