Photonic integrated circuit

Abstract

This invention provides a photonic integrated circuit. The photonic integrated circuit includes an internal circuit, a sealing ring, and a spot size converter (SSC). The sealing ring continuously surrounds the internal circuit. The spot size converter (SSC) is connected between the internal circuit and an external optical fiber. The sealing ring includes an aperture through which the SSC passes. Therefore, the sealing ring of this invention provides an aperture for the spot size converter to pass through while maintaining continuity, thus not only maintaining the blocking function of the sealing ring but also allowing the spot size converter to pass through. This ensures the functionality and transmission of the photonic integrated circuit while maximizing the use of a continuous sealing ring to protect the internal circuit, guaranteeing the stable and reliable operation of the photonic integrated circuit and ensuring its performance.

Description

[Technical Field] This invention relates to a photonic integrated circuit based on semiconductor technology, and more particularly to a photonic integrated circuit. [Background Technology] A photonic integrated circuit (PIC) is an electronic circuit that integrates optical components (such as waveguides, modulators, and lasers) onto a single chip. In contrast, an electronic integrated circuit (EIC) integrates only electronic devices (such as transistors and capacitors) onto a single chip. In short, PIC is often used to refer to a photonic chip that contains photonic components and can manipulate and transmit light. PICs transmit data using light instead of electricity, enabling faster data transmission speeds, lower power consumption, and higher bandwidth.

[0001] Therefore, the industry urgently needs to provide PICs with improved performance. [Summary of the Invention] One embodiment of the present invention provides a photonic integrated circuit. The photonic integrated circuit includes internal circuitry, a sealing ring, and a spot size converter (SSC). The sealing ring continuously surrounds the internal circuitry. The spot size converter (SSC) is connected between the internal circuitry and an external optical fiber. The sealing ring includes an aperture through which the spot size converter passes. Furthermore, the sealing ring comprises multiple metal layers, wherein the first metal layer among the multiple metal layers is discontinuous, and the second metal layer among the multiple metal layers is continuous. This ensures that the sealing ring remains continuous and uninterrupted, reducing negative impacts on its protective effect, while allowing the spot size converter to pass through the sealing ring via the discontinuous first metal layer, thereby guaranteeing the normal connection and transmission of the spot size converter.

[0002] Furthermore, the spot size converter is located within a discontinuous region of the first metal layer. This allows the spot size converter to pass through the sealing ring via the discontinuous first metal layer, thereby ensuring normal connection and transmission of the spot size converter. Furthermore, the second metal layer covers the first metal layer and any discontinuous areas of the first metal layer. This ensures that the sealing ring remains continuous and uninterrupted, thereby reducing any negative impact on the protective effect of the sealing ring.

[0003] Furthermore, the width of the hole gradually decreases towards the upper surface of the sealing ring. This reduces the negative impact on the protective effect of the sealing ring and minimizes the cross-sectional area of ​​the disconnected portion.

[0004] Furthermore, the bottom surface of the spot size converter is substantially flush with the bottom surface of the sealing ring or the bottom surface of the contact layer of the sealing ring. This ensures that the spot size converter is installed smoothly and stably.

[0005] Furthermore, the spot size converter is separated from the metal layer by a dielectric layer, thereby reducing the negative impact of the metal layer on the transmission of the spot size converter.

[0006] Further including: a V-groove located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove; and a first blocking strip contacting the sealing ring and the inner wall of the V-groove, wherein the angle between the extending direction of the first blocking strip and the extending direction of the spot size converter is greater than 0° and less than or equal to 90°. This further utilizes the first blocking strip to prevent impurities such as moisture from entering the internal circuit through the holes or openings, thus further protecting the internal circuit.

[0007] Further, it includes a second blocking strip that contacts the sealing ring and extends toward the first blocking strip, wherein the angle between the extending direction of the second blocking strip and the extending direction of the spot size converter is greater than or equal to 0° and less than 90°. This further utilizes the second blocking strip to prevent impurities such as moisture from entering the internal circuit through the hole or opening, thus further protecting the internal circuit. Furthermore, the width of the sealing ring is greater than the width of either the first or the second blocking strip. The first and second blocking strips can be formed using the same process steps as the sealing ring to form a protective layer.

[0008] Furthermore, the sealing ring and either the first or second blocking strip comprise the same number of metal layers as the sealing ring. The first and second blocking strips can be formed using the same process steps as the sealing ring to form a protective layer.

[0009] Furthermore, each of the first and second blocking strips is separated from the internal circuitry by the sealing ring. The first and second blocking strips can be formed using the same process steps as the sealing ring to form a protective layer.

[0010] Furthermore, the first and second blocking strips respectively contact different ring portions of the sealing ring. This forms protection and barriers against impurities in different parts and directions, further protecting the internal circuitry. One embodiment of the present invention provides a photonic integrated circuit. The photonic integrated circuit includes internal circuitry, a sealing ring, and a spot size converter (SSC). The sealing ring surrounds the internal circuitry. The spot size converter (SSC) is connected between the internal circuitry and an external optical fiber. The sealing ring includes multiple metal layers and a hole through which the spot size converter passes, the hole being formed within a portion of the multiple metal layers.

[0011] Furthermore, the photonic integrated circuit further includes at least one blocking strip disposed near the hole and separated from the internal circuit by the sealing ring. This blocking strip further prevents impurities such as moisture from entering the internal circuit through the hole or opening, thus further protecting the internal circuit.

[0012] Further comprising: a V-groove located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove; and wherein the at least one blocking strip contacts the sealing ring and the inner wall of the V-groove, and the at least one blocking strip is spaced apart from the external optical fiber. This further utilizes the first blocking strip to prevent impurities such as moisture from entering the internal circuit through the hole or opening, thus further protecting the internal circuit.

[0013] Another embodiment of the present invention provides a photonic integrated circuit. The photonic integrated circuit includes an internal circuit, a sealing ring, a spot size converter (SSC), a V-groove, and a first blocking strip. The sealing ring surrounds the internal circuit. The spot size converter (SSC) passes through an opening in the sealing ring and connects the internal circuit to an external optical fiber. The V-groove is located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove. The first blocking strip is connected to the sealing ring. The first blocking strip contacts the inner wall of the V-groove and is spaced apart from the external optical fiber. Thus, even if the sealing ring has an opening, i.e., the sealing ring is discontinuous and all metal layers have breaks, the first blocking strip can prevent impurities such as moisture from entering the internal circuit through the opening, further protecting the internal circuit.

[0014] Furthermore, the sealing ring includes a first ring portion and a second ring portion connected to the first ring portion, wherein the opening is located in the first ring portion and the first blocking strip contacts the second ring portion. This forms the desired blocking structure, preventing moisture and other impurities from entering the internal circuitry through the opening, thus further protecting the internal circuitry.

[0015] Further, it includes a second blocking strip extending in a direction different from that of the first blocking strip, wherein the second blocking strip contacts the first ring portion. Thus, the first and second blocking strips form a composite blocking structure, further preventing impurities such as moisture from entering the internal circuit through the opening, thereby further protecting the internal circuit.

[0016] Furthermore, the second blocking strip contacts the inner wall of the V-groove and is spaced apart from the external optical fiber. The blocking strip does not contact the external optical fiber to avoid affecting the signal transmission of the external optical fiber.

[0017] The photonic integrated circuit of the present invention includes an internal circuit, a sealing ring, and a spot size converter (SSC). The sealing ring continuously surrounds the internal circuit. The spot size converter (SSC) is connected between the internal circuit and an external optical fiber. The sealing ring includes an aperture through which the spot size converter passes. Therefore, the sealing ring of the present invention provides an aperture for the spot size converter to pass through while maintaining continuity, thus not only maintaining the blocking function of the sealing ring but also allowing the spot size converter to pass through. This ensures the functionality and transmission of the photonic integrated circuit while using a continuous sealing ring to protect the internal circuit, guaranteeing the stable and reliable operation of the photonic integrated circuit and its performance. [Attached Image Description] A more comprehensive understanding of the invention can be obtained by reading the following detailed description and examples, and by referring to the accompanying drawings, wherein: Figure 1 This is a schematic perspective view of a photonic integrated circuit according to certain embodiments of the present invention; Figure 2 For photonic integrated circuits according to certain embodiments of the present invention Figure 1 A schematic cross-sectional view of line A-A' shown; Figure 3 For photonic integrated circuits according to certain embodiments of the present invention Figure 1 A schematic cross-sectional view of line A-A' shown; Figure 4 For photonic integrated circuits according to certain embodiments of the present invention Figure 1 A schematic cross-sectional view of line A-A' shown; Figure 5 This is a schematic top view of a photonic integrated circuit according to certain embodiments of the present invention; Figure 6 For photonic integrated circuits according to certain embodiments of the present invention Figure 5 The enlarged view shown.

Detailed Implementation Methods

[0018] It should be understood that when an element or layer is referred to as "located on," "connected to," or "coupled to" another element or layer, it may be directly located on, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as "directly located on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same designations refer to the same element throughout the text. The term "and / or" as used herein includes any and all combinations of one or more of the listed related items. In this embodiment and description, the term "basically" means that a value may deviate from a reference value within industrial tolerances, such as approximately 5%, 10%, 20%, or other similar deviations.

[0019] In traditional photonic integrated circuit (or photonic chip) design, the spot size converter (SSC) is crucial for efficient optical coupling, but it requires a discontinuous sealing ring to allow light to pass through. However, this discontinuous sealing ring allows moisture to enter the chip, potentially leading to performance degradation. Therefore, there is an urgent need for a novel sealing ring to improve the durability and performance of photonic integrated circuit (PIC) chips.

[0020] Figure 1 This is a schematic perspective view of a photonic integrated circuit 500A according to certain embodiments of the present invention. Figure 2 for Figure 1 The diagram shown is a schematic cross-sectional view of a photonic integrated circuit 500A according to certain embodiments of the present invention along line A-A'. For ease of explanation, Figure 1 The dielectric layer of the 500A photonic integrated circuit interconnect structure is omitted.

[0021] like Figure 1 and Figure 2 As shown, the photonic integrated circuit 500A includes a chip (or die) 200A, one or more external optical fibers 300, and a spot-size converter (SSC) 350.

[0022] Chip 200A may include a semiconductor substrate 202, internal circuitry 210, a dielectric layer 230, and a sealing ring 240A. Chip 200A may include at least one V-groove (not shown) for accommodating at least one external optical fiber 300, wherein the number of V-grooves may correspond to the number of external optical fibers 300. At least one V-groove is located outside and adjacent to (i.e., close to) the sealing ring. Each V-groove may be a V-groove formed on the semiconductor substrate 202. The closer the V-groove is to the upper surface of the semiconductor substrate 202, the larger its opening width, thereby facilitating the stable positioning of the external optical fiber 300.

[0023] Chip 200A has a circuit region RC and a peripheral region RP surrounding the circuit region RC. The peripheral region RP is located near the edge 200E of chip 200A. In some embodiments, semiconductor substrate 202 may comprise silicon. In other embodiments, semiconductor substrate 202 may be SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, semiconductor-on-insulator (SOI), and other commonly used semiconductor substrates. In some embodiments, semiconductor substrate 202 is contained within an SOI substrate. The SOI substrate may include an insulating layer (not shown), an oxide layer 202-1, and a silicon layer 202-2. Oxide layer 202-1 is formed on the insulating layer (not shown). Silicon layer 202-2 is formed on oxide layer 202-1. In some embodiments, oxide layer 202-1 comprises silicon oxide. In some embodiments, silicon layer 202-2 is used to form waveguide 360 ​​and internal circuitry 210.

[0024] By doping with p-type or n-type impurities, the semiconductor substrate 202 can have the desired conductivity type. In some embodiments, the insulating structure includes a buried oxide layer and a shallow trench isolation (STI) structure (not shown) formed on top of the semiconductor substrate 202. The insulating structure may surround the internal circuitry 210 and provide physical and electrical isolation for the internal circuitry 210 in the active region (not shown) of the semiconductor substrate 202.

[0025] Internal circuitry 210 is disposed in the circuit region RC of semiconductor substrate 202. In some embodiments, internal circuitry 210 may include photonic integrated circuits (PICs) composed of photonic elements, such as photodetectors, grating couplers, modulators, and lasers. Internal circuitry 210 may also include circuit wiring (including conductive layer patterns (not shown) belonging to the first conductive layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, and the eighth conductive layer M8, and interconnection structures 260 of conductive vias belonging to the first via V1, the second conductive via V2, the third conductive via V3, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh via V7) connected to the photonic elements.

[0026] In some embodiments, waveguide 360 ​​of chip 200A is disposed on semiconductor substrate 202 and adjacent to internal circuitry 210. Furthermore, waveguide 360 ​​is coupled to internal circuitry 210. In some embodiments, waveguide 360 ​​is a semiconductor waveguide (e.g., a silicon waveguide).

[0027] The interconnect structure 260 of chip 200A is disposed on semiconductor substrate 202. Internal circuitry 210 may be covered and embedded therein by the interconnect structure 260. In some embodiments, the interconnect structure 260 includes a dielectric layer 230 and a sealing ring 240A.

[0028] A dielectric layer 230 is disposed on a semiconductor substrate 202. The dielectric layer 230 is vertically stacked on the semiconductor substrate 202. The dielectric layer 230 may serve as an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. In some embodiments, the dielectric layer 230 may be made of silicon oxide, silicon oxynitride, undoped silicate glass (USG), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof. In some embodiments, the dielectric layer 230 may be made of a low-dielectric-constant material (e.g., a dielectric constant less than that of silicon dioxide) with a dielectric constant (k) of about 2.9 to 3.8, an ultra-low-dielectric-constant material with a dielectric constant (k) of about 2.5 to 3.9, and an extremely low-dielectric-constant (ELK) material with a dielectric constant (k) less than about 2.5. For example, the dielectric layer 230 may comprise carbon-doped oxides, porous carbon-doped silicon dioxide, polymers such as polyimide or silicon oxycarbide polymer (SiOC), or combinations thereof. In some embodiments, the dielectric layer 230 is formed by plasma-enhanced chemical vapor deposition (PECVD). It should be noted that the number of low-dielectric-constant dielectric layers 230 is determined by the customer's design, and the scope of the invention is not limited.

[0029] A spot size converter (SSC) 350 is disposed on a semiconductor substrate 202. The SSC 350 extends from a peripheral region RP to a circuit region RC. Furthermore, the SSC 350 connects to and optically couples between the internal circuitry 210 and an external optical fiber 300 (e.g., an optical fiber). The SSC 350 is one example of connecting an external component (such as the external optical fiber 300) and the internal circuitry 210; in other embodiments, the SSC 350 may be replaced with other connecting components that connect external components (such as the external optical fiber 300) and the internal circuitry 210.

[0030] In some embodiments, the SSC 350 may be made of silicon, silicon nitride (SiN) or other suitable materials.

[0031] A sealing ring 240A is disposed on the oxide layer 202-1 of the semiconductor substrate 202. The sealing ring 240A is located between the circuit region RC and the peripheral region RP, and continuously surrounds the circuit region RC without any breaks. Furthermore, the sealing ring 240A may continuously surround the internal circuit 210 and the waveguide 360. In some embodiments, the sealing ring 240A may include a silicon layer 202-2, a contact layer 242, a multilayer metal layer ML, and a multilayer conductive via CV embedded in the dielectric layer 230. The sealing ring 240A may further include the dielectric layer 230 and a passivation layer 250 disposed on the dielectric layer 230. For example, as... Figure 1 As shown, the sealing ring 240A may have eight metal layers ML, which are respectively labeled from bottom to top as the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, and the eighth metal layer M8. The contact layer 242 is directly disposed below the first metal layer M1 and coupled to it.

[0032] Furthermore, the sealing ring 240A may have multiple layers of conductive vias CV, alternately arranged and electrically connected (coupled) with metal layers ML. For example, as Figure 1 As shown, the sealing ring 240A may have seven conductive vias CV, which are labeled from bottom to top as the first conductive via V1, the second conductive via V2, the third conductive via V3, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7. The first conductive via V1 is coupled between the first metal layer M1 and the second metal layer M2. The second conductive via V2 is coupled between the second metal layer M2 and the third metal layer M3. The third conductive via V3 is coupled between the third metal layer M3 and the fourth metal layer M4. The fourth conductive via V4 is coupled between the fourth metal layer M4 and the fifth metal layer M5. The fifth conductive via V5 is coupled between the fifth metal layer M5 and the sixth metal layer M6. The sixth conductive via V6 is coupled between the sixth metal layer M6 and the seventh metal layer M7. The seventh conductive via V7 is coupled between the seventh metal layer M7 and the eighth metal layer M8.

[0033] In some embodiments, the conductive via CV is a via strip. The conductive via CV may have a top view shape corresponding to the top view shape of the upper metal layer ML.

[0034] In some embodiments, the contact layer 242 may be made of a metal, such as tungsten. In some embodiments, the metal layer ML and the conductive via CV may be made of a metal, such as copper (Cu), aluminum (Al), or an alloy thereof.

[0035] It should be noted that the number of metal layers ML and the number of conductive vias CV of the sealing ring 240A are defined by the customer's design, and the scope of the present invention is not limited.

[0036] like Figure 2 As shown, the sealing ring 240A may include a hole (or opening) HA through which the SSC350 passes. (As...) Figure 1As shown, the sealing ring 240A may include a first ring portion 240-1, and the hole (opening) HA is located in the first ring portion 240-1. The sealing ring 240A may also include a second ring portion 240-2 and a third ring portion 240-3. The second ring portion 240-2 and the third ring portion 240-3 are respectively connected to two opposite ends of the first ring portion 240-1. The V-groove and the external optical fiber 300 may be disposed in the space between the second ring portion 240-2 and the third ring portion 240-3. In some embodiments, the longitudinal extension direction of the V-groove, the external optical fiber 300, and the SSC350 is substantially perpendicular to the longitudinal extension direction of the first ring portion 240-1. The longitudinal extension directions of the second ring portion 240-2 and the third ring portion 240-3 are substantially perpendicular to the longitudinal extension direction of the first ring portion 240-1. Therefore, the longitudinal extension directions of the V-groove, the outer optical fiber 300, and the SSC350 are substantially parallel to the longitudinal extension directions of the second ring portion 240-2 and the third ring portion 240-3. The sealing ring 240A may also include additional ring portions to form a sealing ring of the desired shape. In some embodiments, the SSC350 is separated from the metal layer ML and conductive via CV of the sealing ring 240A by the dielectric layer 230. In some embodiments, the via HA is formed at least in the bottom metal layer (e.g., the first metal layer M1) and the metal layer above the bottom metal layer (e.g., the second metal layer M2), i.e., the bottom and the metal layer above the metal layer ML of the sealing ring 240A. For example, the via HA is formed at least in the contact layer 242, the first metal layer M1, the first conductive via V1, the second metal layer M2, and the second conductive via V2. More specifically, in the sealing ring 240A, the contact layer 242, the first metal layer M1, the second metal layer M2, and the first conductive via V1 are discontinuous. Furthermore, the third metal layer M3, the fourth metal layer M4, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, the eighth metal layer M8, the second conductive via V2, the third conductive via V3, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7 are continuous. In some embodiments, the sealing ring 240A comprises multiple metal layers (M1–M8), and the hole HA is formed only in some (i.e., certain) metal layers, not in all metal layers. Therefore, the sealing ring 240A remains continuous. Thus, the sealing ring of the present invention provides a hole through which the spot size converter can pass while maintaining continuity, thereby not only maintaining the blocking function of the sealing ring but also allowing the spot size converter to pass through. Thus, while ensuring the functionality and transmission of the photonic integrated circuit, continuous sealing rings are used as much as possible to protect the internal circuit, ensuring the stable and reliable operation of the photonic integrated circuit and guaranteeing its performance.

[0037] In some embodiments, the third metal layer M3, fourth metal layer M4, fifth metal layer M5, sixth metal layer M6, seventh metal layer M7, eighth metal layer M8, second conductive via V2, third conductive via V3, fourth conductive via V4, fifth conductive via V5, sixth conductive via V6, and seventh conductive via V7 may cover discontinuous regions of contact layer 242, first metal layer M1, second metal layer M2, and first conductive via V1. In some embodiments, the discontinuous regions of contact layer 242, first metal layer M1, second metal layer M2, and first conductive via V1 may overlap each other, and they have the same width W1A.

[0038] In some embodiments, the sidewalls 242S of the contact layer 242 used to define the hole HA, the sidewalls M1S of the first metal layer M1 and the sidewalls M2S of the second metal layer M2 are aligned with each other.

[0039] In some embodiments, the via HA may extend into the silicon layer 202-2 of the semiconductor substrate 202. The width (not shown) of the discontinuous region of the silicon layer 202-2 may be the same as the width W1A of the discontinuous region of the contact layer 242, the first metal layer M1, the second metal layer M2, and the first conductive via V1. Furthermore, the sidewall 202-BS of the silicon layer 202-2 of the semiconductor substrate 202 is aligned with the corresponding sidewalls 242S, M1S, and M2S.

[0040] In some embodiments, the width W1A of the discontinuous region of the contact layer 242, the first metal layer M1, the second metal layer M2, and the first conductive via V1 can also be used as the width W1A of the via HA. ​​In some embodiments, the width W1A of the via HA can remain a fixed value. In a cross-sectional view, the via HA can have a rectangular shape.

[0041] SSC 350 can pass through the discontinuous region of contact layer 242, first metal layer M1, second metal layer M2, and first conductive via V1. SSC 350 is separated from metal layer ML by dielectric layer 230.

[0042] In some embodiments, the bottom surface 350B of the SSC 350 may be substantially flush with the bottom surface of the sealing ring 240A. For example, the bottom surface 350B of the SSC 350 may be flush with the bottom surface of the silicon layer 202-2. In some embodiments, the bottom surface 350B of the SSC 350 may be substantially flush with other surfaces. For example, the bottom surface 350B of the SSC 350 may be flush with the bottom surface 242B of the contact layer 242. The upper surface 350T of the SSC 350 may be flush with the upper surface 242T of the contact layer 242.

[0043] In some embodiments, the distance S1A between the hole HA and the upper surface 350T of the SSC 350 can be greater than, less than, or equal to the width W2 of the SSC 350, for example, about 2-3 μm. In some embodiments, the distance S2A between the hole HA and the side surface 350S of the SSC 350 is the same as the distance S1A and the width W2 of the SSC 350, for example, about 2-3 μm. In some embodiments, the maximum width W1A of the hole HA is substantially equal to three times the width W2 of the SSC 350, for example, about 6-9 μm.

[0044] When the spacing S1A, spacing S2A, and maximum width W2 are reasonably controlled within appropriate ranges, moisture can be effectively prevented from penetrating through the sealing ring 240A, thereby protecting the internal circuit 210. Furthermore, by appropriately setting the spacing S1A and spacing S2A, signal transmission through the SSC 350 can be made more stable and reliable, thereby reducing interference from the metal layer.

[0045] In some embodiments, the interconnect structure 260 further includes one or more passivation layers 250. The passivation layer 250 is then deposited on the semiconductor substrate 202 and covers the sealing ring 240A. In some embodiments, the passivation layer 250 comprises a single-layer or multi-layer structure, formed of silicon oxide or silicon nitride. In some embodiments, the passivation layer 250 has a multi-layer structure, comprising an inorganic passivation layer (e.g., silicon oxide or silicon nitride) and an organic passivation layer (e.g., a solder mask or polyimide) located on the inorganic passivation layer.

[0046] The photonic integrated circuit 500A aims to redesign the sealing ring 240A to form at least one rectangular hole HA in the bottom metal layer (e.g., the first metal layer M1) and the metal layer above the bottom of the sealing ring 240A metal layer ML (e.g., the second metal layer M2). Furthermore, the hole HA can extend to a portion of the semiconductor substrate (e.g., the silicon layer 202-2 of the semiconductor substrate 202). The sealing ring 240A can block moisture while still enabling the functionality of the SSC (e.g., SSC 350), thereby improving the chip's durability and performance. The novel sealing ring 240A maintains the light path but prevents moisture infiltration. The sealing ring 240A includes a narrow hole HA to minimize copper loss (discontinuous areas of the sealing ring 240A) and to bring the metal as close as possible to the SSC 350. The photonic integrated circuit 500A can further reduce the size of the hole HA in the sealing ring 240A to minimize moisture infiltration. In some embodiments, the hole HA can be closed at the upper metal layer (the third metal layer M3 or the third metal layer M4). In some embodiments, the bottom surface 350B of the SSC 350 is substantially flush with the bottom surface of the sealing ring 240A.

[0047] Figure 1This is also a schematic perspective view of a photonic integrated circuit 500B according to certain embodiments of the present invention. Figure 3 According to certain embodiments of the present invention Figure 1 The diagram shows a schematic cross-sectional view of the photonic integrated circuit 500B along line A-A'. For simplicity, it is not shown in the image. Figure 1 and Figure 2 The same or similar components described in the embodiments will not be repeated here. For ease of explanation, Figure 2 The dielectric layer of the 500B photonic integrated circuit interconnect structure is omitted.

[0048] like Figure 2 and Figure 3 As shown, the difference between photonic integrated circuit 500A and photonic integrated circuit 500B includes at least the fact that photonic integrated circuit 500B may include a sealing ring 240B having an inverted cone (reverse cone, inverted cone) hole HB (opening).

[0049] like Figure 1 and Figure 3 As shown, the photonic integrated circuit 500B includes a chip 200B, one or more external optical fibers 300, and a spot size converter (SSC) 350.

[0050] Chip 200B may include semiconductor substrate 202, internal circuitry 210, dielectric layer 230, and sealing ring 240B.

[0051] A sealing ring 240B is disposed on the oxide layer 202-1 of the semiconductor substrate 202. The sealing ring 240B is located between the circuit region RC and the peripheral region RP, and surrounds the circuit region RC. Furthermore, the sealing ring 240B may continuously surround the internal circuit 210 and the waveguide 360. In some embodiments, the sealing ring 240B may include a silicon layer 202-2, a contact layer 242, a multi-level metal layer ML (e.g., a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, a sixth metal layer M6, a seventh metal layer M7, and an eighth metal layer M8), and a multi-level conductive via CV (e.g., a first conductive via V1, a second conductive via V2, a third conductive via V3, a fourth conductive via V4, a fifth conductive via V5, a sixth conductive via V6, and a seventh conductive via V7), all embedded in the dielectric layer 230. The sealing ring 240B may also include the dielectric layer 230 and a passivation layer 250.

[0052] like Figure 3As shown, the sealing ring 240B may include a hole (discontinuous region) HB through which the SSC 350 passes. Furthermore, the SSC 350 is separated from the metal layer ML and the conductive via CV by the dielectric layer 230. In some embodiments, the hole HB (opening) is formed at least in the bottom metal layer (e.g., the first metal layer M1) and the metal layer above the bottom metal layer (e.g., the second metal layer M2) of the sealing ring 240B. For example, the hole HB is formed in the contact layer 242, the first metal layer M1, the first conductive via V1, the second metal layer M2, the second conductive via V2, the third metal layer M3, the third conductive via V3, and the fourth metal layer M4. More specifically, in the sealing ring 240B, the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the first conductive via V1, the second conductive via V2, and the third conductive via V3 are discontinuous. Furthermore, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, the eighth metal layer M8, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7 are continuous. In some embodiments, the sealing ring 240B comprises multiple metal layers (M1–M8), and the hole HB is formed only in some (i.e., certain) of the metal layers, not in all of them. Therefore, the sealing ring 240B still remains continuous.

[0053] In some embodiments, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, the eighth metal layer M8, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7 may cover the discontinuous areas of the contact layer 242, the first metal layer M1, the second metal layer M2, and the first conductive via V1.

[0054] In some embodiments, the width of the discontinuous region of the contact layer 242 is the same as the width W1B-1 of the discontinuous region of the first metal layer M1. Furthermore, the sidewalls 242S of the contact layer 242 used to define the hole HB are aligned with the sidewalls M1S of the first metal layer M1.

[0055] In some embodiments, the discontinuous regions of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4, as well as the discontinuous regions of the first conductive via V1, the second conductive via V2, and the third conductive via V3, may overlap each other, and they have different widths W1B. For example, the widths W1B-1 of the discontinuous region of the first metal layer M1, W1B-2 of the discontinuous region of the second metal layer M2, W1B-3 of the discontinuous region of the third metal layer M3, and W1B-4 of the discontinuous region of the fourth metal layer M4 may gradually decrease toward the upper surface 240BT of the sealing ring 240B.

[0056] In some embodiments, the sidewalls M2S of the second metal layer M2, the sidewalls M3S of the third metal layer M3, and the sidewalls M4S of the fourth metal layer M4 used to define the hole HB are not aligned with the corresponding sidewalls 242S and M1S.

[0057] Similarly, the width of the discontinuous regions of the first conductive via V1, the second conductive via V2, and the third conductive via V3 can gradually decrease toward the upper surface 240BT of the sealing ring 240B.

[0058] In some embodiments, the aperture HB may extend to the silicon layer 202-2 of the semiconductor substrate 202. The width of the discontinuous region (not shown) may be the same as the width of the discontinuous region of the contact layer 242 (i.e., width W1B-1) and the width W1B-1 of the discontinuous region of the first metal layer M1. Furthermore, the sidewall 202-BS of the silicon layer 202-2 of the semiconductor substrate 202 is aligned with the corresponding sidewalls 242S and M1S.

[0059] In some embodiments, the width W1B of the discontinuous region of the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the first conductive via V1, the second conductive via V2, and the third conductive via V3 can also be used as the width W1B of the hole HB. In some embodiments, the width W1B of the hole HB can gradually decrease towards the upper surface 240BT of the sealing ring 240B.

[0060] In a cross-sectional view of the sealing ring 240B extending near the hole HB, the hole HB may have an inverted conical shape.

[0061] The spot size converter (SSC) 350 is located in the discontinuous region of the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the first conductive via V1, the second conductive via V2, and the third conductive via V3.

[0062] In some embodiments, the bottom surface 350B of SSC 350 is substantially flush with the bottom surface of sealing ring 240B. For example, the bottom surface 350B of SSC 350 may be flush with the bottom surface 242B of contact layer 242 (i.e., the bottom surface of sealing ring 240B). The upper surface 350T of SSC 350 may be flush with the upper surface 242T of contact layer 242.

[0063] In some embodiments, the distance S1B between the hole HB and the upper surface 350T of the SSC 350 is greater than the width W2 of the SSC 350. In some embodiments, the maximum distance S2B between the hole HB and the side surface 350S of the SSC 350 is the same as the width W2 of the SSC 350, for example, about 2-3 μm. In some embodiments, the maximum width W1B of the hole HB is approximately three times the width W2 of the SSC 350, for example, about 6-9 μm. In some embodiments, the minimum width W1B of the hole HB may be less than the width W2 of the SSC 350.

[0064] When the spacing S1B, the maximum spacing S2B, and the maximum width W1B are kept within appropriate ranges, the sealing ring 240B can effectively prevent unwanted moisture from penetrating and reaching the internal circuitry 210. Furthermore, by appropriately setting the spacing S1B and spacing S2B, signal transmission through the SSC 350 can be made more stable and reliable, thereby reducing interference from the metal layer.

[0065] The photonic integrated circuit 500B aims to redesign the sealing ring 240B by forming an anti-conical aperture HB in at least the bottom metal layer (e.g., the first metal layer M1) and the metal layer immediately above the bottom metal layer (e.g., the second metal layer M2). Furthermore, the aperture HB can extend to a portion of the semiconductor substrate (e.g., the silicon layer 202-2 of the semiconductor substrate 202). The sealing ring 240B can block moisture while still enabling the functionality of the SSC (e.g., SSC 350), thereby improving chip durability and performance. The novel sealing ring 240B maintains the optical path but prevents moisture ingress. The sealing ring 240B includes a narrow aperture HB to minimize copper loss (discontinuous areas of the sealing ring 240B) and to bring the metal as close as possible to the SSC 350. The photonic integrated circuit 500B can further reduce the size of the sealing ring aperture HB to minimize moisture penetration. In some embodiments, the aperture HB can be gradually closed and sealed in an upper metal layer (e.g., the fifth metal layer M5 or the sixth metal layer M6). In some embodiments, the bottom surface 350B of SSC 350 is substantially flush with the bottom surface of sealing ring 240B.

[0066] Figure 1 This is also a schematic perspective view of a photonic integrated circuit 500C according to certain embodiments of the present invention. Figure 4 According to certain embodiments of the present invention Figure 1 The diagram shows a schematic cross-sectional view of the photonic integrated circuit 500C along line A-A'. For simplicity, it is not shown in the original text. Figure 1-3 The same or similar embodiments will not be described again here. For ease of explanation, Figure 1 The dielectric layer of the 500C photonic integrated circuit interconnect structure is omitted.

[0067] like Figure 2 and Figure 4 As shown, the difference between photonic integrated circuit 500A and photonic integrated circuit 500C includes at least the fact that photonic integrated circuit 500C may include a sealing ring 240C with an inverted conical hole HC (opening).

[0068] like Figure 1 and Figure 4 As shown, the photonic integrated circuit 500C includes a chip 200C, one or more external optical fibers 300, and a spot size converter (SSC) 350.

[0069] Chip 200C may include semiconductor substrate 202, internal circuitry 210, dielectric layer 230, and sealing ring 240C.

[0070] A sealing ring 240C is disposed on the oxide layer 202-1 of the semiconductor substrate 202. The sealing ring 240C is located between the circuit region RC and the peripheral region RP, and surrounds the circuit region RC. Furthermore, the sealing ring 240C may continuously surround the internal circuit 210 and the waveguide 360. In some embodiments, the sealing ring 240C may include a silicon layer 202-2, a contact layer 242, a multi-level metal layer ML (e.g., a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, a sixth metal layer M6, a seventh metal layer M7, and an eighth metal layer M8), and a multi-level conductive via CV (e.g., a first conductive via V1, a second conductive via V2, a third conductive via V3, a fourth conductive via V4, a fifth conductive via V5, a sixth conductive via V6, and a seventh conductive via V7), all embedded in the dielectric layer 230. The sealing ring 240C may also include the dielectric layer 230 and a passivation layer 250.

[0071] like Figure 3As shown, the sealing ring 240C may include a hole (discontinuous region) HC through which the SSC350 passes. Furthermore, the SSC350 is separated from the metal layer ML and the conductive via CV by a dielectric layer 230. In some embodiments, the hole HC (opening) is formed at least in the bottom metal layer (e.g., the first metal layer M1) and the metal layer immediately above the bottom metal layer (e.g., the second metal layer M2) of the sealing ring 240C. For example, the hole HC is formed in the contact layer 242, the first metal layer M1, the first conductive via V1, the second metal layer M2, the second conductive via V2, the third metal layer M3, the third conductive via V3, and the fourth metal layer M4. More specifically, in the sealing ring 240C, the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the first conductive via V1, the second conductive via V2, and the third conductive via V3 are discontinuous. Furthermore, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, the eighth metal layer M8, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7 are continuous. Therefore, although the sealing ring in some embodiments is discontinuous (i.e., has a broken section), the embodiments provide a blocking strip 244-1, which can be used to block or reduce the passage of impurities such as moisture through the broken section of the sealing ring. This not only maintains the blocking function but also allows the spot size converter to pass through. Thus, while ensuring the functionality and transmission of the photonic integrated circuit, it protects the internal circuit as much as possible, ensuring the stable and reliable operation of the photonic integrated circuit and guaranteeing its performance. In some embodiments, the sealing ring 240C includes multiple metal layers (M1–M8), and the hole HC is formed only in some (i.e., certain) of the metal layers, not in all of them. Therefore, the sealing ring 240C still remains continuous. Therefore, the sealing ring of this invention, while maintaining continuity, provides a hole through which the spot size converter can pass. This not only maintains the blocking function of the sealing ring but also allows the spot size converter to pass through. Thus, while ensuring the functionality and transmission of the photonic integrated circuit, it utilizes a continuous sealing ring to protect the internal circuitry as much as possible, ensuring the stable and reliable operation of the photonic integrated circuit and guaranteeing its performance.

[0072] In some embodiments, the fifth metal layer M5, the sixth metal layer M6, the seventh metal layer M7, the eighth metal layer M8, the fourth conductive via V4, the fifth conductive via V5, the sixth conductive via V6, and the seventh conductive via V7 may cover the discontinuous areas of the contact layer 242, the first metal layer M1, the second metal layer M2, and the first conductive via V1.

[0073] In some embodiments, the discontinuous regions of the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the first conductive via V1, the second conductive via V2, and the third conductive via V3 may overlap each other, and they have different widths W1C. For example, the widths W1C-01 of the discontinuous region of the contact layer 242, W1C-1 of the discontinuous region of the first metal layer M1, W1C-2 of the discontinuous region of the second metal layer M2, W1C-3 of the discontinuous region of the third metal layer M3, and W1C-4 of the discontinuous region of the fourth metal layer M4 may gradually decrease toward the upper surface 240CT of the sealing ring 240C.

[0074] In some embodiments, the sidewalls 242S of the contact layer 242 used to define the hole HC, the sidewalls M1S of the first metal layer M1, the sidewalls M2S of the second metal layer M2, the sidewalls M3S of the third metal layer M3, and the sidewalls M4S of the fourth metal layer M4 are not aligned with each other.

[0075] Similarly, the width of the discontinuous regions of the first conductive via V1, the second conductive via V2, and the third conductive via V3 can gradually decrease toward the upper surface 240CT of the sealing ring 240C.

[0076] In some embodiments, the via HC may extend into the silicon layer 202-2 of the semiconductor substrate 202. The width W1C-00 of the discontinuous region of the silicon layer 202-2 may be greater than the width W1C-01 of the discontinuous region of the contact layer 242. In some embodiments, the sidewalls 202-BS of the silicon layer 202-2 of the semiconductor substrate 202 used to define the via HC are not aligned with the corresponding sidewalls 242S, M1S, M2S, M3S, and M4S.

[0077] In some embodiments, the width W1C of the discontinuous region of the contact layer 242, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the first conductive via V1, the second conductive via V2, and the third conductive via V3 can also be used as the width W1C of the hole HC. In some embodiments, the width W1C of the hole HC can gradually decrease towards the upper surface 240CT of the sealing ring 240C.

[0078] In a cross-sectional view near the extension direction of the sealing ring 240C close to the orifice HC, the orifice HC may have an inverted conical shape.

[0079] In some embodiments, SSC350 is located in the discontinuous region of silicon layer 202-2, contact layer 242, first metal layer M1, second metal layer M2, third metal layer M3, fourth metal layer M4, and first conductive via V1, second conductive via V2 and third conductive via V3.

[0080] In some embodiments, the bottom surface 350B of the SSC350 may be flush with the bottom surface 202-2B of the silicon layer 202-2. The top surface 350T of the SSC350 may be flush with the bottom surface 242B of the contact layer 242 (i.e., the bottom surface of the sealing ring 240C).

[0081] In some embodiments, the distance S1C between the hole HC and the upper surface 350T of the SSC350 is greater than the width W2 of the SSC350. In some embodiments, the maximum distance S2C between the hole HC and the side surface 350S of the SSC350 is the same as the width W2 of the SSC350, for example, about 2-3 μm. In some embodiments, the maximum width W1C of the hole HC is substantially the same as three times the width W2 of the SSC350, for example, about 6-9 μm. In some embodiments, the minimum width W1C of the hole HC may be less than the width W2 of the SSC350.

[0082] When the pitch S1C, maximum pitch S2C, and maximum width W1C are kept within appropriate ranges, the sealing ring 240C can effectively prevent unwanted moisture from penetrating and reaching the internal circuitry 210. Furthermore, by appropriately setting the pitches S1C and S2C, signal transmission through the SSC350 can be made more stable and reliable, thereby reducing interference from the metal layer.

[0083] The photonic integrated circuit 500C aims to redesign the sealing ring 240C to form at least one anti-conical aperture HC in the bottom metal layer (e.g., the first metal layer M1) and the metal layer immediately above the bottom metal layer (e.g., the second metal layer M2). Furthermore, the aperture HC can extend to a portion of the semiconductor substrate (e.g., silicon layer 202-2 of the semiconductor substrate 202). The sealing ring 240C can block moisture while still enabling the functionality of the SSC (e.g., SSC350), thereby improving chip durability and performance. This novel sealing ring 240C maintains the optical path but prevents moisture ingress. The sealing ring 240C includes a narrow aperture to minimize copper loss (discontinuous areas of the sealing ring 240C) and to bring the metal as close as possible to the SSC350. The photonic integrated circuit 500C can further reduce the size of the sealing ring aperture HC to minimize moisture penetration. In some embodiments, the aperture HC can be gradually closed and sealed in the upper metal layer (starting from the fifth metal layer M5 or the sixth metal layer M6). In some embodiments, the bottom surface 350B of SSC350 may be flush with the bottom surface 202-2B of silicon layer 202-2.

[0084] Figure 5 This is a schematic top view of a photonic integrated circuit 500D according to certain embodiments of the present invention. Figure 6 According to certain embodiments of the present invention Figure 5 The image shows an enlarged view of the photonic integrated circuit 500D. For simplicity, it is shown alongside... Figure 1-4 The same or similar embodiments will not be described again here. For ease of explanation, Figure 5 The dielectric layer of the 500D photonic integrated circuit interconnect structure is omitted.

[0085] like Figure 1 and Figure 5 As shown, the difference between photonic integrated circuit 500A (or photonic integrated circuit 500B and 500C) and photonic integrated circuit 500D includes at least the following: photonic integrated circuit 500D may include a sealing ring 240D having one or more blocking strips 244.

[0086] like Figure 5 and Figure 6 As shown, the photonic integrated circuit 500D includes a chip 200D, one or more external optical fibers 300, and a spot size converter (SSC) 350.

[0087] Chip 200D may include a semiconductor substrate 202, internal circuitry 210, a dielectric layer (same as or similar to the dielectric layer 230 of photonic integrated circuits 500A-500C), and a sealing ring 240D. Chip 200D may include at least one V-groove 370, and an external optical fiber 300 may be disposed within the V-groove 370. The number of V-grooves 370 may correspond to the number of external optical fibers 300. At least one V-groove 370 is located outside and adjacent to (i.e., close to) the sealing ring 240D. Each V-groove 370 may be a V-groove formed on the semiconductor substrate 202. A gap may exist between the inner sidewall 371 of the V-groove 370 and the external optical fiber 300 disposed therein. This gap may be filled with a dielectric material. In some embodiments, such as Figure 5 and Figure 6 As shown, the photonic integrated circuit 500D includes three V-grooves 370 and three external optical fibers 300. The closer the V-grooves 370 are to the upper surface of the semiconductor substrate 202, the larger their opening width, thereby facilitating the firm and stable positioning of the external optical fibers 300.

[0088] A sealing ring 240D is disposed on the oxide layer of the semiconductor substrate 202 of the chip 200D. The sealing ring 240D is located between the circuit region RC and the peripheral region RP, and surrounds the circuit region RC. Furthermore, the sealing ring 240D may continuously surround the internal circuitry 210 and the waveguide 360. For example, the sealing ring 240D may have the same or similar structure as sealing rings 240A / 240B / 240C. In some embodiments, the sealing ring 240D comprises multiple metal layers (M1–M8), and the hole HD is formed only in some (i.e., some) of the metal layers, not in all of them. Alternatively, in some embodiments, the sealing ring 240D may have a different structure than sealing rings 240A / 240B / 240C. For example, the difference between sealing ring 240D and sealing rings 240A / 240B / 240C is that the hole HD is formed through all metal layers (M1–M8). The hole HD is not formed in the dielectric layer 230 and / or passivation layer 250 above the metal layer ML. For example, the sealing ring 240D may be discontinuous and may include at least one break (opening) through which the SSC 350 passes. More specifically, each metal layer (M1–M8) in the metal layer ML includes a corresponding break such that the sealing ring 240D is interrupted in all metal layers. Thus, the break (opening) interrupts the sealing ring 240D, thereby forming a discontinuous sealing ring 240D. In some embodiments, the break (opening) is located in the first ring portion 240-1 of the sealing ring 240D. In some embodiments, the sealing ring 240D may include a hole (discontinuous region) HD through which the SSC 350 passes. In some embodiments, the hole HD of the sealing ring 240D may have the same or similar design as the hole HA of the sealing ring 240A or the hole HB of the sealing ring 240B.

[0089] like Figure 5 and Figure 6As shown, the sealing ring 240D further includes one or more blocking strips 244 (including blocking strips 244-1 and 244-2). The blocking strips 244 are disposed near the hole HD of the sealing ring 240D. The blocking strips 244 may be disposed in the space between the second ring portion 240-2 and the third ring portion 240-3. In some embodiments, the angle between the longitudinal (length direction) extending direction of the blocking strip 244 and the longitudinal (length direction) extending direction of the SSC 350 (or V-groove 370 or external optical fiber 300) may be between 0° and 180°. At least one blocking strip 244 simultaneously contacts the sealing ring 240D and the inner sidewall 371 of the V-groove 370. By providing simultaneous contact with the sealing ring 240D and the inner sidewall 371, at least one blocking strip 244 can effectively inhibit the entry of impurities (e.g., moisture) and protect the internal circuitry 210 even when the sealing ring 240D is discontinuous. Therefore, although the sealing ring in some embodiments is discontinuous (i.e., has a broken section), the embodiments provide a blocking strip 244-1. This blocking strip 244-1 can be used to block or reduce the passage of impurities such as moisture through the broken section of the sealing ring. This not only maintains the blocking function but also allows the spot size converter to pass through. Thus, while ensuring the functionality and transmission of the photonic integrated circuit, it protects the internal circuit as much as possible, ensuring the stable and reliable operation of the photonic integrated circuit and guaranteeing its performance.

[0090] A barrier strip 244 is disposed on the outside of the sealing ring 240D. The barrier strip 244 can be arranged to block the path PH of moisture diffusion through the hole HD of the sealing ring 240D, thereby preventing moisture from entering the internal circuit 210.

[0091] In some embodiments, the blocking strip 244 may include blocking strips 244-1 and 244-2. Each of the blocking strips 244-1 and 244-2 is separated from the internal circuitry 210 by a sealing ring 240D.

[0092] In some embodiments, the blocking strips 244-1 are disposed on opposite sides of the SSC 350 and extend substantially parallel to each other. That is, one blocking strip 244-1 is disposed on each side. The blocking strips 244-1 connect to and contact the first ring portion 240-1 of the sealing ring 240D. In some embodiments, the angle between the longitudinal (length direction) extending direction of the blocking strip 244-1 and the longitudinal (length direction) extending direction of the SSC 350 (or the V-groove 370 or the external optical fiber 300) can be greater than or equal to 0 degrees and less than 90 degrees. In some embodiments, the longitudinal (length direction) extending direction of the blocking strip 244-1 can be parallel to the longitudinal (length direction) extending direction of the SSC 350 (or the V-groove 370 or the external optical fiber 300). Furthermore, the blocking strips 244-1 can intersect with the moisture diffusion path PH.

[0093] In some embodiments, the blocking strip 244-1 is connected to the sealing ring 240D. Since the moisture diffusion path PH near the hole HD of the sealing ring 240D is formed substantially along the sealing ring 240D, the longitudinal (length direction) extension direction of the blocking strip 244-1 can be perpendicular to the extension direction of the portion of the sealing ring 240D (first ring portion 240-1) to which the blocking strip 244-1 is connected. Alternatively, the blocking strip 244-1 can be separated from the sealing ring 240D. In some embodiments, the blocking strip 244-1 can extend in a straight line and may or may not contact the inner wall 371 of the corresponding V-groove 370. In some embodiments, the blocking strip 244-1 simultaneously contacts both the sealing ring 240D (first ring portion 240-1) and the inner wall 371 of the V-groove 370. In some embodiments, the blocking strip 244-1 can contact the inner wall 371 and extend to its outer side (i.e., into the corresponding V-groove 370). However, the blocking strip 244-1 does not contact the external optical fiber 300. In other words, the blocking strip 244-1 is spaced apart from the external optical fiber 300.

[0094] In some embodiments, the blocking strip 244-2 is configured to overlap with the spot size converter (SSC) 350. In some embodiments, the angle between the longitudinal (length direction) extension direction of the blocking strip 244-2 and the longitudinal (length direction) extension direction of the SSC 350 (or V-groove 370 or external fiber 300) is greater than 0 degrees and less than or equal to 90 degrees. In some embodiments, the longitudinal (length direction) extension direction of the blocking strip 244-2 may be perpendicular (or orthogonal) to the longitudinal (length direction) extension direction of the SSC 350 (or V-groove 370 or external fiber 300). Furthermore, the blocking strip 244-2 may intersect (e.g., substantially perpendicular to) the moisture diffusion path PH. In some embodiments, the blocking strip 244-1 contacts the sealing ring 240D (first ring portion 240-1) and extends toward the blocking strip 244-2. In some embodiments, the first blocking strip 244-1 and the second blocking strip 244-2 respectively contact different ring portions of the sealing ring 240D. For example, as... Figure 5 and Figure 6 As shown, the first blocking strip 244-1 contacts the first ring portion 240-1 of the sealing ring 240D, while the second blocking strip 244-2 contacts the second ring portion 240-2 and the third ring portion 240-3 of the sealing ring 240D.

[0095] In some embodiments, the blocking strip 244-2 is connected to the sealing ring 240D. The blocking strip 244-2 is connected to the second ring portion 240-2 and / or the third ring portion 240-3 of the sealing ring 240D. The blocking strip 244-2 contacts the second ring portion 240-2 and / or the third ring portion 240-3 of the sealing ring 240D. In some embodiments, the blocking strip 244-2 simultaneously contacts the sealing ring 240D and the inner wall 371 of the V-groove 370. Since the moisture diffusion path PH of the hole HD near the sealing ring 240D is formed substantially along the sealing ring 240D, the longitudinal (length direction) extension direction of the blocking strip 244-2 can be perpendicular to the extension direction of the portion of the sealing ring 240D to which the blocking strip 244-2 is connected. Alternatively, the blocking strip 244-2 can be separated from the sealing ring 240D. In some embodiments, the blocking strip 244-2 can extend in a straight line and can contact the inner wall 371 of the corresponding V-groove 370. The blocking strip 244-2 may contact the sealing ring 240D. When multiple SSCs 350 (and corresponding external optical fibers 300) are provided, a portion of the blocking strip 244-2 located between two adjacent external optical fibers 300 may contact the inner sidewalls 371 of two corresponding V-grooves 370. Furthermore, a portion of the blocking strip 244-2 located between the external optical fiber 300 and the sealing ring 240D may contact the inner sidewall 371 of the corresponding V-groove 370 and the sealing ring 240D (the second ring portion 240-2 or the third ring portion 240-3). In some embodiments, the blocking strip 244-2 may extend beyond the inner sidewall 371 and enter the corresponding V-groove 370. However, the blocking strip 244-2 does not contact the external optical fibers 300. In other words, the blocking strip 244-2 is spaced apart from the external optical fibers 300. Regardless of whether the sealing ring 240D is continuous or discontinuous, since the blocking strip 244-2 at least contacts the inner wall 371 of the corresponding V-groove 370, it can reduce the entry of impurities (e.g., moisture) into the internal circuit 210, thereby protecting the internal circuit 210. Furthermore, a blocking strip 244-1 with an extension direction different from the blocking strip 244-2 can be provided to further suppress the entry of impurities (e.g., moisture) into the internal circuit 210. In some embodiments, the longitudinal (length direction) extension direction of the blocking strip 244-2 is substantially perpendicular to the longitudinal (length direction) extension direction of the SSC 350 or the external optical fiber 300.

[0096] In some embodiments, the blocking strips 244-1 and 244-2 extend in different directions, corresponding (perpendicular) to the extending direction of the sealing ring 240D portion to which they are connected. For example, as Figure 4 and Figure 5As shown, the longitudinal (length direction) extension direction of the blocking strip 244-2 is perpendicular to the longitudinal (length direction) extension direction of the blocking strip 244-1. The longitudinal (length direction) extension direction of the blocking strip 244-2 is perpendicular to the longitudinal (length direction) extension direction of the SSC 350. In some embodiments, the blocking strip 244-2 simultaneously contacts the sealing ring 240D and the inner wall 371 of the V-groove 370, while the blocking strip 244-1 contacts the sealing ring 240D but not the inner wall 371 of the V-groove 370 (e.g., the blocking strip 244-1 is spaced apart from the inner wall 371). This configuration simplifies the manufacturing process while effectively protecting the internal circuitry 210. In some embodiments, the blocking strips 244-2 and 244-1 simultaneously contact the sealing ring 240D and the inner wall 371 of the V-groove 370, thereby more effectively protecting the internal circuitry 210.

[0097] The blocking strip 244 can serve as a virtual ring portion or extension of the sealing ring 240D. Therefore, the blocking strip 244 can have the same or similar structure and material as the sealing ring 240D.

[0098] In some embodiments, the blocking strip 244 and the sealing ring 240D may contain the same number of metal layers ML and the same number of conductive vias CV. In some embodiments, the width WD of the sealing ring 240D is greater than the width WD1 of the blocking strip 244-1 and the width WD2 of the blocking strip 244-2. Furthermore, the width WD1 of the blocking strip 244-1 may be the same as or different from the width WD2 of the blocking strip 244-2.

[0099] In some embodiments, the blocking strip 244 may be connected to the sealing ring 240D and grounded. Alternatively, the blocking strip 244 may be separated from the sealing ring 240D and in a floating state.

[0100] The photonic integrated circuit 500C combines the advantages of photonic integrated circuits 500A, 500B, and 50C. Furthermore, the photonic integrated circuit 500C aims to redesign the sealing ring 240D with the blocking strip 244 to further block the moisture diffusion path PH through the hole HD of the sealing ring 240D, while still achieving the functionality of the SSC (e.g., SSC 350), thereby improving the chip's durability and performance. This may involve an innovative new sealing ring structure that both ensures optical path and prevents moisture ingress.

[0101] This invention provides a photonic integrated circuit. The photonic integrated circuit includes internal circuitry, a sealing ring, and a spot size converter (SSC). The sealing ring continuously surrounds the internal circuitry. The spot size converter (SSC) is connected between the internal circuitry and an external optical fiber. The sealing ring includes a hole through which the SSC passes.

[0102] In some embodiments, the sealing ring includes a plurality of metal layers, wherein a first metal layer of the plurality of metal layers is discontinuous and a second metal layer of the plurality of metal layers is continuous.

[0103] In some embodiments, the SSC is located in a discontinuous region of the first metal layer.

[0104] In some embodiments, the second metal layer covers the first metal layer and the discontinuous regions of the first metal layer.

[0105] In some embodiments, the maximum width of the hole is 9 μm.

[0106] In some embodiments, the width of the hole gradually decreases toward the upper surface of the sealing ring.

[0107] In some embodiments, the bottom surface of the SSC is substantially flush with the bottom surface of the sealing ring.

[0108] In some embodiments, the SSC is separated from the metal layer by a dielectric layer.

[0109] In some embodiments, the photonic integrated circuit further includes a V-groove and a first blocking strip. The V-groove is located outside and adjacent to the sealing ring. The external optical fiber is disposed within the V-groove. The first blocking strip contacts the sealing ring and the inner sidewall of the V-groove. The angle between the extension direction of the first blocking strip and the extension direction of the SSC is greater than 0° and less than or equal to 90°.

[0110] In some embodiments, the longitudinal (length direction) extension direction of the first blocking strip is parallel to the longitudinal (length direction) extension direction of the SSC.

[0111] In some embodiments, the photonic integrated circuit further includes a second blocking strip that contacts the sealing ring and extends toward the first blocking strip. The angle between the extension direction of the second blocking strip and the extension direction of the SSC is greater than or equal to 0° and less than 90°.

[0112] In some embodiments, the longitudinal (length direction) extension direction of the second barrier strip is perpendicular to the extension direction of the sealing ring portion connecting the second barrier strip.

[0113] In some embodiments, the longitudinal (length direction) extension direction of the second blocking strip is perpendicular to the longitudinal (length direction) extension direction of the first blocking strip.

[0114] In some embodiments, the photonic integrated circuit further includes a third blocking strip disposed near the hole, wherein the first blocking strip and the third blocking strip are located on opposite sides of the SSC and are parallel to each other.

[0115] In some embodiments, each of the first, second, and third blocking strips is connected to or separated from the sealing ring.

[0116] In some embodiments, the width of the sealing ring is greater than the width of either the first blocking strip or the second blocking strip.

[0117] In some embodiments, the sealing ring and either the first blocking strip or the second blocking strip comprise the same number of metal layers as the sealing ring.

[0118] In some embodiments, each of the first and second blocking bars is separated from the internal circuitry by the sealing ring.

[0119] In some embodiments, the first blocking strip and the second blocking strip respectively contact different ring portions of the sealing ring.

[0120] This invention provides a photonic integrated circuit. The photonic integrated circuit includes an internal circuit, a sealing ring, and a spot size converter (SSC). The sealing ring surrounds the internal circuit. The spot size converter (SSC) is connected between the internal circuit and an external optical fiber. The sealing ring includes multiple metal layers and a hole through which the SSC passes, and the hole is formed in a portion of the multiple metal layers.

[0121] In some embodiments, the photonic integrated circuit further includes at least one blocking strip disposed near the hole and separated from the internal circuit by the sealing ring.

[0122] In some embodiments, the longitudinal (length direction) extension direction of the blocking strip is parallel or perpendicular to the longitudinal (length direction) extension direction of the SSC.

[0123] In some embodiments, the photonic integrated circuit further includes a V-groove located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove. The at least one blocking strip contacts the sealing ring and the inner wall of the V-groove, and the at least one blocking strip is spaced apart from the external optical fiber.

[0124] This invention provides a photonic integrated circuit. The photonic integrated circuit includes an internal circuit, a sealing ring, a spot size converter (SSC), a V-groove, and a first blocking strip. The sealing ring surrounds the internal circuit. The spot size converter (SSC) passes through an opening in the sealing ring and connects the internal circuit to an external optical fiber. The V-groove is located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove. The first blocking strip is connected to the sealing ring. The first blocking strip contacts the inner wall of the V-groove and is spaced apart from the external optical fiber.

[0125] In some embodiments, the sealing ring includes a first ring portion and a second ring portion connected to the first ring portion. The opening is located in the first ring portion, and the first blocking strip contacts the second ring portion.

[0126] In some embodiments, the photonic integrated circuit further includes a second blocking strip extending in a direction different from the extending direction of the first blocking strip. The second blocking strip contacts the first ring portion.

[0127] In some embodiments, the second blocking strip contacts the inner wall of the V-groove and is spaced apart from the outer optical fiber.

[0128] While the invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, the invention is intended to cover various modifications and similar structures. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A photonic integrated circuit, characterized in that, include: Internal circuitry; A sealing ring continuously surrounds the internal circuit. as well as A beam size converter connects the internal circuitry to the external optical fiber. The sealing ring includes a hole through which the spot size converter passes.

2. The photonic integrated circuit as described in claim 1, characterized in that, The sealing ring comprises multiple metal layers, wherein the first metal layer of the multiple metal layers is discontinuous, and the second metal layer of the multiple metal layers is continuous.

3. The photonic integrated circuit as described in claim 2, characterized in that, The spot size converter is located in the discontinuous region of the first metal layer.

4. The photonic integrated circuit as described in claim 3, characterized in that, The second metal layer covers the first metal layer and the discontinuous areas of the first metal layer.

5. The photonic integrated circuit as described in claim 1, characterized in that, The width of the hole gradually decreases towards the upper surface of the sealing ring.

6. The photonic integrated circuit as described in claim 1, characterized in that, The bottom surface of the spot size converter is substantially flush with the bottom surface of the sealing ring or the bottom surface of the contact layer of the sealing ring.

7. The photonic integrated circuit as described in claim 2, characterized in that, The spot size converter is separated from the metal layer by a dielectric layer.

8. The photonic integrated circuit as described in claim 1, characterized in that, Further includes: A V-groove is located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove; as well as The first blocking strip contacts the sealing ring and the inner wall of the V-groove, wherein the angle between the extending direction of the first blocking strip and the extending direction of the spot size converter is greater than 0° and less than or equal to 90°.

9. The photonic integrated circuit as described in claim 8, characterized in that, Further includes: The second blocking strip contacts the sealing ring and extends toward the first blocking strip, wherein the angle between the extension direction of the second blocking strip and the extension direction of the spot size converter is greater than or equal to 0° and less than 90°.

10. The photonic integrated circuit as described in claim 9, characterized in that, The width of the sealing ring is greater than the width of either the first blocking strip or the second blocking strip.

11. The photonic integrated circuit as described in claim 10, characterized in that, The sealing ring and either the first blocking strip or the second blocking strip contain the same number of metal layers as the sealing ring.

12. The photonic integrated circuit as described in claim 9, characterized in that, Each of the first and second blocking bars is separated from the internal circuitry by the sealing ring.

13. The photonic integrated circuit as described in claim 9, characterized in that, The first and second blocking strips respectively contact different ring portions of the sealing ring.

14. A photonic integrated circuit, characterized in that, include: Internal circuitry; A sealing ring surrounds the internal circuitry; as well as A beam size converter connects the internal circuitry to the external optical fiber. The sealing ring includes multiple metal layers and a hole through which the spot size converter passes, and the hole is formed in a portion of the multiple metal layers.

15. The photonic integrated circuit as described in claim 14, characterized in that, The photonic integrated circuit further includes at least one blocking strip disposed near the hole and separated from the internal circuit by the sealing ring.

16. The photonic integrated circuit as described in claim 15, characterized in that, Further includes: A V-groove, located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove; and The at least one blocking strip contacts the sealing ring and the inner wall of the V-groove, and the at least one blocking strip is spaced apart from the external optical fiber.

17. A photonic integrated circuit, characterized in that, include: Internal circuitry; A sealing ring surrounds the internal circuitry; A spot size converter passes through the opening of the sealing ring and connects the internal circuit to the external optical fiber; A V-groove, located outside and adjacent to the sealing ring, wherein the external optical fiber is disposed within the V-groove; and A first blocking strip is connected to the sealing ring, wherein the first blocking strip contacts the inner wall of the V-groove and is spaced apart from the external optical fiber.

18. The photonic integrated circuit as described in claim 17, characterized in that, The sealing ring includes a first ring portion and a second ring portion connected to the first ring portion, wherein the opening is located in the first ring portion and the first blocking strip contacts the second ring portion.

19. The photonic integrated circuit as described in claim 18, characterized in that, Further includes: The second blocking strip extends in a direction different from that of the first blocking strip, wherein the second blocking strip contacts the first ring portion.

20. The photonic integrated circuit as described in claim 19, characterized in that, The second blocking strip contacts the inner wall of the V-groove and is spaced apart from the outer optical fiber.

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