Electro-wetting display panel and display device

Abstract

This invention proposes an electrowetting display panel and a display device. The electrowetting display panel includes an array substrate, a fluid layer, and a counter substrate stacked together. The pixel unit of the array substrate includes a pixel electrode, a first thin-film transistor, and a control electrode. A first insulating layer between the source and the second gate of the first thin-film transistor is further provided with a fluid channel. The control electrode extends through the first insulating layer to a first metal layer. The control electrode is used to receive a target control voltage and drive a second fluid of a target volume to move in the fluid channel to adjust the parasitic capacitance between the second gate and the source. The target control voltage changes in correlation with the grayscale voltage of the pixel unit. It can adjust the parasitic capacitance value according to the real-time working state of the pixel unit, specifically offsetting the feedthrough voltage deviation under different pixels, different grayscale levels, and different working scenarios, effectively improving the uneven flicker problem of the electrowetting display panel and improving the display effect.

Description

Technical Field

[0001] This invention belongs to the field of electrowetting display panel technology, and particularly relates to an electrowetting display panel and display device. Background Technology

[0002] Electrowetting electronic paper, with its advantages such as ultra-low power consumption, paper-like display effect, wide viewing angle, and flexible display, is widely used in various display scenarios such as e-readers, smart tags, automotive displays, and wearable devices, and is currently a key research and industrialization direction in the field of passive display technology. As market demands for electronic paper display quality continue to rise, display defects such as screen flicker, uneven brightness, and grayscale distortion have become key technical bottlenecks restricting the high-end application of electrowetting electronic paper. Among these, uneven flicker is a common technical problem that has long been difficult to completely solve within the industry.

[0003] The physical cause of screen flickering due to electrowetting of electronic paper lies in the parasitic capacitive coupling effect during the turn-off process of thin-film transistors (TFTs). The TFTs within the pixel circuit possess inherent gate-source parasitic capacitance characteristics. During display driving, the horizontal scan signal continuously switches between turn-on and turn-off voltages. This voltage transition is transmitted to the pixel electrodes through gate-source parasitic capacitance coupling, causing a fixed DC voltage offset at the pixel electrodes. This offset is defined in the industry as the feedthrough voltage. The presence of the feedthrough voltage directly alters the actual applied voltage across the pixel, resulting in a deviation between the actual operating voltage and the preset target voltage.

[0004] In actual panel operation scenarios, there are differences in the transmission delay of the line scan signal at different pixel positions. At the same time, the pixel capacitance parameters change in real time under different grayscale display states. These two factors together cause significant differences in the feedthrough voltage offset of different pixels. Especially in the industry-standard AC drive mode, the positive and negative frame drive voltages cannot achieve perfectly symmetrical output, which will cause periodic fluctuations in pixel brightness. These fluctuations are visually perceived by the human eye and appear as screen flicker. Moreover, the degree of flicker is inconsistent in different areas of the pixel, ultimately causing a display defect of uneven flickering across the entire screen, which seriously reduces the display quality and visual experience of e-paper.

[0005] Currently, the industry has developed two main technical solutions to address the flickering problem of electrowetting electronic paper: static structural compensation and dynamic capacitance adjustment compensation. However, both solutions have significant technical flaws and cannot completely eliminate the problem of uneven flickering.

[0006] The traditional static compensation scheme works by designing fixed gate-source parasitic capacitance parameters for different pixel regions. These preset capacitance parameters offset the feedthrough voltage deviation caused by line scanning delay, bringing the pixel operating voltage closer to a preset standard value. However, this scheme is a passive, fixed structural compensation method. All capacitance compensation parameters are finalized during panel manufacturing, and no parameter adjustments can be made after panel fabrication. In actual display, the ink and droplets inside the pixels of an electrowetting panel continuously flow and change shape with grayscale transitions, directly causing drastic dynamic fluctuations in pixel capacitance. Fixed static capacitance parameters cannot adapt to these real-time changes in pixel capacitance, resulting in extremely low compensation accuracy and failing to effectively improve the uneven flickering problem during dynamic display.

[0007] One existing patented technology presents a dynamic storage capacitor compensation scheme. This scheme uses a variable dielectric material to fabricate the pixel storage capacitor, transforming the traditional fixed storage capacitor into a variable capacitor structure with adjustable parameters. It can adjust the storage capacitor value according to the real-time display refresh rate of the panel, slightly reducing screen flicker in low-frequency display scenarios and optimizing overall panel power consumption in high-frequency display scenarios. However, this dynamic compensation scheme has fundamental technical limitations and cannot effectively solve the problem of uneven flicker caused by electrowetting of electronic paper. First, the capacitor adjustment mode of this scheme is a fixed preset adjustment, which can only achieve optimization effects for specific refresh rate scenarios and cannot adapt to full refresh rate operating scenarios, resulting in a very limited optimization effect. Furthermore, this scheme only adjusts the parameters of the storage capacitor, completely ignoring the feedthrough voltage differences caused by dynamic changes in pixel capacitance. It cannot suppress the flicker component caused by dynamic fluctuations in pixel capacitance, and its improvement effect on uneven flicker is very limited.

[0008] Secondly, the pixel storage capacitor has a dual function: it can not only regulate the pixel feedthrough voltage but also stabilize the pixel operating voltage, ensuring grayscale display accuracy. This solution, which compensates for the feedthrough voltage by adjusting the storage capacitor alone, directly disrupts the balance of the pixel voltage, causing secondary display defects such as pixel grayscale voltage shift, grayscale display distortion, and uneven color. While improving the flicker problem, it introduces new image quality issues, making the technology less practical.

[0009] In summary, current electrowetting display compensation technologies cannot simultaneously adapt to the dual flickering causes of pixel scanning delay differences and pixel capacitance dynamic fluctuations. They suffer from numerous defects, such as low compensation accuracy, poor adaptability, easy grayscale distortion, and inability to achieve full-domain adaptive compensation, making it difficult to meet the high-definition, stable, and flicker-free display requirements of high-end electrowetting electronic paper. Summary of the Invention

[0010] The purpose of this invention is to provide an electrowetting display panel that solves the problems of low compensation accuracy and grayscale distortion in traditional electrowetting display compensation technology.

[0011] A first aspect of the present invention provides an electrowetting display panel, comprising an array substrate, a fluid layer and an opposing substrate stacked together, wherein the fluid layer comprises a non-conductive first fluid and a conductive second fluid; The opposing substrate includes a first substrate and a first common electrode layer stacked on the side of the first substrate facing the array substrate; The array substrate is provided with a second common electrode layer, multiple rows of scan lines, multiple columns of data lines and an array of pixel units. The pixel unit includes a pixel electrode, a first thin film transistor and a control electrode. The first thin film transistor includes a drain, a semiconductor layer, a source, a first gate and a second gate. The first gate and the second gate are both connected to the same scan line. The drain is connected to one of the data lines and the source is connected to the pixel electrode. The array substrate includes a second substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a pixel electrode layer stacked together. The first gate, the second gate, and the second common electrode layer are located on the first metal layer. The drain, the semiconductor layer, the source, and the control electrode are located on the second metal layer. The pixel electrode is located on the pixel electrode layer. The first gate is disposed opposite to the semiconductor layer, and the second gate is disposed opposite to the source. The first insulating layer between the source and the second gate of each first thin-film transistor is further provided with a fluid channel. The control electrode extends through the first insulating layer to the first metal layer. The control electrode is used to receive a target control voltage and drive the second fluid of a target volume to move in the fluid channel to adjust the parasitic capacitance between the second gate and the source. The target control voltage is correlated with the grayscale voltage of the pixel unit.

[0012] Optionally, the array substrate further includes a storage area for storing the second fluid, and the fluid channel corresponding to each of the first thin-film transistors is connected to the storage area.

[0013] Optionally, the inner surface of the fluid channel is provided with a hydrophobic layer.

[0014] Optionally, the pixel unit further includes a second thin-film transistor, and the control electrode includes a first control electrode and a second control electrode; The second thin-film transistor of the pixel unit in the i-th row is connected to the scan line, the first control electrode and the second control electrode in the (i-1)-th row respectively. The first thin-film transistor of the pixel unit in the i-th row is connected to the scan line in the i-th row. The first control electrode is used to input the target control voltage. The second control electrode extends through the first insulating layer to the first metal layer. The second gate is disposed near the extension of the second control electrode. The extension of the second control electrode is arranged on the outer periphery of the source, the fluid channel and the second gate. The orthogonal projection of the extension of the second control electrode on the array substrate covers the source, the fluid channel and the second gate, where i is a positive integer and greater than 1.

[0015] Optionally, the second control electrode is located between the source electrode and the first control electrode.

[0016] Optionally, the first control electrode of each column of pixel units is connected and arranged in parallel with the data line; The first thin-film transistor and the second thin-film transistor are arranged diagonally relative to the pixel electrode.

[0017] Optionally, the fluid channel includes a first end face facing the control electrode and a second end face facing away from the control electrode, wherein the area of ​​the second end face of the fluid channel is larger than the area of ​​the first end face of the fluid channel, and the second end face is used to introduce the second fluid.

[0018] A second aspect of the present invention provides a display device, including a driving circuit for a display panel and an electrowetting display panel as described above, wherein the driving circuit for the display panel is connected to the electrowetting display panel.

[0019] Optionally, the electrowetting display panel includes a display area and a non-display area, and the array substrate further includes a detection pixel located in the non-display area. The first common electrode layer corresponding to the detection pixel includes a first common electrode and a second common electrode. The first common electrode is used to input a common electrode voltage, the detection pixel is used to input a test grayscale voltage, and the second common electrode is used to obtain the pixel capacitance between the detection pixel and the first common electrode. The driving circuit of the display panel is connected to the data line, the scan line, the detection pixel, the second common electrode, and the control electrode. The driving circuit of the display panel is used for: During the testing period, test grayscale voltages of different sizes are output, and pixel capacitances of different sizes are obtained. A mapping table is established based on the test grayscale voltages and the pixel capacitances. During the display period, a line scan signal and a grayscale voltage are output to the scan line and the data line respectively to drive the pixel unit to display. The pixel capacitance size is determined based on the grayscale voltage and the mapping table, and the target control voltage of the control electrode is determined based on the pixel capacitance size.

[0020] Optionally, the first common electrode and the second common electrode form an interdigitated structure.

[0021] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The electrowetting display panel mentioned above includes an array substrate, a fluid layer and a counter substrate stacked together. The array substrate is provided with a second common electrode layer, multiple rows of scan lines, multiple columns of data lines and pixel units arranged in an array. The pixel unit includes a pixel electrode, a first thin film transistor and a control electrode. The array substrate includes a second substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a pixel electrode layer stacked together. The first insulating layer between the source and the second gate of the first thin film transistor is also provided with a fluid channel. The control electrode extends through to the first metal layer. The control electrode is used to receive a target control voltage and drive the second fluid of the target volume to move in the fluid channel to adjust the parasitic capacitance between the second gate and the source. The target control voltage changes in correlation with the grayscale voltage of the pixel unit. It can adjust the parasitic capacitance value according to the real-time working state of the pixel unit, and specifically offset the feedthrough voltage deviation under different pixels, different grayscale and different working scenarios, effectively improve the uneven flicker problem of the electrowetting display panel and improve the display effect. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the first structure of the electrowetting display panel provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a second structure of the electrowetting display panel provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a first type of interlayer structure for the source and the second gate provided in Embodiment 1 of the present invention. Figure 4 A schematic diagram of the first type of equivalent capacitance of the source and the second gate provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of a third structure of the electrowetting display panel provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the fourth structure of the electrowetting display panel provided in Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of a second interlayer structure for the source and the second gate provided in Embodiment 1 of the present invention; Figure 8This is a schematic diagram of the second equivalent capacitance of the source and the second gate provided in Embodiment 1 of the present invention. Figure 9 This is a schematic diagram of the fifth structure of the electrowetting display panel provided in Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the sixth structure of the electrowetting display panel provided in Embodiment 2 of the present invention; Figure 11 This is a schematic diagram of the seventh structure of the electrowetting display panel provided in Embodiment 2 of the present invention; Figure 12 This is a schematic diagram of the structure of the display device provided in Embodiment 2 of the present invention; Figure 13 This is a schematic diagram of the structure of the display device provided in Embodiment 3 of the present invention; Figure 14 This is a schematic diagram of the structure of the opposing substrate of the detection pixel provided in Embodiment 3 of the present invention; Figure 15 This is a schematic diagram of the structure of the first common electrode layer provided in Embodiment 3 of the present invention.

[0023] The figures in the diagram are labeled as follows: 100. Electrowetting display panel; 200. Driving circuit for display panel; 210. Source driving circuit; 220. Gate driving circuit; 230. Voltage output circuit; 240. Timing controller; 101. Display area; 102. Non-display area; 103. Detection pixel; 131. First substrate; 132. First common electrode layer; 1321. First common electrode; 1322. Second common electrode; 10. Data line; 20. Scan line; 30. Pixel unit; 40. Second common electrode layer; 31. First thin-film transistor; 32. Second thin-film transistor; 110. Array substrate; 120. 130. Fluid layer; 111. Opposed substrate; 112. Second substrate; 113. First metal layer; 114. First insulating layer; 115. Second insulating layer; 116. Third insulating layer; 117. Pixel electrode layer; 118. Fourth insulating layer; 11. First gate; 1171. Pixel electrode; 12. Second gate; 13. Drain; 14. Semiconductor layer; 15. Source; 16. Fluid channel; 17. Control electrode; 18. Storage area; 19. Hydrophobic layer; 171. First control electrode; 172. Second control electrode; 161. First end face; 162. Second end face; Cd1, dielectric capacitance between the source and fluid channel interface; Cd2, dielectric capacitance between the second gate and fluid channel interface; C2d, dielectric capacitance between the second gate and source; C0, total interface capacitance of the inactive region; Ci1, first dielectric capacitance; Ci2, second dielectric capacitance. Detailed Implementation

[0024] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0025] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0026] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0028] Example 1 A first aspect of the present invention provides an electrowetting display panel 100.

[0029] like Figure 1 and Figure 2 As shown, the electrowetting display panel 100 includes an array substrate 110, a fluid layer 120 and an opposing substrate 130 stacked together. The fluid layer 120 includes a non-conductive first fluid and a conductive second fluid. The opposing substrate 130 includes a first substrate 131 and a first common electrode layer 132 stacked on the side of the first substrate 131 facing the array substrate 110; The array substrate 110 is provided with a second common electrode layer 40, multiple rows of scan lines 20, multiple columns of data lines 10, and an array of pixel units 30. The pixel unit 30 includes a pixel electrode 1171, a first thin film transistor 31, and a control electrode 17. The first thin film transistor 31 includes a drain 13, a semiconductor layer 14, a source 15, a first gate, and a second gate 12. The first gate and the second gate 12 are both connected to the same scan line 20. The drain 13 is connected to one of the data lines 10, and the source 15 is connected to the pixel electrode 1171. The array substrate 110 includes a second substrate 111, a first metal layer 112, a first insulating layer 113, a second metal layer 114, a second insulating layer 115, and a pixel electrode layer 117 stacked together. The first gate 11, the second gate 12, and the second common electrode layer 40 are located on the first metal layer 112. The drain 13, the semiconductor layer 14, the source 15, and the control electrode 17 are located on the second metal layer 114. The pixel electrode 1171 is located on the pixel electrode layer 117. Each first thin-film transistor 31 has a first insulating layer 113 between its source 15 and second gate 12, which is further provided with a fluid channel 16. A control electrode 17 extends through the first insulating layer 113 to the first metal layer 112. The control electrode 17 is used to receive the target control voltage and drive the second fluid of the target volume to move in the fluid channel 16 to adjust the parasitic capacitance between the second gate 12 and the source 15. The target control voltage changes in correlation with the grayscale voltage of the pixel unit 30.

[0030] In this embodiment, the overall structure of the electrowetting display panel 100 adopts a multi-layer film stacking architecture. The structure includes an array substrate 110, a fluid layer 120, and an opposing substrate 130. The array substrate 110, the fluid layer 120, and the opposing substrate 130 are stacked sequentially from bottom to top. Together, they constitute the complete display main structure of the electrowetting display panel 100. The grayscale display and screen flicker compensation functions are realized by relying on the electro-driven flow characteristics of the electrowetting fluid.

[0031] The fluid layer 120 is the dielectric layer for the electrowetting display panel 100, containing two fluid media with completely different physical properties: a non-conductive first fluid and a conductive second fluid. The two fluids are immiscible and can undergo relative displacement under an electric field. By changing the coverage area of ​​the two fluids in the pixel display area, different brightness grayscale display effects are achieved. The first fluid is transparent, and the second fluid is colored. In an optional embodiment, the second fluid is electronic ink, which is conductive and attracted and moved upon receiving an electrical signal. The first fluid can be water, a salt solution, etc.

[0032] The opposing substrate 130 serves as the upper substrate structure of the panel, undertaking the function of common electrode voltage output and optical display coordination. It includes a first substrate 131 and a first common electrode layer 132. The first common electrode layer 132 is integrally stacked on the side of the first substrate 131 facing the array substrate 110. The first substrate 131 can be made of a transparent rigid substrate material, possessing high light transmittance, high flatness, temperature resistance, and insulation stability, providing a stable supporting substrate for the first common electrode layer 132. The first common electrode layer 132 is made of a transparent conductive material, capable of outputting a uniform common electrode voltage across the entire area, providing a voltage reference for the electric field formation, fluid drive, and grayscale display of the pixel unit 30, ensuring the reference consistency of the operating voltage of all pixels on the screen.

[0033] The array substrate 110 serves as the circuit and structural substrate for the electrowetting display panel 100, undertaking all functions of signal transmission, pixel driving, capacitance compensation, and circuit control. The substrate surface integrates a second common electrode layer 40, multiple rows of scan lines 20, multiple columns of data lines 10, and a large number of pixel units 30 arranged in a matrix array. The multiple rows of scan lines 20 are arranged in parallel at equal intervals in the horizontal direction, and the multiple columns of data lines 10 are arranged in parallel at equal intervals in the vertical direction. The scan lines 20 and data lines 10 intersect each other perpendicularly, dividing the array substrate 110 into uniform pixel arrangement areas. Each intersecting area corresponds to an independent pixel unit 30, realizing independent driving and control of the pixel array.

[0034] The structure of a single pixel unit 30 includes a pixel electrode 1171, a first thin-film transistor 31, and a control electrode 17. The first thin-film transistor 31 is a switching device for pixel display, controlling the charging and off states of a single pixel. Figure 2 As shown, the first thin-film transistor 31 includes a drain 13, a semiconductor layer 14, a source 15, a first gate 11, and a second gate 12. The first gate 11 and the second gate 12 are both connected to the scan lines 20 of the corresponding rows. Each structure is matched with the logic of the circuit connection. The first gate 11 is connected to the scan lines 20 of the corresponding rows and can receive the row scan signal output by the row scan lines 20 in real time to control the conduction and turn-off of the first thin-film transistor 31. The drain 13 is connected to the data lines 10 of the corresponding columns and is used to receive the gray level voltage transmitted by the data lines 10. The source 15 is connected to the pixel electrode 1171. When the first thin-film transistor 31 is turned on, the gray level voltage of the data lines 10 can be transmitted to the pixel electrode 1171 through the drain 13, the semiconductor layer 14, and the source 15, so that the pixel electrode 1171 forms a driving electric field, which drives the fluid in the fluid layer 120 to move and complete the corresponding gray level display.

[0035] The array substrate 110 is fabricated using a multilayer thin-film ordered stacking process. From bottom to top, a second substrate 111, a first metal layer 112, a first insulating layer 113, a second metal layer 114, a second insulating layer 115, and a pixel electrode layer 117 are stacked sequentially. Each film layer has a clearly defined functional area and is arranged in a regular manner, working together to achieve multiple functions such as circuit conduction, electrical isolation, structural support, and functional compensation. The second substrate 111 is the base structure of the array substrate 110 and is made of a high-strength insulating substrate material, providing a flat and stable support foundation for all film layers and circuit structures.

[0036] The array substrate 110 further includes a third insulating layer 116 and a fourth insulating layer 118. The second insulating layer 115, the third insulating layer 116, the pixel electrode layer 117 and the fourth insulating layer 118 are stacked in sequence. A transparent hydrophobic layer is also stacked on the fourth insulating layer 118 and the first common electrode layer 132 respectively. The transparent hydrophobic layer is in contact with the fluid layer 120. By changing the electric field, the wettability of the surface of the transparent hydrophobic layer is changed, thereby causing the first fluid and the second fluid to deform and shift.

[0037] The first metal layer 112 is the bottom circuit metal layer, mainly integrating and fabricating the first gate 11, the second gate 12, and the second common electrode layer 40. The second common electrode layer 40 is the common potential structure of the array substrate 110. The source 15 of the pixel unit 30 overlaps with the second common electrode layer 40 of the first metal layer 112 to form a pixel storage capacitor with fixed parameters. The parameters of this storage capacitor remain constant and do not participate in adjustment, so it can stably undertake the functions of pixel voltage maintenance and basic feedthrough voltage fine adjustment, and help stabilize the electric field environment of the pixel unit 30. The first gate 11 and the second gate 12 are set for the first thin film transistor 31 of each pixel unit 30 to realize the reception of the row scanning signal. The first insulating layer 113 is fully covered and stacked on the surface of the first metal layer 112, with high insulation performance and dielectric stability. It can completely isolate the first metal layer 112 from the upper second metal layer 114, avoid short circuit leakage between the two metal structures, and ensure the safety and stability of the circuit operation. The array substrate 110 also has a multi-layer insulating structure with a second insulating layer 115 and a third insulating layer 116. The second insulating layer 115 has a larger overall thickness than conventional insulating layers, which has excellent planarization effect and can effectively reduce voltage fluctuations during the operation of the pixel electrode 1171, greatly enhancing the driving stability of the pixel electrode 1171. The second insulating layer 115 fully covers the surface of the second metal layer 114, and has high insulation performance and dielectric stability. The first insulating layer 113 and the second insulating layer 115 work together to achieve isolation between different metal layers and semiconductor structures, ensuring the stability of circuit operation.

[0038] The second metal layer 114 is the upper functional metal layer, integrating the drain 13, semiconductor layer 14, source 15, and control electrode 17 to form the complete conductive and switching structure of the first thin-film transistor 31. It also integrates the control electrode 17 structure to achieve circuit control function for dynamic capacitance adjustment. The second insulating layer 115 is stacked on top of the second metal layer 114 to further achieve electrical isolation, preventing signal interference and short circuits between the upper pixel electrode 1171 and the lower metal circuit. The third insulating layer 116 is stacked on the second insulating layer 115, and the pixel electrode layer 117 is fabricated on the surface of the third insulating layer 116, independently set for each pixel unit 30. It serves as the electrode structure for pixel electric field output, directly acting on the fluid layer 120 to achieve display driving. The fourth insulating layer 118 is the outermost insulating protective layer of the array substrate 110, fully covering the surface of the pixel electrode layer 117. It protects the internal circuit structure and optimizes the flatness of the substrate surface, improving the stability of fluid flow. Semiconductor layer 14, as the switching semiconductor structure of thin-film transistor, is a functional layer that realizes the switching of transistor on and off, ensuring the execution of pixel charging and shutdown actions.

[0039] The third insulating layer 116 has a through hole, and the pixel electrode 1171 extends through the through hole to be connected to the source electrode 15. When the source electrode 15 receives the gray level voltage, it transmits the gray level voltage to the pixel electrode 1171.

[0040] The first gate 11 is disposed opposite to the semiconductor layer 14 and together with the drain 13, the semiconductor layer 14 and the source 15, forms the switching structure of the first thin film transistor 31. The first gate 11 is used to receive the row scan signal and provide it to the first thin film transistor 31. The second gate 12 is disposed opposite to the source 15 to form a parasitic capacitance.

[0041] To achieve parasitic capacitance adjustment, a fluid channel 16 is formed in the first insulating layer 113 region between the source 15 and the second gate 12 of the first thin-film transistor 31. This fluid channel 16 is a functional structure for dynamic adjustment of the gate-source parasitic capacitance. The fluid channel 16 can communicate with the fluid medium of the fluid layer 120 or with other storage areas 18 storing the second fluid, allowing the conductive second fluid to freely enter, exit, and move. The control electrode 17 extends vertically through the first insulating layer 113 to the first metal layer 112, forming a positional correspondence with the fluid channel 16. The control electrode 17 can receive the target control voltage output by the external driving circuit in real time, and generate a driving electric field through the change of the target control voltage, driving the corresponding volume of the second fluid to move and change volume within the fluid channel 16.

[0042] The area occupied, filling height, and distribution volume of the second fluid in the fluid channel 16 directly change the dielectric composition between the second gate 12 and the source 15, thereby adjusting the parasitic capacitance parameters between the second gate 12 and the source 15 in real time. This structure dynamically adjusts the filling state in the fluid channel 16 by driving the second fluid with an electric field, transforming the traditional fixed gate-source parasitic capacitance into a variable capacitance structure that can be dynamically adjusted in real time. Furthermore, the magnitude of the target control voltage is related to the grayscale voltage of the pixel unit 30, and the parasitic capacitance value can be adjusted according to the real-time working state of the pixel, specifically offsetting the feedthrough voltage deviation under different pixels, different grayscale levels, and different working scenarios, effectively improving the uneven flicker problem of the electrowetting display panel 100. At the same time, the storage capacitance formed by the source 15 and the second common electrode layer 40 of the first metal layer 112 remains constant and does not participate in the adjustment, and can stably undertake the functions of pixel voltage maintenance and basic feedthrough voltage fine adjustment. It will not cause grayscale voltage shift problems due to the dynamic adjustment of parasitic capacitance, and will not interfere with the working state of the original storage capacitor of the pixel. It can effectively avoid secondary problems of grayscale voltage inaccuracy and greatly improve the accuracy and adaptability of flicker compensation.

[0043] like Figure 3 and Figure 4 As shown, Cd1 is the dielectric capacitance between the source electrode 15 and the fluid channel 16 interface, and Cd2 is the dielectric capacitance between the second gate electrode 12 and the fluid channel 16 interface. Cd2 has a large capacitance and its volume varies with the second fluid. C2d is the dielectric capacitance formed between the second gate electrode 12 and the source electrode 15, and its capacitance is variable. C0 is the total interface capacitance of the inactive regions. When the grayscale voltage is different, the target control voltage received by the control electrode 17 is different, and the second fluid in the fluid channel 16 changes accordingly. Therefore, the equivalent capacitance, i.e., the parasitic capacitance, between the source electrode 15 and the second gate electrode 12 changes as a sum of the three capacitances. Thus, by controlling the volume occupied by the second fluid in the fluid channel 16, a large capacitance change and compensation function for the parasitic capacitance can be achieved, thereby adjusting the feedthrough voltage deviation under different pixels, different grayscale levels, and different working scenarios, and improving the display effect of the electrowetting display panel 100.

[0044] The second fluid can be obtained from fluid layer 120 or from other fluid layers 120. In an optional embodiment, to avoid affecting the volume of the second fluid in fluid layer 120 or the display effect of electrowetting the display panel 100, in an optional embodiment, such as... Figure 5 As shown, the array substrate 110 is also provided with a storage area 18, which is used to store the second fluid, and the fluid channel 16 corresponding to each first thin film transistor 31 is connected to the storage area 18.

[0045] In this embodiment, the array substrate 110 of the electrowetting display panel 100 is further provided with a storage area 18. The storage area 18 is a reserved fluid-containing space, integrated inside the pixel circuit area of ​​the array substrate 110, without occupying additional external space of the panel, requiring no additional film layer structure or manufacturing process, and is compatible with existing panel mass production processes. The function of the storage area 18 is to store a sufficient amount of conductive second fluid, providing a stable fluid supply and reserve support for the fluid channel 16 of the pixel unit 30, ensuring the continuity and stability of fluid replenishment during dynamic capacitor adjustment.

[0046] Each first thin-film transistor 31 on the array substrate 110 corresponds to an independent fluid channel 16, which is connected to the storage region 18 through a flow channel. All fluid channels 16 share the same storage region 18 for fluid circulation and replenishment. During batch fabrication, the storage region 18 and the flow channels of each channel can be formed simultaneously through a single etching process, ensuring the smoothness of the fluid pathway and structural consistency. When the control electrode 17 applies a target control voltage to drive the second fluid in the fluid channel 16 to move, the fluid can flow freely bidirectionally between the storage region 18 and the fluid channel 16 according to the capacitance adjustment requirements.

[0047] In practical operation, when it is necessary to increase the gate-source parasitic capacitance parameter, the control electrode 17 outputs a corresponding target control voltage, driving the second fluid inside the storage area 18 to flow into the fluid channel 16, increasing the filling volume and coverage area of ​​the second fluid in the channel, changing the channel dielectric parameters, and increasing the parasitic capacitance value. When it is necessary to decrease the gate-source parasitic capacitance parameter, the voltage on the control electrode 17 is adjusted, driving the excess second fluid in the fluid channel 16 back to the storage area 18, reducing the fluid filling volume in the channel, and lowering the parasitic capacitance value. The setting of the storage area 18 ensures that the fluid channel 16 of each pixel can obtain sufficient fluid support, avoiding the problem of limited capacitance adjustment range caused by insufficient fluid storage in a single pixel, greatly widening the dynamic adjustment range of parasitic capacitance, and improving the ultimate performance of flicker compensation.

[0048] The unified storage area 18 design enables balanced allocation of fluid resources across all pixels, avoiding compensation accuracy deviations caused by differences in fluid reserves among different pixels. This further optimizes the consistency of feedthrough voltage across all pixels, improving the effect of non-uniform flicker from a structural perspective. This structure requires no additional fluid supply devices; fluid circulation scheduling can be achieved through the panel's built-in structure, without increasing the overall panel size or manufacturing cost, demonstrating strong process compatibility and practicality.

[0049] In an optional embodiment, a storage area 18 is formed inside the first substrate 131, and the fluid channels 16 corresponding to each pixel unit 30 are connected to the storage area 18 through the guide trenches. The target control voltage drives the second fluid to move between the fluid channels 16 and the storage area 18 through the guide trenches.

[0050] Furthermore, in order to improve the flow effect of the second fluid, prevent it from penetrating into the first insulating layer 113, and improve the adjustability of the parasitic capacitance, in an optional embodiment, such as Figure 6 As shown, a hydrophobic layer 19 is provided on the inner surface of the fluid channel 16. The hydrophobic layer 19 is uniformly formed by coating, deposition, or coating processes using a superhydrophobic insulating material. The film thickness is uniform and consistent, covering and adhering to the sidewalls and bottom walls of the fluid channel 16, with no exposed substrate areas. The hydrophobic layer 19 has good hydrophobic and insulating properties, as well as excellent flatness and wear resistance, and can maintain stable surface properties over a long period of time, meeting the long-term operating requirements of the panel.

[0051] The hydrophobic layer 19 significantly reduces the adhesion tension of the second fluid on the inner wall of the fluid channel 16, preventing fluid adhesion and residue. Under the electric field drive of the control electrode 17, the second fluid can achieve rapid and residue-free movement and switching within the fluid channel 16. The fluid response speed and position control accuracy are greatly improved, ensuring that the parameter adjustment of the parasitic capacitance between the gate and source can quickly match the working rhythm of pixel grayscale switching and line scan signal jumps, suppressing the compensation delay problem caused by fluid response lag, and ensuring the real-time performance of dynamic compensation.

[0052] Meanwhile, the uniform hydrophobic layer 19 enables the fluid to form a regular fluid interface within the channel, ensuring the consistency of the fluid filling pattern each time, improving the repeatability and stability of capacitor parameter adjustment, avoiding compensation errors caused by fluid pattern disorder, and further optimizing the uniformity of full-screen pixel flicker compensation.

[0053] The hydrophobic layer 19 structure can be completed simultaneously with the fabrication process of the first insulating layer 113 of the electrowetting display panel 100, without the need for additional complex process steps, and will not increase the difficulty of the fabrication process or the production cost. At the same time, it can significantly improve the working stability and response accuracy of the dynamic capacitance compensation structure, and is an important auxiliary structure for realizing high-precision adaptive flicker compensation.

[0054] Among them, such as Figure 7 and Figure 8 As shown, due to the special multiphase interface design of the fluid channel 16, the solid-liquid interface formed between the hydrophobic layer 19 and the fluid channel 16 generates a first dielectric capacitance Ci1 and a second dielectric capacitance Ci2. The first dielectric capacitance Ci1 and the second dielectric capacitance Ci2 have large and variable capacitances, enabling them to achieve large parasitic capacitance changes within a small pixel area, thus significantly improving the compensation range of parasitic capacitance.

[0055] When the grayscale voltage is different, the target control voltage received by the control electrode 17 is different, and the second fluid in the fluid channel 16 changes accordingly. As a result, the equivalent capacitance between the source electrode 15 and the second gate electrode 12, i.e. the parasitic capacitance, changes as a sum of the three capacitances. Thus, by controlling the amount of the second fluid in the fluid channel 16, a large capacitance change and compensation function of the parasitic capacitance can be achieved, thereby adjusting the feedthrough voltage deviation under different pixels, different grayscale levels, and different working scenarios, and improving the display effect of the electrowetting display panel 100.

[0056] The control electrode 17 may be a corresponding transmission electrode, such as in an optional embodiment. Figure 9 and Figure 10 As shown, the pixel unit 30 also includes a second thin-film transistor 32, and the control electrode 17 includes a first control electrode 171 and a second control electrode 172. The second thin-film transistor 32 of the pixel unit 30 in the i-th row is connected to the scan line 20 in the (i-1)-th row, the first control electrode 171 and the second control electrode 172, respectively. The first thin-film transistor 31 of the pixel unit 30 in the i-th row is connected to the scan line 20 in the i-th row. The first control electrode 171 is used to input the target control voltage. The second control electrode 172 extends through the first insulating layer 113 to the first metal layer 112. The second gate 12 is disposed adjacent to the extension of the second control electrode 172. The extension of the second control electrode 172 is arranged on the outer periphery of the source electrode 15, the fluid channel 16 and the second gate electrode 12. The orthogonal projection of the extension of the second control electrode 172 on the array substrate 110 covers the source electrode 15, the fluid channel 16 and the second gate electrode 12, where i is a positive integer and greater than 1.

[0057] In this embodiment, a row-linkage control driving logic is adopted. For the pixel units 30 arranged in the array, any row of pixels in the array is defined as the i-th row pixel unit 30, and the pixel unit 30 of the adjacent row above it is defined as the (i-1)-th row pixel unit 30. The second thin-film transistor 32 configured in the i-th row pixel unit 30 is a control switching device. Its circuit connection logic forms a staggered linkage design with the first thin-film transistor 31. The second thin-film transistor 32 is stably connected to the scan line 20 of the (i-1)-th row, the first control electrode 171, and the second control electrode 172, respectively. The on and off states of the second thin-film transistor 32 are controlled by the scan line 20 of the (i-1)-th row. The first thin-film transistor 31 of the i-th row pixel unit 30 is connected to the scan line 20 corresponding to the i-th row itself. The pixel display charging action is controlled by the scan signal of this row, realizing time-division and zone-independent control of display driving and capacitor compensation driving.

[0058] The first control electrode 171 serves as a voltage input port, receiving the target control voltage output from the external driving circuit. It is the transmission channel for the target control voltage and can transmit voltage parameters matching the current pixel compensation requirements. The second control electrode 172 adopts a vertically extending covering structure, vertically penetrating the first insulating layer 113 and extending to the first metal layer 112. The extension of the second control electrode 172 is arranged on the outer periphery of the source electrode 15, the fluid channel 16, and the second gate electrode 12. The extended electrode structure covers the peripheral area of ​​the source electrode 15, the fluid channel 16, and the second gate electrode 12 of the corresponding pixel. This allows the orthogonal projection of the extension of the second control electrode 172 onto the array substrate 110 to cover the source electrode 15, the fluid channel 16, and the second gate electrode 12. This can form a uniform and stable driving electric field in a local area of ​​the fluid channel 16. The electric field coverage range matches the fluid activity area of ​​the fluid channel 16, enabling the movement and shape change of the second fluid within the channel.

[0059] In the specific working logic, taking advantage of the fact that the switching response speed of thin-film transistors is much faster than the dynamic response speed of fluid, a pre-compensation control mechanism is adopted. In the frame period before the i-th row of pixels completes the display scan, the scan line 20 of the (i-1)-th row outputs a row enable signal, which turns on the second thin-film transistor 32 corresponding to the i-th row of pixels. This allows the target control voltage input to the first control electrode 171 to be transmitted to the second control electrode 172 through the second thin-film transistor 32, thus establishing a driving electric field in the fluid channel 16 region in advance. This drives the second fluid to complete the position and volume adjustment, and pre-adjusts the gate-source parasitic capacitance to the target compensation value.

[0060] When entering the scanning period of the i-th row of pixels in the current frame, the first thin-film transistor 31 is turned on in the scanning line 20 of this row, completing pixel charging and grayscale display. At this time, the fluid state in the fluid channel 16 has stabilized, and the parasitic capacitance between the gate and source has matched the operating parameters of the current pixel, which can offset the feedthrough voltage offset generated at the moment the row scanning signal is turned off, and suppress the compensation failure problem caused by the lag in capacitance adjustment. This staggered inter-row control structure realizes that the capacitance parameters of each pixel unit 30 can be independently adjusted, achieving pixel-level fine dynamic compensation and solving the technical problem that traditional global uniform compensation cannot adapt to single-pixel difference defects.

[0061] The first control electrode 171 and the second control electrode 172 are located in the second metal layer 114, and their relative positions can be set accordingly. In an optional embodiment, the second control electrode 172 is located between the source electrode 15 and the first control electrode 171. The second control electrode 172 adopts a centrally staggered arrangement structure inside the pixel unit 30, and its specific position is set in the area between the source electrode 15 and the first control electrode 171. This position layout has multiple advantages such as uniform electric field distribution, high driving efficiency, and low signal interference.

[0062] After the second control electrode 172 is positioned in this region, its distance from the source electrode 15, the fluid channel 16, and the second gate electrode 12 is equal. The output driving electric field can uniformly cover the entire fluid channel 16 region, avoiding problems such as unilateral fluid offset and uneven filling caused by electric field deviation. This ensures that the second fluid moves smoothly and regularly within the channel, improving the accuracy and stability of capacitor regulation. At the same time, this layout can minimize the signal transmission path from the first control electrode 171 to the second control electrode 172, reducing voltage signal transmission loss and delay, ensuring that the target control voltage can be quickly and completely applied to the second control electrode 172, and improving the response speed of capacitor regulation.

[0063] The first control electrode 171 can be independently set for each pixel unit 30 or uniformly set in rows. In an optional embodiment, such as... Figure 9 As shown, the first control electrode 171 of each column of pixel units 30 is connected and arranged in parallel with the data line 10; The first thin-film transistor 31 and the second thin-film transistor 32 are arranged diagonally opposite to the pixel electrode 1171.

[0064] In this embodiment, the first control electrode 171 corresponding to each column of pixel unit 30 in the array substrate 110 adopts a vertically connected integral molding design. The first control electrodes 171 of all pixel units 30 in the same column are connected in series and conduction. The overall wiring structure is arranged in parallel with the data line 10 in the same column. The wiring is neat and orderly, which can greatly simplify the circuit wiring structure, reduce the difficulty of circuit fabrication, and facilitate the driving circuit to realize column-level unified voltage input and control.

[0065] In the spatial layout of a single pixel unit 30, the first thin-film transistor 31 and the second thin-film transistor 32 are arranged diagonally and staggeredly, respectively located on opposite sides of the pixel electrode 1171. The diagonal layout structure can maximize the use of the limited space inside the pixel, avoid problems such as space congestion, film layer overlap interference, and circuit short-circuit risk caused by the stacking of two transistor structures, and at the same time achieve physical isolation between the display switching circuit and the compensation control circuit, suppressing signal interference between the two types of circuits during operation.

[0066] The combination of parallel wiring and diagonal arrangement design makes the circuit structure of the entire array substrate 110 highly regular, significantly improving the consistency of the pixel structure across the entire screen, effectively reducing process deviations during mass production, and improving panel yield. At the same time, the regular circuit layout can reduce the generation of non-target electrical parameters such as stray capacitance and parasitic resistance, further optimizing the stability of circuit operation, ensuring that the dynamic capacitance compensation accuracy of each pixel unit 30 remains consistent, and comprehensively improving the uniformity of flicker reduction across the entire screen.

[0067] The fluid channel 16 can adopt a symmetrical or asymmetrical structure. In an optional embodiment, such as... Figure 11 As shown, the fluid channel 16 includes a first end face 161 facing the control electrode 17 and a second end face 162 facing away from the control electrode 17. The area of ​​the second end face 162 of the fluid channel 16 is larger than the area of ​​the first end face 161 of the fluid channel 16. The second end face 162 is used to introduce a second fluid.

[0068] In this embodiment, the fluid channel 16 adopts an asymmetric variable cross-section structure design, which differs from the traditional constant cross-section straight-through channel structure, and can significantly improve the stability of fluid regulation and the range of capacitance adjustment. The fluid channel 16 is divided into two end faces along the fluid movement direction, namely a first end face 161 facing the control electrode 17 and a second end face 162 facing away from the control electrode 17. The cross-sectional dimensions of the two end faces are different, with the area of ​​the second end face 162 being larger than that of the first end face 161. The larger cross-section second end face 162 serves as the fluid inlet end, directly communicating with the guide groove of the storage area 18, and is responsible for introducing the second fluid into the channel.

[0069] The asymmetrical cross-sectional structure creates a left-high, right-low cross-sectional drop. During the fluid's entry and exit from the channel, capillary action and fluid surface tension can be used simultaneously to limit and stabilize the fluid. When the second fluid flows into the fluid channel 16 from the second end face 162, it automatically moves towards the first end face 161 under capillary action. At the same time, the area of ​​the second end face 162, which has a higher cross-sectional height, generates greater surface tension, forming a reverse limiting force. This allows the fluid to remain stably at the target position, avoiding problems such as excessive fluid movement and backflow turbulence. This significantly improves the locking accuracy of the fluid position, thereby enhancing the stability of the gate-source parasitic capacitance parameters and optimizing the accuracy of capacitance compensation.

[0070] Compared to a symmetrical fluid channel 16 with a uniform cross-section, this asymmetrical structure, under the same overall channel size and width, can effectively increase the contact area between the fluid and the inner wall of the channel. The size of the first dielectric capacitance Ci1 and the second dielectric capacitance Ci2 depends on the fluid contact area. When the fluid channel 16 adopts an asymmetrical cross-section structure, the formation range of the first dielectric capacitance Ci1 and the second dielectric capacitance Ci2 can be expanded, significantly improving the adjustable range and upper limit of the dynamic capacitance. At the same time, the asymmetrical structure has better fluid recovery performance. When the control voltage is removed or adjusted, the fluid can quickly return to its initial state, avoiding capacitance adjustment deviations caused by fluid residue and position shift, and ensuring the consistency and repeatability of capacitance compensation parameters during multiple grayscale switching processes.

[0071] The fluid channel 16 contains multiple adjustable capacitor structures, including a first dielectric capacitor Ci1 and a second dielectric capacitor Ci2 formed at the solid-liquid interface, first and second dielectric capacitors between the electrodes and the interface, and an air dielectric capacitor formed between the second gate 12 and the source electrode 15. It also includes a fixed interface capacitor in the inactive region as a reference capacitor. The coordinated adjustable nature of these multiple capacitors allows for a wide range of capacitor parameter adjustments within a very small pixel area, improving the dynamic adaptation capability of flicker compensation. This covers feedthrough voltage deviations across all grayscale levels, positions, and operating conditions, achieving full-domain flicker optimization. The asymmetric structure design of the multi-phase interface further expands the adjustable capacitor range, ensuring large capacitance adjustments can be achieved even with a small pixel structure.

[0072] Example 2 A second aspect of the present invention provides a display device, such as... Figure 12 As shown, the display device includes a driving circuit 200 for the display panel and an electrowetting display panel 100. The specific structure of the electrowetting display panel 100 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The driving circuit 200 for the display panel is connected to the electrowetting display panel 100.

[0073] In this embodiment, the display device is an integrated electrowetting display terminal, which includes an electrowetting display panel 100 and a display panel driving circuit 200. The electrowetting display panel 100 adopts the structure of the electrowetting display panel 100 disclosed in any of the above embodiments. The display panel driving circuit is connected to the electrowetting display panel 100 through flexible circuit board bonding, pin docking, etc., and provides the panel with all driving signals, control voltages, detection signal processing and data storage and calculation functions.

[0074] The display device, controlled by the driving circuit, can achieve all functions of the panel, including grayscale display driving, real-time pixel capacitance detection, dynamic parasitic capacitance adjustment, and closed-loop flicker compensation. It can be applied to various terminal products such as e-paper readers, smart electronic price tags, automotive auxiliary displays, flexible wearable displays, and industrial ultra-low power displays. The driving circuit can match the pixel array structure and circuit logic of the panel, outputting precise timing and stable amplitude line scanning signals, grayscale voltages, and target control voltages. Simultaneously, it collects real-time detection data of the pixel capacitance of the electrowetting display panel 100, completes data processing and parameter matching, ensuring stable, high-definition, and flicker-free operation of the electrowetting display panel 100.

[0075] In one optional embodiment, corresponding to the output mode of each signal, the driving circuit 200 of the display panel may include a source driving circuit 210, a gate driving circuit 220 and a voltage output circuit 230. The source driving circuit 210 is connected to the data line 10 of the electrowetting display panel 100 and is used to output grayscale voltage. The gate driving circuit 220 is connected to the scan line 20 of the electrowetting display panel 100 and is used to output line scanning signal. The voltage output circuit 230 is connected to the control electrode 17 and is used to output target control voltage.

[0076] The driving circuit 200 of the display panel may also include a timing controller 240, which is connected to the source driving circuit 210, the gate driving circuit 220 and the voltage output circuit 230 respectively, and controls each circuit to output signals of corresponding magnitude and timing.

[0077] Example 3 Furthermore, in order to achieve closed-loop regulation of parasitic capacitance, in an optional embodiment, such as Figure 13 As shown, the electrowetting display panel 100 includes a display area 101 and a non-display area 102. The array substrate 110 also includes a detection pixel 103, which is located in the non-display area 102. Figure 14 As shown, the first common electrode layer 132 corresponding to the detection pixel 103 includes a first common electrode 1321 and a second common electrode 1322. The first common electrode 1321 is used to input the common electrode voltage, the detection pixel 103 is used to input the test grayscale voltage, and the second common electrode 1322 is used to obtain the pixel capacitance between the detection pixel 103 and the first common electrode 1321. The display panel's driving circuit 200 is connected to the data line 10, scan line 20, detection pixel 103, second common electrode 1322, and control electrode 17. The display panel's driving circuit 200 is used for: During the testing period, test grayscale voltages of different sizes are output, and pixel capacitances of different sizes are obtained. A mapping table is established based on the test grayscale voltages and pixel capacitances. During the display period, the line scan signal and grayscale voltage are output to the scan line 20 and the data line 10 respectively to drive the pixel unit 30 to display, and the pixel capacitance size is determined based on the grayscale voltage and the mapping table, and the target control voltage of the control electrode 17 is determined based on the pixel capacitance size.

[0078] In this embodiment, the electrowetting display panel 100 is divided into two main areas with independent functions: a display area 101 and a non-display area 102. The display area 101 is the panel's image output area, filled with conventionally arranged pixel units 30, responsible for displaying images, text, and screens. The non-display area 102 is a reserved area at the edge of the panel, which does not participate in the screen display and is used to integrate and deploy functional auxiliary structures. The detection pixels 103 are independently set inside the non-display area 102, do not occupy the space of the display area 101, and will not have any impact on the panel resolution and display effect.

[0079] The lower substrate structure of the detection pixel 103 is completely consistent with the lower substrate structure of the conventional pixels in the display area 101, but the structure of the first common electrode layer 132 on the upper substrate is different. The first common electrode layer 132 corresponding to the position of the detection pixel 103 is split into two independent electrode structures, namely the first common electrode 1321 and the second common electrode 1322. The two electrodes are functionally independent and do not interfere with each other. The first common electrode 1321 continuously receives a stable common electrode voltage to provide a stable electric field reference for the detection pixel 103 and maintain the basic working state of the detection pixel 103. The detection pixel 103 can receive various test grayscale voltages output by the source driving circuit 210 to simulate the full grayscale display process of a conventional pixel. The second common electrode 1322 serves as a detection electrode and is responsible for real-time acquisition of the capacitance parameters between the detection pixel 103 and the first common electrode 1321, that is, the pixel capacitance values ​​corresponding to different grayscale voltages.

[0080] The driving circuit 200 of the display panel is simultaneously connected to the data line 10, scan line 20, detection pixel 103, second common electrode 1322, and control electrode 17 of the electrowetting display panel 100. It can coordinate the entire closed-loop operation of display driving, data detection, calculation matching, and compensation control. The overall working process is divided into two independent working stages: the testing period and the display period. Parameter calibration and screen display are completed in time and zone.

[0081] During the testing periods of equipment factory calibration, power-on self-test, or timed calibration, the timing controller 240 in the display panel's drive circuit 200 controls the source drive circuit 210 to continuously output test grayscale voltages of different amplitudes and levels to the detection pixel 103, enabling the detection pixel 103 to sequentially complete full-gradient grayscale display. In each stable grayscale display state, the second common electrode 1322 collects the pixel capacitance value at the corresponding grayscale in real time. The timing controller 240 records the test grayscale voltage parameters and the corresponding pixel capacitance parameters. After data sampling, processing, and matching, a complete mapping table corresponding one-to-one between grayscale voltage and pixel capacitance is established and stored in the storage module, providing data support for subsequent real-time compensation.

[0082] During the normal display period of the device, the timing controller 240 continuously outputs row scanning signals to each row scan line 20 of the electrowetting display panel 100 and outputs the corresponding grayscale voltage to each column data line 10 according to the preset display timing control gate drive circuit 220 and source drive circuit 210, thereby driving the pixel units 30 of the display area 101 row by row and column by column to complete the display. Simultaneously with the display driving, the timing controller 240 retrieves the stored mapping table in real time and quickly matches and queries the corresponding pixel capacitance value under this working state based on the grayscale voltage amplitude of the current pixel output.

[0083] The timing controller 240 combines the pixel capacitance value, the line scan delay parameter of the pixel unit 30, and the real-time working status of the panel to calculate the gate source parasitic capacitance compensation value required for the current pixel through a built-in algorithm. It further calculates the target control voltage that the control electrode 17 needs to output and controls the voltage output circuit 230 to output the matching target control voltage to the control electrode 17 of the corresponding pixel unit 30. This adjusts the filling volume and distribution state of the second fluid in the fluid channel 16, thereby realizing the dynamic adaptive adjustment of the gate source parasitic capacitance.

[0084] Through the detection and compensation mechanism, it can adapt to the dynamic fluctuation characteristics of pixel capacitance with grayscale changes. At the same time, it can be compatible with various abnormal working conditions that occur during the long-term use of the electrowetting display panel 100, such as thin film transistor characteristic drift, panel aging, parameter offset, etc. It can update and match the optimal compensation parameters in real time, forming a complete closed-loop adaptive system of detection, calculation, control, and compensation. This solves the technical defects of existing fixed compensation and preset compensation schemes that cannot adapt to dynamic working conditions, and maximizes the improvement of the uneven flicker problem of the electrowetting display panel 100.

[0085] The structures of the first common electrode 1321 and the second common electrode 1322 can be correspondingly configured, for example, using a strip shape or a square shape. In an optional embodiment, such as... Figure 15 As shown, the first common electrode 1321 and the second common electrode 1322 form an interdigitated structure. The conductive strips of the two electrodes interweave and are arranged at intervals, resulting in a regular and symmetrical overall structure with no overlapping or open circuits. The interdigitated structure maximizes the effective area of ​​the two electrodes facing each other, improving the accuracy and sensitivity of pixel capacitance detection. It can capture minute changes in pixel capacitance parameters, ensuring the accuracy of the grayscale voltage and pixel capacitance mapping table.

[0086] Meanwhile, the interdigitated electrode structure can achieve uniform electric field distribution, making the electric field distribution inside the detection pixel 103 highly consistent with the electric field distribution of the regular pixels in the display area 101. This ensures that the detected capacitance parameters can truly reflect the actual working parameters of the display pixels, suppressing detection errors and operating condition deviations, and matching the compensation parameters with the actual display conditions.

[0087] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An electrowetting display panel, characterized in that, The system includes an array substrate, a fluid layer, and a counter substrate stacked together, wherein the fluid layer includes a non-conductive first fluid and a conductive second fluid. The opposing substrate includes a first substrate and a first common electrode layer stacked on the side of the first substrate facing the array substrate; The array substrate is provided with a second common electrode layer, multiple rows of scan lines, multiple columns of data lines and an array of pixel units. The pixel unit includes a pixel electrode, a first thin film transistor and a control electrode. The first thin film transistor includes a drain, a semiconductor layer, a source, a first gate and a second gate. The first gate and the second gate are both connected to the same scan line. The drain is connected to one of the data lines and the source is connected to the pixel electrode. The array substrate includes a second substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a pixel electrode layer stacked together. The first gate, the second gate, and the second common electrode layer are located on the first metal layer. The drain, the semiconductor layer, the source, and the control electrode are located on the second metal layer. The pixel electrode is located on the pixel electrode layer. The first gate is disposed opposite to the semiconductor layer, and the second gate is disposed opposite to the source. The first insulating layer between the source and the second gate of each first thin-film transistor is further provided with a fluid channel. The control electrode extends through the first insulating layer to the first metal layer. The control electrode is used to receive a target control voltage and drive the second fluid of a target volume to move in the fluid channel to adjust the parasitic capacitance between the second gate and the source. The target control voltage is correlated with the grayscale voltage of the pixel unit.

2. The electrowetting display panel as described in claim 1, characterized in that, The array substrate is further provided with a storage area for storing the second fluid, and the fluid channel corresponding to each of the first thin-film transistors is connected to the storage area.

3. The electrowetting display panel as described in claim 1, characterized in that, The inner surface of the fluid channel is provided with a hydrophobic layer.

4. The electrowetting display panel as described in claim 1, characterized in that, The pixel unit further includes a second thin-film transistor, and the control electrode includes a first control electrode and a second control electrode; The second thin-film transistor of the pixel unit in the i-th row is connected to the scan line, the first control electrode and the second control electrode in the (i-1)-th row respectively. The first thin-film transistor of the pixel unit in the i-th row is connected to the scan line in the i-th row. The first control electrode is used to input the target control voltage. The second control electrode extends through the first insulating layer to the first metal layer. The second gate is disposed near the extension of the second control electrode. The extension of the second control electrode is arranged on the outer periphery of the source, the fluid channel and the second gate. The orthogonal projection of the extension of the second control electrode on the array substrate covers the source, the fluid channel and the second gate, where i is a positive integer and greater than 1.

5. The electrowetting display panel as described in claim 4, characterized in that, The second control electrode is located between the source electrode and the first control electrode.

6. The electrowetting display panel as described in claim 4, characterized in that, The first control electrode of each column of pixel units is connected and arranged in parallel with the data line; The first thin-film transistor and the second thin-film transistor are arranged diagonally relative to the pixel electrode.

7. The electrowetting display panel as described in any one of claims 1 to 6, characterized in that, The fluid channel includes a first end face facing the control electrode and a second end face facing away from the control electrode. The area of ​​the second end face of the fluid channel is larger than the area of ​​the first end face of the fluid channel. The second end face is used to introduce the second fluid.

8. A display device, characterized in that, The device includes a driving circuit for a display panel and an electrowetting display panel as described in any one of claims 1 to 7, wherein the driving circuit for the display panel is connected to the electrowetting display panel.

9. The display device as claimed in claim 8, characterized in that, The electrowetting display panel includes a display area and a non-display area. The array substrate also includes a detection pixel located in the non-display area. The first common electrode layer corresponding to the detection pixel includes a first common electrode and a second common electrode. The first common electrode is used to input a common electrode voltage, the detection pixel is used to input a test grayscale voltage, and the second common electrode is used to obtain the pixel capacitance between the detection pixel and the first common electrode. The driving circuit of the display panel is connected to the data line, the scan line, the detection pixel, the second common electrode, and the control electrode. The driving circuit of the display panel is used for: During the testing period, test grayscale voltages of different sizes are output, and pixel capacitances of different sizes are obtained. A mapping table is established based on the test grayscale voltages and the pixel capacitances. During the display period, a line scan signal and a grayscale voltage are output to the scan line and the data line respectively to drive the pixel unit to display. The pixel capacitance size is determined based on the grayscale voltage and the mapping table, and the target control voltage of the control electrode is determined based on the pixel capacitance size.

10. The display device as claimed in claim 9, characterized in that, The first common electrode and the second common electrode form an interdigitated structure.

Images