Method of manufacturing a silicon-based thermooptically activated function semiconductor device and related apparatus

Abstract

This application provides a method and related equipment for manufacturing a silicon-based thermo-optical activation function semiconductor device, including providing a silicon substrate; preparing a buried oxide layer on the surface of the silicon substrate; forming a top silicon layer on the surface of the buried oxide layer and patterning the top silicon layer to form a binary aperiodic topological structure of silicon and silicon dioxide; forming a thin-film heating electrode on the patterned top silicon surface, and connecting the thin-film heating electrode to a normalized driving voltage to make the output transmittance of the device exhibit a Sigmoid variation characteristic. This method can improve the accuracy of nonlinear mapping.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and related equipment for manufacturing a silicon-based thermo-optical activation function semiconductor device. Background Technology

[0002] Photonic neural networks hold promise for low-cost, high-performance artificial intelligence inference and high-speed optical signal processing. With the explosive growth in computing power demands for training and inference of large AI models, the computing power and energy consumption of data center GPU and TPU clusters have become key bottlenecks restricting overall system performance. Photonic neural networks utilize optical computing to perform matrix-vector multiplication operations in neural networks. Leveraging the GHz-level multiplexed bandwidth and near-zero static power consumption of on-chip integrated optical waveguides, they can significantly reduce the energy consumption of AI inference chips while supporting the intensive computing bandwidth requirements on the Tbps level.

[0003] Optical computation can only perform linear matrix multiplication. Activation units must be introduced to complete nonlinear mapping in order for the network to acquire deep learning feature fitting capabilities. However, the nonlinear implementation methods used in current photonic architectures suffer from insufficient accuracy in nonlinear mapping. Summary of the Invention

[0004] The main objective of this application is to propose a method and related equipment for manufacturing silicon-based thermo-optical activation function semiconductor devices to improve the accuracy of nonlinear mapping.

[0005] To achieve the above objectives, this application proposes a method for manufacturing a silicon-based thermo-optical activation function semiconductor device, including... Provide silicon substrates; A buried oxide layer is prepared on the surface of a silicon substrate; A top layer of silicon is deposited on the surface of the buried oxide layer, and the top layer of silicon is patterned to form a binary aperiodic topological structure of silicon and silicon dioxide. A thin-film heating electrode is formed on the patterned top silicon surface. The thin-film heating electrode is connected to a normalized driving voltage, so that the output transmittance of the device exhibits Sigmoid variation characteristics.

[0006] Optionally, in one embodiment, the topology optimization process for the binarized aperiodic topology of silicon and silicon dioxide includes: Using a four-parameter Sigmoid temperature-transmittance transfer function as the optimization target, the etching arrangement of the top silicon layer is continuously adjusted through iterative calculations to obtain a binarized aperiodic topology whose structural optical response converges to the target Sigmoid nonlinear characteristics.

[0007] Alternatively, in one embodiment, structural size smoothing constraints and progressive binary constraints are introduced during the iteration process of etching arrangement.

[0008] Optionally, in one embodiment, the thin-film heating electrode is disposed at the center of the binary aperiodic topology, and the material of the thin-film heating electrode is titanium nitride (TiN).

[0009] Optionally, in one embodiment, the thickness of the buried oxide layer is set to 2 μm.

[0010] Optionally, in one embodiment, the top silicon layer has a thickness of 220 nm, and the binarized aperiodic topology is set within a 6 μm × 6 μm topology optimization region.

[0011] Alternatively, in one embodiment, silicon dioxide is deposited on the surface of the semiconductor device to form an upper cladding layer.

[0012] This application also provides a semiconductor device, which is manufactured by the methods described above.

[0013] This application also provides a chip, which includes the semiconductor device provided in the foregoing.

[0014] This application also provides an electronic device, which includes the semiconductor device or the chip provided in the foregoing aspects.

[0015] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: A silicon-based optical waveguide substrate structure is formed by sequentially fabricating a buried oxide layer and a top silicon layer on a silicon substrate. A binary aperiodic topological configuration of alternating silicon and silicon dioxide is formed by patterning the top silicon layer. A thin-film heating electrode is then fabricated in the corresponding region of this topological structure. During the application of a normalized driving voltage to the thin-film heating electrode, the Joule heat generated by the electrode can continuously regulate the refractive index distribution of the top silicon layer, thereby changing the optical field interference and coupling transmission state inside the topological structure. This causes the transmitted light intensity of the device to exhibit a standard Sigmoid nonlinear evolution law as the driving voltage changes. The high-fit Sigmoid transmission response obtained by customized optimization of the topological configuration can improve the accuracy of nonlinear mapping. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of the manufacturing method of the silicon-based thermo-optical activation function semiconductor device provided in the embodiments of this application; Figure 2 This is a schematic diagram of the adjoint method topology optimization framework provided in the embodiments of this application; Figure 3 This is a schematic diagram of the random initial density field corresponding to the initial Bragg grating configuration provided in the embodiments of this application; Figure 4 This is a schematic diagram of the optimized binarized aperiodic topology provided in the embodiments of this application; Figure 5 This is a light field distribution diagram of the device provided in the embodiments of this application at two temperatures; Figure 6 This is a schematic diagram showing the fitting results of the normalized transmittance and the target Sigmoid curve obtained from the FDTD steady-state simulation provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0020] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0021] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] The following explains some terms used in the embodiments of this application: Topology optimization: using continuous density variables The distribution of materials is described in ∈[0,1]. The reverse design method is used to find the optimal binarized (Si and SiO2) structure through gradient descent algorithm iteration.

[0024] The adjoint method is an efficient numerical method for calculating the gradients of all parameters in the entire design domain with respect to the objective function using two electromagnetic field simulations (forward + adjoint). It is particularly suitable for the design of large-scale photonic devices that require global optimization, without the need for separate perturbation simulations for each design parameter.

[0025] Transverse Electric (TE): A guided mode in which the electric field direction is parallel to the upper surface of the chip (horizontal direction), such as using TE0 as the basic mode as the working mode.

[0026] Neural network activation function: A non-linear transformation function introduced into a neural network that determines the network's expressive power and training dynamics. Common activation functions include ReLU, Sigmoid, and Tanh.

[0027] Thermo-Optic Effect (TOE): A physical phenomenon in which the refractive index of a material changes with temperature; the thermo-optic coefficient of crystalline silicon. (e.g., 1.86×10) -4 K -1 ), approximately SiO2 ( For example, 1.0×10 -5 K -1 It is 18 times that of silicon, which is the physical basis for realizing silicon-based tunable photonic devices.

[0028] Heaviside projection maps a continuous gray-level density field to a function of a near-binary (0 / 1) distribution. The projection sharpness is determined by parameters. control.

[0029] Gaussian Spatial Filter: An operator that performs convolution filtering on a density field using a Gaussian kernel function, used to embed manufacturing constraints and ensure minimum feature size.

[0030] Minimum Feature Size (MFS): The smallest resolvable Si linewidth or air slot width in the topology.

[0031] With the ever-expanding computing power demands for large-scale AI model training and inference, existing GPU and TPU clusters in data centers are facing immense pressure to expand computing power and suffer from high overall energy consumption, becoming a key bottleneck restricting overall system performance improvement. Photonic neural networks, with their low cost and high performance, possess significant application potential in AI inference and high-speed optical signal processing. This architecture relies on optical computation to achieve matrix-vector multiplication at the core of the neural network. On-chip integrated optical waveguides provide GHz-level multiplexed bandwidth while exhibiting near-zero static power consumption, significantly reducing AI inference chip power consumption and meeting the Tbps-level high-density computing bandwidth requirements. Furthermore, photonic neural networks can be applied to various scenarios such as accelerating forward training of optical interconnects in data centers, edge AI inference, and signal processing at optical sensing front-ends.

[0032] The on-chip Mach-Zehnder interferometer mesh is the core hardware structure for matrix-vector multiplication in photonic neural networks. This structure is built from cascaded 2×2 multimode interferometric couplers, with phase modulation via a thermo-optical phase shifter, enabling arbitrary unitary matrix transformations. The related scheme has been prototyped and verified on a silicon photonic neural network chip. Compared to traditional electronic matrix multiplication units, the interferometer mesh is compatible with standard complementary metal-oxide-semiconductor (CMOS) fabrication processes, allowing for wafer-level batch testing. Matrix weight update reuse frequencies can reach GHz levels, and it offers significant advantages in static power consumption. Extensive academic research has been conducted in this area, and commercial prototypes have been launched. However, the lack of physical devices that can directly realize nonlinear activation functions in photonic systems has long been a major obstacle to improving the energy efficiency of photonic neural networks. The current common engineering approach is to first use a photoelectric detection circuit to convert the matrix multiplication output optical signal into an electrical signal, and then use a digital circuit to solve the activation function operations such as the Rectified Linear Unit (ReLU) and Sigmoid for each neuron. The power consumption of a single neuron activation stage can reach the milliwatt level. When the number of neurons in the chip reaches the million level, the total power consumption of the activation module will exceed the kilowatt level, which will significantly reduce the overall end-to-end energy efficiency of the photonic neural network.

[0033] To address the challenge of deviceizing activation functions in photonics, two main technical approaches have been proposed: one is based on designing parameterized thermo-optic switches using geometric parameters such as waveguide width, waveguide gap, and heating region length; the other utilizes germanium-antimony-tellurium (GST) phase change materials and electro-absorption modulators (EAMs) to construct nonlinear optoelectronic devices. However, both approaches require heterogeneous integration or additional thin-film deposition processes, making them incompatible with standard CMOS fabrication processes. Furthermore, the device transfer function is limited by the design freedom of structural parameters, making it difficult to accurately fit sigmoid activation curves. The topology optimization algorithm based on the adjoint method only requires two finite-difference time-domain (FDTD) iterations to solve for the gradients of all design parameters, demonstrating high optimization efficiency in the design of silicon photonic passive devices. However, most existing optimization strategies only take single optical indicators such as coupling efficiency and extinction ratio as optimization targets, and do not incorporate the temperature-transmittance activation transfer function adapted to the sigmoid type into the optimization constraints. Some designs also require the addition of a bottom metal reflector, which increases the complexity of the process flow.

[0034] Based on this, embodiments of this application provide a method for manufacturing a silicon-based thermo-optical activation function semiconductor device to solve the above-mentioned problems.

[0035] Please see Figure 1 The schematic diagram shown illustrates a process for manufacturing a silicon-based thermo-optical activated function semiconductor device, including: Step 101: Provide a silicon substrate.

[0036] Step 102: Prepare a buried oxide layer on the surface of a silicon substrate.

[0037] Step 103: Set a top layer of silicon on the surface of the buried oxide layer and pattern the top layer of silicon to form a binary aperiodic topological structure of silicon and silicon dioxide.

[0038] Step 104: Form a thin film heating electrode on the patterned top silicon surface. Connect the thin film heating electrode to a normalized driving voltage so that the output transmittance of the device exhibits Sigmoid variation characteristics.

[0039] In this embodiment, the silicon substrate can be a substrate wafer formed from single-crystal silicon material, serving as the carrier substrate for the semiconductor. On the pre-treated silicon substrate, a dense and uniformly thick silicon dioxide insulating layer, i.e., a buried oxide layer, is generated through ion implantation high-temperature annealing or a two-wafer bonding and separation process. This layer can isolate the bottom silicon substrate from the upper optical waveguide structure, prevent the light field from leaking downwards to the silicon substrate and causing losses, and simultaneously isolate the electrode heat from dissipating rapidly downwards, thus regulating the thermal field distribution.

[0040] The top silicon layer can refer to a single-crystal silicon thin film, which can be processed by photolithography and etching to form optical waveguides, resonant cavities, and photonic microstructures. Here, the optical field mode can be modulated by the top-layer silicon patterning. The top silicon layer is selectively removed by photolithography and dry etching to form an aperiodic groove structure. Subsequently, silicon dioxide is deposited to fill the grooves and the surface is planarized, so that the remaining silicon area and the silicon dioxide filling in the grooves are laterally alternating, forming a binary aperiodic topological structure of silicon and silicon dioxide.

[0041] Binarized aperiodic topology can refer to a binary representative structure that contains only two media (silicon and silicon dioxide). Aperiodic means that the unit arrangement does not have a periodic lattice arrangement rule. The topology relies on the arrangement of micro- and nano-pores / color blocks to control the interference, coupling, and resonance behavior of the light field, that is, it relies on the aperiodic topology to customize the intrinsic response of the light field transmission.

[0042] Thin-film heating electrodes can be metal thin-film resistive structures. After applying voltage, they rely on Joule heating to generate a temperature rise. They are commonly used electrothermal units for thermo-optical modulation and are often made of high-temperature resistant metals such as titanium, platinum, and nickel-chromium. They serve as heat sources to raise the temperature of the underlying topological silicon structure globally or locally, thereby changing the refractive index of the silicon material and achieving continuously adjustable light transmittance.

[0043] Normalized driving voltage refers to a voltage control strategy that maps the voltage amplitude to a fixed range (0~1 or 0~rated maximum value), eliminating driving deviations caused by individual device differences and facilitating the design of a unified control algorithm. Here, the input excitation can be standardized, and continuous voltage changes correspond to continuous temperature changes, thereby continuously modulating the transmittance.

[0044] The Sigmoid variation characteristic can be described as an S-shaped nonlinear function that exhibits a monotonically steep change at the center and tends to saturate at both ends. A thin-film resistive heating electrode is deposited and patterned on the surface of a fabricated silicon-based microstructure. An external driving circuit is connected to the electrode, inputting a normalized, continuously adjustable voltage. Joule heating of the electrode alters the refractive index of the top-layer silicon, modulating the optical interference and resonance state within the topological structure. Ultimately, the device's light output transmittance monotonically changes with the driving voltage, forming a Sigmoid nonlinear response that meets the requirements of neural networks, thus realizing the physical deviceization of the photon activation function.

[0045] The method for manufacturing a silicon-based thermo-optical activation function semiconductor device provided in this application involves sequentially fabricating a buried oxide layer and a top silicon layer on a silicon substrate to form a silicon-based optical waveguide substrate structure. A binary aperiodic topological configuration of alternating silicon and silicon dioxide is formed by patterning the top silicon layer. A thin-film heating electrode is then fabricated in the corresponding region of this topological structure. During the application of a normalized driving voltage to the thin-film heating electrode, the Joule heat generated by the electrode continuously modulates the refractive index distribution of the top silicon layer, thereby altering the optical field interference and coupling transmission state within the topological structure. This causes the transmitted light intensity of the device to exhibit a standard Sigmoid nonlinear evolution law as the driving voltage changes. The high-fit Sigmoid transmission response obtained through customized optimization of the topological configuration can improve the accuracy of the nonlinear mapping.

[0046] In one embodiment, the topology optimization process for the binary aperiodic topology of silicon and silicon dioxide includes: Using a four-parameter Sigmoid temperature-transmittance transfer function as the optimization target, the etching arrangement of the top silicon layer is continuously adjusted through iterative calculations to obtain a binarized aperiodic topology whose structural optical response converges to the target Sigmoid nonlinear characteristics.

[0047] In this implementation, the standard Sigmoid function has only two core adjustment parameters: upper and lower saturation amplitudes and midpoint steepness. The four-parameter Sigmoid adds baseline offset and amplitude scaling factor on this basis. The four-parameter Sigmoid temperature-transmittance transfer function is used as the preset target response curve for topology optimization, which specifies the transmittance variation law that the device must match under different heating temperatures.

[0048] The top silicon design region is selected as the topology optimization solution domain, and the binary distribution of silicon and silicon dioxide within the region is used as an adjustable design variable. In each iteration, the actual temperature-transmittance response corresponding to the current structure is first solved by finite-difference time-domain optical field simulation. The adjoint method is then used to quickly solve for the gradient information of all structural variables with respect to the fitting error, and the pixel distribution of the top silicon etching arrangement is finely adjusted along the gradient descent direction. The iterative cycle of optical field simulation, error calculation, gradient solution, and topology update is repeated to continuously reduce the fitting residual between the measured optical response of the device and the target sigmoid curve. When the overall error is lower than the preset convergence threshold and the structural arrangement no longer changes significantly, the optimization is considered to have converged, and the final output is a silicon / silicon dioxide binary aperiodic topology layout that meets the nonlinear matching accuracy.

[0049] Using a four-parameter sigmoid as the optimization target, it can flexibly adapt to the different requirements of different neural networks for activation function amplitude, bias, slope, and inflection point position, making it more adaptable. Compared with fixed-shape modulation structure, it has higher fitting accuracy. Moreover, it uses the top silicon etching morphology as the direct optimization variable, and the final output layout can be directly connected to photolithography fabrication without additional structural transformation, resulting in good design and process integration.

[0050] In one implementation, structural size smoothing constraints and progressive binary constraints are introduced during the iterative process of etching arrangement.

[0051] In this implementation, free iteration of topology optimization easily produces geometrically ill-conditioned features such as fragmented needle tips, extremely narrow bridges, isolated tiny pixels, and sharp, concave-convex corners. Size smoothing constraints are a type of regularization constraint that uses mathematical methods such as spatial filtering, gradient limiting, and minimum feature size limits to suppress drastic structural abrupt changes, constrain the minimum linewidth and minimum gap of the structure, and avoid ultra-fine morphologies that cannot be fabricated by the process. After each round of updating the top-layer silicon etching arrangement, spatial smoothing is performed on the silicon / silicon dioxide distribution within the design domain, forcibly constraining the minimum linewidth and minimum gap of silicon pillars and silicon dioxide trenches, avoiding nanoscale extremely narrow structures, breakpoints, and isolated island burrs that cannot be achieved by optimization-generated photolithography or dry etching.

[0052] Topology optimization often uses continuous density interpolation fields (0-1 continuous values ​​representing the proportions of the two media) in the initial stage. Directly forcing binary constraints can lead to optimization oscillations and difficulty in convergence. Asymptotic binary constraints are a step-by-step constraint strategy that gradually tightens the penalty coefficient with each iteration, slowly compressing the intermediate grayscale range, forcing the continuous density field to eventually approach only two extreme values: 0 (silicon dioxide) and 1 (silicon). In the early stages of optimization, intermediate virtual densities between silicon and silicon dioxide are allowed in the design domain, ensuring that the optimization seeks a wide range of values ​​and is not prone to getting trapped in local optima. As the number of iterations increases, the binary penalty weight is gradually increased, continuously compressing the proportion of intermediate transition states. In the later stages of iteration, the structure approaches a strict binary distribution, ultimately resulting in a standard binary topology layout with only silicon and backfilled silicon dioxide.

[0053] Smoothing constraints on structural dimensions avoid the generation of ultra-small feature sizes in optimization. The optimization results directly match the limits of photolithography and etching processes, eliminating the need for manual pattern reshaping in the later stages. At the same time, the smooth structure can reduce the severe scattering of local light fields, reduce the optical loss of devices, and improve the stability of transmission curve fitting. Compared with one-step forced binary strategies, progressive binary constraints result in smoother optimization convergence, are less prone to oscillations and falling into local optima, and have stronger global optimization capabilities.

[0054] In one embodiment, the thin-film heating electrode is disposed at the center of the binary aperiodic topology, and the material of the thin-film heating electrode is titanium nitride (TiN).

[0055] In this embodiment, titanium nitride is a high-melting-point, chemically stable conductive ceramic material with good resistivity, oxidation resistance, and thermal stability. The titanium nitride thin-film heating electrode is precisely fabricated at the planar geometric center of the binary aperiodic topological structure. When a driving voltage is applied to the electrode, Joule heating is generated as a whole. The heat diffuses uniformly from the center to the surrounding area, causing the temperature of the entire topological silicon structure to change synchronously. By utilizing the thermo-optic effect of silicon material, the interference and resonance state of the overall optical field are continuously modulated. Ultimately, the transmittance of the device exhibits a preset four-parameter Sigmoid variation law with the driving voltage, realizing an on-chip physical photon activation function.

[0056] With the electrodes centrally positioned, heat radiates outward from the center, resulting in a smoother and more uniform temperature gradient distribution across the entire topology. This avoids distortion of the transmission response caused by local overheating or underheating, improving the accuracy and repeatability of the Sigmoid curve fitting. Titanium nitride has strong thermal stability, making it less prone to oxidation and material phase transformation in high-temperature environments, and exhibiting minimal resistance drift during long-term operation.

[0057] In one embodiment, the thickness of the buried oxide layer is set to 2 μm.

[0058] In this embodiment, the refractive index of silicon is much greater than that of silicon dioxide. A thickness of 2μm is sufficient to completely confine the transmitted light field inside the top silicon waveguide region, preventing the evanescent field from penetrating the buried oxide layer and coupling into the bottom silicon substrate, thus avoiding radiation loss. This ensures the accuracy of the transmittance control of the topology and prevents the Sigmoid transmission curve from drifting and becoming distorted due to light loss. If the thickness is too small, significant light leakage is likely to occur; if the thickness is too large, material redundancy and an overall wafer thickness will be excessive. The thermal conductivity of silicon dioxide is much lower than that of single-crystal silicon. The 2μm buried oxide layer forms a moderately insulating buffer layer, which avoids the problem of rapid heat loss from the electrode to the substrate, high power consumption during heating, and decreased modulation sensitivity due to an excessively thin layer, while also preventing heat accumulation, temperature runaway, and excessively long thermal response relaxation time due to excessively thick insulation.

[0059] In one implementation, the top silicon layer has a thickness of 220 nm, and the binarized aperiodic topology is set within a 6 μm × 6 μm topology optimization region.

[0060] In this implementation, the topology optimization region can be the planar solution boundary range defined by the topology optimization algorithm. The algorithm only iteratively adjusts the silicon / silicon dioxide distribution within this rectangular region, while the structure outside the region remains fixed. This is used to limit the physical size of the device and constrain the optimization degrees of freedom. The planar boundary range of the binarized aperiodic topology can be a square region with a horizontal width of 6μm and a vertical width of 6μm. All silicon etching morphologies and backfill silicon oxide arrangements are constrained within this square window.

[0061] A 220nm top silicon thickness stably supports fundamental mode transmission, suppresses higher-order mode excitation, reduces mode dispersion and interference clutter, and ensures that the transmission response of the topology is determined solely by the structural arrangement, guaranteeing the accuracy of the four-parameter sigmoid curve fitting. The optical functional area of ​​a single active unit is only 6μm × 6μm, resulting in a small device footprint. This allows for large-scale array arrangement on photonic neural network chips, adapting to the high-density integration requirements of matrix multiplication arrays, significantly increasing on-chip neuron integration density, and meeting the wiring layout requirements of large-scale photonic neural networks.

[0062] In one embodiment, silicon dioxide is deposited on the surface of the semiconductor device to form an upper cladding layer.

[0063] In this embodiment, after the patterning of the titanium nitride thin film heating electrode is completed, a silicon dioxide thin film is grown over the entire surface of the semiconductor device using a vapor deposition process. This silicon dioxide layer constitutes the upper cladding of the optical waveguide structure. The buried oxide layer below serves as the lower cladding. The two layers of low-refractive-index silicon dioxide, together with the intermediate silicon-based topological core layer, form a complete horizontal optical field confinement structure, which together restricts the optical field to propagate within the silicon core layer. This significantly suppresses upward radiation leakage of the optical field, reduces transmission loss, and ensures a stable and controllable temperature-transmittance sigmoid modulation curve.

[0064] In one example, a schematic diagram of the adjoint method topology optimization framework can be found by referring to... Figure 2 As shown, the process includes an initial Bragg grating structure, an initial setup module, an optimization module, and an FDTD solver module. A bidirectional data exchange path is established between the optimization module and the FDTD solver module to achieve closed-loop computation for iterative updates of the structural morphology. The initial Bragg grating structure is set at the leftmost end of the process. This structure serves as the initial geometric configuration for the topology optimization iterative computation and is directly input into the initial setup module on the right at the start of the iteration, providing the initial substrate for the medium distribution.

[0065] The initial setup module completes the definition of device geometric boundaries, the construction of the physical model of thermo-optical materials, and the assignment of the initial dielectric field. It is called up again to update the global dielectric parameters before each round of FDTD optical field simulation calculation.

[0066] The design domain is a 6μm × 6μm planar region in the 220nm top silicon layer, discretized on a 20nm grid. (e.g., 90,000) independent density variables ∈[0,1], where =0 represents SiO2. =1 represents silicon. The TiN thin film heating electrode located at the center of the design domain is at a normalized driving voltage. Joule heating occurs under the influence of ∈[0,1], and silicon undergoes temperature field changes. The refractive index in the figure is calculated using the first-order approximation. , in =3.4757, =298.15K, =1.86×10⁻⁴K -1 The dielectric constant of each grid point within the design domain is determined by both the density variable ρ and the temperature-dependent dielectric constant. =1 when taking , =0 is taken The device uses the TE0 guided mode as input and normalizes the transmittance. As driving voltage The functions constitute the transfer characteristics of the device. That is... Figure 2 In the initial setup section, the refractive index at multiple temperatures is initialized as follows: .

[0067] The optimization module performs three-stage processing on the data output by the initial setup module, including three progressively iterative levels: grayscale stage, binarization stage, and process tolerance optimization stage. In the grayscale stage, the density variable is allowed to take continuous intermediate grayscale values ​​within the range of 0 to 1, and a large-scale global optimization is carried out to initially reduce the deviation between the simulated transmission characteristics and the target Sigmoid curve. In the binarization stage, progressive binary constraints are introduced to gradually compress intermediate grayscale components and promote the convergence of the density distribution towards silicon and silicon dioxide media, matching the process requirements of photolithography and etching binary structures. In the process tolerance optimization stage, structural size smoothing constraints are introduced to control the minimum linewidth and minimum gap of the structure, eliminate micro-distorted structures that cannot be fabricated by photolithography, and improve the adaptability of the layout to the fabrication process. After completing one round of density field update, the optimization module transmits the updated dielectric distribution to the FDTD solver module through a bidirectional data exchange path to carry out a new round of simulation calculations.

[0068] To incorporate the Sigmoid transfer function into the adjoint method objective function, the FDTD solver module can solve for the time-domain electromagnetic field distribution along... Uniform sampling ∈[0,1] =11 measurement points The objective function is defined as the mean square error between the simulated transmittance and the target Sigmoid curve at each measurement point. , .

[0069] in, =0.5795、 =-2.1873、 =0.9660、 =-0.0377 represents the target Sigmoid four parameters. The adjoint method employs two FDTD simulations at each measurement point, i.e., forward plus adjoint calculation. About all Gradient of each density variable The computational cost is independent of the number of design parameters N, making parallel optimization across the entire design domain possible. For example... Figure 2 The simulation operation used 11 evaluation temperatures Tk as 11 different dielectric constant environments for the same silicon material at different temperatures for optimization. The objective function for the multi-temperature average coupling efficiency is: , Its gradient is, .

[0070] The L-BFGS-B optimizer uses the adjoint gradient to drive the density field topological evolution, resulting in a non-periodic Si and SiO2 binarized patterns that normalize the transmittance. The mean square error of the target Sigmoid curve at M measurement points is minimized, thus enabling the physical Sigmoid activation function to be achieved without any auxiliary materials or bottom metal mirrors in the standard single-etch SOI process.

[0071] In one example, the TE0 guided mode enters the design domain through the input of a 220nm silicon waveguide. The TiN heating electrode is heated by the Joule heating effect under the action of the driving voltage V, and the refractive index of the silicon region is... =1.86×10 -4 K -1 The rate of scattering varies with temperature. The aperiodic Si and SiO2 patterns formed in the density field control the temperature-dependent refractive index distribution through scattering and interference modulation, ultimately resulting in a normalized transmittance at the output. It exhibits a sigmoid-shaped response with respect to V. In photonic neural network applications, the device achieves a four-parameter transfer function without any auxiliary material deposition or a bottom metal mirror using a standard 220nm SOI single-etch process. =0.5795, =-2.1873, =0.9660, =-0.0377、 =0.9980 and a physical sigmoid activation function with a difference of less than 0.3% from ReLU in MNIST classification accuracy.

[0072] In one example, the random initial density field corresponding to the initial Bragg grating configuration can be referenced. Figure 3 As shown, this represents the initial density assignment state. The color codes on the right indicate the range of dielectric constant values, with the red area corresponding to the dielectric constant of silicon. The blue area corresponds to the dielectric constant of silicon dioxide. The overall arrangement presents a periodic vertical stripe grating pattern. A uniform random perturbation with an amplitude of 0.2 is superimposed on a baseline of 0.5. , in It provides initial conditions for global topological exploration and breaks symmetric local extrema by using uniform random noise with an amplitude of 0.2.

[0073] A schematic diagram of the optimized binarized aperiodic topology output after iterative convergence can be found by referring to Figure 4 As shown, the black area represents the silicon-retained region (ρ=1), and the white area represents the silicon dioxide-backfilled region after etching (ρ=0). The structure no longer possesses the periodic grating arrangement characteristics, forming an aperiodic topology within the design domain.

[0074] The light field distribution diagrams of the device at the two temperatures can be referred to Figure 5 As shown, there are two sets of steady-state optical field simulation results, one at room temperature (T=298.15K) and the other at high temperature (T=723.15K). At room temperature, the optical field energy is concentrated in the resonant region in the middle of the topology, forming a local distribution of high-intensity optical field. When the temperature is raised to 723.15K, the silicon refractive index changes due to the first-order thermo-optic effect of silicon, the resonant condition of the topology shifts, the peak position of the optical field and the energy distribution are reconstructed synchronously, and the overall transmittance of the device changes accordingly. That is, the non-periodic topology can rely on the Joule heating of the TiN electrode to control the temperature field, realize the voltage-temperature-transmittance continuous nonlinear modulation, and match the target four-parameter Sigmoid transfer function.

[0075] During the optimization process, Heaviside projection is used to transform the continuous gray-level density field The mapping ∈ [0,1] is close to a binary distribution. .

[0076] in =0.5 is the projection threshold. Parameters used to control projection sharpness. When the value is 1, the projection function is close to linear, the density field maintains gray-level continuity, which is beneficial for the transmission of gradient information and global exploration of the structure. As the projection function gradually increases, it tends to become a step function, and the density variable is forced to converge to 0 or 1 to achieve structure binarization. When the gradient is too large, it tends to zero, causing optimization to stall. Therefore, a gradual scheduling strategy is adopted to increase the gradient in stages. Value. Optimization is carried out in three stages. The first stage is the grayscale exploration stage, focusing on Heaviside projection sharpness. With the density field fixed at 1 and maintaining a continuous gray-scale distribution, the L-BFGS-B optimizer, driven by a four-parameter sigmoid fitting objective function, updates the density variable through iterative gradient updates, performing approximately 200 iterations. This allows the structure to explore high sigmoid fitting regions under free topological degrees of freedom, forming a coarse-grained functional structure.

[0077] The second stage is the gradual binarization stage. The value is increased exponentially from 1 to 32 each time. After the update, L-BFGS-B was restarted and optimized for approximately 50 iterations, with the Heaviside projection function following... By gradually increasing the gray density towards the 0 and 1 ends, while continuously embedding the Gaussian space filter to ensure that the MFS is about 60nm, most of the density field variables eventually converge to a state close to pure Si or pure SiO2.

[0078] The third stage is the stage of refining process tolerance. With a fixed value of 64, approximately 100 final iterations are performed on the near-binary structure to eliminate manufacturing-infeasible features such as isolated gray pixels, outputting a fully binarized aperiodic topology structure requiring no post-processing. Manufacturing constraints are embedded using a 30nm radius Gaussian space filter throughout the process, corresponding to a minimum feature size of 60nm. The final result achieves normalized transmittance of the TE0 guided mode at 1550nm. High-precision matching with the target Sigmoid curve.

[0079] Figure 6 This paper presents the fitting results of the normalized transmittance obtained from FDTD steady-state simulation with the target Sigmoid curve, and verifies the performance of the obtained activation function on a standard machine learning benchmark dataset for neural network tasks. Specifically, it shows the curve of the device's normalized transmittance as a function of temperature and its fitting comparison curve with the target Sigmoid function; the horizontal axis represents temperature in degrees Celsius (°C), ranging from approximately 0 to 450°C; the vertical axis represents normalized transmittance, ranging from 0 to 1. 1-fom1(data) is the actual normalized transmittance simulation data obtained from steady-state electromagnetic simulation; Sigmoid fit (R²=0.998) is the fitting curve obtained by fitting the four-parameter Sigmoid function to all the above simulation data using the Levenberg-Marquardt nonlinear least squares method. 21 measurement points are uniformly sampled in [0,1], each... Lumerical FDTD steady-state simulation was performed to record the normalized transmittance. The simulation sequence was fitted with a four-parameter Sigmoid function using the Levenberg-Marquardt nonlinear least squares method to obtain the fitting parameters. =0.5795, =-2.1873, =0.9660, =-0.0377, goodness of fit =0.9980. On the standard 220nm SOI platform, the dynamic range of the obtained activation function is -0.0377 to 0.9283, which highly corresponds to the standard Sigmoid function. The activation function was integrated into a fully connected multilayer perceptron, and its image classification performance was compared with that of four standard activation functions (ReLU, Sigmoid, Tanh, and Linear) on the MNIST standard machine learning benchmark dataset. The results show that the proposed physical Sigmoid activation function achieves classification accuracy of 97.8% and 98.0% respectively on MNIST, with a difference of less than 0.3%, demonstrating that the proposed physical Sigmoid activation function has comparable engineering feasibility to the standard ReLU in classification tasks.

[0080] This application also provides a semiconductor device, which is prepared by the method provided in any of the foregoing embodiments.

[0081] This application also provides a chip that includes the semiconductor device provided in the above embodiments.

[0082] This application also provides an electronic device, which includes the semiconductor device or the chip provided in the above embodiments.

[0083] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

Claims

1. A method for manufacturing a silicon-based thermo-optical activation function semiconductor device, characterized in that, include: Provide silicon substrates; A buried oxide layer is prepared on the surface of the silicon substrate; A top silicon layer is formed on the surface of the buried oxide layer, and the top silicon layer is patterned to form a binary aperiodic topological structure of silicon and silicon dioxide. A thin-film heating electrode is formed on the patterned top silicon surface. The thin-film heating electrode is connected to a normalized driving voltage, so that the output transmittance of the device exhibits Sigmoid variation characteristics.

2. The method according to claim 1, characterized in that, The topology optimization process for the binary aperiodic topology structure of silicon and silicon dioxide includes: Using a four-parameter Sigmoid temperature-transmittance transfer function as the optimization target, the etching arrangement of the top silicon layer is continuously adjusted through iterative calculations to obtain a binarized aperiodic topology whose structural optical response converges to the target Sigmoid nonlinear characteristics.

3. The method according to claim 2, characterized in that, The iterative process of the etching arrangement is to introduce structural size smoothing constraints and progressive binary constraints.

4. The method according to claim 1, characterized in that, The thin-film heating electrode is located at the center of the binary aperiodic topology, and the material of the thin-film heating electrode is titanium nitride (TiN).

5. The method according to claim 1, characterized in that, The thickness of the buried oxide layer is set to 2 μm.

6. The method according to claim 1, characterized in that, The top silicon layer has a thickness of 220 nm, and the binarized aperiodic topology is set within a 6 μm × 6 μm topology optimization region.

7. The method according to claim 1, characterized in that, The surface of the semiconductor device is deposited with silicon dioxide to form an upper cladding layer.

8. A semiconductor device, characterized in that, The semiconductor device is prepared by the method described in any one of claims 1 to 7.

9. A chip, characterized in that, The chip includes the semiconductor device of claim 8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 8 or the chip of claim 9.

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