Wafer test jump method and system

Abstract

This invention relates to the field of electronic digital data processing technology and can be applied to wafer mass production testing scenarios for integrated circuits, silicon photonics chips, and other optoelectronic integrated chips. In particular, it relates to a wafer testing skip-test method and system. The method includes: mapping process parameter data, functional unit test data, and spatial feature data to each die of the wafer under test, obtaining the process parameter offset, functional parameter offset, and spatial feature parameter offset for each die; determining the comprehensive risk value and risk level of each die; and controlling the testing equipment to perform differentiated skip-test actions on each die according to the testing strategy corresponding to the risk level of each die. This invention can achieve differentiated test configuration based on die-level risk differences, accurately matching specific risk types with testing resources, enabling the skipping of unnecessary test items for low-risk dies from the source, and fully utilizing various existing data from the wafer manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology and can be applied to wafer mass production testing scenarios for integrated circuits, silicon photonics chips and other optoelectronic integrated chips. Typical applications include wafer probe testing of products such as silicon photonics transceiver chips, optical switch matrices, and optical computing chips. In particular, it relates to a wafer testing skip test method and system. Background Technology

[0002] As semiconductor manufacturing processes evolve towards advanced nodes, the integration density of individual chips continues to increase. The number of test items in wafer probe testing can reach thousands, and the proportion of testing time in chip manufacturing costs is rising year by year. Reducing testing time and lowering testing costs are core optimization directions in the mass production stage.

[0003] In related technologies, the current mainstream solutions for improving testing efficiency and quality control in wafer probe testing can be mainly divided into two categories: The first category is adaptive testing technology, which uses the reticle unit as the smallest decision granularity. During the testing process, the functional yield of the tested dies is calculated while testing. When the yield confidence reaches a preset threshold, the testing of the remaining dies in that unit is terminated in advance. The solutions of mainstream testing equipment manufacturers have integrated process control monitoring modules (PCM) to assist in dynamically adjusting the test content with process data. However, it is still essentially a reticle-level decision within the testing process. A certain proportion of dies must be tested before a judgment can be triggered, which always results in redundancy in the pre-testing and a natural ceiling on efficiency improvement. The second category is static quality screening rules, such as Part Average Test (PAT) and Good Die in Bad Neighborhood (GDBN) rules. These methods, after the entire testing cycle is completed, offline labeling and removal of high-risk dies based on test results and spatial distribution characteristics. This is a post-test quality control measure, used only to ensure shipment quality, and does not participate in the scheduling and optimization of the testing process, thus failing to reduce testing time. The "good product bad neighborhood rule" is a die quality screening rule based on the density of defects in a spatial neighborhood. The "part average test" is a die quality screening rule based on statistical distribution.

[0004] Current solutions for improving test efficiency and quality control in wafer probe testing cannot directly skip unnecessary tests on low-risk dies at the source, resulting in persistent redundancy in pre-testing and an upper limit to the time reduction ratio. These solutions typically only utilize existing data from the wafer manufacturing process for post-process analysis, batch-level control, or finished product screening, without integrating it into the pre-test scheduling stage, thus failing to fully utilize existing data from the wafer manufacturing process. Furthermore, when skipping tests or early stopping, these solutions often employ a uniform strategy on a reticle or wafer basis, failing to differentiate test configurations based on die-level risk differences. This easily leads to problems such as "redundant testing of low-risk dies and insufficient testing coverage of high-risk dies," resulting in limited accuracy in balancing efficiency and quality. In related technologies, there is a lack of clear directional mapping logic between process parameters, yield data and test item configuration in the test efficiency improvement and quality control solutions for wafer probe testing. Most of them are general-purpose full-item additional tests or full-item early stop, which cannot accurately match test resources according to specific risk types. Test redundancy and quality risk cannot achieve optimal balance. Summary of the Invention

[0005] This invention provides a wafer testing skipping method and system to address the problems in related technologies regarding test efficiency improvement and quality control schemes for wafer probe testing. These schemes cannot directly skip unnecessary test items for low-risk dies from the source, cannot fully utilize various existing data from the wafer manufacturing process, cannot achieve differentiated test configurations for die-level risk differences, and cannot accurately match test resources according to specific risk types.

[0006] According to one aspect of the present invention, a wafer testing skipping method is provided, comprising: The process parameter data, functional unit test data, and spatial feature data of the wafer under test are acquired. The process parameter data, functional unit test data, and spatial feature data are mapped to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset of each grain. Based on the offsets of process parameters, functional parameters, and spatial characteristic parameters of each grain, the comprehensive risk value and risk level of each grain are determined. Based on the testing strategy corresponding to the risk level of each die, control the testing equipment to perform differentiated skip testing actions on each die.

[0007] According to another aspect of the present invention, a wafer test skipping system is provided, comprising: a data access unit, a risk pre-classification unit, and a test scheduling and execution unit; The data access unit is used to acquire process parameter data, functional unit test data and spatial feature data of the wafer under test, and map the process parameter data, the functional unit test data and the spatial feature data to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset and spatial feature parameter offset of each grain. The risk pre-classification unit is used to determine the comprehensive risk value and risk level of each grain based on the process parameter offset, functional parameter offset and spatial characteristic parameter offset of each grain. The test scheduling and execution unit is used to control the test equipment to perform differentiated skip test actions on each die according to the test strategy corresponding to the risk level of each die. The data access unit, the risk pre-classification unit, and the test scheduling execution unit operate on computer storage media or industrial servers.

[0008] The technical solution of this invention involves acquiring process parameter data, functional unit test data, and spatial feature data of the wafer under test before the start of the test. This data is then mapped to each die of the wafer under test, resulting in the process parameter offset, functional parameter offset, and spatial feature parameter offset for each die. Based on these offsets, the comprehensive risk value and risk level of each die are determined. During the wafer under test, the testing equipment is controlled to perform differentiated skip test actions on each die according to the test strategy corresponding to its risk level. The technical solution of this invention addresses the problems in related technologies regarding test efficiency improvement and quality control schemes for wafer probe testing. These problems include the inability to directly skip unnecessary test items for low-risk dies from the source, the inability to fully utilize existing data from the wafer manufacturing process, the inability to implement differentiated test configurations based on die-level risk differences, and the inability to accurately match test resources according to specific risk types. The solution integrates wafer process parameter data, functional unit test data, and spatial characteristic data before the formal start of wafer testing to perform risk pre-classification at the single die level, determining the risk level of each die. Then, during wafer testing, based on the test strategy corresponding to the risk level of each die, the testing equipment is controlled to perform differentiated skip test actions on each die. This achieves differentiated test configuration based on die-level risk differences, accurately matches specific risk types with test resources, and enables skipping unnecessary test items for low-risk dies from the source, fully utilizing existing data from the wafer manufacturing process.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a wafer testing skipping method provided in Embodiment 1 of the present invention.

[0012] Figure 2 This is a schematic diagram of a wafer testing skipping system provided in Embodiment 2 of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "target," "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] Example 1 Figure 1This is a flowchart illustrating a wafer testing skipping method provided in Embodiment 1 of the present invention. This embodiment is applicable to wafer probe testing. Skipping tests refers to a scheduling optimization technique that directly skips some or all test items of a specified die in the test scheduling, thereby reducing the overall test time. This method can be executed by a wafer testing skipping system, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes: Step 101: Obtain the process parameter data, functional unit test data, and spatial feature data of the wafer under test. Map the process parameter data, functional unit test data, and spatial feature data to each die of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset of each die.

[0016] Optionally, the wafer testing skipping method of this embodiment of the invention operates on a single wafer cycle. The wafer under test can be a wafer that currently requires wafer probe testing. A wafer is a circular silicon wafer used in semiconductor manufacturing, which is formed into a large number of dies through processes such as photolithography and etching, and serves as the carrier for wafer probe testing. A die is an independent chip functional unit on the wafer, and is the basic object of wafer probe testing. After being diced and packaged, it becomes a finished chip. Wafer probe testing is an electrical performance test performed on undicated dies on a wafer in semiconductor manufacturing. Step 101 is completed before the wafer under test is started, and does not occupy the machine testing time.

[0017] Optionally, process parameter data, functional unit test data, and spatial characteristic data of the wafer under test can be acquired before the test begins. Process parameter data refers to the PCM process parameter data of the wafer under test, which are the measured values ​​of the core process parameters at the PCM test points on the wafer scribe line. The measured values ​​of the core process parameters can be one of the following: sheet resistance, threshold voltage, static leakage current, contact resistance, and breakdown voltage. The die process parameter offset can refer to the die-related value in the PCM process parameter data. Functional unit test data refers to the building block (BB) functional unit test data of the wafer under test, which are the test results of the BB. The die functional parameter offset can refer to the die-related value in the BB functional unit test data. Spatial characteristic data refers to the spatial characteristic data of defects in the die neighborhood of the wafer under test, which is data that can be used to characterize the spatial distribution of defective dies on the wafer under test. The spatial characteristic parameter offset of a die can refer to the spatial risk characteristics of the die within a preset neighborhood range, calculated based on the spatial characteristic data of the die's neighborhood defects on the tested wafer. PCM process parameter data, BB functional unit test data, and die neighborhood defect spatial characteristic data are all existing data from the wafer manufacturing process. The process monitoring functional unit is a basic functional test structure embedded in the wafer or scribe line, used to verify circuit-level functional performance. The process control and monitoring module is a test structure deployed on the wafer scribe line, used to monitor process parameter fluctuations.

[0018] Optionally, the process parameter data includes at least one of sheet resistance, threshold voltage, static leakage current, and waveguide transmission loss; the functional unit test data includes at least one of on-chip monitoring ring insertion loss, photoelectric responsivity, extinction ratio, heater resistance, half-wave power, open / short circuit test value, and memory cell erase / write performance.

[0019] heater resistance ( ) is the DC ohmic resistance of the heating unit of the thermo-optical phase shifter, which characterizes the electric drive characteristics.

[0020] Half-wave power ( This refers to the process by which the two arms of the Mach-Zehnder interferometer (MZI) generate... The heater drive power required for the radian phase difference is a key indicator characterizing the energy consumption of the thermo-optical phase shifter.

[0021] Optionally, mapping the process parameter data, the functional unit test data, and the spatial feature data to each die of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset of each die includes: mapping the process parameter data to each die of the wafer under test using a spatial interpolation method to obtain the process parameter offset of each die; mapping the functional unit test data to each die of the wafer under test according to spatial attribution rules or nearest neighbor principles to obtain the functional parameter offset of each die; and determining the spatial risk characteristics of each die of the wafer under test within a preset neighborhood range based on the spatial feature data to obtain the spatial feature parameter offset of each die.

[0022] Optionally, spatial interpolation can be performed based on process parameter data to map the process parameter data to each functional die, obtaining the process parameter offset for each die. Mapping the process parameter data to each die of the wafer under test using spatial interpolation methods to obtain the process parameter offset for each die includes: when the test point density is less than a preset density threshold, mapping the process parameter data to each die of the wafer under test using a first spatial interpolation method to obtain the process parameter offset for each die; when the test point density is greater than or equal to the preset density threshold, mapping the process parameter data to each die of the wafer under test using a second spatial interpolation method to obtain the process parameter offset for each die. The test point density can refer to the density of PCM test points on the wafer scribe line of the wafer under test. The preset density threshold can be a pre-set value. The first spatial interpolation method can be Kriging interpolation, and the second spatial interpolation method can be inverse distance weighted interpolation. When the test point density is less than a preset density threshold, a first spatial interpolation method maps the process parameter data to each grain of the wafer under test, obtaining the process parameter offset for each grain. This method can adapt to the spatial correlation of process parameters, balancing spatial correlation and interpolation accuracy. When the test point density is greater than or equal to the preset density threshold, a second spatial interpolation method maps the process parameter data to each grain of the wafer under test, obtaining the process parameter offset for each grain. This method can reduce computational overhead when the test point density is high. The inverse distance weighted interpolation method is a spatial interpolation method based on inverse distance weighting. It has simple calculation logic, low computational overhead, and is suitable for scenarios with high test point density. The Kriging interpolation method is a geostatistical interpolation method based on spatial correlation. It can fully utilize the spatial continuity characteristics of process parameters, and its mapping accuracy is better than that of the inverse distance weighted interpolation method.

[0023] Optionally, if the BB is embedded within the reticle, the functional unit test data can be mapped to each die of the wafer under test according to spatial affiliation rules, obtaining the functional parameter offset of each die. If the BB is centrally deployed in the trace, the functional unit test data can be mapped to the dies within the surrounding range (usually taking the radius) according to the nearest neighbor principle. (BBB cells within the range) to obtain the functional parameter offset of each grain.

[0024] Optionally, the spatial distribution pattern of defective grains in historical production batches of the same product can be determined based on spatial feature data. Then, based on this pattern, spatial risk characteristics such as historical defect density or edge region defect probability within a preset neighborhood of a single grain can be calculated, centered on the grain. This yields the spatial feature parameter offset for each grain. The grain's spatial feature parameter offset corresponds to the risk assessment logic of GDBN.

[0025] Step 102: Determine the comprehensive risk value and risk level of each grain based on the offset of process parameters, functional parameters, and spatial characteristic parameters of each grain.

[0026] Optionally, the overall risk value of a die can be a numerical value used to assess the reliability risk of the die. A higher overall risk value indicates a higher reliability risk, while a lower overall risk value indicates a lower reliability risk. The risk level of each die can be a classification based on its overall risk value. The risk level of each die is used to guide differentiated skip testing actions for each die. Each die's risk level is one of low, medium, or high risk.

[0027] Optionally, based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each grain, the comprehensive risk value and risk level of each grain are determined, including: determining the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each grain; determining the comprehensive risk value of each grain based on the comprehensive risk value calculation formula, the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain; and determining the risk level of each grain based on the preset risk threshold and the comprehensive risk value of each grain.

[0028] Optionally, the process parameter risk score of the die can be a numerical value used to assess the reliability risk of the die from the perspective of process parameters. The functional parameter risk score of the die can be a numerical value used to assess the reliability risk of the die from the perspective of functional parameters. The spatial characteristic parameter risk score of the die can be a numerical value used to assess the reliability risk of the die from the perspective of spatial characteristic parameters.

[0029] Optionally, based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each grain, the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain are determined, including: determining the process parameter risk score of each grain based on the nominal value and historical statistical value corresponding to the process parameter offset and the process parameter offset of each grain; determining the functional parameter risk score of each grain based on the nominal value and historical statistical value corresponding to the functional parameter offset and the functional parameter offset of each grain; and performing linear normalization on the spatial characteristic parameter offset of each grain to map the spatial characteristic parameter offset of each grain to a preset numerical range to obtain the spatial characteristic parameter risk score of each grain.

[0030] Optionally, for each of the process parameter offsets and functional parameter offsets, the nominal value can be a pre-set standard value for the offset. The historical statistical value can be the standard deviation of all statistically recorded offsets, a statistic characterizing the dispersion of the offsets. The risk score for the grain corresponding to the offset can be determined using the following formula, based on the nominal value, historical statistical value, and grain offset: ; ;in, This represents the offset of the grain. The nominal value corresponding to the offset. These are the historical statistical values ​​corresponding to the offset. Risk score for the grain corresponding to the offset. The numerical range is 0 (The determined grain offset and the corresponding nominal value are consistent) corresponds to 0 points (no risk), 3 (Reaching the process control red line) corresponds to 100 points (full risk), deviation exceeding 3 The time score is capped at 100 points. When the grain offset exceeds 3... When the preset multiple (such as 2 times) is used, the risk level of the crystal is directly determined to be high risk, and it will no longer participate in the weighted calculation of the comprehensive risk value, so as to improve the processing efficiency and reliability in extreme abnormal scenarios.

[0031] Optionally, for the spatial feature parameter offset of each grain, the spatial feature parameter offset can be linearly normalized, mapping the spatial feature parameter offset of each grain to a preset numerical range. The linearly normalized spatial feature parameter offset is then determined as the spatial feature parameter risk score of the grain. The preset numerical range can be... Specifically, the spatial characteristic parameter offset of the grain can be normalized and mapped based on the historical defect density in the neighborhood. The historical normal level corresponds to 0 points, the control red line density corresponds to 100 points, and the limit is capped when it exceeds the limit.

[0032] Optionally, based on the comprehensive risk value calculation formula, the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain, the comprehensive risk value of each grain is determined, including: performing the following operation for each grain: using the following comprehensive risk value calculation formula, based on the grain's process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score, the comprehensive risk value of the grain is determined: ; This represents the overall risk value of the grain. Risk score for the process parameters of the grain. Risk score for the functional parameters of the grain. Risk score for the spatial characteristic parameters of the grain. , , These are pre-set weighting coefficients corresponding to the offsets of process parameters, functional parameters, and spatial characteristic parameters, satisfying... . The numerical range is The comprehensive risk value calculation formula can be a pre-set weighted summation formula used to calculate the comprehensive risk value of a die based on the risk scores of its process parameters, functional parameters, and spatial characteristic parameters. For example, in the initial stage, the weighting coefficients in the comprehensive risk value calculation formula are calibrated by process and testing experts based on product type experience; a typical initial reference value for consumer-grade products is... , , For industrial-grade or automotive-grade products, the weighting of process parameter risk scores and spatial characteristic parameter risk scores can be appropriately increased.

[0033] Optionally, the preset risk threshold includes a low-risk threshold and a high-risk threshold; the risk level of each grain is determined based on the preset risk threshold and the comprehensive risk value of each grain, including: performing the following operations for each grain: if the comprehensive risk value of the grain is less than or equal to the low-risk threshold, the risk level of the grain is determined to be low-risk; if the comprehensive risk value of the grain is greater than the low-risk threshold and less than or equal to the high-risk threshold, the risk level of the grain is determined to be medium-risk; if the comprehensive risk value of the grain is greater than the high-risk threshold, the risk level of the grain is determined to be high-risk.

[0034] Optionally, preset risk thresholds include a low-risk threshold and a high-risk threshold. The low-risk threshold and high-risk threshold can be two pre-set values ​​used to classify all dies into three consecutive, non-overlapping risk levels. The low-risk threshold is lower than the high-risk threshold. If the overall risk value of a die is less than or equal to the low-risk threshold, the die's risk level is determined to be low-risk. If the overall risk value of a die is greater than the low-risk threshold but less than or equal to the high-risk threshold, the die's risk level is determined to be medium-risk. If the overall risk value of a die is greater than the high-risk threshold, the die's risk level is determined to be high-risk. The low-risk threshold and high-risk threshold are typically calibrated based on the product grade (consumer / industrial / automotive grade) of the wafer being tested, the acceptable defective parts per million (DPPM) target, and historical yield levels. The initial values ​​of the low-risk threshold and high-risk threshold can be jointly determined by process and testing experts and can be continuously optimized through batch iterations. The defective parts per million (DPPM) is a core indicator for measuring the level of shipment quality.

[0035] Step 103: Based on the test strategy corresponding to the risk level of each die, control the test equipment to perform differentiated skip test actions on each die.

[0036] Optionally, based on the testing strategy corresponding to the risk level of each die, the testing equipment is controlled to perform differentiated skip testing actions on each die, including: for dies with a low risk level, the testing equipment is controlled to perform core function tests from the standard test items; wherein, the core function test items include electrical core test items and / or optical core test items; for dies with a medium risk level, the testing equipment is controlled to perform standard test items; for dies with a high risk level, the testing equipment is controlled to perform standard test items and additional reliability test items.

[0037] Optionally, the standard test items can be multiple pre-set tests that need to be performed on the die during wafer probe testing. Standard test items include core function test items and non-core test items. Core function test items include electrical core test items and / or optical core test items. Electrical core test items refer to the baseline test items used to determine the basic electrical connectivity and logic function of the die, and to ensure basic yield. These mainly include open / short circuit tests (OS), key DC parameters (threshold voltage Vth, saturation current Idsat, static leakage current Ioff, etc.), and core function continuity tests. Optical core test items are mandatory for silicon photonics chips, including insertion loss (IL), extinction ratio (ER), return loss (RL), and photoresponsivity. Non-core test items refer to test items that do not affect the determination of the basic electrical connectivity and logic function of the chip. They are mainly used for fine-grained optical performance parameters (such as wavelength tuning accuracy, small signal modulation curve fitting parameters), yield statistics, or marginal scenario verification, including performance binning sub-parameters, verification of secondary Internet Protocol (IP) modules, marginal operating condition coverage testing, and redundant repetitive test items. Insertion loss is the amount of output power lost relative to input power after the optical signal passes through the device, measured in dB. Extinction ratio is the ratio of the average optical power at high and low levels of the optical signal, characterizing the contrast of the optical modulation signal. Return loss is the ratio of incident optical power to the optical power reflected back to the input port of the device, measured in dB, and measures the matching performance of the device port.

[0038] Optionally, the testing strategy for low-risk scenarios could be to skip all non-core test items and retain only core functional test items as basic verification, maximizing test time compression while ensuring a minimum quality level. The testing strategy for medium-risk scenarios could be to execute all standard test items without skipping or adding tests, maintaining standard test coverage. The testing strategy for high-risk scenarios could be to add reliability test items to the standard test items. Added test items are adaptively matched based on the risk characteristics of the chip, focusing on the dominant risk type or using a comprehensive matching based on the combined results of multiple risk characteristics. Adaptive matching refers to a mechanism that flexibly matches corresponding added test items based on the type, number, and severity of risk characteristics, encompassing various forms such as targeted matching, multi-feature comprehensive matching, and full-coverage matching.

[0039] For mature consumer product lines with highly stable processes, historical CP yields exceeding preset high yield thresholds (e.g., 99.5%), and comprehensive functional fallback capabilities for subsequent final packaging and testing (FT), as an extreme optimization scenario, after multiple batches of verification show that the shipment DPPM meets control targets, a configuration can be enabled to skip all items and directly mark low-risk dies as qualified, further reducing processing time. This scenario is an optional extension configuration and is not a mandatory requirement of the basic solution.

[0040] Optionally, the testing equipment can be a pre-set tester and probe station for testing the wafer under test. The probe station is the device that carries the wafer and performs stepping positioning during wafer testing, working in conjunction with the tester to perform point-by-point testing of the die. Based on the testing strategy corresponding to the risk level of each die, the tester and probe station can be controlled to perform differentiated skip testing actions on each die: for low-risk dies, the tester and probe station perform the core functional tests from the standard test items; for medium-risk dies, the tester and probe station perform the standard test items; for high-risk dies, the tester and probe station perform both the standard test items and additional reliability tests. Additional reliability tests can refer to additional reliability tests corresponding to the risk type of the wafer under test.

[0041] Optionally, the risk type of the wafer under test can be a pre-defined text describing the risks that the wafer under test may encounter. The wafer under test can have multiple risk types. The reliability test items corresponding to the risk types of the wafer under test can be additional test items determined based on the dominant risk type of the wafer under test, used for reliability testing. The dominant risk type of the wafer under test can be the risk type with the highest importance among the various risk types of the wafer under test. The reliability test items corresponding to the risk types of the wafer under test can also be additional test items determined based on the superposition of multiple risk types of the wafer under test, used for reliability testing.

[0042] Optionally, if the dominant risk type of the wafer under test is PCM gate oxide-related parameter deviation, the additional reliability test item corresponding to the risk type of the wafer under test is gate oxide integrity (GOI) specific testing. If the dominant risk type of the wafer under test is high leakage current parameter, the additional reliability test item corresponding to the risk type of the wafer under test is multi-temperature zone quiescent power supply current (IDDQ) testing. Quiescent power supply current (standby leakage current) is a core reliability characterization parameter, enhancing reliability coverage. If the dominant risk type of the wafer under test is high neighborhood defect density, the additional reliability test items corresponding to the risk type of the wafer under test are edge failure-related parameters and metal interconnect reliability testing. If the dominant risk type of the wafer under test is BB optoelectronic parameter deviation, the additional reliability test items corresponding to the risk type of the wafer under test are multi-temperature zone optical power scan testing and high and low temperature optical wavelength stability testing. Quiescent power supply current is the total power supply current in the static standby state of the circuit and is a core reliability characterization parameter. Gate oxide integrity is a specific test for the reliability of the gate oxide layer of metal oxide semiconductor (MOS).

[0043] Optionally, if the wafer under test has multiple dominant risk types, reliability test items corresponding to each dominant risk type can be added together. If a single dominant risk type of the wafer under test cannot be clearly identified, all reliability test items can be added by default. All reliability test items can be multiple pre-set, addable test items used for wafer reliability testing.

[0044] Optionally, it also includes: after each preset number of test batches are completed, adjusting the weight coefficients and the preset risk threshold in the comprehensive risk value calculation formula using a machine learning algorithm or a grid search algorithm.

[0045] Optional, after completing a preset number of test batches (default) After each batch, a model iteration is performed to continuously optimize the grading accuracy. The iteration inputs for the model are the actual yield data of the current batch, failure die statistics, failure feedback from subsequent final packaging tests, and reliability test results. The iteration objectives and constraints are: a hard constraint that the reliability escape rate does not exceed the control target; and an optimization objective that maximizes the proportion of low-risk dies, ensuring efficiency improvement without compromising quality standards. The iteration method employs machine learning algorithms or grid search algorithms to adjust the weighting coefficients and preset risk thresholds in the comprehensive risk value calculation formula, optimizing the balance between skip testing efficiency and quality, and adapting to process drift and product maturity changes. Machine learning algorithms include, but are not limited to, logistic regression and random forest algorithms.

[0046] Optionally, the technical solution of this invention is adapted to multi-site concurrent testing probe cards. Test sequences can be generated in batches according to the grain classification results. Grains within a single puncture range undergo corresponding tests according to their respective risk levels, without requiring adjustments to the probe card hardware, and is compatible with existing concurrent testing modes. A test site is a parallel channel on the probe card that can independently complete a test. Multi-channel concurrent testing refers to the simultaneous completion of testing on multiple grains in a single puncture.

[0047] Optionally, during the execution of the differentiated skip test action, when any type of offset of the target die exceeds a preset multiple of the preset offset threshold, the risk level of the target die is determined to be high risk; when the yield of any die tested in any photomask reaches a preset confidence threshold, the testing of the remaining dies in the photomask is terminated.

[0048] The target die can be any die. The various offsets of the target die refer to the offsets of its process parameters, functional parameters, and spatial characteristic parameters. Each type of offset has a corresponding preset offset threshold. The preset offset threshold can be a value used to measure whether the offset is abnormal. When any type of offset of the target die exceeds a preset multiple of the preset offset threshold, the risk level of the target die can be directly determined as high risk, and it will no longer participate in the weighted calculation of the overall risk value.

[0049] The wafer under test contains multiple photomasks. A photomask is the smallest unit of exposure in the photolithography process, containing multiple dies; this is the standard decision granularity for test scheduling in the industry. The yield of the tested dies within a photomask is the ratio between the total number of qualified dies in the photomask and the total number of dies in the photomask. The preset confidence threshold can be a pre-set value. When the yield of any tested die within a photomask reaches the preset confidence threshold, testing of the remaining dies within that photomask can be terminated directly.

[0050] The technical solution of this invention involves acquiring process parameter data, functional unit test data, and spatial feature data of the wafer under test before the start of the test. This data is then mapped to each die of the wafer under test, resulting in the process parameter offset, functional parameter offset, and spatial feature parameter offset for each die. Based on these offsets, the comprehensive risk value and risk level of each die are determined. During the wafer under test, the testing equipment is controlled to perform differentiated skip test actions on each die according to the test strategy corresponding to its risk level. The technical solution of this invention addresses the problems in related technologies regarding test efficiency improvement and quality control schemes for wafer probe testing. These problems include the inability to directly skip unnecessary test items for low-risk dies from the source, the inability to fully utilize existing data from the wafer manufacturing process, the inability to implement differentiated test configurations based on die-level risk differences, and the inability to accurately match test resources according to specific risk types. The solution integrates wafer process parameter data, functional unit test data, and spatial characteristic data before the formal start of wafer testing to perform risk pre-classification at the single die level, determining the risk level of each die. Then, during wafer testing, based on the test strategy corresponding to the risk level of each die, the testing equipment is controlled to perform differentiated skip test actions on each die. This achieves differentiated test configuration based on die-level risk differences, accurately matches specific risk types with test resources, and enables skipping unnecessary test items for low-risk dies from the source, fully utilizing existing data from the wafer manufacturing process.

[0051] The technical solution of this invention provides a more thorough reduction in test redundancy and a greater improvement in efficiency. By pre-screening, the technical solution skips unnecessary tests on low-risk wafers at the source, eliminating inherent redundancy in pre-testing compared to the adaptive "test-and-stop" approach. For mature product lines with stable processes, test duration can be reduced. The compression, specifically the efficiency improvement, increases with product yield and process maturity, and the efficiency improvement effect is significantly better than existing solutions. In mature mass-produced product lines, the proportion of low-risk grains typically reaches [a certain percentage]. This is the core source of test duration compression.

[0052] The technical solution of this invention can release the value of multi-source data in advance, achieving cost reduction and quality improvement in parallel. This invention applies PCM, BB, and spatial defect data—originally used only for post-analysis—to test scheduling in advance, constructing a direct mapping mechanism of "risk characteristics → test strategy," fully exploring the engineering value of existing data. This invention, while reducing testing costs, also specifically enhances test coverage for high-risk chips, achieving cost reduction and quality improvement in parallel.

[0053] The technical solution of this invention can achieve fine-grained classification at the grain level, resulting in higher balancing accuracy. This solution refines the decision-making granularity from the reticle level to the grain level, configuring differentiated testing depths for grains with different risks. This avoids redundancy or insufficient coverage caused by a "one-size-fits-all" strategy, significantly improving the balance between efficiency and quality.

[0054] The technical solution of this invention has an extremely simple architecture and very low implementation cost. It requires no modification to the core testing logic of the testing equipment; only a pre-grading calculation module needs to be added to the scheduling layer, making it fully compatible with existing production line equipment and processes. The algorithm logic of this invention is simple, with low computational load, a short proof-of-concept (POC) cycle, and an extremely low barrier to mass production implementation.

[0055] Optionally, in a specific example of a silicon photonic chip, the wafer under test is a 400G silicon photonic transceiver chip integrating a Mach-Zehnder modulator (MZM) and a germanium photodetector (GePD). The initial values ​​of the weighting coefficients in the comprehensive risk value calculation formula are: (Weighting coefficients corresponding to process parameter offsets, focusing on waveguide doping concentration-related parameters). (Weighting coefficients corresponding to the functional parameter offsets, focusing on the performance of the photoelectric conversion unit). (Weighting coefficients corresponding to the spatial feature parameter offsets). The low-risk threshold is 30, and the high-risk threshold is 70.

[0056] The first grain is a single grain within the wafer being tested. The process parameter offset for the first grain is 0.5. The black-bottom (BB) test (e.g., GePD dark current) of the first die was normal, and the neighborhood defect density of the first die was 0.3%. The spatial characteristic parameter risk score was calculated with a neighborhood defect density of 2% as the control threshold, corresponding to 100 points; 0% neighborhood defect density corresponded to 0 points; and a neighborhood defect density of 0.3% was linearly normalized to obtain 15 points. The process parameter risk score was calculated with a threshold of 0.5. For process parameter offset, 3 The control threshold is calculated to be approximately 16.7 points; the overall risk value = 16.7 × 0.35 + 0 × 0.4 + 15 × 0.25 ≈ 9.6 points. Based on the calculation, the overall risk value of the first die is 9.6 points, classifying it as low-risk. For the first die, non-core test items such as performance grading (e.g., fine wavelength tuning test) and secondary IP (e.g., redundant monitoring circuit) are skipped, retaining only core functional test items (e.g., open / short circuit OS, basic insertion loss IL scan), reducing single-die test time by approximately 48%. Performance grading is a classification test used to differentiate products with different performance specifications based on test parameters; it is a non-mandatory classification test item.

[0057] The second grain is a grain within the wafer being tested. The process parameter offset for the second grain is 2.2. The neighborhood defect density of the second grain is 1.8%. Calculations show that the overall risk score for the second grain is 78 points, classifying it as high-risk. To further enhance the coverage of optical performance stability, multi-temperature zone optical power scanning and high-power optical stress aging tests are added to the standard test items for the second grain.

[0058] Statistics show that the low-risk die ratio of this silicon photonics wafer is approximately 55%, the medium-risk ratio is approximately 40%, and the high-risk ratio is approximately 5%. After applying the technical solution of this invention, the overall test time is reduced by approximately 33%, and no increase in reliability escape rate has been observed. The technical solution of this invention can also be adapted to wafer testing scenarios for other semiconductor devices such as traditional electrical chips, memory chips, and power chips, requiring only corresponding adjustments to the weighting coefficients and risk thresholds.

[0059] Optionally, the technical solution of this invention can increase the number of risk levels according to product requirements, such as dividing them into five levels: extremely low, low, medium, high, and extremely high, to achieve a more refined differentiation strategy.

[0060] Optionally, the technical solution of this embodiment of the invention can add other features such as equipment status, photolithography slots, and wafer positions to the scoring model to further improve the classification accuracy.

[0061] Optionally, for mature products with sufficient data, the technical solution of this invention can use machine learning models such as logistic regression and random forest to replace linear weighted scoring, thereby improving the accuracy of classification.

[0062] Optionally, for ultra-large-scale wafers with a high number of grains, the technical solution of this invention can adopt block interpolation or a simplified Kriging model to improve computational efficiency while ensuring interpolation accuracy and adapt to the computing power requirements of mass production environments.

[0063] Optionally, the technical solution of this invention can be used in combination with the reticle-level adaptive early stop scheme in the testing process: first, the grain-level skip test is completed through pre-screening before testing, and the reticle-level adaptive early stop is executed based on the real-time yield confidence during the remaining testing process, thereby achieving dual test duration compression.

[0064] Example 2 Figure 2 This is a schematic diagram of a wafer testing jump test system provided in Embodiment 2 of the present invention. This embodiment is applicable to situations involving wafer probe testing. Figure 2As shown, the wafer test skipping system 200 may specifically include: a data access unit 201, a risk pre-classification unit 202, and a test scheduling and execution unit 203. Its structure and functions are described below. In the figure, solid lines represent the main business data flow and control flow, while dashed lines represent configuration parameters and feedback data flow.

[0065] The data access unit 201 is used to acquire process parameter data, functional unit test data and spatial feature data of the wafer under test, and map the process parameter data, the functional unit test data and the spatial feature data to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset and spatial feature parameter offset of each grain.

[0066] The risk pre-classification unit 202 is used to determine the comprehensive risk value and risk level of each grain based on the offset of process parameters, functional parameters and spatial characteristic parameters of each grain.

[0067] The test scheduling and execution unit 203 is used to control the test equipment to perform differentiated skip test actions on each die according to the test strategy corresponding to the risk level of each die.

[0068] The data access unit 201, the risk pre-classification unit 202, and the test scheduling execution unit 203 operate in a computer storage medium or an industrial server.

[0069] Optionally, the data access unit 201 can be a hardware or software module used to acquire process parameter data, functional unit test data, and spatial feature data of the wafer under test, and map these data to each die of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset of each die. The data access unit 201 interfaces with the Manufacturing Execution System (MES), Statistical Process Control (SPC) system, and BB test unit, and is deployed at the edge of the factory's industrial control network. The input data of the data access unit 201 consists of process parameter data, functional unit test data, spatial feature data, and wafer reticle coordinates to die mapping table data output from external systems. The output data of the data access unit 201 consists of the process parameter offset, functional parameter offset, and spatial feature parameter offset of each die, i.e., a standardized die-level feature dataset after data cleaning and spatial interpolation mapping. The input of the data access unit 201 interfaces externally with the MES, SPC system, and BB test unit. MES (Manufacturing Execution System) is a factory-level manufacturing execution management system that carries data from the entire wafer fabrication process, including yield. SPC (Structured Process Control) is a system for statistically controlling process parameters, used to monitor process fluctuations and stability. The output of data access unit 201 internally interfaces with risk pre-grading unit 202. Data access unit 201 uses an industrial-grade data acquisition gateway, supporting the Semiconductor Equipment Communications Standard / Generic Equipment Model (SECS / GEM) protocol, responsible for accessing, cleaning, and spatially mapping multi-source heterogeneous data at the die level, outputting a standardized feature dataset. Data access unit 201 is compatible with mainstream manufacturers' testing equipment and business systems. The Semiconductor Equipment Communications Standard protocol is a universal communication interface specification for production line equipment.

[0070] Optionally, the risk pre-grading unit 202 can be a hardware or software module used to determine the comprehensive risk value and risk level of each die based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each die. The risk pre-grading unit 202 is also used to adjust the weighting coefficients and preset risk thresholds in the comprehensive risk value calculation formula using machine learning algorithms or grid search algorithms after each preset number of test batches are completed. The risk pre-grading unit 202 is a front-end calculation module of the test scheduling system, deployed in the local industrial control room of the test workshop. The input data of the risk pre-grading unit 202 includes: the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each die; and preset configuration parameters. The preset configuration parameters include the weighting coefficients in the comprehensive risk value calculation formula, the preset risk threshold, and the mapping rules between risk levels and test items. The output data of the risk pre-grading unit 202 can be a data table containing the risk level of each die and the test strategy corresponding to the risk level of each die. The input end of the risk pre-grading unit 202 is internally connected to the data access unit 201. The output of the risk pre-grading unit 202 is internally connected to the test scheduling and execution unit 203. The risk pre-grading unit 202 has a built-in weighted scoring model that can calculate the comprehensive risk value and classify the risk level of a single die. It then outputs a data table containing the die's risk level and the corresponding test strategy based on preset mapping rules. The risk pre-grading unit 202 only needs to perform the calculation once before each wafer is tested, resulting in low computational load and minimal impact on the testing equipment's effective operating time. It serves as the core innovative component of the system.

[0071] Optionally, the test scheduling execution unit 203 may be a hardware module or software module configured to control the test equipment to perform differentiated skip test actions on each die according to the test strategy corresponding to the risk level of each die. The test scheduling execution unit 203 is the scheduling control end of the test machine, and is deployed beside the test machine. The input data of the test scheduling execution unit 203 is a data table output by the risk pre-classification unit 202, which includes the risk level of each die and the test strategy corresponding to the risk level of each die. The output data of the test scheduling execution unit 203 is a die test item execution sequence, a probe station stepping control instruction, and a test machine item start-stop control instruction. The input end of the test scheduling execution unit 203 is internally connected to the risk pre-classification unit 202. The output end of the test scheduling execution unit 203 is externally connected to the test equipment. The test equipment includes a wafer tester and a probe station. The test scheduling execution unit 203 may adopt a programmable test control module matched with the test machine, generate test execution sequences in batches after receiving the data table including the risk level of each die and the test strategy corresponding to the risk level of each die, control the probe station and the test machine to complete differentiated tests according to the sequences, and realize skip test scheduling. The test scheduling execution unit 203 supports a multi-site parallel test mode, and is compatible with various probe cards such as vertical probes and Micro-Electro-Mechanical Systems (MEMS).

[0072] Optionally, after the wafer under test is loaded, the data access unit 201 acquires process parameter data, functional unit test data and spatial feature data of the wafer under test, maps the process parameter data, functional unit test data and spatial feature data to each die of the wafer under test, obtains the process parameter offset, functional parameter offset and spatial feature parameter offset of each die, completes multi-source data collection and die mapping, and then outputs the process parameter offset, functional parameter offset and spatial feature parameter offset of each die to the risk pre-classification unit 202. The risk pre-classification unit 202 determines the comprehensive risk value and risk level of each die according to the process parameter offset, functional parameter offset and spatial feature parameter offset of each die, completes risk rating and strategy configuration for all dies, and then outputs the data table including the risk level of each die and the test strategy corresponding to the risk level of each die to the test scheduling execution unit 203. The test scheduling execution unit 203 controls the test equipment to perform differentiated skip test actions on each die according to the test strategy corresponding to the risk level of each die, and completes the test process of the entire wafer.

[0073] The technical solution of this invention can integrate wafer process parameter data, functional unit test data, and spatial feature data before the formal commencement of wafer testing to complete risk pre-classification at the single-die level, determining the risk level of each die. Then, during wafer testing, based on the test strategy corresponding to the risk level of each die, the testing equipment is controlled to perform differentiated skip tests on each die. This achieves differentiated test configuration for die-level risk differences, accurately matching specific risk types with test resources, and skipping unnecessary test items on low-risk dies from the source. It can fully utilize various existing data in the wafer manufacturing process. The system architecture of the technical solution of this invention is extremely simple, fully compatible with existing production line equipment, and only requires the addition of pre-classification capabilities at the test scheduling layer.

[0074] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0075] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A wafer testing method for skipped testing, characterized in that, include: The process parameter data, functional unit test data, and spatial feature data of the wafer under test are acquired. The process parameter data, functional unit test data, and spatial feature data are mapped to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset of each grain. Based on the offsets of process parameters, functional parameters, and spatial characteristic parameters of each grain, the comprehensive risk value and risk level of each grain are determined. Based on the testing strategy corresponding to the risk level of each die, control the testing equipment to perform differentiated skip testing actions on each die.

2. The wafer testing skipping method according to claim 1, characterized in that, The process parameter data, the functional unit test data, and the spatial feature data are mapped to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset, and spatial feature parameter offset for each grain, including: The process parameter data is mapped to each grain of the wafer under test using a spatial interpolation method to obtain the process parameter offset of each grain. Based on spatial attribution rules or nearest neighbor principles, the functional unit test data is mapped to each grain of the wafer under test to obtain the functional parameter offset of each grain. Based on the spatial feature data, the spatial risk characteristics of each grain of the tested wafer within a preset neighborhood range are determined, and the spatial feature parameter offset of each grain is obtained.

3. The wafer testing skipping method according to claim 2, characterized in that, The process parameter data is mapped to each grain of the wafer under test using a spatial interpolation method to obtain the process parameter offset for each grain, including: When the test point density is less than the preset density threshold, the process parameter data is mapped to each grain of the wafer under test using the first spatial interpolation method to obtain the process parameter offset of each grain. When the test point density is greater than or equal to a preset density threshold, the process parameter data is mapped to each grain of the wafer under test using a second spatial interpolation method to obtain the process parameter offset of each grain.

4. The wafer testing skipping method according to claim 1, characterized in that, Based on the offsets of process parameters, functional parameters, and spatial characteristic parameters for each grain, the comprehensive risk value and risk level of each grain are determined, including: Based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each grain, determine the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain. The comprehensive risk value of each grain is determined based on the comprehensive risk value calculation formula, the risk scores of process parameters, functional parameters, and spatial characteristic parameters for each grain. The risk level of each grain is determined based on the preset risk threshold and the comprehensive risk value of each grain.

5. The wafer testing skipping method according to claim 4, characterized in that, Based on the process parameter offset, functional parameter offset, and spatial characteristic parameter offset of each grain, determine the process parameter risk score, functional parameter risk score, and spatial characteristic parameter risk score of each grain, including: Based on the nominal value and historical statistical value corresponding to the process parameter offset, and the process parameter offset of each grain, determine the process parameter risk score of each grain. Based on the nominal value and historical statistical value corresponding to the functional parameter offset, and the functional parameter offset of each grain, determine the functional parameter risk score of each grain; The spatial characteristic parameter offsets of each grain are linearly normalized to map them to a preset numerical range, thereby obtaining the spatial characteristic parameter risk score of each grain.

6. The wafer testing skipping method according to claim 4, characterized in that, The preset risk thresholds include low-risk thresholds and high-risk thresholds; Based on the preset risk threshold and the comprehensive risk value of each grain, the risk level of each grain is determined, including: Perform the following operations for each grain: If the overall risk value of a grain is less than or equal to the low-risk threshold, then the risk level of the grain is determined to be low-risk. If the overall risk value of a grain is greater than the low-risk threshold and less than or equal to the high-risk threshold, then the risk level of the grain is determined to be medium risk. If the overall risk value of a grain is greater than the high-risk threshold, then the risk level of the grain is determined to be high-risk.

7. The wafer testing skipping method according to claim 4, characterized in that, Also includes: After each preset number of test batches are completed, the weighting coefficients and the preset risk threshold in the comprehensive risk value calculation formula are adjusted using machine learning algorithms or grid search algorithms.

8. The wafer testing skipping method according to claim 1, characterized in that, Based on the testing strategy corresponding to the risk level of each die, the testing equipment is controlled to perform differentiated skip testing actions on each die, including: For chips with a low risk level, the control testing equipment performs core functional tests on the chips from the standard test items; wherein, the core functional tests include electrical core tests and / or optical core tests; For dies with a risk level of medium risk, the control testing equipment performs standard test items on the dies; For high-risk dies, the control testing equipment performs standard tests and additional reliability tests on the dies.

9. The wafer testing skipping method according to claim 1, characterized in that, During the execution of the differentiated skip test, when any type of offset of the target die exceeds a preset multiple of the preset offset threshold, the risk level of the target die is determined to be high risk; when the yield of any die tested in any photomask reaches a preset confidence threshold, the testing of the remaining dies in the photomask is terminated.

10. The wafer testing skipping method according to claim 1, characterized in that, The process parameter data includes at least one of sheet resistance, threshold voltage, static leakage current, and waveguide transmission loss; the functional unit test data includes at least one of on-chip monitoring ring insertion loss, photoelectric responsivity, extinction ratio, heater resistance, half-wave power, open / short circuit test value, and memory cell erase / write performance.

11. A wafer testing skipping system, characterized in that, include: Data access unit, risk pre-classification unit, and test scheduling and execution unit; The data access unit is used to acquire process parameter data, functional unit test data and spatial feature data of the wafer under test, and map the process parameter data, the functional unit test data and the spatial feature data to each grain of the wafer under test to obtain the process parameter offset, functional parameter offset and spatial feature parameter offset of each grain. The risk pre-classification unit is used to determine the comprehensive risk value and risk level of each grain based on the offset of process parameters, functional parameters and spatial characteristic parameters of each grain. The test scheduling and execution unit is used to control the test equipment to perform differentiated skip test actions on each die according to the test strategy corresponding to the risk level of each die. The data access unit, the risk pre-classification unit, and the test scheduling execution unit operate on computer storage media or industrial servers.

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