Fan drive device with standardized interface and compatible driving method thereof

Abstract

This invention discloses a standardized interface wind turbine drive device and its compatible drive method, relating to the field of wind turbine drive technology. A universal wind turbine drive module is positioned between the host computer motherboard and the wind turbine. The universal wind turbine drive module has a low-voltage area and a high-voltage area. The high-voltage area includes a high-voltage interface, relays K1 and K2, while the low-voltage area includes a low-voltage interface CN2, an MCU core unit, a DIP switch SW1, and a wind turbine interface CN5. The DIP switch SW1 is used to manually set the operating parameters of the drive module without software tools. This invention, by setting a universal wind turbine drive module between the host computer motherboard and the wind turbine, and defining a three-wire standardized interface protocol consisting of analog speed command voltage, digital speed feedback pulse, and low-voltage DC low-voltage power supply, allows the host computer motherboard to achieve plug-and-play wind turbine drive functionality simply by configuring its universal analog output port and pulse input port via software.

Description

Technical Field

[0001] This invention relates to the field of wind turbine drive technology, and in particular to a wind turbine drive device with a standardized interface and a compatible drive method thereof. Background Technology

[0002] Currently, in electrical equipment, DC fans generally adopt a motherboard-integrated solution for drive. This solution directly designs and integrates the fan drive circuit and control logic onto the host computer motherboard. The host computer drives the fan by directly outputting pulse-width modulation (PWM) signals through the onboard microcontroller (MCU), and uses the feedback sampling circuit integrated on the motherboard to detect the fan speed feedback (FG) signal, forming a closed-loop control. The drive circuit shares the same power system with other functional circuits on the motherboard, and the fan power circuit and signal circuit are not physically isolated.

[0003] However, the above-mentioned integrated motherboard solution has the following problems and drawbacks in practical applications: 1. The drive circuit is deeply bound to the electrical parameters (such as operating voltage and feedback pulse division ratio) of a specific fan model. There is no standardized electrical interface and signal protocol between the host computer motherboard and the fan. When replacing a fan with a different specification, the motherboard hardware circuit must be modified simultaneously, the PCB layout must be redesigned, and a new mold must be made, making plug-and-play impossible. 2. The drive circuit is physically integrated into the motherboard and cannot be expanded as an independent module. Any upgrade to the drive function (such as adding speed self-learning, multi-mode speed offset, hierarchical fault diagnosis, etc.) requires a complete redesign or replacement of the motherboard. For products with fixed hardware or a large inventory of motherboards, the upgrade cost is extremely high and the cycle is long. 3. The wind turbine power circuit and the mainboard low-voltage control circuit share the same power system without physical isolation. When the wind turbine power circuit experiences abnormalities such as short circuits or overloads, it may directly affect the core control circuit of the mainboard, reducing system reliability. 4. The closed-loop speed regulation calculation, feedback signal processing and fault diagnosis logic of the wind turbine are entirely dependent on the motherboard MCU, which occupies the computing resources and I / O ports of the main control chip, increasing the complexity of the motherboard software design and the development cycle. Summary of the Invention

[0004] The purpose of this invention is to provide a wind turbine drive device with a standardized interface and a compatible drive method thereof to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a wind turbine drive device with a standardized interface, comprising: A universal fan drive module is located between the host computer motherboard and the fan. The general-purpose wind turbine drive module is provided with a low-voltage area and a high-voltage area. The high-voltage area is provided with a high-voltage interface, relay K1 and relay K2. The low-voltage area is provided with a low-voltage interface CN2, an MCU core unit, a DIP switch SW1 and a wind turbine interface CN5. The low-voltage interface CN2 is used to receive the analog speed command voltage signal output by the host computer motherboard, output the processed fan speed feedback pulse signal to the host computer motherboard, and receive the low-voltage DC low voltage provided by the host computer motherboard to power the control circuit of the drive module. The MCU core unit includes a main controller, a two-stage FG frequency division processing unit, and a multi-stage fault protection unit. The main controller receives the analog speed command voltage signal, calculates the PWM duty cycle according to preset control logic, adjusts the duty cycle offset according to the speed offset mode set by the DIP switch, and outputs the PWM drive signal. The two-stage FG frequency division processing unit divides and converts the original FG pulses of the fan to obtain the internal speed signal, and converts the internal speed signal into a feedback pulse format that conforms to the host computer motherboard protocol. The multi-stage fault protection unit performs fault detection and protection. The contacts of relay K1 are connected in series between the external AC power supply and the high-voltage terminal of the fan. The contacts of relay K2 are connected in series between the external AC power supply and the high-voltage terminal of the fan through an internal circuit. The coils of relay K1 and relay K2 are electrically connected to the I / O port of the MCU core unit. The MCU core unit controls the relay K1 or relay K2 to be energized according to the DIP switch settings. The DIP switch SW1 is used to manually set the operating parameters of the drive module without the need for software tools.

[0006] Preferably, the low-voltage interface CN2 includes: The Vsp interface is used to receive the analog speed command voltage signal output by the host computer motherboard; The FG interface is used to output the processed fan speed feedback pulse signal to the host computer motherboard. The Vcc interface is used to receive low-voltage DC power from the host computer motherboard to power the control circuit of the drive module. The GND interface shares a common ground with the host computer. The Vsp, FG, and Vcc interfaces coexist on the drive module, forming a three-wire standardized interface that simultaneously receives voltage commands, provides feedback speed pulses, and obtains low-voltage power supply.

[0007] Preferably, the two-stage FG frequency division processing unit includes: The first-level frequency division processing unit is used to perform frequency division and conversion on the original FG pulse of the fan according to the input feedback frequency division ratio to obtain the internal speed signal for closed-loop speed regulation. The second-level frequency division processing unit is used to convert the internal speed signal into a feedback pulse format that conforms to the host computer motherboard protocol according to the output feedback frequency division ratio.

[0008] Preferably, the multi-level fault protection unit includes: The FG feedback-free fault protection circuit is used to provide a fault alarm indication and lock the fault state until power is cut off and reset when the FG feedback pulse of the fan is detected to be lost. The Vsp overvoltage fault protection circuit is used to forcibly shut down the PWM output when the analog speed command voltage signal is detected to exceed the preset protection threshold, and automatically restore normal output when the voltage signal falls back to below the recovery threshold.

[0009] Preferably, the main controller calculates the basic PWM duty cycle according to the duty cycle equation Y=KX, where Y is the PWM duty cycle, X is the analog speed command voltage signal, and K is a preset constant; the speed offset mode includes seven effective modes and one hold mode, each of the effective modes corresponding to a preset duty cycle offset ratio; the hold mode maintains the offset value of the previous effective speed offset mode unchanged; when the system is powered on and initialized, the hold mode is detected and processed according to the standard mode.

[0010] Preferably, the DIP switch SW1 has multiple positions for setting the output feedback division ratio, input feedback division ratio, high-voltage output type, and speed offset mode; both relays K1 and K2 are normally open relays, and remain open during the system power-on initialization phase. The MCU core unit selectively drives relay K1 or relay K2 to engage only after detecting a valid analog speed command voltage signal, according to the high-voltage output type set by the DIP switch; the low-voltage area of ​​the general-purpose fan drive module also has a communication expansion interface CN8, which is used to support communication-type fans or customized communication protocols.

[0011] A wind turbine driver compatibility method with a standardized interface includes the following steps: S1 Low Voltage Power-On and Configuration Identification Steps: The general-purpose fan drive module receives low-voltage DC power from the host computer motherboard to power its control circuit, and reads all the DIP switch positions to determine the operating parameters. S2 speed command receiving steps: The MCU of the drive module receives the analog speed command voltage signal output by the host computer motherboard through the Vsp interface; S3 High Voltage Analysis Step: After the main controller detects a valid analog speed command voltage signal, it drives the corresponding relay type according to the high voltage output determined by the DIP switch. S4 PWM duty cycle calculation steps: The main controller calculates the basic PWM duty cycle according to the preset control logic, and adds the corresponding duty cycle offset according to the speed offset mode determined by the DIP switch, and clamps the offset results that exceed the preset range. S5 motor drive steps: The main controller outputs the final PWM signal and activates the final relay to output high voltage to the fan to drive the fan to operate; S6 Speed ​​Feedback Two-Level Processing Steps: The main controller receives the original FG pulse signal from the fan, performs a first-level frequency division calculation according to the input feedback frequency division ratio to obtain the internal speed signal for closed-loop speed regulation, and then performs a second-level frequency division calculation according to the output feedback frequency division ratio to obtain the feedback pulse format that conforms to the host computer motherboard protocol. S7 Feedback Signal Forwarding Step: The main controller forwards the FG feedback pulse signal, which has been processed by the two stages, to the host computer motherboard through the FG interface of the weak current interface CN2, so that the host computer motherboard can know the actual speed of the fan and form a closed loop.

[0012] Preferably, in step S4, the duty cycle equation is Y=KX, where Y is the PWM duty cycle, X is the analog speed command voltage signal, and K is a preset constant. The speed offset mode includes seven effective modes and one holding mode: the duty cycle offset ratio of the standard mode is 0%; the duty cycle offset ratios of the high-speed mode, ultra-high-speed mode, and turbine mode are +10%, +15%, and +20%, respectively; the duty cycle offset ratios of the low-speed mode, ultra-low-speed mode, and silent mode are -10%, -15%, and -20%, respectively, and the current mode is confirmed by the DIP switch; the holding mode maintains the offset value of the previous effective speed offset mode unchanged; when the system is powered on and initialized, if the speed offset mode is detected as the holding mode, it is processed according to the standard mode; in step S3, when the high-voltage output type determined by the DIP switch is AC high voltage, the MCU drives the relay K1 to engage to conduct external AC power to the high-voltage terminal of the fan; when the high-voltage output type determined by the DIP switch is DC high voltage, the MCU drives the relay K2 to engage.

[0013] Preferably, the method further includes: S8 FG no-feedback fault handling step: when no FG feedback pulse signal is received from the fan within a preset detection period, an FG no-feedback fault is determined to have occurred, a fault alarm indication is given and the fault state is locked; even if the FG signal returns to normal during the fault lockout period, the fault state is still maintained; fault recovery can only be achieved by disconnecting the system power supply and reconnecting it; S9 Vsp overvoltage fault handling step: when the voltage signal of the Vsp interface is detected to exceed a preset protection threshold, a Vsp overvoltage fault is determined to have occurred, a fault alarm indication is given and the PWM output is forcibly shut down to stop the fan; when the Vsp voltage drops below the preset recovery threshold, the fault state is automatically released and normal PWM output is restored without power-off reset.

[0014] Preferably, the method further includes a communication extension step S10: communicating with the fan via the communication extension interface of the drive module to support a communication-type fan or a customized communication protocol; in S6, the first-level frequency division conversion performs frequency division conversion on the FG original pulse according to the input feedback frequency division ratio set by the DIP switch, and the second-level frequency division conversion converts the internal speed signal into the feedback pulse format according to the output feedback frequency division ratio set by the DIP switch. The input feedback frequency division ratio and the output feedback frequency division ratio are independent of each other and can be configured independently by the DIP switch.

[0015] The technical effects and advantages of this invention are as follows: (1) This invention sets up a universal fan drive module between the host computer motherboard and the fan, and defines a three-wire standardized interface protocol consisting of analog speed command voltage (Vsp), digital speed feedback pulse (FG) and low-voltage DC weak current power supply (Vcc). This allows the host computer motherboard to be compatible with DC fans with different electrical parameters by simply configuring its universal analog output port and pulse input port through software, without modifying the hardware circuit, redesigning the PCB or re-molding, thus achieving plug-and-play fan drive. (2) The fan drive function of this invention is physically separated from the motherboard into an independent module. When it is necessary to adapt to new fans or expand functions, only the drive module needs to be replaced or upgraded. At the same time, the output feedback frequency division ratio, input feedback frequency division ratio, high power output type and speed offset mode and other working parameters can be manually set without software tools through the DIP switch SW1. The host computer motherboard does not need to modify the original hardware, which reduces the hardware modification cost and maintenance cycle of system function iteration. (3) This invention uses independent low-voltage and high-voltage power supply circuits. The host computer only provides low-voltage DC low-voltage power to power the module control circuit; the high-voltage power required by the fan power circuit is introduced through an independent interface and physically isolated by relays K1 / K2. The connection of the high-voltage circuit is controlled by the MCU and Vsp command signals on the low-voltage side, forming a controlled power-on sequence; when the fan power circuit has abnormalities such as short circuit or overload, it will not directly affect the core control circuit of the host computer, thus improving the system safety and reliability. (4) This invention delegates all core operations of the bottom-level closed-loop control of the wind turbine, including Vsp voltage acquisition, PWM duty cycle calculation and speed offset superposition, and two-level frequency division conversion of FG feedback pulse, to an independent MCU within the drive module. The host computer only needs to maintain Vsp voltage output and read FG feedback pulse, which reduces the computing resources and I / O port occupation of the host computer MCU, making the motherboard hardware and software design simpler; (5) This invention incorporates multi-level fault detection and protection logic independent of the host computer within the drive module. When the FG feedback pulse is detected to be lost, a red LED flashes at a preset frequency to trigger an alarm and latches the fault state, requiring a power-off reset to recover. When the Vsp voltage exceeds a preset protection threshold, a green LED flashes to trigger an alarm and forcibly shuts off the PWM output, automatically restoring normal operation when the voltage drops below the recovery threshold. All of the above fault protections do not rely on host computer software intervention and are executed directly by the local MCU, improving the timeliness and reliability of fault response. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic block diagram of the standardized interface fan drive device of the present invention; Figure 2 This is a schematic diagram of the operating method of the fan drive device of the present invention; Figure 3 This is an example diagram illustrating the relationship between the DIP switch configuration and the PWM duty cycle of the present invention; Figure 4 This is a schematic diagram of the operating principle of an existing motherboard-integrated fan drive solution. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Considering that existing motherboard-integrated DC fan driver solutions suffer from hardware binding, poor compatibility, inability to upgrade independently, lack of separation between strong and weak current circuits, and occupation of host computer resources, the following section will discuss... Figure 4 The diagram shown illustrates the operating principle of the old technology. A brief explanation of the existing technology is as follows: In the old technology, the fan drive circuit and control logic are directly designed and solidified on the host computer motherboard. The host computer directly outputs PWM signals to drive the fan through the onboard MCU, and uses the feedback sampling circuit integrated on the motherboard to detect the fan speed feedback (FG) signal to form a closed-loop control. The drive circuit and other functional circuits on the motherboard share the same power supply system, and the fan power supply circuit and signal circuit are not physically isolated.

[0019] The present invention proposes a standardized interface wind turbine drive device and its compatible drive method. By decoupling the wind turbine drive function from the host computer motherboard into an independent standardized module, and defining a unified three-wire standardized interface protocol consisting of analog speed command voltage (Vsp), digital speed feedback pulse (FG), and low-voltage DC weak current power supply (Vcc), the host computer motherboard without wind turbine drive function can be compatible with different models of DC wind turbines without hardware modification.

[0020] Example 1: Structure of a fan drive device with a standardized interface The following is combined Figure 1 The diagram showing the device structure and connection relationship of each component of the present invention further illustrates the specific structure of the fan drive device of the present invention.

[0021] The general-purpose fan drive module is located between the host computer motherboard and the fan. The general-purpose fan drive module has a low-voltage area and a high-voltage area. The high-voltage area has high-voltage interfaces (CN1, CN9, CN3), relay K1 and relay K2, and the low-voltage area has a low-voltage interface CN2, an MCU core unit, a DIP switch SW1, a fan interface CN5 and LED indicator lights.

[0022] The low-voltage interface CN2 includes: a Vsp interface for receiving the analog speed command voltage signal output from the host computer motherboard; an FG interface for outputting a processed fan speed feedback pulse signal to the host computer motherboard; a Vcc interface for receiving low-voltage DC power from the host computer motherboard to power the control circuit of the drive module; and a GND interface, which shares a common ground with the host computer. The Vsp, FG, and Vcc interfaces coexist on the drive module, forming a standardized three-wire interface that simultaneously receives voltage commands, provides speed feedback pulses, and obtains low-voltage power.

[0023] The MCU core unit includes a main controller, a two-stage FG frequency divider processing unit, and a multi-stage fault protection unit. The main controller receives the analog voltage signal from the Vsp interface, calculates the PWM duty cycle according to preset control logic, adjusts the duty cycle offset according to the speed offset mode set by the DIP switch, and then outputs the PWM drive signal. The two-stage FG frequency divider processing unit divides and converts the original FG pulses from the fan to obtain the internal speed signal, and then converts the internal speed signal into a feedback pulse format conforming to the host computer motherboard protocol. The multi-stage fault protection unit performs fault detection and protection.

[0024] The contacts of relay K1 are connected in series between the external AC power supply (CN1) and the high-voltage terminal of the fan (CN3), and the contacts of relay K2 are connected in series between the external DC power supply (CN9) and the high-voltage terminal of the fan. The coils of relay K1 and relay K2 are electrically connected to the I / O port of the MCU, and the MCU controls relay K1 or relay K2 to be energized according to the DIP switch settings.

[0025] The DIP switch SW1 is used to manually set the operating parameters of the drive module without the need for software tools. The LED indicators include red and green LEDs for fault alarm indication.

[0026] Example 2: Two-stage FG frequency division processing The following is combined Figure 2 The schematic diagram of the present invention further illustrates the specific working process of the two-stage FG frequency division processing unit. Figure 2 The signal flow of the feedback path is shown in the figure: fan - CN5 FG pin - MCU - two-stage frequency division processing - CN2 FG pin - host computer motherboard.

[0027] The two-stage FG frequency division processing unit includes: a first-stage frequency division processing unit and a second-stage frequency division processing unit.

[0028] The first-stage frequency division processing unit is used to perform frequency division and conversion of the original FG pulses of the fan according to the input feedback frequency division ratio to obtain an internal speed signal for closed-loop speed regulation. For example, when Dip 2 of DIP switch SW1 is set to 1, the input feedback frequency division ratio is 1 / 29 PPR. The first-stage frequency division processing unit converts the 29 original pulses output by the fan per revolution into an internal speed signal for the main controller to perform closed-loop speed regulation calculations.

[0029] The second-stage frequency divider processing unit is used to convert the internal speed signal into a feedback pulse format that conforms to the host computer motherboard protocol according to the output feedback frequency division ratio. For example, when the DIP 1 of the DIP switch SW1 is set to 0, the output feedback frequency division ratio is 1 / 4 PPR. The second-stage frequency divider processing unit converts the internal speed signal into a format of 4 pulses per revolution, and then forwards it to the host computer through the FG interface of the low-voltage interface CN2.

[0030] The input feedback division ratio and the output feedback division ratio are independent of each other and can be configured independently via DIP switches.

[0031] Example 3: Multi-level fault protection The following is combined Figure 1 The LED indicator positions shown are as follows: Figure 2 The diagram shown further illustrates the specific working process of the multi-level fault protection unit.

[0032] The multi-level fault protection unit includes: FG no-feedback fault protection circuit and Vsp overvoltage fault protection circuit.

[0033] The FG (Fan Generator) feedback-free fault protection circuit is used to issue a fault alarm and latch the fault state when the FG feedback pulse of the wind turbine is detected to be lost, until power is cut off and reset. Specifically, if the main controller does not receive a feedback pulse from the wind turbine within a preset detection period, it determines that an FG feedback-free fault has occurred, drives a red LED to flash at a frequency of 1Hz to issue an alarm, and latches the fault state. During the fault lockout period, even if the FG signal returns to normal, the fault state remains and can only be restored by disconnecting the system power and then powering it back on.

[0034] The Vsp overvoltage fault protection circuit is used to forcibly shut down the PWM output when the voltage signal detected at the Vsp interface exceeds a preset protection threshold, and automatically resume normal output when the voltage signal falls back below the recovery threshold. Specifically, when the Vsp voltage exceeds the preset protection threshold, the main controller drives the green LED to flash as an alarm and forcibly shuts down the PWM output to protect the fan; when the Vsp voltage falls back below the recovery threshold, the fault state is automatically cleared and the PWM output is restored without power-off reset.

[0035] When multiple faults exist simultaneously, each fault corresponds to a different number of LED flashes, and the fault with fewer LED flashes has a higher priority than the fault with more LED flashes.

[0036] Example 4: PWM Duty Cycle Calculation and Velocity Offset Mode The following is combined Figure 3 The diagram shown illustrates the relationship between the DIP switch configuration and the PWM duty cycle of the present invention, further illustrating the preset control logic of the main controller.

[0037] The main controller calculates the base PWM duty cycle based on the duty cycle equation Y=KX, where Y is the PWM duty cycle, X is the analog voltage signal from the Vsp interface, and K is a preset constant. In this embodiment, K=15, i.e., Y=15X. For example, when Vsp=3.0V, the base duty cycle Y=45%; when Vsp=5.0V, the base duty cycle Y=75%.

[0038] like Figure 3As shown, the velocity offset mode includes seven effective modes and one hold mode, each effective mode corresponding to a preset duty cycle offset ratio: 000 (Standard Mode): Duty cycle offset ratio is 0%, final duty cycle = Y; 001 (High-speed mode): Duty cycle offset is +10%, final duty cycle = Y + 10%; 010 (Ultra-high-speed mode): Duty cycle offset ratio is +15%, final duty cycle = Y + 15%; 011 (Turbo Mode): Duty cycle offset is +20%, final duty cycle = Y + 20%; 100 (Low Speed ​​Mode): Duty cycle offset is -10%, final duty cycle = Y - 10%; 101 (Ultra-low speed mode): Duty cycle offset ratio is -15%, final duty cycle = Y - 15%; 110 (Silent Mode): Duty cycle offset is -20%, final duty cycle = Y - 20%; 111 (Hold Mode): Maintains the offset value of the previous effective speed offset mode unchanged. When 111 is detected during system power-on initialization, it is processed as 000 (Standard Mode).

[0039] The main controller clamps offset results that exceed the preset maximum duty cycle or are below 0%.

[0040] Example 5: Relay Safety Power-On Sequence The following is combined Figure 2 The schematic diagram of the operation principle of the present invention further illustrates the controlled power-on timing of relays K1 and K2. Figure 2 The signal flow of the high-voltage control path is shown in the figure: host computer - Vsp - MCU - K1 / K2 coil - external power supply to the fan.

[0041] Both relays K1 and K2 are normally open relays, remaining open during system power-on initialization, ensuring no power is supplied to the fan's high-voltage side. The MCU core unit selectively activates either relay K1 or K2 only upon detecting a valid analog speed command voltage signal, based on the high-voltage output type set by DIP switch SW1. When the high-voltage output type determined by the DIP switch is AC high voltage, the MCU core unit drives the relay K1 to engage, and conducts the external AC power to the high-voltage terminal of the fan through CN1 and CN3. When the DIP switch determines the high-voltage output type as DC high voltage, the MCU core unit drives the relay K2 to engage, converting the external DC power supply CN1 into a DC voltage of 310V internally, which is then conducted to the high-voltage terminal of the fan via CN9.

[0042] The controlled power-on sequence, which first detects the Vsp and then conducts the high-voltage power, ensures that the fan will not start unexpectedly without a speed command, and at the same time achieves physical isolation between the high-voltage circuit and the low-voltage control circuit.

[0043] Example 6: Wind Turbine Drive Compatibility Method with Standardized Interface The following is combined Figure 2 The schematic diagram of the operation principle of the present invention is shown, which further illustrates the specific process of the wind turbine drive compatibility method of the present invention, including: steps 1 to 7.

[0044] Step 1, Low Voltage Power-On and Configuration Identification: The general-purpose fan drive module receives low-voltage DC power from the host computer motherboard through the Vcc interface of CN2, and supplies power to the control circuit after DC-DC conversion on the board; the MCU core unit reads all the positions of the DIP switch SW1 to determine the output feedback frequency division ratio, input feedback frequency division ratio, high voltage output type and speed offset mode.

[0045] Step 2, Speed ​​Command Reception Step: The MCU of the driver module receives the analog speed command voltage signal output by the host computer motherboard through the Vsp interface of CN2.

[0046] Step 3, High Voltage Analysis Step: After the main controller detects a valid analog speed command voltage signal, it drives the corresponding relay type (K1 or K2) according to the high voltage output type determined by the DIP switch.

[0047] Step 4: PWM duty cycle calculation steps: The main controller calculates the basic PWM duty cycle according to the preset control logic (Y=KX), and adds the corresponding duty cycle offset according to the speed offset mode determined by the DIP switch. The offset results that exceed the preset maximum duty cycle or are lower than 0% are clamped.

[0048] Step 5, Motor Drive Steps: The main controller outputs the final PWM signal and activates the final relay to output high voltage to the fan to drive the fan to operate.

[0049] Step 6: Two-stage speed feedback processing steps: The main controller receives the original FG pulse signal from the fan (via CN5), performs the first-stage frequency division and conversion according to the input feedback frequency division ratio to obtain the internal speed signal for closed-loop speed regulation, and then performs the second-stage frequency division and conversion according to the output feedback frequency division ratio to obtain the feedback pulse format that conforms to the host computer motherboard protocol.

[0050] Step 7, Feedback Signal Forwarding Step: The main controller forwards the FG feedback pulse signal, which has been processed in two stages, to the host computer motherboard through the FG interface of the weak current interface CN2, so that the host computer motherboard can know the actual speed of the fan and form a closed loop.

[0051] Example 7: Comprehensive Working Process The following is combined Figures 1 to 3 This further illustrates the complete working process of the fan drive device of the present invention in a commercial air conditioning system.

[0052] Scenario: The main control board (host computer) of a commercial air conditioning system has been finalized in hardware, with reserved analog voltage output ports, pulse input ports, and 15Vdc power output ports, but no fan drive circuit has been designed. Now, this drive module is used to drive a newly selected DC brushless fan.

[0053] System Connections (see) Figure 1 ): Host computer motherboard-CN2: Analog output port connected to Vsp (0~6.5Vdc), pulse input port connected to FG, 15Vdc power supply connected to Vcc, and GND connected in total; External AC power supply - CN1: 220Vac connection; CN3-Fan: Connect the power line to the fan power input terminal; CN5-Fan: 12Vdc connects to the fan Hall power supply, FG connects to the fan feedback signal line, PWM connects to the fan control signal line, GND is the common ground; SW1 DIP switch settings: Dip 1=0 (output 4 PPR), Dip 2=1 (input 29 PPR), Dip 3=0 (K1 output AC220V), Dip 4-6=001 (high-speed mode).

[0054] Work process (see) Figure 2 ): Step 1, Power-on Initialization: Upon system power-on, the host computer supplies 15Vdc power to the driver module via the Vcc pin of CN2. This 15Vdc power is then converted to 5V via DC-DC conversion on the board to power the MCU core unit. The MCU reads all switches on SW1: Output divider ratio = 4 PPR, Input divider ratio = 29 PPR, High voltage type = AC220V, Speed ​​offset mode = High speed mode. K1 and K2 remain open; the fan is not powered.

[0055] Step 2, Start-up: The host computer outputs 3.0Vdc to the Vsp pin of CN2 via the control software. After the MCU detects a valid Vsp, it calculates the base duty cycle Y=45% according to Y=15X. After adding the high-speed mode offset +10%, the final duty cycle is 55%. The MCU outputs a PWM signal through CN5, which drives relay K1 to engage. 220Vac is then connected to the fan through K1, and the fan is powered on and operates at a 55% duty cycle.

[0056] Step 3, Closed-loop speed control and two-stage FG processing: The user adjusts Vsp from 3.0V to 5.0V. The MCU recalculates: base duty cycle Y = 75%, final duty cycle = 75% + 10% = 85%, and the fan accelerates.

[0057] The raw pulse output from the fan is input to the MCU via the FG pin of CN5. The MCU performs two stages of processing: Level 1: Convert the original FG pulse into an internal speed signal according to the 29 PPR set by Dip 2, for its own closed-loop speed regulation; Second stage: Convert the internal speed signal into the host computer protocol format according to the 4 PPR set by Dip 1, and forward it to the host computer via the FG pin of CN2.

[0058] The host computer reads the FG pulse frequency to obtain the current actual speed and completes the closed loop.

[0059] Step 4, Mode Switching: The user changes Dip 4-6 from 001 to 110 (silent mode). The MCU reads the new value, and the final duty cycle is 75% - 20% = 55%, causing the fan to slow down. If the user dials it back to 111, the MCU maintains the silent mode offset value of -20%; if it dials it to 010, the final duty cycle is 75% + 15% = 90%, causing the fan to speed up.

[0060] Step 5, Fault Protection: If the fan stalls and causes the FG pulse to be lost, and the MCU does not receive the FG within the detection cycle, the red LED will flash at 1Hz and latch. Even if the FG recovers, the red light will still flash, requiring a power-off reset. If the host computer abnormally outputs Vsp=8.0V (exceeding the protection threshold), the green LED will flash, and the PWM will be forcibly shut down. After Vsp falls back below the recovery threshold, the green LED will return to a constant light, and the PWM will automatically recover.

[0061] The technical solution of this embodiment, by setting a universal fan drive module between the mainboard of the electrical equipment and the fan, allows the mainboard to provide only three-wire interfaces (Vsp, FG, Vcc) via CN2, enabling compatibility with different models of DC fans without hardware modification. This achieves modularity, plug-and-play functionality, and independent upgrades for the fan drive. Simultaneously, physical isolation between strong and weak currents is achieved through K1 / K2 dual relays, and the MCU's autonomous closed-loop control releases upper-computer resources. Local multi-level fault protection ensures safe system operation. When it is necessary to replace the fan or upgrade functions, only the DIP switches or the drive module need to be adjusted; the upper-computer mainboard does not require modification of the original hardware, significantly reducing the system's total lifecycle cost.

[0062] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A fan drive device with a standardized interface, characterized in that, include: A universal fan drive module is located between the host computer motherboard and the fan. The general-purpose wind turbine drive module is provided with a low-voltage area and a high-voltage area. The high-voltage area is provided with a high-voltage interface, relay K1 and relay K2. The low-voltage area is provided with a low-voltage interface CN2, an MCU core unit, a DIP switch SW1 and a wind turbine interface CN5. The low-voltage interface CN2 is used to receive the analog speed command voltage signal output by the host computer motherboard, output the processed fan speed feedback pulse signal to the host computer motherboard, and receive the low-voltage DC low voltage provided by the host computer motherboard to power the control circuit of the drive module. The MCU core unit includes a main controller, a two-level FG frequency division processing unit, and a multi-level fault protection unit. The main controller is used to receive the analog speed command voltage signal and calculate the PWM duty cycle according to the preset control logic. After adjusting the duty cycle offset according to the speed offset mode set by the DIP switch, it outputs the PWM drive signal. The two-stage FG frequency division processing unit is used to divide and convert the original FG pulse of the fan to obtain the internal speed signal, and convert the internal speed signal into a feedback pulse format that conforms to the host computer motherboard protocol. The multi-level fault protection unit is used to perform fault detection and protection; The contacts of relay K1 are connected in series between the external AC power supply and the high-voltage terminal of the fan. The contacts of relay K2 are connected in series between the external AC power supply and the high-voltage terminal of the fan through an internal circuit. The coils of relay K1 and relay K2 are electrically connected to the I / O port of the MCU core unit. The MCU core unit controls the relay K1 or relay K2 to be energized according to the DIP switch settings. The DIP switch SW1 is used to manually set the operating parameters of the drive module without the need for software tools.

2. The fan drive device with a standardized interface according to claim 1, characterized in that, The low-voltage interface CN2 includes: The Vsp interface is used to receive the analog speed command voltage signal output by the host computer motherboard; The FG interface is used to output the processed fan speed feedback pulse signal to the host computer motherboard. The Vcc interface is used to receive low-voltage DC power from the host computer motherboard to power the control circuit of the drive module. The GND interface shares a common ground with the host computer. The Vsp, FG, and Vcc interfaces coexist on the drive module, forming a three-wire standardized interface that simultaneously receives voltage commands, provides feedback speed pulses, and obtains low-voltage power supply.

3. The fan drive device with a standardized interface according to claim 1, characterized in that, The two-stage FG frequency division processing unit includes: The first-level frequency division processing unit is used to perform frequency division and conversion on the original FG pulse of the fan according to the input feedback frequency division ratio to obtain the internal speed signal for closed-loop speed regulation. The second-level frequency division processing unit is used to convert the internal speed signal into a feedback pulse format that conforms to the host computer motherboard protocol according to the output feedback frequency division ratio.

4. The fan drive device with a standardized interface according to claim 1, characterized in that, The multi-level fault protection unit includes: The FG feedback-free fault protection circuit is used to provide a fault alarm indication and lock the fault state until power is cut off and reset when the FG feedback pulse of the fan is detected to be lost. The Vsp overvoltage fault protection circuit is used to forcibly shut down the PWM output when the analog speed command voltage signal is detected to exceed the preset protection threshold, and automatically restore normal output when the voltage signal falls back to below the recovery threshold.

5. A fan drive device with a standardized interface according to claim 1, characterized in that, The main controller calculates the basic PWM duty cycle according to the duty cycle equation Y=KX, where Y is the PWM duty cycle, X is the analog speed command voltage signal, and K is a preset constant; the speed offset mode includes seven effective modes and one hold mode, each effective mode corresponding to a preset duty cycle offset ratio; the hold mode maintains the offset value of the previous effective speed offset mode unchanged. When the system is powered on and initialized, the hold mode is detected, and the system is processed according to the standard mode.

6. A fan drive device with a standardized interface according to claim 1, characterized in that, The DIP switch SW1 has multiple positions for setting the output feedback division ratio, input feedback division ratio, high-voltage output type, and speed offset mode. Relays K1 and K2 are both normally open relays, remaining open during system power-on initialization. The MCU core unit selectively drives relay K1 or K2 to engage only after detecting a valid analog speed command voltage signal, based on the high-voltage output type set by the DIP switch. The low-voltage area of ​​the general-purpose fan drive module also includes a communication expansion interface CN8, which supports communication-type fans or customized communication protocols.

7. A wind turbine drive compatibility method with a standardized interface, characterized in that, Includes the following steps: S1 Low Voltage Power-On and Configuration Identification Steps: The general-purpose fan drive module receives low-voltage DC power from the host computer motherboard to power its control circuit, and reads all the DIP switch positions to determine the operating parameters. S2 speed command receiving steps: The MCU of the drive module receives the analog speed command voltage signal output by the host computer motherboard through the Vsp interface; S3 High Voltage Analysis Step: After the main controller detects a valid analog speed command voltage signal, it drives the corresponding relay type according to the high voltage output determined by the DIP switch. S4 PWM duty cycle calculation steps: The main controller calculates the basic PWM duty cycle according to the preset control logic, and adds the corresponding duty cycle offset according to the speed offset mode determined by the DIP switch, and clamps the offset results that exceed the preset range. S5 motor drive steps: The main controller outputs the final PWM signal and activates the final relay to output high voltage to the fan to drive the fan to operate; S6 Speed ​​Feedback Two-Level Processing Steps: The main controller receives the original FG pulse signal from the fan, performs a first-level frequency division calculation according to the input feedback frequency division ratio to obtain the internal speed signal for closed-loop speed regulation, and then performs a second-level frequency division calculation according to the output feedback frequency division ratio to obtain the feedback pulse format that conforms to the host computer motherboard protocol. S7 Feedback Signal Forwarding Step: The main controller forwards the FG feedback pulse signal, which has been processed by the two stages, to the host computer motherboard through the FG interface of the weak current interface CN2, so that the host computer motherboard can know the actual speed of the fan and form a closed loop.

8. The wind turbine drive compatibility method with a standardized interface according to claim 7, characterized in that, In step S4, the duty cycle equation is Y=KX, where Y is the PWM duty cycle, X is the analog speed command voltage signal, and K is a preset constant. The speed offset mode includes seven effective modes and one holding mode: the duty cycle offset ratio of the standard mode is 0%; the duty cycle offset ratios of the high-speed mode, ultra-high-speed mode, and turbine mode are +10%, +15%, and +20%, respectively; the duty cycle offset ratios of the low-speed mode, ultra-low-speed mode, and silent mode are -10%, -15%, and -20%, respectively, and the current mode is confirmed by the DIP switch; the holding mode maintains the offset value of the previous effective speed offset mode unchanged; when the system is powered on and initialized, if the speed offset mode is detected as the holding mode, it is processed according to the standard mode; in step S3, when the high-voltage output type determined by the DIP switch is AC high voltage, the MCU drives the relay K1 to engage to conduct external AC power to the high-voltage terminal of the fan; when the high-voltage output type determined by the DIP switch is DC high voltage, the MCU drives the relay K2 to engage.

9. A wind turbine drive compatibility method with a standardized interface according to claim 7, characterized in that, The method further includes: S8 FG no-feedback fault handling step: when no FG feedback pulse signal is received from the fan within a preset detection period, an FG no-feedback fault is determined to have occurred, a fault alarm indication is given and the fault state is latched; even if the FG signal returns to normal during the fault latching period, the fault state is still maintained; fault recovery can only be achieved by disconnecting the system power supply and reconnecting it; S9 Vsp overvoltage fault handling step: when the voltage signal of the Vsp interface is detected to exceed a preset protection threshold, a Vsp overvoltage fault is determined to have occurred, a fault alarm indication is given and the PWM output is forcibly shut down to stop the fan; when the Vsp voltage drops below the preset recovery threshold, the fault state is automatically released and normal PWM output is restored without power-off reset.

10. A wind turbine drive compatibility method with a standardized interface according to claim 7, characterized in that, The method further includes a communication extension step S10: communicating with the fan via the communication extension interface of the drive module to support a communication-type fan or a customized communication protocol; in S6, the first-level frequency division conversion performs frequency division conversion on the FG original pulse according to the input feedback frequency division ratio set by the DIP switch, and the second-level frequency division conversion converts the internal speed signal into the feedback pulse format according to the output feedback frequency division ratio set by the DIP switch. The input feedback frequency division ratio and the output feedback frequency division ratio are independent of each other and can be configured independently by the DIP switch.

Images