A data processing low-power consumption control method and system based on clock domain adjustment

Abstract

This invention relates to the field of low-power design technology for digital signal processors, and discloses a low-power control method and system for data processing based on clock domain adjustment. The method includes acquiring real-time operating data of each functional module within the processor, classifying the load status of each module by load classification; extracting the interaction timestamps between modules, obtaining asynchronous timing characteristics through timing analysis, and classifying idle modules awaiting preceding data into busy modules on critical paths; extracting historical clock flip characteristics of modules to generate clock adjustment instructions, calculating the frequency switching transition time, and performing phase compensation on overtime delay instructions to obtain differentiated clock control signals; inputting the control signals into a clock gating unit to shut down the clock of idle modules and increase the frequency of busy modules to achieve low-power results. This method achieves fine-grained clock adjustment at the module level, balancing real-time performance and low-power benefits, and ensuring the safety of frequency switching timing.

Description

Technical Field

[0001] This invention relates to the field of low-power design technology for digital signal processors, and in particular to a low-power control method and system for data processing based on clock domain modulation. Background Technology

[0002] Multi-core CPUs are core computing components in real-time radar signal processing and edge intelligent computing scenarios. Their dynamic power consumption mainly comes from the continuous flipping of the clock network, with clock tree power consumption accounting for 30% to 50% of the chip's total dynamic power consumption. When the various functional modules within the processor work collaboratively in a pipeline, they exhibit inherent asynchronous timing characteristics: the data interaction rhythm, computational load, and idle period of different modules change dynamically with the task. Idle modules waiting for data from the preceding stage continue to flip their clocks, generating ineffective power consumption, while critical path computing modules are constrained by a globally unified clock, unable to increase their frequency as needed to compress computation latency. As edge devices increasingly demand higher battery life and thermal design capabilities, fine-grained clock domain tuning has become a core direction for processor low-power optimization.

[0003] Existing low-power solutions mostly employ global dynamic voltage and frequency regulation or chip-level clock gating, adjusting the overall chip frequency uniformly by monitoring the overall chip utilization, or shutting down the main clock tree when the chip is in sleep mode. However, global unified regulation cannot detect module-level load differences, nor can it independently shut down the clock or increase the frequency for a single module, easily leading to idle modules consuming power while busy modules experience performance limitations. Existing local clock regulation schemes do not consider the transition delay of switching across clock domains, and direct frequency adjustment can easily cause timing violations leading to pipeline interruptions. Furthermore, they lack the ability to accurately identify asynchronous timing of modules, making it impossible to accurately distinguish between idle and busy modules, and the adjustment accuracy is insufficient to meet real-time processing requirements. Existing core-level frequency regulation schemes only support coarse-grained core regulation, failing to identify load differences among internal core functional modules and not addressing switching timing safety issues.

[0004] In summary, existing technologies cannot achieve fine-grained, timing-safe low-power clock domain control for asynchronous loads of multi-core CPU functional modules. Summary of the Invention

[0005] This invention provides a low-power control method and system for data processing based on clock domain adjustment, in order to solve the problem in the prior art that it is impossible to achieve fine-grained, timing-safe low-power control of the clock domain for asynchronous loads of multi-core central processing unit functional modules.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a low-power control method for data processing based on clock domain modulation, comprising: The real-time operating data of each functional module inside the digital signal processor is acquired, and the load status is classified according to the real-time operating data to obtain the current load status of each functional module. Based on the current load status, extract the timestamp information of data interaction between each functional module, obtain the asynchronous timing characteristics between modules through timing analysis, and determine the idle modules waiting for the previous level data and the busy modules in the critical path calculation based on the asynchronous timing characteristics. Historical clock flip features are extracted for the idle module and the busy module, corresponding clock adjustment instructions are generated, the state transition time of the frequency switching process is calculated, and if the state transition time is greater than the preset switching delay threshold, clock phase compensation is performed to obtain a differentiated clock control signal. The differentiated clock control signal is input into the preset clock gating unit to perform a clock shutdown operation on the idle module and a local frequency boost operation on the busy module, thereby obtaining a low-power control result.

[0007] Secondly, the present invention provides a low-power control system for data processing based on clock domain adjustment, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the low-power control method for data processing based on clock domain adjustment as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the data processing low-power control method based on clock domain modulation as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention performs time-series analysis by extracting the timestamp information of data interaction between functional modules. Based on asynchronous time-series characteristics, it accurately divides idle modules waiting for previous data and busy modules calculating critical paths, realizing fine-grained perception of module-level operating status. This solves the problem that the existing global unified adjustment method cannot identify module load differences, resulting in idle modules consuming power ineffectively and busy modules having limited performance.

[0010] (2) This invention generates differentiated clock adjustment instructions by extracting the historical clock flip characteristics of the module, calculates the state transition time of frequency switching and performs clock phase compensation for overtime delay scenarios, thereby achieving timing safety assurance for cross-clock domain switching and solving the problem that existing local clock adjustment does not consider the switching transition delay, which is prone to timing violations and pipeline interruption.

[0011] (3) By inputting a compensated differential clock control signal to the clock gating unit, the present invention performs clock shutdown on idle modules and local frequency boost on busy modules, thereby achieving a dynamic balance between power consumption and performance and solving the problem that existing low-power solutions cannot balance low-power benefits and real-time computing performance requirements. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating a low-power control method for data processing based on clock domain adjustment provided in the first embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides a low-power control method for data processing based on clock domain adjustment, comprising the following steps: In step S11, real-time operating data of each functional module within the digital signal processor is acquired, and the real-time operating data is classified by load status to obtain the current load status of each functional module, including: Extract instruction cycles and memory access frequencies from real-time running data, construct a multi-dimensional running feature set, and perform dimensionality reduction processing on the running feature set to obtain the core feature vector; The core feature vector is classified into states to obtain a classification label sequence. The state mapping table is then queried based on the classification labels to obtain the current load state of each functional module.

[0015] It should be noted that this embodiment is based on a 28nm CMOS process digital signal processor, and all parameters are calibrated based on silicon pre-simulation and typical tape-out data of this process node. The annotation samples used for the initial parameter calibration are all generated by silicon pre-functional simulation, covering full load, full temperature range of -40℃ to 125℃, and ±10% core voltage full voltage scenarios. Those skilled in the art can reproduce the sample set and calibrate the parameters through the same simulation process. The values ​​can be adjusted according to the target process node during actual tape-out.

[0016] Real-time operational data is acquired through the processor's built-in hardware performance counter. The 10-microsecond acquisition cycle is determined based on the sampling capability and real-time control requirements of the hardware performance counter under the 28nm process. The acquisition range covers all functional modules in the pipeline with independent clock domains, including the Fast Fourier Transform module, pulse compression module, constant false alarm rate (CFAR) detection module, and target tracking module. No additional hardware sampling circuit is required; data acquisition can be completed by reusing the processor's native performance counter unit. In addition to instruction cycle and memory access frequency, the multi-dimensional operational feature set includes two auxiliary features: cache hit rate and bus utilization rate. These four features collectively reflect the actual operational load of the module. The instruction cycle is the number of instructions completed by the module per unit time; the memory access frequency is the number of cache accesses per unit time; the cache hit rate reflects the module's data locality; and the bus utilization rate reflects the module's utilization of the on-chip bus.

[0017] The load state classification adopts a two-layer architecture: background calibration and real-time execution. The calibration layer runs during processor idle time slots with a cycle of 1 millisecond; the execution layer runs during a 10-microsecond real-time control cycle. All calculations are basic arithmetic operations, and the power consumption of the control logic itself is negligible. The calibration layer uses the Z-Score method for feature standardization. During each update, the feature values ​​of all samples within 1 millisecond are accumulated and divided by the number of samples to obtain the feature mean. Then, the sum of squares of the differences between each sample and the mean is calculated, divided by the number of samples, and the square root is taken to obtain the feature standard deviation. During standardization, the feature value is subtracted from the mean and then divided by the standard deviation to unify features with different dimensions into a distribution with a mean of 0 and a variance of 1. The mean and standard deviation are updated with new samples.

[0018] Dimensionality reduction is achieved using feature-weighted fusion. Weights are determined based on the mutual information statistics of 1 million labeled samples: the mutual information between instruction cycle and load state is the highest, contributing the most to load differentiation, and is weighted at 0.4; memory access frequency is second, with a weight of 0.3; cache hit rate reflects the module's data waiting state, with a weight of 0.2; and bus occupancy has the lowest correlation with load, with a weight of 0.1. The four standardized features are multiplied by their corresponding weights and then summed to obtain a one-dimensional core feature vector, completing the dimensionality reduction from four dimensions to one dimension. This retains over 95% of the load differentiation information. The weights are fine-tuned by the calibration layer each round based on the mutual information statistics of new samples.

[0019] State classification is achieved using a dual-threshold comparison, with an initial idle threshold of 20 and a heavy load threshold of 70, calibrated based on simulation results of a bimodal distribution of module load under 28nm process technology. Core feature values ​​less than 20 are classified as idle, values ​​greater than or equal to 20 and less than or equal to 70 as light load, and values ​​greater than 70 as heavy load. The core features of the three load classes exhibit a bimodal distribution with clear class boundaries, achieving a classification accuracy of 97%. During each calibration layer update, the core feature range of 0 to 100 is divided into 100 equal-width bins. The number of samples within each bin is counted, and the two lowest-count valleys are found and updated as new idle and heavy load thresholds, eliminating the need for complex model training. When the histogram has only one or zero valid valleys, the valid classification thresholds from the previous round are retained, and the threshold is marked as frozen. Once the histogram shows two or more valid valleys and stabilizes for three consecutive calibration cycles, the thresholds are automatically unfrozen and dynamic updates resume.

[0020] After each calibration layer run, the updated feature mean, standard deviation, fusion weights, and classification threshold are solidified into the latest state mapping table. This table is replaced with the old table via atomic operations for the real-time layer to query, ensuring a seamless update process without state interruptions. The initial state mapping table is a label mapping table solidified in on-chip ROM after pre-training. Label 0 corresponds to the idle state, label 1 to the lightly loaded state, and label 2 to the heavily loaded state. The real-time layer can directly obtain the corresponding load state by querying the mapping table. The mapping table is dynamically updated every 1 millisecond to adapt to changes in load distribution. The classification confidence is the relative distance of the core feature value to the nearest classification threshold. The farther the feature value is from the threshold, the higher the confidence. The confidence threshold is set to 0.8: when the distance of the feature value from the nearest threshold exceeds 80% of the corresponding interval length, the classification accuracy can reach 99%; when the distance is less than 20%, the accuracy is less than 70%. Samples with a confidence below 0.8 are marked as unobservable states and are treated as heavily loaded by default. The load state is updated only after three consecutive cycles of consistent classification results to avoid state instability. The setting of 100 cold start cycles is determined based on the simulation of the load statistical convergence speed under the 28nm process. When there is no historical data during the cold start phase, it is marked as overloaded by default to avoid accidental clock shutdown and startup failure. After running 100 acquisition cycles to accumulate enough data, it automatically switches to the threshold classification results dynamically updated by the calibration layer.

[0021] Specifically, the real-time execution layer triggers a status acquisition every 10 microseconds. It collects real-time operational data from each functional module using hardware performance counters, extracting four metrics per unit time: instruction execution count, memory access count, cache hit count, and bus occupancy duration. A multi-dimensional operational feature set is constructed for each module. The latest status mapping table is directly queried, and standardized parameters, fusion weights, and classification thresholds are read. The four features are first normalized, then multiplied by their respective weights and summed to obtain a one-dimensional core feature vector. This vector is then compared with two classification thresholds to obtain classification labels. Classification confidence is calculated using the relative distance between the features and the thresholds. The status mapping table is queried using the classification labels as indexes, mapping the labels to three actual load states: light load, heavy load, and idle. The results are then sent to the next stage for time-series analysis. Samples with a confidence score below 0.8 are marked as unobservable and treated as heavy load by default. The status is updated only after three consecutive periods of consistent classification to avoid frequent jumps. The background calibration layer triggers an update every 1 millisecond, completing the mapping table refresh in four steps: First, it collects four-class feature samples from all modules within the past 1 millisecond, accumulates the sample values ​​and squared values ​​for each feature, calculates the new feature mean and standard deviation, and updates the standardization parameters; Second, it calculates the mutual information between each feature and the labeled load label, and fine-tunes the fusion weights of the four features according to the mutual information ratio; Third, it performs a 100-bin histogram statistical analysis on the core feature values ​​of all samples in the range of 0 to 100, traverses all bins to find the two valleys with the fewest samples, and updates them as the new classification thresholds; Fourth, it writes the new parameters into the new state mapping table, atomically replacing the old table for the real-time layer to query. The entire update process only uses addition, multiplication, and comparison operations, runs in the processor's idle time slots, and does not interrupt the real-time control flow.

[0022] For example, in a radar signal processing pipeline, the real-time layer acquires the operating data of the Fast Fourier Transform module every 10 microseconds, obtaining an instruction cycle of 50,000 times per second, a memory access frequency of 20,000 times per second, a cache hit rate of 92%, and a bus utilization rate of 78%, constructing a four-dimensional feature set. Querying the current mapping table and performing normalized weighting yields a core feature value of 86, a distance of 16 from the overload threshold of 70, an overload interval length of 30, and a relative distance of approximately 0.92, corresponding to a classification confidence score of 0.92, which corresponds to label 2. Querying the mapping table shows that label 2 is in an overloaded state; therefore, this module is marked as overloaded, triggering subsequent timing analysis. Data collected from the target tracking module shows an instruction cycle of 2000 times per second, a memory access frequency of 500 times per second, a cache hit rate of 35%, and a bus utilization rate of 12%. The weighted result yields a core feature value of 12, a distance of 8 from the idle threshold of 20, an idle interval length of 20, and a relative distance of 0.4 (i.e., a classification confidence of 0.75), which is below the 0.8 threshold. Therefore, it is marked as unobservable and treated as overloaded by default. If the classification is consistently labeled 0 with a confidence score above 0.8 for three consecutive cycles, it is ultimately marked as an idle candidate module. The calibration layer collects new samples in the background every 1 millisecond. When the load distribution changes, the weights and thresholds are automatically updated. The real-time layer can directly look up tables without participating in statistical calculations.

[0023] In step S12, timestamp information of data interaction between functional modules is extracted based on the current load state, and asynchronous timing characteristics between modules are obtained through timing analysis, including: Extract the data inflow timestamps and data outflow timestamps from each functional module to obtain a timestamp sequence, and perform alignment processing on the timestamp sequence to obtain a standardized time series sequence; The standardized time sequence is compared point by point to obtain the transmission delay value between modules. The transmission delay values ​​that exceed the preset delay threshold are clustered to obtain the asynchronous time sequence characteristics between modules.

[0024] It should be noted that the data inflow timestamp is the moment the data packet enters the module's input buffer, and the data outflow timestamp is the moment the data packet is processed and written to the output buffer. Both types of timestamps are automatically marked by an on-chip 64-bit global time counter with a precision of 1 nanosecond. Each data packet header carries a unique 16-bit sequence number, which is transmitted along with the data in the pipeline. The timestamp is bound to the corresponding sequence number during timestamp marking. The out-of-order range of the on-chip bus scheduling does not exceed three consecutive packet bits. Therefore, there is no need for complex dynamic time warping algorithms for sequence alignment. The inflow and outflow timestamps of the same data packet can be directly matched using the unique sequence number carried by the data packet. The matching process is a hardware lookup table by sequence number, with a latency of less than 5 nanoseconds and no computational overhead. The alignment window is the most recent 1000 data packets, and the alignment error is 0.

[0025] The transmission delay value is the difference between the outgoing and incoming timestamps of the same data packet, calculated directly packet-by-packet by a hardware subtractor, reflecting the time consumed by the module to process a single packet of data. The preset delay threshold is set to 40 microseconds, determined statistically based on the maximum processing delay per packet in a typical radar pulse processing pipeline under a 200MHz base clock. Under normal full load, the module's single-packet processing delay is below 40 microseconds; delays exceeding this threshold are considered abnormal waiting delays and are the focus of cluster analysis. This cluster analysis employs lightweight binning statistics, eliminating the need for iterative calculations. Clustering features are obtained through incremental statistics using a fixed-length sliding window. The sliding window size is fixed at the most recent 1000 data packets, with a single-packet processing cycle of 10 microseconds, corresponding to a 10-millisecond time window. The sliding step size is one data packet. Each new data packet automatically discards the oldest data packet within the window, updating the cluster statistics packet-by-packet. Clustering yields three core asynchronous timing features: the average delay exceeding the threshold (arithmetic mean of all delays exceeding the threshold within the window), reflecting the overall level of abnormal waiting by the module; the maximum blocking delay (maximum delay exceeding the threshold within the window), reflecting the longest idle time of the module; and the proportion of delays exceeding the threshold (ratio of packets exceeding the threshold within the window to the total number of packets in the window), reflecting the frequency of idle time by the module. These three features together constitute the asynchronous timing features between modules. All statistics are implemented using hardware counters; single-step updates require only addition and comparison operations, eliminating iterative clustering overhead.

[0026] Specifically, the system filters modules with heavy or light loads, extracts the inflow timestamps, outflow timestamps, and corresponding packet sequence numbers of the most recent 1000 data packets, and matches the two timestamps of the same data packet by sequence number to obtain a standardized time sequence of consistent length. This sequence can cover up to 3 packet bits of out-of-order range on the bus, eliminating timestamp mismatch issues. The system subtracts from each packet to obtain the single-packet transmission delay value, filters out abnormal delay values ​​exceeding a 40-microsecond threshold, and incrementally updates the cluster statistics using a sliding window. When a new data packet enters the window, if the delay exceeds the threshold, this delay value is added to the total over-threshold delay. The sum is divided by the current number of over-threshold packets to obtain the average over-threshold delay. This delay is compared with the current maximum blocking delay of the window; if it is greater than the current maximum value, the maximum delay is updated. The over-threshold count is incremented by 1, and the over-threshold count is divided by the fixed total number of packets in the window (1000) to obtain the over-threshold delay percentage. When an old data packet leaves the window, if its latency exceeds a threshold, the corresponding value is subtracted from the total over-threshold latency, and the average over-threshold latency is recalculated. If the leaving data packet represents the maximum blocking latency of the current window, all over-threshold packets within the window are traversed to update the maximum latency. If the packet's latency exceeds the threshold, the over-threshold count is decremented by 1, and the over-threshold latency percentage is recalculated. Finally, three clustering statistics—average over-threshold latency, maximum blocking latency, and over-threshold latency percentage—are obtained, representing the asynchronous timing characteristics between modules, and are then fed into the subsequent module partitioning logic.

[0027] For example, when the Fast Fourier Transform module is determined to be in an overload state, the inflow timestamp, outflow timestamp, and sequence number of the most recent 1000 radar echo data packets are extracted. Due to the bus scheduling having a maximum of 3 packet bits out of order, the outflow timestamp sequence length is 997. 1000 one-to-one time pairs are obtained by directly looking up the sequence number in the table. The single packet delay range is calculated to be 32 microseconds to 92 microseconds. 327 abnormal delay values ​​exceeding the 40 microsecond threshold are filtered out. The cluster statistics are updated packet by packet using a sliding window. When a new over-threshold packet enters, the delay value is accumulated, the maximum value is compared and updated, and the count is incremented by one. When an old over-threshold packet leaves, the corresponding delay is subtracted, the maximum value is updated if necessary, and the count is decremented by one. The total out-of-threshold delay within the final window is 17004 microseconds. Dividing this by 327 out-of-threshold packets yields an average out-of-threshold delay of approximately 52 microseconds. Traversing the out-of-threshold packets reveals a maximum blocking delay of 92 microseconds. Dividing the out-of-threshold count of 327 by the total number of packets of 1000 yields an out-of-threshold delay ratio of 32.7%. These three cluster statistics represent the asynchronous timing characteristics between the Fast Fourier Transform module and the subsequent Constant False Alarm Rate (CFAR) detection module, reflecting abnormal waiting and idling conditions of the modules.

[0028] Based on the asynchronous timing characteristics, idle modules waiting for preceding data and busy modules performing critical path computations are identified, including: The current load difference value is obtained by weighted calculation based on the module blocking duration and resource utilization rate in the asynchronous timing characteristics. If the load difference value is greater than the preset load difference threshold, the topology execution graph of the functional module is parsed to obtain the module dependency relationship, and the state is divided in combination with the real-time throughput of the module to determine the idle module and the busy module.

[0029] It should be noted that the module blocking duration is the maximum blocking delay among asynchronous timing features, reflecting the longest idle time the module waits for data from the preceding stage; the resource utilization rate is the proportion of the module's current arithmetic logic unit usage, directly collected through hardware performance counters. The load difference value is calculated using a linear weighted average. Before weighting, the blocking duration and resource utilization rate are Min-Max linearly normalized. This is done by subtracting the historical minimum value of the feature from its current value, dividing by the difference between the historical maximum and minimum values, and finally multiplying by 100. This maps both types of features to a numerical range of 0 to 100, eliminating the influence of dimensional differences on the weighting result. The historical minimum and maximum values ​​used for normalization are updated every 1 millisecond by the calibration layer to adapt to dynamic changes in load distribution. With the blocking duration weight set to 0.6 and the resource utilization rate weight set to 0.4, based on Gini importance analysis of 100,000 simulation samples, it was determined that the blocking duration has a higher distinguishing effect on the idle state of the module. Statistically, the state classification accuracy under this weight combination can reach more than 95%. After normalization, the two features are multiplied by their corresponding weights and summed to obtain the load difference value in the range of 0 to 100.

[0030] The preset load difference threshold is fixed at 60, which is selected based on the ROC curve of 100,000 labeled samples in the pre-training phase. True positives (TP) are defined as samples whose classification results match the labeled labels, and false positives (FP) are defined as samples whose classification results do not match the labeled labels. This covers typical business modes such as radar search and tracking, as well as the entire operating range from -40℃ to 125℃ and ±10% core voltage fluctuation. At this threshold, the state division F1 value is the highest, and the misclassification rate across all scenarios is less than 3%, meeting the robustness design requirements. The topology execution graph is a directed acyclic pipeline graph statically stored in on-chip ROM during business process configuration. The topology is updated synchronously when the business process is reconfigured. Nodes in the graph represent functional modules, and directed edges represent data flow between modules. Module dependencies, critical path markers, and peak throughput parameters for each module are pre-stored. No runtime topology traversal calculation is required; the hardware directly reads the pre-stored markers to obtain module dependencies and critical path information without additional computational overhead.

[0031] The module's real-time throughput is the number of data packets processed by the module per unit time, directly counted by a hardware counter, reflecting the module's actual processing rate. Throughput thresholds are set based on the module's peak processing capacity: 10% of the peak capacity for idle modules and 70% for busy modules. These thresholds are based on the bimodal load distribution of the module under typical digital signal processor load scenarios, with the trough of the two load peaks serving as the threshold point. At this threshold, the distinction between idle and busy modules is highest. When throughput is below 10% of the peak, the module is essentially in an idling waiting state; when it is above 70% of the peak, the module is in a full-load computing state. The thresholds are dynamically updated by the calibration layer. State classification uses direct hardware logic judgment. When the load difference exceeds the threshold, the pre-stored critical path markers and real-time throughput are directly read. If the non-critical path is satisfied, the module waits for data from the preceding stage. Modules with throughput below 10% of the peak are marked as idle modules; modules satisfying critical paths and with throughput above 70% of the peak are marked as busy modules. The judgment logic only requires hardware AND / OR gates, with a latency of less than 3 nanoseconds. For modules that do not meet either the idle or busy judgment criteria, the current clock configuration remains unchanged until the next control cycle for reassessment.

[0032] Specifically, the maximum blocking delay is extracted from asynchronous timing characteristics as the module blocking duration. The resource utilization rate of the current module is collected, and the updated feature maximum / minimum value parameters from the calibration layer are read and subjected to Min-Max linear normalization, linearly mapping the blocking duration and resource utilization rate to a numerical range of 0 to 100. A linear weighted average is performed with a blocking duration weight of 0.6 and a resource utilization rate weight of 0.4 to obtain the current load difference value. A hardware comparator compares the load difference value with a preset threshold of 60. If the difference value is lower than the threshold, it indicates load balance among modules, and no clock adjustment is needed; if the difference value is higher than the threshold, it indicates significant load imbalance, triggering the module state partitioning process. The statically fixed topology execution graph pre-stored information is directly read to obtain module dependencies and critical path markings, eliminating the need for runtime topology traversal calculations. Real-time throughput data of each module is collected, and conditional judgments are made through hardware logic: modules waiting for preceding data, non-critical paths, and those with throughput below 10% of the peak are marked as idle modules; modules on critical paths and with throughput above 70% of the peak are marked as busy modules. A unique identifier list for each type of module is output and sent to the next stage.

[0033] For example, considering the asynchronous timing characteristics of the Fast Fourier Transform (FFT) and Constant False Alarm Rate (CFAR) detection modules, the maximum blocking delay of 85 microseconds is extracted as the blocking duration of the CFAR detection module. The historical minimum blocking duration is 0 microseconds, and the historical maximum is 100 microseconds. After Min-Max normalization, the value is 85. The current resource utilization rate of the CFAR detection module is collected as 85%, which is also normalized to 85. The load difference value is calculated according to weights, and it is 85, which is higher than the preset load difference threshold of 60, triggering state division. The pre-stored topology information of the radar signal processing pipeline is read, and the execution order is pulse compression, FFT, CFAR detection, and target tracking. Target tracking is a non-critical path module, while pulse compression, FFT, and CFAR detection are critical path modules. The throughput of each module was collected. The throughput of the target tracking module was only 8% of the peak value, which is below the 10% idle threshold. The throughput of the Fast Fourier Transform and Constant False Alarm Rate (CFAR) modules was 88% and 82% of the peak value, respectively, which is above the 70% busy threshold and located on the critical path. Therefore, the target tracking module was marked as an idle module waiting for data from the preceding stage, and the Fast Fourier Transform and CFAR modules were marked as busy modules for critical path calculation.

[0034] In step S13, historical clock flip features are extracted for the idle module and the busy module, and corresponding clock adjustment instructions are generated, including: Based on the historical clock flip records of the idle module and the busy module, the clock flip density of different modules is obtained by using a sliding window statistical method. Based on the clock flip density, the low-frequency active cycle characteristics of the idle module and the high-frequency duty cycle characteristics of the busy module are extracted. If the low-frequency active cycle characteristics are lower than a preset gating threshold, an idle clock gating instruction is generated. If the high-frequency duty cycle characteristics are higher than a preset boosting threshold, a busy frequency boosting instruction is generated. The two types of instructions together constitute the clock adjustment instruction.

[0035] It should be noted that the historical clock flip record records the number of level transitions of the module clock signal within the past 500 microseconds. This is collected through a rising edge counter of the clock management unit, with the counter incrementing by 1 on each rising edge of the clock. The sampling precision is 1 nanosecond. The 500-microsecond observation window covers a complete business processing cycle of a typical digital signal processor pipeline, which can fully reflect the clock activity pattern of the module. The window length is set based on the processing interval of a typical digital signal processor pipeline business, which is typically 400 to 600 microseconds. The window length selection is based on the autocorrelation analysis of clock activity, and the 500-microsecond window can cover the complete clock activity cycle. The sliding window statistics use a sliding window with a length of 50 microseconds and a step size of 10 microseconds. The number of clock transitions within the window is counted window by window. The number of transitions within the window is divided by the window length to obtain the number of flips per unit time, i.e., the clock flip density. The sliding window statistics can smooth out the density error caused by instantaneous glitches. The window length can cover the maximum period of clock jitter, and the step size setting ensures the real-time performance of feature updates. Non-overlapping calculations are used during sliding statistics to avoid duplicate statistics.

[0036] The low-frequency active cycle characteristic is the percentage of time within the observation window where the idle module switching density is greater than 0, reflecting the actual activity ratio of idle modules. The high-frequency duty cycle characteristic is the percentage of time within the observation window where the busy module switching density reaches more than 90% of the theoretical maximum value, reflecting the high load duration of busy modules. A preset gating threshold is set to 15%, meaning that clock shutdown is triggered when the percentage of active time for idle modules falls below 15%. This threshold is determined based on simulation results of wake-up energy consumption for typical pipeline modules under 28nm CMOS technology. The energy consumption from module shutdown to wake-up is approximately 75 nanojoules, with 1 nanojoule of energy saved per microsecond during shutdown. At this threshold, the energy saving benefit of shutdown for 500 microseconds exceeds the wake-up energy consumption, avoiding the energy inversion problem caused by frequent shutdowns and wake-ups. The preset upsampling threshold is set to 85%, which means that the frequency is triggered when the high load time of the busy module is higher than 85%. This threshold is determined based on the throughput sensitivity analysis of the target pipeline under a base clock of 200MHz. When the high load ratio exceeds 85%, the module is the bottleneck of the critical path, and the frequency upsampling can linearly shorten the overall latency. When the ratio is lower than 85%, the bottleneck is located in other modules, and the frequency upsampling cannot improve the overall performance, but instead increases energy consumption.

[0037] The dynamic voltage and frequency adjustment mapping table is derived from pre-silicon simulation and post-silicon testing calibration of transistor device models under 28nm process technology. It covers the full operating temperature range from -40°C to 125°C. Each frequency point corresponds to the minimum stable voltage at different temperatures; the higher the frequency, the higher the required operating voltage. The mapping table covers commonly used frequency points from 100 MHz to 800 MHz. Each frequency point has been verified for temperature and process corner, and the voltage value obtained from the table ensures stable operation of the module across the entire operating range. The clock gating instruction includes the module identifier and a shutdown / enable bit, while the clock upsampling instruction includes the module identifier and the target frequency value. These two types of instructions together constitute the clock adjustment instruction. The instruction uses a 32-bit fixed format encoding, which can be directly parsed by the clock management unit.

[0038] Specifically, for the marked idle and busy modules, the clock management unit collects clock level transition records over the past 500 microseconds to obtain historical clock flip records. A sliding window with a length of 50 microseconds and a step size of 10 microseconds is used to count the number of clock transitions window by window, calculating the number of flips per unit time within each window to obtain the clock flip density sequence for each module. For idle modules, the percentage of time with a flip density greater than 0 within the observation window is counted to obtain low-frequency active cycle characteristics; for busy modules, the percentage of time with a flip density exceeding 90% of the theoretical maximum value is counted to obtain high-frequency duty cycle characteristics. The low-frequency active cycle characteristics of the idle modules are compared with a 15% gating threshold. If the value is lower than the threshold, an idle clock gating instruction is generated for the corresponding module, containing the module ID and a shutdown enable bit. The high-frequency duty cycle characteristics of the busy modules are compared with an 85% boosting threshold. If the value is higher than the threshold, the dynamic voltage-frequency adjustment mapping table is consulted to obtain the corresponding target frequency, generating a busy frequency boosting instruction for the corresponding module, containing the module ID and the target frequency value. These two types of instructions together constitute the clock adjustment instruction for this step.

[0039] For example, for the target tracking module marked as an idle module, clock toggle records over the past 500 microseconds are collected. Using a 50-microsecond sliding window, the toggle density is statistically determined to be 12 times per microsecond. The low-frequency active cycle characteristic is calculated to be 10%, which is lower than the 15% gating threshold. Therefore, a clock gating instruction for the target tracking module is generated, which includes the module ID and a shutdown enable bit. For the Fast Fourier Transform (FFT) module marked as a busy module, the toggle density is statistically determined to be 85 times per microsecond, and the high-frequency duty cycle characteristic is 92%, which is higher than the 85% up-frequency threshold. By querying the dynamic voltage-frequency adjustment mapping table, the target up-frequency value at the current frequency of 200 MHz is found to be 250 MHz, corresponding to a stable operating voltage of 950 mV. Therefore, a frequency up-frequency instruction for the FFT module is generated, which includes the module ID and the 250 MHz target frequency value. These two types of instructions together constitute the clock adjustment instruction.

[0040] The state transition time during frequency switching is calculated, including: Based on the clock adjustment command, the current operating voltage and the target operating voltage of the module are obtained, and the voltage adjustment difference is calculated. The basic stabilization time is obtained by determining the phase-locked loop phase-locking period based on the voltage regulation difference, and the state transition time is calculated by combining the timing margin of the frequency switching process.

[0041] It should be noted that the current operating voltage is acquired through an on-chip integrated successive approximation voltage sensor with a sampling accuracy of 10 mV and a sampling rate of 1 MHz, enabling real-time acquisition of the module's core power supply voltage. The target operating voltage is obtained by querying a dynamic voltage frequency adjustment mapping table, which stores stable operating voltage values ​​at different frequencies and temperatures; the higher the frequency, the higher the required operating voltage. The voltage regulation difference is the difference between the target voltage and the current voltage, reflecting the voltage range that the phase-locked loop (PLL) needs to adjust. The larger the difference, the longer the time required for the PLL to relock. The PLL phase lock period is the time required for the PLL to relock the phase after voltage adjustment, calculated using a linear interpolation algorithm based on the PLL characteristic curve. The PLL characteristic curve is a voltage difference-lock time curve obtained from actual silicon measurements. The curve is marked with the lock time under typical voltage differences at 100 mV intervals. Non-typical points are calculated by linear interpolation between adjacent points, with an interpolation error of less than 0.5 microseconds. The larger the voltage difference, the longer the lock period.

[0042] Timing margin is the redundancy of setup and hold times for logic gates during frequency switching. This margin is determined based on static timing analysis results under worst-case process corner, temperature, and voltage scenarios in 28nm CMOS technology, with a typical value of 2 microseconds. It covers timing changes caused by process deviations and temperature fluctuations, ensuring no setup / hold time violations during switching. The state transition time is the sum of the basic stabilization time and the timing margin, reflecting the total time from command issuance to clock stabilization, and serves as the input for phase compensation judgment.

[0043] Specifically, the module identifier and target frequency in the clock adjustment command are analyzed. The current operating voltage of the module is collected by the on-chip voltage sensor. The target operating voltage corresponding to the target frequency is obtained by consulting the dynamic voltage-frequency adjustment mapping table. The voltage adjustment difference is obtained by subtracting the current voltage from the target voltage. Based on the phase-locked loop characteristic curve obtained from post-silicon testing, the time required for the phase-locked loop to relock the phase under this voltage difference is calculated by linear interpolation, thus obtaining the basic stabilization time. The timing margin mapping table obtained from static timing analysis is consulted to obtain the timing margin under the current voltage and target frequency. The basic stabilization time is added to the timing margin to obtain the state transition time, which is then output to the subsequent phase compensation step.

[0044] For example, the upsampling command of the Fast Fourier Transform module is parsed, with a target frequency of 250 MHz. The corresponding target operating voltage is found to be 950 mV by consulting the dynamic voltage frequency adjustment mapping table. The current operating voltage is measured at 800 mV by a voltage sensor, and the voltage regulation difference is calculated to be 150 mV. Based on the phase-locked loop (PLL) characteristic curve, a 100 mV voltage difference corresponds to a lock-in time of 5 microseconds, a 200 mV voltage difference corresponds to a lock-in time of 11 microseconds, and a 150 mV voltage difference is located between two typical points. Through two-point linear interpolation, the PLL phase-locking period corresponding to this voltage difference is calculated to be 8 microseconds, meaning the basic stabilization time is 8 microseconds. Consulting the static timing mapping table, the timing margin at this voltage frequency is found to be 2 microseconds. Therefore, the state transition time is 8 microseconds plus 2 microseconds, totaling 10 microseconds. If a module increases its frequency to 600 MHz, the target operating voltage is found to be 1100 mV when the mapping table is consulted. The current operating voltage is collected as 800 mV, and the voltage difference is calculated to be 300 mV. Based on the phase-locked loop characteristic curve, a voltage difference of 200 mV corresponds to a locking time of 11 microseconds, and a voltage difference of 400 mV corresponds to a locking time of 17 microseconds. Through linear interpolation, the basic stabilization time corresponding to a voltage difference of 300 mV is found to be 14 microseconds. The corresponding timing margin is found to be 2 microseconds. The total state transition time is 14 microseconds plus 2 microseconds, totaling 16 microseconds.

[0045] If the state transition time is greater than a preset switching delay threshold, clock phase compensation is performed to obtain a differentiated clock control signal, including: If the state transition time is greater than the preset switching delay threshold, the clock edge alignment error between different clock adjustment commands is extracted, and the phase offset is calculated. The phase compensation step size is determined based on the phase offset and clock duty cycle, and a phase adjustment vector is generated to perform phase compensation on the clock adjustment command to obtain a differentiated clock control signal.

[0046] It should be noted that the preset switching delay threshold is set to 12 microseconds. This threshold is determined based on the statistical characteristics of typical pipeline time slots of digital signal processors. The typical pipeline data packet processing interval is 20 microseconds, the idle time slot between two data packets is 12 microseconds, and 8 microseconds are reserved for interrupt processing and context state saving time. Therefore, the total duration of the clock switching process must be controlled within 12 microseconds to avoid occupying the effective data packet processing time and affecting the real-time performance of services.

[0047] Phase compensation is integrated into the PLL's internal feedback loop, achieving a smooth phase transition through the PLL's built-in programmable phase interpolator. This architecture is consistent with ADIDPLL's phase buildout mechanism and TICDC5801A's programmable phase alignment function, representing a mature standard implementation for commercial clock chips. Compensation is completed within the PLL feedback loop, and the PLL output is the phase-aligned clock signal, directly connected to the original clock tree without introducing additional clock skew or disrupting the original clock tree balance. The establishment of all modules maintains time constraints compatible with the original design, requiring no additional timing convergence.

[0048] Clock edge alignment error is the arrival time difference of the rising edge of the clock corresponding to the adjustment command in different clock domains. It is measured by the PLL's built-in time-to-digital converter with a measurement accuracy of 10 picoseconds, accurately capturing the phase difference across clock domains. The time-to-digital converter converts the time difference into digital code through the PLL's internal delay chain. Each delay unit delays by 10 picoseconds, covering a time difference measurement range of 0 to 2 nanoseconds. Phase offset is the proportion of alignment error to the entire clock cycle, obtained by dividing the alignment error by the clock cycle and multiplying by 360 degrees. It reflects the phase difference angle between two clocks, with a value range of 0 to 360 degrees. The clock duty cycle is fixed at 50%, meaning that the high level and low level each occupy half a clock cycle. This duty cycle is the standard clock configuration for digital circuits, ensuring that the high and low level times of the clock meet the logic sampling requirements.

[0049] The phase compensation step size is dynamically determined based on the phase offset and a fixed 50% clock duty cycle. The physical minimum compensation step size of the PLL's built-in programmable phase interpolator is 3 degrees, meaning a single voltage-controlled delay unit corresponds to a 3-degree phase offset. This forms the hardware basis for step size selection, and all actual step sizes are integer multiples of 3 degrees to match the hardware control granularity of the interpolator. Step size calculation is strictly constrained by the 50% clock duty cycle. Digital circuit triggers require a clock high / low level pulse width of no less than 45% of the clock period, or 162 degrees. Therefore, the maximum single-step step size cannot exceed 15 degrees, ensuring that after each adjustment, the clock high / low level width is always no less than 165 degrees. This satisfies the setup time, hold time, and minimum pulse width requirements of all digital logic, fundamentally avoiding clock glitches and logic mis-triggering.

[0050] Under the constraint of a maximum safe step size of 15 degrees, the actual compensation step size is dynamically selected based on the total phase offset, balancing compensation speed and adjustment smoothness. When the phase offset is ≤30°, a 3° step size is used, with a maximum of 10 compensation steps, resulting in the smoothest adjustment process, suitable for fine calibration with small phase differences. When 30° < phase offset ≤90°, a 9° step size is used, with a maximum of 10 compensation steps, twice the compensation speed compared to the minimum step size. Furthermore, the 9° step size is much smaller than the 15° safety limit, preventing the generation of narrow pulses. When the phase offset is >90°, a 15° step size is used, requiring a maximum of 18 compensation steps to complete 360° full-scale offset calibration. The total compensation time does not exceed 20 clock cycles, requiring only 100 nanoseconds at a 200MHz reference clock, far less than the compensation window reserved in the time slot, and does not occupy effective data processing time. Compared to a fixed step size, the dynamic step size mechanism avoids the risk of glitches caused by large step sizes and solves the problem of excessively long compensation time under small step sizes and large offsets, while simultaneously meeting timing safety and real-time requirements.

[0051] The phase adjustment vector is a control sequence consisting of multiple consecutive phase adjustment steps. Gradual phase adjustment is achieved by adjusting the feedback loop phase through the PLL's built-in phase interpolator. The total delay range covers the entire 360-degree phase, enabling full-phase adjustment. One step is adjusted and the interpolator control word is updated every clock cycle to avoid timing violations caused by sudden phase jumps. The differentiated clock control signal is the final clock control word after phase compensation, containing clock enable, frequency value, and phase adjustment value for each module. It uses a 32-bit fixed encoding format and can be directly sent to the clock gating unit for execution. For adjustment commands with transition times below the threshold, they are directly output as differentiated clock control signals without compensation.

[0052] Specifically, the state transition time calculated in the previous step is compared with a preset switching delay threshold of 12 microseconds. If the state transition time is greater than the threshold, the phase compensation process is initiated. The rising edge arrival time of the clock corresponding to different clock adjustment commands is measured using the PLL's built-in time-to-digital converter. The time difference between the rising edges of the two clocks is calculated to obtain the clock edge alignment error. The alignment error is divided by the current clock cycle length, multiplied by 360°, and rounded to the nearest integer to obtain the phase offset within the range of 0° to 360°. The phase compensation step size is dynamically calculated based on the phase offset and a fixed clock duty cycle of 50%. First, a maximum safe step size of 15° is determined based on the duty cycle constraint. The corresponding step size is selected based on the range of the phase offset: a 3° step size is selected for offsets not exceeding 30°, a 9° step size is selected for offsets between 30° and 90°, and a 15° step size is selected for offsets exceeding 90°. All step sizes are integer multiples of the minimum hardware step size of 3°. The total phase offset is divided by the single-step step size to obtain the number of compensation steps. The total phase offset is decomposed into multiple consecutive equal-step adjustment amounts to form a phase adjustment vector. The phase adjustment vector is written into the control register of the PLL's built-in phase interpolator. By adjusting the PLL feedback phase, the phase offset of the output clock is gradually achieved. One step is adjusted each clock cycle to achieve a smooth clock phase transition, eliminating the timing violation risk caused by large phase jumps. The control signal after compensation is the differentiated clock control signal. For instructions with a transition time below a threshold, the differentiated clock control signal is directly output.

[0053] For example, in a radar signal processing scenario, when the pulse Doppler processing module upclocks to 600 MHz, the previously calculated state transition time is 16 microseconds, which is higher than the 12 microsecond threshold, thus initiating phase compensation. The rising edge alignment error between the source clock and the target clock is measured to be 450 picoseconds using the PLL's built-in time-to-digital converter. The current reference clock period is 2000 picoseconds. The calculated phase offset is 450 picoseconds divided by 2000 picoseconds and then multiplied by 360 degrees, resulting in 81 degrees. Based on the 81-degree phase offset and a 50% clock duty cycle, the compensation step size is determined. Since 81 degrees falls within the 30-90 degree range, a 9-degree step size is chosen. During the 9-degree step adjustment, the minimum clock pulse width is 171 degrees, which is much larger than the minimum pulse width requirement of the trigger, preventing the generation of narrow pulses.

[0054] The total 81° offset is decomposed into nine consecutive 9° steps, forming a phase adjustment vector of length 9. This vector is written to the PLL phase interpolator control register, and the feedback phase is adjusted over nine clock cycles to smoothly offset the output clock phase by 81 degrees. Each cycle adjusts the phase by 9 degrees. During the compensation process, the clock high and low level widths consistently meet the 50% duty cycle requirement, with no clock glitches or narrow pulses less than 1 nanosecond in width. The total compensation time is only 45 nanoseconds, far less than the time slot reservation window. The final output is a differentiated clock control signal after phase compensation. There are no sudden phase jumps during clock switching, ensuring timing safety. If a module's phase offset is 24 degrees, less than 30 degrees, compensation is completed in 8 steps with a minimum step size of 3 degrees, resulting in the smoothest adjustment process. If a module's phase offset is 180 degrees, greater than 90 degrees, compensation is completed in 12 steps with a maximum safe step size of 15 degrees, resulting in a total compensation time of 60 nanoseconds with no timeout risk. If the state transition time of the Fast Fourier Transform module when upsampling to 250 MHz is 10 microseconds, which is lower than the 12 microsecond threshold, then the clock adjustment command can be directly output as a differentiated clock control signal without phase compensation.

[0055] In step S14, the differentiated clock control signal is input to a preset clock gating unit to perform a clock shutdown operation on the idle module and a local frequency boost operation on the busy module, thereby obtaining a low-power control result, including: The gate enable signal and frequency multiplication factor are obtained by analyzing the differential clock control signal; The idle module power consumption status is obtained by shutting down the idle module clock tree according to the gating enable signal, and the busy module power consumption status is obtained by increasing the local clock frequency of the busy module according to the frequency multiplication factor. The low power consumption control result is obtained by combining the power consumption status of each module.

[0056] It should be noted that the clock gating unit is a latch-based glitch-free clock gating circuit. This structure is a typical glitch-free clock gating structure supported by the standard cell library under the 28nm process. It is distributed in the leaf nodes of the clock tree of each module rather than the root node of the clock tree, which can realize independent clock control of a single module without affecting the clock operation of other modules. The specific circuit structure is a low-level transparent latch plus a two-input AND gate. The input of the low-level transparent latch is connected to the gating enable signal, the latch clock is connected to the inverted module clock, the latch output is connected to one input of the AND gate, the other input of the AND gate is connected to the module clock, and the output of the AND gate is the gating clock. This structure only updates the gating enable signal during the low level of the clock, which in principle avoids the generation of glitches when the clock is turned off, ensures the safety of the clock turn-off process, and prevents narrow pulses from triggering the subsequent logic to flip incorrectly. The gating enable signal is a 1-bit control bit. When it is 1, the clock tree of the corresponding module is turned off, and when it is 0, the clock output remains normal. The bit field of the 32-bit control word is defined as follows: bits 31 to 24 (8 bits in total) are the gating enable bits of 8 modules, supporting individual control of up to 8 independent clock domains; bits 3 to 0 (4 bits in total) are the frequency multiplication factor of the corresponding module, corresponding to the frequency multiplication coefficient of the digital phase-locked loop, which can configure the local clock of the module to be 1 to 8 times the base clock. The codes 0001 to 1000 correspond to 1 to 8 times the frequency, respectively, supporting frequency configuration from 100 MHz to 800 MHz under a 100 MHz base clock; bits 23 to 4 (20 bits in total) are reserved bits, which can be used for subsequent phase adjustment, voltage control and other function expansions, and can achieve single-module frequency increase without modifying the global clock configuration.

[0057] The power consumption of an idle module is the leakage current power consumption of the module after the clock is turned off. After the clock is turned off, the module clock toggle stops completely, the dynamic power consumption drops to 0, and only the transistor subthreshold leakage current power consumption is retained, typically a few milliwatts to tens of milliwatts. During the module clock off period, the empty / full flag of the input buffer is directly connected to the clock control circuit in hardware. When the buffer is not empty, the clock is automatically enabled to wake up the module. The wake-up process does not require software intervention, and the wake-up delay is less than 1 microsecond, which will not affect data processing. The power consumption of a busy module is the sum of the dynamic power consumption and leakage current power consumption of the module after frequency increase. The dynamic power consumption is approximately proportional to the clock frequency. After the frequency increases, the dynamic power consumption increases linearly with the frequency, but the module processing time decreases proportionally with the frequency increase. The overall energy consumption to complete the same computing task is actually reduced. The low power control result is the sum of the power consumption of all modules, and also includes performance data such as the processing delay of the critical path and the overall power consumption reduction ratio, reflecting the overall effect of low power control. Clock shutdown, PLL reconfiguration, and phase compensation operations are all completed within the time slots between two data packet processing operations. During these time slots, the module has no valid computational tasks, and the total phase compensation duration does not exceed 100 nanoseconds, far less than the 12 microsecond switching safety threshold. Therefore, clock switching will not interrupt ongoing computational tasks or cause data errors or timing violations. The on-chip power sensor calculates real-time power consumption by collecting the module's power supply current and voltage. With a sampling accuracy of 1 milliwatt and a sampling rate of 10 kilohertz, it represents a typical configuration for on-chip power sensors using 28nm technology, enabling real-time acquisition of the module's dynamic power consumption and leakage current.

[0058] Specifically, the differentiated clock control signal obtained through phase compensation in the previous stage is sent to the clock gating unit. Bit-domain parsing is performed on the 32-bit control word, extracting the high 8 bits as the gating enable signal for each module, extracting the low 4 bits as the frequency multiplication factor for the corresponding module, and reserving the remaining 20 bits for later parsing. For idle modules with the gating enable bit set to 1, the module waits for the current data packet to complete processing and enter the time slot. A latch-based glitch-free gating circuit shuts down the leaf node clock tree of the module, cutting off the clock toggle path. When a new data packet is detected in the module's input buffer, the clock is automatically woken up. The power consumption status of the idle module is obtained by collecting the leakage current value under the shutdown steady-state using an on-chip power sensor.

[0059] For busy modules with an effective frequency multiplication factor, the frequency multiplication factor of the digital phase-locked loop is reconfigured during the time slot interval. The new multiplication factor is written first, and after the lockout indication signal becomes valid, the module's local clock is smoothly boosted to the target frequency through phase compensation. Before locking, the original clock output is maintained to avoid glitches. The dynamic power consumption and leakage current power consumption after frequency stabilization are collected to obtain the power consumption status of the busy module. After all module clocks are adjusted, the power consumption values ​​of all idle and busy modules are added to the reference power consumption of conventional modules that do not participate in clock adjustment, such as constantly powered logic and the global clock tree, to obtain the overall power consumption value. Simultaneously, the processing delay change of the critical path and the overall power consumption reduction ratio are statistically analyzed and used as the low-power control result output.

[0060] In summary, this invention discloses a low-power control method for data processing based on clock domain adjustment. This invention identifies the load state by acquiring real-time running data from the acquisition module, accurately divides idle and busy modules based on asynchronous timing characteristics, generates differentiated clock adjustment instructions and performs phase compensation to ensure safe switching, and finally uses a clock gating unit to achieve module-level clock shutdown and local frequency upsampling. This achieves fine-grained low-power control at the digital signal processor module level, significantly reducing overall dynamic power consumption while ensuring critical path computing performance. It solves the problem in existing technologies that cannot achieve fine-grained, timing-safe low-power clock domain control for asynchronous loads of multi-core CPU functional modules.

[0061] The second embodiment of the present invention provides a low-power data processing control system based on clock domain adjustment, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the low-power data processing control method based on clock domain adjustment as described above.

[0062] It should be noted that the low-power data processing control system based on clock domain adjustment provided in this embodiment of the invention is used to execute all the process steps of the low-power data processing control method based on clock domain adjustment in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0063] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A low-power control method for data processing based on clock domain modulation, characterized in that, include: The real-time operating data of each functional module inside the digital signal processor is acquired, and the load status is classified according to the real-time operating data to obtain the current load status of each functional module. Based on the current load status, extract the timestamp information of data interaction between each functional module, obtain the asynchronous timing characteristics between modules through timing analysis, and determine the idle modules waiting for the previous level data and the busy modules in the critical path calculation based on the asynchronous timing characteristics. Historical clock flip features are extracted for the idle module and the busy module, corresponding clock adjustment instructions are generated, the state transition time of the frequency switching process is calculated, and if the state transition time is greater than the preset switching delay threshold, clock phase compensation is performed to obtain a differentiated clock control signal. The differentiated clock control signal is input into the preset clock gating unit to perform a clock shutdown operation on the idle module and a local frequency boost operation on the busy module, thereby obtaining a low-power control result.

2. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, The process of acquiring real-time operating data of each functional module within the digital signal processor, classifying the real-time operating data by load status, and obtaining the current load status of each functional module includes: Extract instruction cycles and memory access frequencies from real-time running data, construct a multi-dimensional running feature set, and perform dimensionality reduction processing on the running feature set to obtain the core feature vector; The core feature vector is classified into states to obtain a classification label sequence. The state mapping table is then queried based on the classification labels to obtain the current load state of each functional module.

3. The low-power control method for data processing based on clock domain adjustment according to claim 1, characterized in that, The step of extracting the timestamp information of data interaction between functional modules based on the current load status, and obtaining the asynchronous timing characteristics between modules through time series analysis, includes: Extract the data inflow timestamps and data outflow timestamps from each functional module to obtain a timestamp sequence, and perform alignment processing on the timestamp sequence to obtain a standardized time series sequence; The standardized time sequence is compared point by point to obtain the transmission delay value between modules. The transmission delay values ​​that exceed the preset delay threshold are clustered to obtain the asynchronous time sequence characteristics between modules.

4. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, The method for determining idle modules waiting for preceding data and busy modules performing critical path computations based on the asynchronous timing characteristics includes: The current load difference value is obtained by weighted calculation based on the module blocking duration and resource utilization rate in the asynchronous timing characteristics. If the load difference value is greater than the preset load difference threshold, the topology execution graph of the functional module is parsed to obtain the module dependency relationship, and the state is divided in combination with the real-time throughput of the module to determine the idle module and the busy module.

5. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, The step of extracting historical clock flip features for the idle module and the busy module, and generating corresponding clock adjustment instructions, includes: Based on the historical clock flip records of the idle module and the busy module, the clock flip density of different modules is obtained by using a sliding window statistical method. Based on the clock flip density, the low-frequency active cycle characteristics of the idle module and the high-frequency duty cycle characteristics of the busy module are extracted. If the low-frequency active cycle characteristics are lower than a preset gating threshold, an idle clock gating instruction is generated. If the high-frequency duty cycle characteristics are higher than a preset boosting threshold, a busy frequency boosting instruction is generated. The two types of instructions together constitute the clock adjustment instruction.

6. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, The state transition time of the frequency switching process includes: Based on the clock adjustment command, the current operating voltage and the target operating voltage of the module are obtained, and the voltage adjustment difference is calculated. The basic stabilization time is obtained by determining the phase-locked loop phase-locking period based on the voltage regulation difference, and the state transition time is calculated by combining the timing margin of the frequency switching process.

7. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, If the state transition time is greater than a preset switching delay threshold, clock phase compensation is performed to obtain a differentiated clock control signal, including: If the state transition time is greater than the preset switching delay threshold, the clock edge alignment error between different clock adjustment commands is extracted, and the phase offset is calculated. The phase compensation step size is determined based on the phase offset and clock duty cycle, and a phase adjustment vector is generated to perform phase compensation on the clock adjustment command to obtain a differentiated clock control signal.

8. The low-power control method for data processing based on clock domain modulation according to claim 1, characterized in that, The step of inputting the differentiated clock control signal into a preset clock gating unit to perform a clock shutdown operation on the idle module and a local frequency boost operation on the busy module to obtain a low-power control result includes: The gate enable signal and frequency multiplication factor are obtained by analyzing the differential clock control signal; The idle module power consumption status is obtained by shutting down the idle module clock tree according to the gating enable signal, and the busy module power consumption status is obtained by increasing the local clock frequency of the busy module according to the frequency multiplication factor. The low power consumption control result is obtained by combining the power consumption status of each module.

9. A low-power data processing control system based on clock domain modulation, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the low-power data processing control method based on clock domain adjustment as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the low-power data processing control method based on clock domain modulation as described in any one of claims 1 to 8.

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