Display panel, display module and display device

Abstract

This application discloses a display panel, a display module, and a display device. The display panel includes a display area and a peripheral area surrounding the display area. The peripheral area has a bonding area for bonding a driver chip. The display panel includes: a substrate; a touch electrode disposed on one side of the substrate and located in the display area; a plurality of touch test traces, one end of each touch test trace being electrically connected to the touch electrode, and the other end extending to a first edge of the display panel; the bonding area being located between the first edge of the display panel and the display area in a column direction; and a plurality of bonding pads disposed in the peripheral area. In the column direction, the bonding pads are located on the side of the bonding area away from the display area, and the bonding pads are used for connection to a circuit board.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, display module, and display device. Background Technology

[0002] Touch technologies mainly include resistive, capacitive, and infrared optical touch. Among them, capacitive touch technology is characterized by its high responsiveness and is widely used in smartphones and tablets. Display panels using capacitive touch technology include touch electrodes, touch signal lines, and a driver chip. The touch signal line is electrically connected between the touch electrodes and the touch driver chip to transmit signals. However, existing display panels still require further improvement. Summary of the Invention

[0003] The purpose of this application is to provide a display panel, a display module, and a display device.

[0004] This application discloses a display panel, including a display area and a peripheral area surrounding the display area, wherein the peripheral area is provided with a bonding area for bonding a driver chip, and the display panel includes: Substrate; The touch electrode is disposed on one side of the substrate and located in the display area; Multiple touch test traces are provided, one end of each touch test trace is electrically connected to the touch electrode, and the other end extends to the first edge of the display panel. The bonding area is located between the first edge of the display panel and the display area in the column direction. Multiple bonding pads are provided in the peripheral area. In the column direction, the bonding pads are located on the side of the bonding area away from the display area. The bonding pads are used to connect to the circuit board. At least one virtual pad is provided in the peripheral area. In the column direction, the virtual pad is located on the side of the bonding area away from the display area. At least a portion of the virtual pad's orthogonal projection on the substrate overlaps with the orthogonal projection of the touch test trace on the substrate. The surface of the virtual pad away from the substrate can be attached to the circuit board.

[0005] In some alternative implementations, the virtual pad is used to connect to a fixed power signal terminal of the circuit board.

[0006] In some alternative implementations, the at least one virtual pad includes a plurality of virtual pads, some of which are located on one side of the bonded pad in the row direction, and other virtual pads are located on the other side of the bonded pad in the row direction.

[0007] In some alternative embodiments, the display panel further includes: a first shielding layer disposed on the side of the touch test trace away from or close to the substrate, wherein the orthographic projection of the first shielding layer on the substrate overlaps with the orthographic projection of at least one of the touch test traces on the substrate, and the first shielding layer is electrically connected to the virtual pad.

[0008] In some alternative embodiments, the first shielding layer is disposed on the side of the touch test trace away from the substrate and is disposed in the same layer as at least a portion of the virtual pad.

[0009] In some alternative embodiments, along a direction away from the substrate, the display panel includes a first gate electrode layer, a first source / drain electrode layer, and a second source / drain electrode layer disposed sequentially, with at least a portion of the touch test trace located on the first gate electrode layer, and at least a portion of the virtual pad and at least a portion of the first shielding layer located on the first source / drain electrode layer or the second source / drain electrode layer; or along a direction away from the substrate, the display panel includes a first gate electrode layer, a second gate electrode layer, a first source / drain electrode layer, and a second source / drain electrode layer disposed sequentially, with at least a portion of the touch test trace located on the first gate electrode layer or the second gate electrode layer, and at least a portion of the virtual pad and at least a portion of the first shielding layer located on the first source / drain electrode layer or the second source / drain electrode layer.

[0010] In some alternative embodiments, the first shielding layer is disposed on the side of the touch test trace away from the substrate, and the display panel further includes: a second shielding layer disposed on the side of the touch test trace close to the substrate, wherein the orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of at least one of the touch test traces on the substrate, the orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of the first shielding layer on the substrate, and the second shielding layer is electrically connected to the first shielding layer.

[0011] In some alternative embodiments, the orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of the virtual pad on the substrate.

[0012] In some alternative embodiments, there are two first shielding layers, with one portion of the touch test traces located on one side of the bonding area in the row direction and overlapping with the orthographic projection of one of the first shielding layers on the substrate; the other portion of the touch test traces located on the other side of the bonding area in the row direction and overlapping with the orthographic projection of the other first shielding layer on the substrate.

[0013] In some alternative implementations, the touch test trace includes two first segments spaced apart and a second segment connecting the two first segments, wherein the impedance of the second segment is greater than the impedance of the first segment.

[0014] In some alternative implementations, the cross-sectional area of ​​the second line segment is smaller than that of the first line segment; or the first line segment is a double-layered trace and the second line segment is a single-layered trace.

[0015] In some optional embodiments, the display panel further includes: a plurality of switching transistors corresponding to the plurality of touch test traces, each touch test trace including two spaced-apart first segments, each of the switching transistors being connected between the two first segments of the corresponding touch test trace; a test control trace, one end of which is electrically connected to the gate of the switching transistor, and the other end extending to a first edge of the display panel; and a shutdown trace, one end of which is electrically connected to the gate of the switching transistor, and the other end extending to the bonding area, and used to receive a shutdown signal sent by the driver chip.

[0016] In some alternative embodiments, the display panel further includes: a touch signal line, one end of which is connected to the touch electrode and the other end of which extends to the bonding area to connect to the driver chip; wherein, one end of the touch test trace away from the first edge of the display panel is connected between the two ends of the touch signal line.

[0017] In some alternative implementations, the length of the first segment connected to the touch signal line is less than the length of the other first segment.

[0018] This application discloses a display module, comprising: a display panel as described in any of the preceding claims; a driver chip bonded to the bonding area; and a circuit board connected to the bonding pads and covering at least a portion of the surface of the virtual pads away from the substrate.

[0019] This application discloses a display device, including the above-described display module.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0022] Figure 1 This is a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0023] Figure 2This is a schematic diagram of the display panel to be cut according to an embodiment of this disclosure.

[0024] Figure 3 This is a schematic diagram of a display module according to an embodiment of the present disclosure.

[0025] Figure 4 This is a schematic diagram of a display panel having a first shielding layer according to an embodiment of the present disclosure.

[0026] Figure 5 , Figure 6 as well as Figure 7 This is a schematic diagram showing the layout of the display panel in the thickness direction according to an embodiment of the present disclosure.

[0027] Figure 8 This is a schematic diagram of the virtual pads and bonding pads of the display panel according to an embodiment of the present disclosure.

[0028] Figure 9 This is a schematic diagram of the touch test wiring of the display panel according to an embodiment of the present disclosure.

[0029] Figure 10 This is a schematic diagram of a display panel with switching transistors according to an embodiment of the present disclosure.

[0030] Figure 11 yes Figure 10 The diagram shows the structure and control pads.

[0031] Figure 12 This is another schematic diagram of a display panel with switching transistors according to an embodiment of the present disclosure.

[0032] Figure 13 for Figure 12 The diagram shows the structure and circuit board.

[0033] Reference numerals: 1. Substrate; 2. Active layer; 3. First gate insulating layer; 4. First gate electrode layer; 5. Interlayer insulating layer; 6. First source / drain electrode layer; 7. Second source / drain electrode layer; 8. First planarization layer; 9. Second planarization layer; 10. First electrode; 11. Light-emitting layer; 12. Second electrode; 13. Pixel defining layer; 14. Encapsulation layer; 15. Buffer layer; 16. Bridging layer; 17. Touch insulating layer; 18. Touch electrode layer; 19. Touch protection layer; 20. Second gate insulating layer Layer; 21, Second gate electrode layer; 22, Touch test trace; 2201, First segment; 2202, Second segment; 23, Bonding pad; 24, Virtual pad; 25, Touch signal line; 26, Test pad; 27, First edge; 28, First shielding layer; 29, Second shielding layer; 30, Control pad; 31, Test control trace; 32, Shutdown trace; 33, Switching transistor; 34, Bonding area; IC, Driver chip; FPC, Circuit board; 100, Touch electrode. Detailed Implementation

[0034] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0035] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0036] Embodiments of this disclosure provide a display panel. For example... Figure 1 and Figure 3 As shown, the display panel may include a display area and a peripheral area. The peripheral area includes at least a bonding area 34 for bonding a driver chip IC. The driver chip IC may be a touch and display driver integrated chip. The display area may be circular, elliptical, polygonal, etc. The peripheral area may surround the display area. The bonding area 34 is spaced apart from the display area. The peripheral area may also include a bent area. The bent area is located between the bonding area 34 and the display area, and is spaced apart from both the bonding area 34 and the display area. The area between the bent area and the display area may be a first fan-out area, and the area between the bent area and the bonding area 34 may be a second fan-out area. In addition, the display area is also a touch area.

[0037] like Figure 5 As shown, the display panel may include a substrate 1. The substrate 1 may be a rigid substrate 1. Specifically, the rigid substrate 1 may be a glass substrate 1 or a PMMA (Polymethyl methacrylate) substrate 1, etc. Alternatively, the substrate 1 may be a flexible substrate 1. Specifically, the flexible substrate 1 may be a PET (Polyethylene terephthalate) substrate 1, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate 1, or a PI (Polyimide) substrate 1.

[0038] Thin-film transistors and light-emitting structures can be disposed on the substrate 1. The thin-film transistors can be electrically connected to the light-emitting structures. Specifically, the display panel can include an active layer 2, a first gate insulating layer 3, a first gate electrode layer 4, an interlayer insulating layer 5, a first source / drain electrode layer 6, and a first planarization layer 8. The active layer 2 can be disposed on the substrate 1, and the first gate insulating layer 3 can be disposed on the substrate 1 and cover the active layer 2. The first gate electrode layer 4 can be disposed on the side of the first gate insulating layer 3 away from the substrate 1. A portion of the pattern of the first gate electrode layer 4 can form the gate of the thin-film transistor. The interlayer insulating layer 5 can be disposed on the side of the first gate insulating layer 3 and the first gate electrode layer 4 facing away from the substrate 1. The first source / drain electrode layer 6 can be disposed on the interlayer insulating layer 5. The first source / drain electrode layer 6 can include multiple mutually insulated patterns, wherein a portion of the pattern of the first source / drain electrode layer 6 located in the display area is connected to the active layer 2 via vias passing through the interlayer insulating layer 5 and the first gate insulating layer 3. The partial pattern of the first source / drain electrode layer 6 located in the display area can constitute the source and drain of a thin-film transistor. The first planarization layer 8 can cover the first source / drain electrode layer 6 and the interlayer insulating layer 5.

[0039] In one implementation, such as Figure 5 and Figure 6 As shown, the display panel may further include a second gate electrode layer 21 and a second gate insulating layer 20. The second gate insulating layer 20 is disposed on the surface of the first gate insulating layer 3 facing away from the substrate 1 and covers the first gate electrode layer 4. The second gate electrode layer 21 may be located on the second gate insulating layer 20. The aforementioned interlayer insulating layer 5 covers the second gate electrode layer 21 and the second gate insulating layer 20.

[0040] In one implementation, such as Figure 7 As shown, the display panel may further include a second source / drain electrode layer 7 and a second planarization layer 9. The second source / drain electrode layer 7 may be disposed on the side of the first planarization layer 8 facing away from the substrate 1. The second source / drain electrode layer 7 may include multiple mutually insulating patterns, wherein a portion of the patterns of the second source / drain electrode layer 7 located in the display area is connected to the first source / drain electrode layer 6 via vias passing through the first planarization layer 8. The second planarization layer 9 may cover both the second source / drain electrode layer 7 and the first planarization layer 8.

[0041] The display panel may further include an anode layer, a pixel defining layer 13, a light-emitting layer 11, and a cathode layer. The anode layer may be disposed on the side of the second planarization layer 9 facing away from the substrate 1, and contact the pattern of the second source / drain electrode layer 7 located in the display area via vias passing through the second planarization layer 9. The pixel defining layer 13 covers the anode layer and the second planarization layer 9, and has multiple openings exposing the anode layer. The light-emitting layer 11 may be disposed within the openings of the pixel defining layer 13. The light emitted by the light-emitting layers 11 located at different openings may be of the same color, or they may be different. The color of the light emitted by the light-emitting layer 11 may include red, green, blue, etc. The cathode layer covers the pixel defining layer 13 and the light-emitting layer 11. The cathode layer, the light-emitting layer 11, and the anode layer can constitute the aforementioned light-emitting structure.

[0042] The display panel may further include an encapsulation layer 14. The encapsulation layer 14 may cover the cathode layer. The encapsulation layer 14 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The first inorganic encapsulation layer and the second inorganic encapsulation layer are disposed opposite to each other, and the organic encapsulation layer covers the space between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0043] The display panel may also include a touch structure. The touch structure may be disposed on the surface of the encapsulation layer 14 facing away from the substrate 1. The touch structure may include a buffer layer 15, a bridging layer 16, a touch insulating layer 17, a touch electrode layer 18, and a touch protective layer 19. The buffer layer 15 may be disposed on the surface of the encapsulation layer 14 facing away from the substrate 1. The bridging layer 16 is disposed on the surface of the buffer layer 15 facing away from the substrate 1. The touch insulating layer 17 covers the bridging layer 16 and the buffer layer 15. The touch electrode layer 18 is disposed on the surface of the touch insulating layer 17 facing away from the substrate 1. The touch electrode layer 18 may include a touch electrode 100. The touch electrode 100 may be located in the display area. In one embodiment, the touch electrode 100 includes a first touch electrode and a second touch electrode arranged in a cross configuration. One of the first touch electrode and the second touch electrode extends along a row direction, and the other extends along a column direction. In the region where the first touch electrode and the second touch electrode intersect, the first touch electrode is connected by the bridging layer 16. Of the first and second touch electrodes, one is a touch sensing electrode and the other is a touch driving electrode. The touch protective layer 19 can cover the touch electrode layer 18 and the touch insulating layer 17. The buffer layer 15, the touch insulating layer 17, and the touch protective layer 19 are made of organic or inorganic materials.

[0044] like Figure 1As shown, the display panel may further include touch signal lines 25. The touch signal lines 25 may be located in the peripheral area. One end of the touch signal line 25 is connected to the touch electrode 100, and the other end extends to the bonding area 34 to connect to the driver chip IC. The touch electrode 100 and the driver chip IC interact via the touch signal lines 25. In one embodiment, the display panel may adopt a 1T1R driving method, that is, each touch driving electrode is connected to one touch signal line 25, and each touch sensing electrode is connected to one touch signal line 25. In another embodiment, the display panel may adopt a 1T2R driving method, that is, each touch driving electrode is connected to one touch signal line 25, and each touch sensing electrode is connected to two touch signal lines 25.

[0045] The display panel also includes multiple touch test traces 22. One end of each touch test trace 22 is electrically connected to the touch electrode 100, and the other end extends to the first edge 27 of the display panel. One end of the touch test trace 22 can be connected between the two ends of the touch signal line 25, meaning the touch test trace 22 can be electrically connected to the touch electrode 100 through a portion of the touch signal line 25. The first edge 27 of the display panel is the edge of the substrate 1 located on the side of the bonding area 34 away from the display area; that is, the bonding area 34 is located in the column direction between the first edge 27 of the display panel and the display area. It should be noted that this first edge 27 can be the cut edge of the display panel. Figure 2 The display panel before cutting is shown, which includes multiple test pads 26. The test pads 26 are connected to touch test traces 22 via signal lines. Before cutting the display panel (cutting line L1), testing (cell testing) is required. Test signals are applied to the test pads 26, and the test signals are transmitted to the touch electrode 100 via the touch test traces 22 to perform touch testing. In one embodiment, the touch test traces 22 can be located in the first gate electrode layer 4 or the second gate electrode layer 21. In another embodiment, the touch test traces 22 are double-layer traces, one layer of which can be located in the second gate electrode layer 21, and the other layer can be the first gate electrode layer 4 or the first source / drain electrode layer 6.

[0046] like Figure 1 and Figure 8 As shown, the display panel also includes multiple bonding pads 23. These bonding pads 23 are located in the peripheral area, and in the column direction, they are situated on the side of the bonding area 34 furthest from the display area. The bonding pads 23 are used for connection to the circuit board (FPC). Furthermore, the bonding pads 23 are also connected to signal lines extending into the bonding area 34. Signals on the circuit board (FPC) can be transmitted to the driver chip IC in the bonding area 34 via the bonding pads 23 and the signal lines. The multiple bonding pads 23 can be sequentially distributed along the extension direction of the first edge 27 of the display panel.

[0047] The display panel also includes at least one virtual pad 24. The virtual pad 24 is located in the peripheral area, and in the column direction, it is situated on the side of the bonding area 34 away from the display area. The at least one virtual pad 24 includes multiple virtual pads 24, some of which are located on one side of the bonding pad 23 in the row direction, while others are located on the other side of the bonding pad 23 in the row direction. The virtual pads 24 and bonding pads 23 can be distributed along the extension direction of the first edge 27. When the circuit board FPC is connected to the aforementioned bonding pad 23, the circuit board FPC is positioned on the surface of the virtual pad 24 away from the substrate 1, and the virtual pad 24 can support the circuit board FPC to balance the forces acting on it.

[0048] At least a portion of the virtual pad 24 overlaps with the orthographic projection of the touch test trace 22 on the substrate 1. At least a portion of the virtual pad 24 may be located in the first source / drain electrode layer 6 or the second source / drain electrode layer 7. The virtual pad 24 is used to connect to a fixed power signal terminal of the circuit board FPC. The voltage of this fixed power signal terminal is constant. In one embodiment, the fixed power signal terminal can be ground (GND). Under high-frequency driving of the display panel, the electrical signal on the touch signal line 25 can affect the floating touch test trace 22, causing radiated electromagnetic interference (EMI) to be emitted, which in turn affects other components. Since the virtual pad 24 of this application is used to connect to the fixed power signal terminal of the circuit board FPC, this configuration allows the virtual pad 24 to shield the touch test trace 22, reducing the impact of radiated EMI on other components.

[0049] like Figure 4 and Figure 6 As shown, the display panel may further include a first shielding layer 28. The first shielding layer 28 is disposed on the side of the touch test trace 22 that is away from or near the substrate 1. Taking the first shielding layer 28 being disposed on the side of the touch test trace 22 that is away from the substrate 1 as an example, at least a portion of the first shielding layer 28 is located on the first source / drain electrode layer 6 or the second source / drain electrode layer 7. Further, the first shielding layer 28 may be disposed on the same layer as at least a portion of the virtual pad 24. The first shielding layer 28 and the virtual pad 24 may be an integral structure. The orthographic projection of the first shielding layer 28 on the substrate 1 overlaps with the orthographic projection of at least one touch test trace 22 on the substrate 1. One first shielding layer 28 may overlap with the orthographic projections of multiple touch test traces 22 on the substrate 1. The first shielding layer 28 is electrically connected to the virtual pad 24, thus enabling the first shielding layer 28 to shield the touch test trace 22.

[0050] There are two first shielding layers 28. Part of the touch test traces 22 are located on one side of the bonding area 34 in the row direction and overlap with the orthographic projection of one first shielding layer 28 on the substrate 1. The other part of the touch test traces 22 are located on the other side of the bonding area 34 in the row direction and overlap with the orthographic projection of the other first shielding layer 28 on the substrate 1.

[0051] like Figure 7 As shown, a first shielding layer 28 is disposed on the side of the touch test trace 22 away from the substrate 1. The display panel also includes a second shielding layer 29, which is disposed on the side of the touch test trace 22 closer to the substrate 1. The orthographic projection of the second shielding layer 29 on the substrate 1 overlaps with the orthographic projection of at least one touch test trace 22 on the substrate 1, and the orthographic projection of the second shielding layer 29 on the substrate 1 overlaps with the orthographic projection of the first shielding layer 28 on the substrate 1. The second shielding layer 29 is electrically connected to the first shielding layer 28. With this configuration, the first shielding layer 28 and the second shielding layer 29 respectively form shields above and below the touch test trace 22. Taking the touch test trace 22 located on the second gate electrode layer 21 as an example, the second shielding layer 29 can be located on the first gate electrode layer 4. Furthermore, the orthographic projection of the second shielding layer 29 on the substrate 1 overlaps with the orthographic projection of the virtual pad 24 on the substrate 1.

[0052] To reduce radiated electromagnetic interference (EMI) of the touch test trace 22, this disclosure may also form isolation cells on the touch test trace 22. In one embodiment, such as Figure 9 As shown, the touch test trace 22 includes two first segments 2201 spaced apart and a second segment 2202 connecting the two first segments 2201 in its extension direction. The impedance of the second segment 2202 is greater than that of the first segment 2201, and this second segment 2202 constitutes the aforementioned isolation unit. Because the second segment 2202 has a higher impedance, the current transmitted from the touch signal line 25 to the touch test trace 22 can be limited. With a smaller current, radiated electromagnetic interference is correspondingly reduced. Specifically, the cross-sectional area of ​​the second segment 2202 is smaller than that of the first segment 2201, so that the impedance of the second segment 2202 is greater than that of the first segment 2201; alternatively, the first segment 2201 is a double-layer trace, and the second segment 2202 is a single-layer trace. Furthermore, the length of the first segment 2201 connected to the touch signal line 25 is shorter than the length of the other first segment 2201.

[0053] In another embodiment, such as Figure 10As shown, the display panel also includes multiple switching transistors 33, test control lines 31, and shutdown lines 32. The multiple switching transistors 33 correspond to multiple touch test lines 22. Each touch test line 22 includes two spaced-apart first segments 2201, and each switching transistor 33 is connected between the two first segments 2201 of its corresponding touch test line 22. The source of each switching transistor 33 is connected to one first segment 2201, and its drain is connected to the other first segment 2201. The length of the first segment 2201 connected to the touch signal line 25 is shorter than the length of the other first segment 2201. One end of the test control line 31 is electrically connected to the gate of the switching transistor 33, and the other end extends to the first edge 27 of the display panel. Figure 11 The diagram shows a display panel before cutting, comprising multiple control pads 30 connected to test control traces 31 via signal lines. Before cutting the display panel, a test (cell test) is required. A conduction signal is applied to the control pads 30, and the switching transistor 33 turns on upon receiving the conduction signal to perform touch testing. One end of the aforementioned shutdown trace 32 is electrically connected to the gate of the switching transistor 33, and the other end extends to the bonding region 34. After the driver chip IC is bonded to the bonding region 34, the shutdown trace 32 can be connected to the driver chip IC and receive a shutdown signal sent by the driver chip IC. The switching transistor 33 turns off upon receiving the shutdown signal. Furthermore, the shutdown trace 32 can be connected to the gate of the switching transistor 33 via the test control trace 31, thus saving wiring. In another embodiment, as... Figure 12 and Figure 13 As shown, the shutdown trace 32 can be connected to the test control line via a trace provided on the circuit board FPC.

[0054] This disclosure also provides a display module. The display module may include the aforementioned display panel, circuit board (FPC), and driver chip (IC). The driver chip (IC) may be disposed in the bonding area 34. The circuit board (FPC) may be bonded to the bonding pads 23. It should be understood that this display module has the same beneficial effects as the display panel provided in the foregoing embodiments.

[0055] Embodiments of this disclosure also provide a display device. This display device may include the display module described above. The display device may include, but is not limited to, any product or component with display functionality, such as electronic paper, mobile phones, tablet computers, monitors, laptops, digital photo frames, and navigators. It should be understood that this display device has the same beneficial effects as the display module provided in the foregoing embodiments.

[0056] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, comprising a display area and a peripheral area surrounding the display area, the peripheral area having a bonding area for bonding a driver chip, characterized in that, The display panel includes: Substrate; The touch electrode is disposed on one side of the substrate and located in the display area; Multiple touch test traces are provided, one end of each touch test trace is electrically connected to the touch electrode, and the other end extends to the first edge of the display panel. The bonding area is located between the first edge of the display panel and the display area in the column direction. Multiple bonding pads are provided in the peripheral area. In the column direction, the bonding pads are located on the side of the bonding area away from the display area. The bonding pads are used to connect to the circuit board. At least one virtual pad is provided in the peripheral area. In the column direction, the virtual pad is located on the side of the bonding area away from the display area. At least a portion of the virtual pad's orthogonal projection on the substrate overlaps with the orthogonal projection of the touch test trace on the substrate. The surface of the virtual pad away from the substrate can be attached to the circuit board.

2. The display panel according to claim 1, characterized in that, The virtual pads are used to connect to the fixed power signal terminals of the circuit board.

3. The display panel according to claim 2, characterized in that, The at least one virtual pad includes a plurality of virtual pads, some of which are located on one side of the bonded pad in the row direction, and other virtual pads are located on the other side of the bonded pad in the row direction.

4. The display panel according to claim 1 or 2, characterized in that, The display panel also includes: A first shielding layer is disposed on the side of the touch test trace that is away from or close to the substrate. The orthographic projection of the first shielding layer on the substrate overlaps with the orthographic projection of at least one of the touch test traces on the substrate. The first shielding layer is electrically connected to the virtual pad.

5. The display panel according to claim 4, characterized in that, The first shielding layer is disposed on the side of the touch test trace away from the substrate, and is disposed in the same layer as at least a portion of the virtual pad.

6. The display panel according to claim 5, characterized in that, Along a direction away from the substrate, the display panel includes a first gate electrode layer, a first source / drain electrode layer, and a second source / drain electrode layer disposed sequentially. At least a portion of the touch test trace is located on the first gate electrode layer, and at least a portion of the virtual pad and at least a portion of the first shielding layer are located on either the first source / drain electrode layer or the second source / drain electrode layer; or Along a direction away from the substrate, the display panel includes a first gate electrode layer, a second gate electrode layer, a first source / drain electrode layer, and a second source / drain electrode layer disposed sequentially. At least a portion of the touch test trace is located in the first gate electrode layer or the second gate electrode layer, and at least a portion of the virtual pad and at least a portion of the first shielding layer are located in the first source / drain electrode layer or the second source / drain electrode layer.

7. The display panel according to claim 4, characterized in that, The first shielding layer is disposed on the side of the touch test trace away from the substrate, and the display panel further includes: A second shielding layer is disposed on the side of the touch test trace close to the substrate. The orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of at least one of the touch test traces on the substrate. The orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of the first shielding layer on the substrate. The second shielding layer is electrically connected to the first shielding layer.

8. The display panel according to claim 7, characterized in that, The orthographic projection of the second shielding layer on the substrate overlaps with the orthographic projection of the virtual pad on the substrate.

9. The display panel according to claim 4, characterized in that, The number of the first shielding layers is two. Part of the touch test traces are located on one side of the bonding area in the row direction and overlap with the orthographic projection of one of the first shielding layers on the substrate; the other part of the touch test traces are located on the other side of the bonding area in the row direction and overlap with the orthographic projection of the other first shielding layer on the substrate.

10. The display panel according to claim 1, characterized in that, The touch test trace includes two first line segments spaced apart and a second line segment connecting the two first line segments, wherein the impedance of the second line segment is greater than the impedance of the first line segment.

11. The display panel according to claim 10, characterized in that, The cross-sectional area of ​​the second line segment is smaller than the cross-sectional area of ​​the first line segment; or The first line segment is a double-layered cable, and the second line segment is a single-layered cable.

12. The display panel according to claim 1, characterized in that, The display panel also includes: Multiple switching transistors are provided, corresponding to the multiple touch test traces. Each touch test trace includes two first line segments spaced apart, and each switching transistor is connected between the two first line segments of the corresponding touch test trace. The test control trace is electrically connected at one end to the gate of the switching transistor and extends to the first edge of the display panel at the other end. The turn-off trace has one end electrically connected to the gate of the switching transistor and the other end extending to the bonding region, and is used to receive the turn-off signal sent by the driver chip.

13. The display panel according to claim 1, 10, or 12, characterized in that, The display panel also includes: A touch signal line, one end of which is connected to the touch electrode, and the other end extends to the bonding area to connect with the driver chip; The end of the touch test trace away from the first edge of the display panel is connected between the two ends of the touch signal line.

14. The display panel according to claim 13, characterized in that, The length of the first line segment connected to the touch signal line is less than the length of the other first line segment.

15. A display module, characterized in that, include: The display panel according to any one of claims 1-14; The driver chip is bound to the binding area; A circuit board, connected to the bonding pads, and covering at least a portion of the surface of the virtual pads away from the substrate.

16. A display device, characterized in that, Includes the display module as described in claim 15.

Images