Storage system, controller, device, control method of storage system, and medium

Abstract

This application discloses a storage system, controller, device, control method for the storage system, and medium, relating to the field of storage technology. The storage system includes: a memory device and a memory controller. The memory controller caches first user data and system metadata. The memory controller is configured to: write system metadata to the memory device in response to a power failure event; and write the first user data to the memory device in response to the completion of writing the system metadata to the memory device. By writing the system metadata to the memory device in advance, the possibility of the storage system failing to resume normal operation due to unsuccessful writing of system metadata to the memory device is reduced, lowering the risk of the storage system becoming unusable and thus reducing the impact on user services.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage system, controller, device, control method for the storage system, and medium. Background Technology

[0002] In solid state drives (SSDs), a power failure event refers to a situation where the SSD device suddenly loses external power during normal operation.

[0003] In related technologies, when an SSD device experiences a power failure, the PLP (Power Loss Protection) process is used to reduce data loss.

[0004] However, during the PLP process, SSD devices often fail to boot and run normally (or become "bricked"). Summary of the Invention

[0005] This application provides a storage system, a controller, a device, a control method for the storage system, and a medium. The technical solution is shown below.

[0006] On one hand, a storage system is provided, the storage system comprising:

[0007] Memory devices, and

[0008] A memory controller, which caches first user data and system metadata, is configured to:

[0009] In response to a power failure event, the system metadata is written to the memory device; and

[0010] In response to the completion of writing the system metadata to the memory device, the first user data is written to the memory device.

[0011] In an optional embodiment, the memory controller is configured to:

[0012] In response to the completion of writing the system metadata to the memory device and the completion of the first write request processing submitted to the memory device, the first user data is written to the memory device;

[0013] The first write request is a write request submitted to the memory device before the power failure event occurs, and the first write request indicates that second user data cached in the memory controller be written to the memory device.

[0014] In an optional embodiment, the memory controller is configured to:

[0015] In response to the occurrence of the power failure event, a second write request is sent to the memory device, the second write request instructing the system metadata to be written to the memory device;

[0016] The memory device is configured as follows:

[0017] The second write request and the first write request are processed in parallel.

[0018] In an optional embodiment, the memory controller is configured to:

[0019] Upon completion of the first write request submitted to the memory device, the updated address mapping is written to the memory device.

[0020] The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

[0021] In an optional embodiment, the memory controller is configured to:

[0022] In response to the power failure event, the logical address corresponding to the user data that has not been written to the memory device is cached, and the user data that has not been written to the memory device includes the first user data;

[0023] In response to the completion of the logical address caching, the system metadata is written to the memory device.

[0024] In an optional embodiment, the memory controller is configured to:

[0025] In response to the occurrence of the power failure event, a reset request is sent to the memory device, the reset request indicating the termination of the data erasure event in the memory device.

[0026] In an optional embodiment, the memory controller is configured to:

[0027] In response to the occurrence of the power failure event, the address mapping data cached in the cache of the memory controller is written into the memory device, the address mapping data including the address mapping relationship between physical addresses and logical addresses;

[0028] In response to the completion of writing the address mapping data to the memory device, the system metadata is written to the memory device.

[0029] In an optional embodiment, the memory controller is configured to:

[0030] In response to the completion of writing the system metadata to the memory device, the verification information corresponding to the first user data is written to the memory device.

[0031] In an optional embodiment, the memory controller is configured to:

[0032] In response to the completion of writing the first user data to the memory device, the updated data of the system metadata cached in the cache of the memory controller is written to the memory device;

[0033] The updated data indicates the update status of the system metadata during the process of writing the system metadata and the first user data into the memory device.

[0034] In an optional embodiment, the storage system includes a solid-state drive (SSD).

[0035] In an optional embodiment, the memory device includes a single-level storage cell (SLC).

[0036] On the other hand, a memory controller is provided, including:

[0037] The cache is configured to cache first user data and system metadata;

[0038] One or more processors, said one or more processors being configured to:

[0039] In response to a power failure event, the system metadata is written to the memory device; and

[0040] In response to the completion of writing the system metadata to the memory device, the first user data is written to the memory device.

[0041] On the other hand, an electronic device is provided, the electronic device comprising:

[0042] The storage system as described in any of the above embodiments, and

[0043] The host coupled to the storage system.

[0044] On the other hand, a control method for a storage system is provided, the method comprising:

[0045] In response to a power failure event, the system metadata cached in the memory controller is written to the memory device;

[0046] In response to the completion of writing the system metadata to the memory device, the first user data cached in the memory controller is written to the memory device.

[0047] In an optional embodiment, the step of writing the first user data cached in the memory controller to the memory device in response to the completion of writing the system metadata to the memory device includes:

[0048] In response to the completion of writing the system metadata to the memory device and the completion of the first write request processing submitted to the memory device, the first user data is written to the memory device;

[0049] The first write request is a write request submitted to the memory device before the power failure event occurs, and the first write request indicates that second user data cached in the memory controller be written to the memory device.

[0050] In an optional embodiment, writing system metadata cached in the memory controller to the memory device in response to a power failure event includes:

[0051] In response to the occurrence of the power failure event, a second write request is sent to the memory device, the second write request instructing the system metadata to be written to the memory device;

[0052] The memory device is used to process the first write request and the second write request in parallel.

[0053] In an optional embodiment, the method further includes:

[0054] In response to the completion of the first write request processing after the system metadata has been written to the memory device and submitted to the memory device, the updated address mapping relationship is written to the memory device.

[0055] The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

[0056] In an optional embodiment, writing system metadata cached in the memory controller to the memory device in response to a power failure event includes:

[0057] In response to the power failure event, the logical address corresponding to the user data that has not been written to the memory device is cached, and the user data that has not been written to the memory device includes the first user data;

[0058] In response to the completion of the logical address caching, the system metadata is written to the memory device.

[0059] In an optional embodiment, the method further includes:

[0060] In response to the power failure event, a reset request is sent to the memory device, the reset request being used to terminate the data erase event in the memory device.

[0061] In an optional embodiment, writing system metadata cached in the memory controller to the memory device in response to a power failure event includes:

[0062] In response to the occurrence of the power failure event, the address mapping data cached in the memory controller is written into the memory device, the address mapping data including the address mapping relationship between physical addresses and logical addresses;

[0063] In response to the completion of writing the address mapping data to the memory device, the system metadata is written to the memory device.

[0064] In an optional embodiment, the method further includes:

[0065] In response to the completion of writing the system metadata to the memory device, the verification information corresponding to the first user data is written to the memory device.

[0066] In an optional embodiment, the method further includes:

[0067] In response to the completion of writing the first user data to the memory device, the updated data of the system metadata cached in the cache of the memory controller is written to the memory device;

[0068] The updated data is used to indicate the update status of the system metadata during the process of writing the system metadata and the first user data into the memory device.

[0069] In an optional embodiment, the storage system includes a solid-state drive (SSD).

[0070] In an optional embodiment, the memory device includes a single-level storage cell (SLC).

[0071] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored in the storage medium, and the at least one computer program is loaded and executed by a processor to implement the control method of the storage system described in any of the above embodiments.

[0072] The technical solution provided in this application may include the following beneficial effects.

[0073] In the event of a power outage, the system metadata cached in the memory controller is first written to the memory device to ensure its integrity. After the system metadata is written, the first user data cached in the memory controller is then written to the memory device. By writing the system metadata to the memory device in advance, the risk of the storage system failing to resume normal operation due to unsuccessful writing of system metadata is reduced, thus mitigating the impact on user services. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 This is a schematic diagram of a computer system provided in an exemplary embodiment of this application;

[0076] Figure 2 This is a schematic diagram of the structure of a solid-state drive provided in an exemplary embodiment of this application;

[0077] Figure 3 This is a schematic diagram of the structure of a memory device provided in an exemplary embodiment of this application;

[0078] Figure 4 This is a circuit diagram of a memory device provided in an exemplary embodiment of this application;

[0079] Figure 5 This is a schematic diagram of a storage system provided in an exemplary embodiment of this application;

[0080] Figure 6 This is a schematic diagram of a memory controller provided in an exemplary embodiment of this application;

[0081] Figure 7 This is a schematic diagram of a computer system provided in another exemplary embodiment of this application;

[0082] Figure 8 This is a flowchart of a control method for a storage system provided in an exemplary embodiment of this application;

[0083] Figure 9 This is an interactive flowchart of a control method for a storage system provided in an exemplary embodiment of this application;

[0084] Figure 10 This is an interactive flowchart of a control method for a storage system provided in another exemplary embodiment of this application;

[0085] Figure 11 This is an interactive flowchart of a control method for a storage system provided in another exemplary embodiment of this application. Detailed Implementation

[0086] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0087] First, the computer system involved in this application will be described.

[0088] The computer system provided in the embodiments of this application may include a host and a storage system. Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1 As shown, system 100 includes a storage system 102 and a host 108 coupled to the storage system 102. The storage system 102 includes a memory device 104 and a memory controller 106 coupled to the memory device 104 and configured to control the memory device 104.

[0089] In an alternative embodiment, system 100 can be integrated into various types of electronic devices. These electronic devices may include mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, and so on.

[0090] The storage system 102 can be implemented as a storage system of the type such as Universal Flash Storage (UFS) or Solid State Disk (SSD). In this embodiment, the storage system 102 is implemented as an SSD for illustration.

[0091] As another example Figure 2 This is a schematic diagram of the structure of a solid-state drive (SSD) involved in this application. Figure 2 As shown, the solid-state drive (SSD) 200 includes a storage device 104 and a storage controller 106. The solid-state drive 200 may also include a connector 210 for coupling the solid-state drive 200 to a host computer.

[0092] In an alternative embodiment, the memory device 104 may be implemented as a NAND flash memory, such as a 3D (3-Dimensional) NAND flash memory. The structure of the memory device 104 will be explained below.

[0093] Figure 3 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application. Figure 3 As shown, the memory device 104 includes peripheral circuitry 300 and a memory array 310.

[0094] The peripheral circuitry 300 is used to write data to and read data from the memory array 310. The peripheral circuitry 300 includes: a voltage generator 302, a page buffer / sensor amplifier 304, a column decoder / bit line (BL) driver 306, a row decoder / word line (WL) driver 308, control logic 312, a register 314, an input / output interface 316, and a data bus 318. It should be understood that in some examples, it may also include... Figure 3 Additional peripheral circuitry not shown.

[0095] Voltage generator 302 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 310.

[0096] Page buffer / sensor amplifier 304 can be configured to read data from memory array 310 and program (write) data to memory array 310 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store a page of programming data (write data) to be programmed into a page of memory array 310. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0097] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more memory strings (e.g., NAND memory strings) by applying a bit line voltage generated from voltage generator 302.

[0098] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select / deselect blocks of the memory array 310 and to select / deselect word lines of the blocks. The row decoder / word line driver 308 can also be configured to drive word lines using a word line voltage (VWL) generated from a voltage generator 302. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive source-select gate lines and drain-select gate lines. Illustratively, the row decoder / word line driver 308 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0099] Control logic 312 can be coupled to other components of each of the peripheral circuits described above and is configured to control the operation of the other components of each peripheral circuit.

[0100] Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0101] Input / output interface 316 can be coupled to control logic 312 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 312, as well as to buffer status information received from control logic 312 and relay it to the host. Input / output interface 316 can also be coupled to column decoder / bit line driver 306 via data bus 318 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory array 310.

[0102] Figure 4 This is a circuit diagram of a memory device provided in an embodiment of this application. Figure 4 As shown, the memory device 104 includes:

[0103] Storage array 310 includes multiple rows of storage cells.

[0104] Multiple word lines 420 are coupled to multiple rows of memory cells.

[0105] Peripheral circuit 300 is coupled to multiple word lines 420 and configured to perform operations such as programming (i.e., writing data) or reading data on selected memory lines among multiple memory cell lines, wherein the selected memory cell line is the memory cell line coupled to the selected word line, in order to perform operations such as programming or reading data.

[0106] The storage array 310 may be a flash memory storage array (such as a NAND flash memory array). The storage array 310 includes a plurality of storage strings 411 arranged in an array, each storage string 411 extending vertically above a substrate (not shown). In some embodiments, each storage string 411 includes a plurality of storage cells 412 that are serially coupled and vertically stacked. Storage cells 412 include, but are not limited to, single-level cells (SLC), multi-level cells (MLC), trinary-level cells (TLC), and quad-level cells (QLC).

[0107] like Figure 4 As shown, each memory string 411 may further include a source select gate (SSG) 413 located at the bottom and a drain select gate (DSG) 414 located at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 413 and the drain select gate 414 can be configured to activate the selected memory string 411 during read and program operations.

[0108] In some embodiments, the drain selection gate 414 of each memory string 411 is coupled to a corresponding bit line 415, and data can be read from or written to the bit line 415 via an output bus (not shown).

[0109] In some embodiments, each memory string 411 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 414) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 414 via one or more DSG lines 416. And / or, in some embodiments, each memory string 411 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 413) or a deselect voltage (e.g., 0V) to the corresponding source select gate 413 via one or more SSG lines 417.

[0110] like Figure 4As shown, the storage string 411 can be organized into multiple blocks 440. For any one of the multiple blocks 440, the block 440 can have a source line (SL) 418. The sources of all storage strings 411 in the block 440 are coupled through the source line 418. The source line is also called the common source line or array common source (ACS).

[0111] The source line 418 can be used for grounding, so that the sources of each memory cell in the memory string of block 440 can be grounded in some subsequent operations. Optionally, in some other operations, the sources of each memory cell in the memory string of block 440 can also be connected to a high voltage through the source line 418.

[0112] Each block 440 is the basic data unit used for the erase operation, meaning that all memory cells 412 on the same block 440 are erased simultaneously. To erase memory cells 412 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0113] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0114] like Figure 4 As shown, the same layer of storage cells 412 of adjacent storage strings 411 in the same block 440 can be coupled through word lines 420. Word lines 420 are used to select which layer of storage cells 412 in the block 440 is affected by read and program operations.

[0115] In some embodiments, each word line 420 is coupled to the page to which the memory cell 412 belongs, and a page is a basic unit of data used for programming operations. The size of a page may be related to the number of memory strings 411 coupled by word lines 420 in a block 440. Each word line 420 may be coupled to the control gate (i.e., gate electrode) of each memory cell 412 in the corresponding page. It is understood that a memory cell row is a plurality of memory cells 412 located on the same page.

[0116] It should be noted that within a block 440, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple one or more pages.

[0117] Peripheral circuitry 300 can be coupled to memory array 310 via bit line 415, word line 420, source line 418, SSG line 417, and DSG line 416. Peripheral circuitry 300 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 310 by applying voltage and / or current signals to memory cells 412 and sensing voltage and / or current signals from memory cells 412 via bit line 415, word line 420, source line 418, SSG line 417, and DSG line 416.

[0118] For any technical details not disclosed in the above hardware embodiments of the computer system, please refer to the descriptions of the storage system embodiments, memory controller embodiments, and method embodiments of this application for understanding.

[0119] Secondly, the storage system involved in this application will be described, and the controller of the storage system involved in the embodiments of this application will be described. The law is executed by this storage system.

[0120] In storage systems, such as solid-state drives (SSDs), a power failure event refers to the sudden loss of external power supply during normal operation of the SSD. Related technologies utilize a Power Loss Protection (PLP) process to minimize data loss when an SSD experiences a power failure. However, during the PLP process, SSDs frequently fail to boot and operate normally (or become "bricked").

[0121] Based on this, this application provides a storage system that can reduce the phenomenon that the storage system cannot resume normal operation due to the failure of system metadata to be successfully written to the storage device, reduce the risk of the storage system becoming "bricked", and thus reduce the impact on user business.

[0122] Figure 5 This is a schematic diagram of a storage system 102 provided in an embodiment of this application. Figure 5 As shown, the storage system 102 includes a memory device 104 and a memory controller 106. Optionally, the storage system 102 includes a solid-state drive (SSD). Optionally, the memory device 104 includes a single-level storage cell (SLC).

[0123] The memory controller 106 caches first user data and system metadata. Illustratively, the memory controller 106 includes a cache that caches the first user data and system metadata.

[0124] User data refers to data that users actively store in storage system 102, such as documents, pictures, videos, application files, etc., which is information that users can directly access and use.

[0125] First user data: This refers to user data temporarily stored in the memory controller 106 and yet to be written to the memory device 104. It is illustrative. When a user initiates a write request, the user data will first enter the buffer of the memory controller 106, and then be gradually written to the memory device 104 by the memory controller 106. First user data refers to user data that is temporarily stored in the buffer of the memory controller 106 and has not yet been written to the memory device 104.

[0126] System metadata: This refers to auxiliary data generated and maintained by the storage system 102 (such as an SSD) during operation. In other words, system metadata is auxiliary data generated by the storage system 102 to manage its own operation. System metadata is used to record the management information, operating status, and key parameters of the storage system 102 to ensure that the storage system 102 continues to operate normally the next time it is powered on. For example, after a power outage event occurs, the system metadata can ensure that the storage system 102 continues to operate normally after power is restored.

[0127] Schematic representation: System metadata includes at least one of the following:

[0128] (1) Address mapping management information

[0129] Address mapping management information includes the update location of the address mapping table, which is used to record L2P (Logical to Physical) mapping information of user data.

[0130] As an illustration, when the L2P mapping information of user data changes, a journal and a snapshot are generated. At this time, the update position of the journal and snapshot is recorded (as system metadata) so that the relevant journal and snapshot can be quickly found when the storage system 102 needs them.

[0131] (2) Memory management information

[0132] Memory management information includes a bad block table and super block information. The bad block table is used to mark unusable or damaged physical blocks in a memory device (e.g., NAND flash memory). The super block information is used to record the status of super blocks (logical units composed of multiple physical blocks) (such as erase / write cycles and remaining lifetime).

[0133] (3) Event log update location

[0134] During the operation of storage system 102, various event logs are generated. It is necessary to record the update location of the event logs (as system metadata) so that storage system 102 can quickly find the relevant event logs when needed.

[0135] It should be noted that the above examples of system metadata are merely illustrative. This application does not limit the specific data types of system metadata. For example, system metadata can also be implemented as: ECC (Error Correction Code) verification information, power management status, firmware version, etc.

[0136] In some embodiments, the memory controller 106 includes a cache that caches first user data and system metadata.

[0137] The memory controller 106 is configured to: write system metadata to the memory device 104 in response to a power failure event; and write first user data to the memory device 104 in response to the completion of writing system metadata to the memory device 104.

[0138] A power failure event refers to an event in which the storage system 102 fails to function properly due to a power supply interruption. In the storage system 102, the methods for detecting a power failure event include at least one of the following: (1) The memory controller 106 monitors the power supply voltage in real time, and determines that a power failure event has occurred when a sudden drop in power supply voltage or a voltage below a threshold is detected. (2) When the memory controller 106 receives an interrupt signal, it determines that a power failure event has occurred, wherein the interrupt signal may be sent by the power management chip inside the storage system 102, or by other external devices connected to the storage system 102.

[0139] After a power failure event occurs, the storage system 102 enters the PLP process. Schematic, the storage system 102 is equipped with a backup capacitor, which can provide power support to the storage system 102 for a period of time. When a power failure event occurs in the storage system 102, the PLP process is implemented through the backup capacitor. Taking SSD as an example, a backup capacitor can be soldered on the SSD's printed circuit board (PCB). After a power failure event occurs in the SSD, the backup capacitor provides power to the SSD, enabling the SSD to enter the PLP process.

[0140] In this application, the PLP process executed in the storage system 102 is as follows: writing system metadata to the memory device 104; and in response to the completion of writing system metadata to the memory device 104, writing first user data to the memory device 104. By writing system metadata to the memory device 104 in advance, the possibility of the storage system 102 failing to resume normal operation due to unsuccessful writing of system metadata to the memory device 104 is reduced. It should be emphasized that the method provided in this application is particularly applicable to PLP anomaly scenarios, which include, but are not limited to: backup capacitors being less than a preset value (i.e., insufficient backup capacitors), backup capacitor performance degradation, and extreme temperatures (such as high temperatures causing backup capacitor performance degradation).

[0141] In PLP (Power Buffer) failure scenarios, using the method provided in this application, if a power outage occurs and the backup capacitor can only provide power support for 2-3 seconds, within these limited 2-3 seconds, system metadata is first written to the memory device 104. If there is still power remaining, the first user data is written to the memory device 104. This maximizes the probability of ensuring the integrity of the system metadata, so that after the storage system 102 recovers power, the completed system metadata can guarantee the normal operation of the storage system 102, reducing the probability of the system becoming unusable. In some embodiments, the aforementioned system metadata refers to the system metadata stored in the cache of the memory device 104 when a power outage occurs, which can be called the first system metadata. Immediately after the power outage occurs, the first system metadata is written to the memory device 104. The first system metadata is the system metadata first written to the memory device 104 after the power outage occurs.

[0142] Optionally, the memory controller 106 is configured to send a second write request to the memory device 104 in response to a power failure event. The second write request instructs the writing of system metadata to the memory device 104. Illustratively, the second write request instructs the writing of system metadata to the SLC of the memory device 104. When a power failure event occurs in the storage system 102, the memory controller 106 first retrieves the system metadata currently cached in the cache (the cache within the memory controller 106), encapsulates this system metadata into the second write request, and sends the second write request to the memory device 104. Upon receiving the second write request, the memory device 104 executes the write process for the system metadata contained therein.

[0143] In some embodiments, the memory controller 106 is configured to cache the logical address corresponding to user data that has not been written to the memory device 104 in response to a power failure event, wherein the user data that has not been written to the memory device 104 includes first user data.

[0144] Here, the logical address is the address used by the user or file system to access user data, and it is different from the actual physical address inside the memory device 104. In this application, when a power failure event occurs in the storage system 102, the memory controller 106 records the logical addresses of user data that have not been written to the memory device 104. Optionally, the memory controller 106 includes an address cache unit, which can be implemented as a CU (Cache Unit). The address cache unit is used to cache the logical addresses of user data; that is, when a power failure event occurs in the storage system 102, the memory controller 106 caches the logical addresses of user data that have not been written to the memory device 104 into the address cache unit.

[0145] In the above scheme, when a power failure occurs, the memory controller 106 caches the logical addresses corresponding to the user data not written to the memory device 104, facilitating subsequent data recovery. During the storage system recovery process, the memory controller 106 directly determines which data needs to be written from the cache to the memory device 104 based on the cache's logical addresses, simplifying the data recovery process and improving recovery efficiency.

[0146] Optionally, in response to the completion of logical address caching, system metadata is written to memory device 104. That is, when a power failure event occurs in storage system 102, memory controller 106 first caches the logical addresses of user data that have not yet been written to memory device 104, and after caching is complete, writes system metadata to memory device 104. In some embodiments, the aforementioned logical addresses may be part of the system metadata; that is, after logical address caching is complete, the logical addresses cached by memory controller 106 are written to memory device 104 together with other system metadata.

[0147] Alternatively, in response to a power failure event, the logical address corresponding to the user data not written to the memory device 104 is cached, and system metadata is written to the memory device 104. Schematic, after a power failure event, the memory controller 106 caches the logical address of the user data not written to the memory device 104, and at the same time, the memory controller 106 writes system metadata to the memory device 104.

[0148] Optionally, the user data not written to the memory device 104 also includes second user data.

[0149] Second user data refers to user data requested for writing in write requests submitted to memory device 104 but not yet completed before a power failure event (i.e., the first write request described below). Illustratively, when a user initiates a write request, the user data first enters the cache of memory controller 106, and is then gradually written to memory device 104 by memory controller 106. User data that has entered the write process of memory device 104 but has not been completed is the second user data. For example, in an SSD, user data that has begun writing to flash memory (such as NAND flash memory) but has not yet completed the erase, programming, or verification steps.

[0150] In some embodiments, the memory controller 106 is configured to: in response to a power failure event, write address mapping data cached in the register of the memory controller 106 into the memory device 104. The address mapping data includes an address mapping relationship between physical addresses and logical addresses. Schematic, the address mapping data includes an address mapping relationship between physical addresses and logical addresses of user data already stored in the memory device. Optionally, in response to a power failure event, the address mapping data cached in the register of the memory controller 106 is written into an SLC or TLC in the memory device 104.

[0151] The memory device 104 can recover the correct access path of data through the written address mapping relationship, which improves the success rate of data recovery and enhances the fault tolerance of the storage system 102.

[0152] The physical address refers to the actual storage location of the memory device 104. Illustratively, the memory controller 106 stores an address mapping table in its register. This address mapping table records the address mapping relationship between physical addresses and logical addresses. In this application, when a power failure occurs in the storage system 102, the memory controller 106 writes the address mapping table into the memory device 104.

[0153] Optionally, in response to the completion of writing address mapping data to memory device 104, system metadata is written to memory device 104. That is, when a power failure event occurs in storage system 102, memory controller 106 first writes address mapping data to memory device 104, and after the address mapping data is written to memory device 104, writes system metadata to memory device 104.

[0154] Alternatively, in response to a power failure event, the address mapping data cached in the register of the memory controller 106 is written to the memory device 104, and system metadata is written to the memory device 104. Schematic, after a power failure event, the memory controller 106 writes the address mapping data to the memory device 104, and at the same time, the memory controller 106 writes system metadata to the memory device 104.

[0155] In some embodiments, in response to a power failure event, the logical addresses corresponding to user data not yet written to memory device 104 are cached; in response to the completion of logical address caching, the address mapping data cached in the cache of memory controller 106 is written to memory device 104; in response to the completion of writing the address mapping data to memory device 104, system metadata is written to memory device 104. Illustratively, after a power failure event, memory controller 106 first caches the logical addresses of user data not yet written to memory device 104; after caching is complete, memory controller 106 writes the address mapping table to memory device 104; and after the address mapping table is written to memory device 104, system metadata is written to memory device 104.

[0156] Schematic, the logical address (which may be called the target logical address) corresponding to the user data not yet written to memory device 104 is recorded in the address mapping table cached by memory controller 106. In the address mapping table, the physical address corresponding to the target logical address is marked as UNC. UNC is used to declare that the physical address corresponding to the logical address is in an undetermined state. Then, this address mapping table is written to memory device 104 as address mapping data so that storage system 102 can accurately determine the user data that needs to be written to memory device 104.

[0157] In other embodiments, in response to a power failure event, the logical addresses corresponding to user data not yet written to memory device 104 are cached, and the address mapping data cached in the cache of memory controller 106 is written to memory device 104, and system metadata is written to memory device 104. Illustratively, after a power failure event, memory controller 106 caches the logical addresses of user data not yet written to memory device 104, and simultaneously, memory controller 106 writes the address mapping table to memory device 104 and writes system metadata to memory device 104.

[0158] In some embodiments, the memory controller 106 is configured to send a reset request to the memory device 104 in response to a power failure event. The reset request indicates the termination of a data erasure event in the memory device 104. Illustratively, when a power failure event occurs in the storage system 102, the memory controller 106 sends a reset signal to the memory device 104. Upon receiving the reset signal, the memory device 104 terminates the current data erasure operation. After the data erasure operation is terminated, the memory device 104 can immediately perform a data write operation, thereby ensuring that new data (such as system metadata, first user data, etc.) can be stored in a timely manner.

[0159] Optionally, the memory controller 106 may send a reset request to the memory device 104 at any time after a power failure event. Illustratively, when a power failure event occurs in the storage system 102, the memory controller 106 immediately sends a reset request to the memory device 104; or, after a power failure event occurs in the storage system 102, once the system metadata and second user data have been written to the memory device 104, the memory controller 106 immediately sends a reset request to the memory device 104.

[0160] In some embodiments, the memory controller 106 is configured to write verification information corresponding to the first user data into the memory device 104 in response to the completion of writing system metadata into the memory device 104.

[0161] Indicatively, after writing system metadata and second user data into memory device 104, the verification information corresponding to the first user data is written into the SLC in memory device 104; or, after writing system metadata, second user data and first user data into memory device 104, the verification information corresponding to the first user data is written into the SLC in memory device 104.

[0162] By writing the verification information corresponding to the first user data into the memory device 104, a direct basis is provided for subsequent data integrity verification. During the data reading or recovery process, the data integrity and accuracy can be accurately determined by comparing the verification information with the actual data read, effectively avoiding information inconsistency caused by data damage or loss, and improving the reliability and trustworthiness of the data.

[0163] Optionally, in response to the completion of writing system metadata to the memory device 104, the verification information corresponding to the first user data is written to the SLC in the memory device 104. Optionally, the verification information can be implemented as a RAID checksum, which is generated through an XOR operation. Illustratively, the first user data includes at least two data blocks, and the verification information refers to the XOR result between at least two data blocks. For example: verification information = user data AXOR user data B; or, verification information = user data AXOR user data B XOR user data C. Here, "XOR" represents the XOR operation symbol. Data recovery or repair operations can be performed using the RAID checksum and remaining data, reducing data loss and improving the system's fault tolerance and recovery capabilities.

[0164] In some embodiments, the memory controller 106 is configured to write updated system metadata cached in the cache of the memory controller 106 to the memory device 104 in response to the completion of writing the first user data to the memory device 104. The updated data indicates the update status of the system metadata during the process of writing the system metadata and the first user data to the memory device 104.

[0165] Optionally, in response to the completion of writing the first user data to the memory device 104, update data of the system metadata cached in the cache of the memory controller 106 is written to the SLC of the memory device 104.

[0166] Schematic illustration: After the memory controller 106 successfully writes the first user data to the memory device 104, it writes the updated system metadata cached in the register to the memory device 104. This updated data records the updates to the system metadata that occur throughout the process of writing the system metadata and the first user data to the memory device 104.

[0167] By writing updated system metadata into the memory device 104, the system metadata stored in the memory device 104 is ensured to reflect the latest system status, which improves the accuracy of the system metadata, facilitates subsequent data recovery, and avoids problems such as data read / write errors caused by untimely updates of system metadata.

[0168] In some embodiments, the first user data includes at least two sub-data. In response to the completion of writing the (i+1)th sub-data to the memory device 104, the (i+1)th updated data cached in the register of the memory controller 106 is written to the memory device 104. The (i+1)th updated data indicates the update status of system metadata during the writing of the ith sub-data to the memory device 104. i is a positive integer.

[0169] This is illustrated illustratively, using an example of at least two sub-data items, including a first sub-data item and a second sub-data item. First sub-data is written to memory device 104. In response to the completion of writing the first sub-data to memory device 104, first updated data of system metadata cached in the cache of memory controller 106 is written to memory device 104. The first updated data indicates the update status of the system metadata during the process of writing the system metadata and the first sub-data to memory device 104. In response to the completion of writing the first updated data to memory device 104, second sub-data is written to memory device 104. In response to the completion of writing the second sub-data to memory device 104, second updated data of system metadata cached in the cache of memory controller 106 is written to memory device 104. The second updated data indicates the update status of the system metadata during the process of writing the second sub-data to memory device 104.

[0170] In the above scheme, during the process of writing the first user data into the memory device 104, the updated system metadata is written into the memory device 104 in stages to ensure the timeliness of the system metadata and further ensure that the system metadata stored in the memory device 104 can reflect the latest system status.

[0171] In some embodiments, if there was a write request submitted to memory device 104 but not completed before the power failure event occurred:

[0172] The memory controller 106 is also configured to write first user data to the memory device 104 in response to the completion of writing system metadata to the memory device 104 and the completion of processing of a first write request submitted to the memory device 104. The first write request is a write request submitted to the memory device 104 before a power failure event occurs, and the first write request indicates that second user data cached in the memory controller 106 be written to the memory device 104.

[0173] Optionally, in response to the completion of writing system metadata to memory device 104 and the completion of the first write request processing submitted to memory device 104, the first user data is written to the SLC of memory device 104.

[0174] After a power failure occurs, if there is a first write request in the storage system 102, the memory device 104 is configured to: process the second write request and the first write request in parallel; or suspend processing of the first write request; and resume processing of the first write request in response to the completion of the second write request.

[0175] (1) When the memory device 104 processes the second write request and the first write request in parallel: After a power failure event occurs, the memory controller 106 immediately sends the second write request to the memory device 104. The memory device 104 executes the write process of system metadata based on the second write request. At the same time, the memory device 104 continues to execute the write process of the second user data.

[0176] In this scenario, the memory device 104 is allowed to simultaneously process the pre-power-down request (second user data) and the power-down triggered system metadata write request (second write request). The parallel processing capability of the memory device 104 shortens the overall write time, completes more critical operations within a limited spare capacitor window, and improves data retention efficiency.

[0177] (2) The memory device 104 suspends processing of the first write request; in response to the completion of the second write request, the processing of the first write request is resumed: after a power failure event occurs, the memory device 104 suspends the writing process of the second user data, and the memory controller 106 immediately sends the second write request to the memory device 104. The memory device 104 executes the writing process of system metadata based on the second write request; after the system metadata is written to the memory device 104, the memory device 104 continues the writing process of the second user data.

[0178] In this case, the memory device 104 is allowed to prioritize system metadata write requests (second write requests) to ensure the storage integrity of system metadata.

[0179] In some embodiments, if the capacity of the backup capacitor is less than a preset capacity, processing of the first write request is paused; processing of the first write request resumes upon completion of processing of the second write request. If the capacity of the backup capacitor is greater than or equal to the preset capacity, the second write request and the first write request are processed in parallel.

[0180] It should be noted that in this application, the second write request is usually completed before the first write request. That is, the storage system 102 will first complete the writing of system metadata to the storage device 104, and then complete the writing of the second user data to the storage device 104. This is because the physical amount of system metadata written is much smaller than that of user data (e.g., user data is in MB / GB, while system metadata is only in KB), which makes the writing of system metadata complete faster.

[0181] In some embodiments, the memory controller 106 is configured to write an updated address mapping to the memory device 104 in response to the completion of processing a first write request submitted to the memory device 104.

[0182] The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data. Illustratively, the memory controller 106 stores an address mapping table in its cache. This table records the address mapping relationship between physical and logical addresses. In this application, when a power failure occurs in the storage system 102, the memory controller 106 caches the logical address of the second user data. When the first write request submitted to the memory device 104 is processed, that is, the second user data has been written to the memory device 104, the actual physical address and the logical address of the second user data can be used as the new address mapping relationship to update the address mapping table (that is, the mapping relationship between the physical address and the logical address of the second user data is recorded in the address mapping table). Then, the updated address mapping table is written to the memory device 104; or, the mapping relationship between the physical address and the logical address of the second user data can be directly written to the memory device 104.

[0183] Optionally, if the address mapping table records the logical address of the second user data and the corresponding physical address identifier is UNC, then the identifier UNC is directly updated to the actual physical address of the second user data. Then, the updated address mapping table is written to the memory device 104.

[0184] In some embodiments, the updated address mapping relationship also includes the mapping relationship between the logical address and the physical address of the system metadata.

[0185] Indicatively, when the second write request submitted to the memory device 104 is completed, that is, the system metadata has been written to the memory device 104, the actual physical address and the logical address of the system metadata can be used as a new address mapping relationship to update the address mapping table (that is, the mapping relationship between the physical address and the logical address of the system metadata is recorded in the address mapping table), and then the updated address mapping table is written to the memory device 104; or, the mapping relationship between the physical address and the logical address of the system metadata can be directly written to the memory device 104.

[0186] In the above scheme, after the data is written, the updated address mapping relationship (the mapping table between logical address and physical address) is written immediately to avoid data addressing errors caused by the address mapping not being updated.

[0187] In some embodiments, the memory controller 106 is configured to write updated system metadata cached in the cache of the memory controller 106 to the memory device 104 in response to the completion of writing the first user data to the memory device 104. The updated data indicates the update status of the system metadata during the process of writing the system metadata and the first user data to the memory device 104.

[0188] Schematic illustration: After the memory controller 106 successfully writes the first user data to the memory device 104, it writes the updated system metadata cached in the register to the memory device 104. This updated data records the updates to the system metadata that occur throughout the entire process of writing the system metadata and the first user data to the memory device 104.

[0189] In summary, the storage system 102 provided in this application, when a power failure occurs, first writes the system metadata cached in the memory controller 106 to the memory device 104 to ensure the integrity of the system metadata. After the system metadata is written, it then writes the first user data cached in the memory controller 106 to the memory device 104. Because the system metadata is written to the memory device 104 in advance, the possibility of the storage system 102 failing to resume normal operation due to unsuccessful writing of system metadata to the memory device 104 is reduced, lowering the risk of the storage system 102 becoming unusable and thus reducing the impact on user services.

[0190] Next, the memory controller involved in this application will be described, and the memory system involved in the embodiments of this application will be explained. The control method is executed by the memory controller.

[0191] Figure 6 This is a schematic diagram of a memory controller 106 provided in an embodiment of this application. Figure 6 As shown, the memory controller 106 includes a cache 601 and one or more processors 602.

[0192] Cache 601 is configured to cache first user data and system metadata. Optionally, cache 601 includes a buffer and a cache in memory controller 106, wherein both the buffer and the cache can be implemented as dynamic random access memory (DRAM). Illustratively, the first user data is cached in the buffer and the system metadata is cached in the cache; or both the first user data and the system metadata are cached in the buffer, without limitation here.

[0193] One or more processors 602 are configured to: write system metadata to memory device 104 in response to a power failure event; and write first user data to memory device 104 in response to completion of writing system metadata to memory device 104.

[0194] In some embodiments, one or more processors 602 are configured to write first user data to memory device 104 in response to the completion of writing system metadata to memory device 104 and the completion of processing of a first write request submitted to memory device 104; wherein the first write request is a write request submitted to memory device 104 before a power failure event occurs, and the first write request indicates writing second user data cached in memory controller 106 to memory device 104.

[0195] In some embodiments, one or more processors 602 are configured to send a second write request to memory device 104 in response to a power failure event, the second write request indicating that system metadata be written to memory device 104.

[0196] In some embodiments, one or more processors 602 are configured to write an updated address mapping relationship into the memory device 104 in response to the completion of a first write request submitted to the memory device 104; wherein the updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

[0197] In some embodiments, one or more processors 602 are configured to: in response to a power failure event, cache the logical address corresponding to user data not written to the memory device 104, the user data not written to the memory device 104 including first user data; and in response to the logical address caching being completed, write system metadata to the memory device 104. Optionally, the user data not written to the memory device 104 may also include second user data.

[0198] In some embodiments, one or more processors 602 are configured to send a reset request to memory device 104 in response to a power failure event, the reset request indicating the termination of a data erasure event in memory device 104.

[0199] In some embodiments, one or more processors 602 are configured to: in response to a power failure event, write address mapping data cached in the cache 601 of the memory controller 106 to the memory device 104, the address mapping data including the address mapping relationship between physical addresses and logical addresses; and in response to the completion of writing the address mapping data to the memory device 104, write system metadata to the memory device 104.

[0200] In some embodiments, one or more processors 602 are configured to write verification information corresponding to the first user data into the memory device 104 in response to completion of writing system metadata into the memory device 104.

[0201] In some embodiments, one or more processors 602 are configured to: in response to completion of writing first user data to memory device 104, write updated data of system metadata cached in cache 601 of memory controller 106 to memory device 104; wherein the updated data indicates the update status of system metadata during the process of writing system metadata and first user data to memory device 104.

[0202] The following explanation uses the storage system provided in this application, implemented as a solid-state drive (SSD), as an example.

[0203] Figure 7 This is a schematic diagram of a computer system provided in an embodiment of this application. For example... Figure 7 As shown, the computer system includes a solid-state drive (SSD) and a host 108.

[0204] The solid-state drive (SSD) includes a storage device 104 and a storage controller 106. Illustratively, the storage controller 106 may be implemented as a System-on-Chip (SOC) chip within the SSD; or the storage controller 106 may be integrated onto the SOC chip within the SSD.

[0205] Memory device 104: This is the part of the SSD used for storing data, typically composed of flash memory (such as NAND flash memory). Memory device 104 is responsible for storing user data and system metadata.

[0206] The memory controller 106 is the core control unit in an SSD, responsible for managing data read / write operations, address mapping, error detection, and correction. The components of the memory controller 106 are as follows:

[0207] Buffer 601: Used for temporary data storage to improve data read and write speed. During write operations, user data is first written to buffer 601, and then gradually written to memory device 104. This reduces frequent access to memory device 104 and improves overall performance.

[0208] One or more processors 602: execute the core control logic of the SSD, such as the PLP process in this application.

[0209] Read-Only Memory (ROM) 603: The ROM is used to store firmware and boot code, which runs when the SSD is powered on, initializes the memory controller 106 and starts the storage system 102.

[0210] Tightly Coupled Memory (TCM) 604: This is a high-speed memory used to store frequently accessed data and code. Tightly coupled memory can provide low-latency access, improving processor performance.

[0211] Hardware Accelerator (Accelerator) 605: Used to accelerate specific operations, such as data encryption, decryption, and compression.

[0212] Error Correction Code Engine (ECC Engine) 606: Used to detect and correct errors during data transmission. By adding redundant information to the original data, the ECC Engine 606 uses this additional information at the receiving end to identify and correct potential errors, significantly improving data integrity and reliability.

[0213] Flash controller 607: Responsible for directly managing the operation of flash memory (such as NAND flash memory), including read and write operations, block management, wear leveling, and garbage collection. Flash controller 607 ensures the efficient and reliable operation of flash memory.

[0214] First interface 608: The first interface is used to connect the host 108 and the memory controller 106, ensuring that the host 108 can perform efficient data exchange with the SSD. For example... Figure 7 As shown, "lane0-lane4" between the first interface 608 and the host 108 represents the physical connection channel between the memory controller 106 and the host 108.

[0215] Second interface 609: The second interface is used to connect the memory device 104 and the memory controller 106, enabling data transmission between the memory device 104 and the memory controller 106. For example... Figure 7 As shown, "Channel#0-Channel#N" between the second interface 609 and the memory device 104 represent independent data channels for data exchange between the memory controller 106 and the memory device 104.

[0216] In this application, the tightly coupled memory (TCM) 604 or the cache in the memory controller 106 Figure 7 The target code (not shown) runs in the memory device 104. The target code is used to implement the PLP process in the SSD, which is the control method of the storage system provided in this application. The target code is stored in the memory device 104.

[0217] In this application, the PLP (Power Loss Protection) process refers to the handling process when an SSD experiences a power loss event. The stages of the PLP process, the meaning of each stage, and the corresponding processing time and energy consumption (i.e., the consumption of backup capacitors) can be found in Table 1.

[0218] Table 1

[0219]

[0220]

[0221] Here, "flush" refers to writing data from the SSD's memory controller 106 to the memory device 104.

[0222] The LBAs (Logical Addresses) that record un-flushed data (i.e., logical addresses of all data submitted to flash memory but not yet completed, and data still in the buffer and not yet flushed) have a much smaller data size than an entire SLC stripe during system metadata flushing. In other words, system metadata flushing typically occupies the storage space of an entire SLC stripe, while the data size of the LBAs recording un-flushed data is much smaller than the size of this SLC stripe. If n = 0.43ms and m = 5.4mJ, then the total duration in Table 1 above is 9.33ms, and the energy consumption is 141.09mJ. If LBAs containing un-flushed data are stored, the physical addresses in the address mapping data (L2P) corresponding to these LBAs are updated to (incomplete or uncertain states) so that the storage system can correctly process this data when power is restored.

[0223] The detection process for the PLP process in this application is as follows: the capacitance value (i.e., power consumption) required for the PLP process can be calculated by reading the health status, and the capacitance value can be reduced by disconnecting the capacitor (only applicable to solutions using multiple capacitors). After reducing the capacitance value, the PLP process is triggered to detect whether the SSD becomes bricked under abnormal PLP scenarios.

[0224] This example illustrates how the minimum capacitance required for the current PLP process is calculated by reading SSD health status parameters (such as NAND flash memory lifespan and temperature). Taking the SSD health status shown in Table 1 as an example, using the storage system control method provided in this application, the capacitance required to complete the system metadata flushing is 17.4mJ + 5.4mJ + 5.44mJ + 5.4mJ = 33.64mJ. Under the same conditions, if a PLP process that prioritizes flushing user data before flushing system metadata is adopted, the capacitance required to complete the system metadata flushing is 124.85mJ.

[0225] The total capacitance is reduced by disconnecting some capacitors. A forced power-off is performed and a PLP process is triggered. Under different capacitance conditions, the SSD is checked to see if it becomes bricked. When the total capacitance is reduced to below 124.85mJ, such as 120mJ, if the PLP process of prioritizing the flushing of user data before flushing system metadata is used, the SSD may become bricked; if the control method of the storage system provided in this application is used, the SSD will not become bricked.

[0226] In summary, the solid-state drive (SSD) provided in this application immediately flushes system metadata after the PLP processing flow stops the current system task, and then processes the write commands submitted to the flash memory and flushes the user data in the buffer. In PLP abnormal scenarios (such as when there are few backup capacitors), the system will not become bricked due to the failure to flush system metadata. This reduces the risk of the SSD becoming bricked in PLP abnormal scenarios, thereby shortening the time for users to recover data and reducing the impact on user business.

[0227] Next, the specific process of the control method for the storage system involved in this application will be described.

[0228] Figure 8 This is a flowchart illustrating a control method for a storage system according to an embodiment of this application. The storage system 102 provided in this application includes a memory device 104 and a memory controller 106. Optionally, the storage system 102 includes a solid-state drive (SSD). Optionally, the memory device 104 includes a single-level storage cell (SLC).

[0229] The control method for the aforementioned storage system is executed by the memory controller 106. This method includes steps 810 and 820.

[0230] Step 810: In response to a power failure event, system metadata cached in memory controller 106 is written to memory device 104.

[0231] Optionally, the memory controller 106 includes a cache 601, which caches system metadata.

[0232] In some embodiments, in response to a power failure event, a second write request is sent to the memory device 104, the second write request instructing the memory device 104 to write system metadata; wherein the memory device 104 is used to process the first write request and the second write request in parallel.

[0233] In some embodiments, in response to a power failure event, the logical address corresponding to user data not written to the memory device 104 is cached, and the user data not written to the memory device 104 includes first user data; in response to the completion of logical address caching, system metadata is written to the memory device 104.

[0234] In some embodiments, in response to a power failure event, a reset request is sent to the memory device 104 to terminate the data erasure event in the memory device 104.

[0235] In some embodiments, in response to a power failure event, address mapping data cached in the memory controller 106 is written to the memory device 104, the address mapping data including the address mapping relationship between physical addresses and logical addresses; in response to the completion of writing the address mapping data to the memory device 104, system metadata is written to the memory device 104.

[0236] Step 820: In response to the completion of writing system metadata to memory device 104, the first user data cached in memory controller 106 is written to memory device 104.

[0237] Optionally, the memory controller 106 includes a cache 601, which caches the first user data.

[0238] In some embodiments, in response to the completion of writing system metadata to memory device 104 and the completion of processing of a first write request submitted to memory device 104, first user data is written to memory device 104; wherein, the first write request is a write request submitted to memory device 104 before a power failure event occurs, and the first write request indicates that second user data cached in memory controller 106 be written to memory device 104.

[0239] In some embodiments, in response to the completion of writing system metadata to memory device 104 and the completion of a first write request processing submitted to memory device 104, an updated address mapping relationship is written to memory device 104; wherein the updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

[0240] In some embodiments, in response to the completion of writing system metadata to memory device 104, verification information corresponding to the first user data is written to memory device 104.

[0241] In some embodiments, in response to the completion of writing the first user data to the memory device 104, update data of the system metadata cached in the cache 601 of the memory controller 106 is written to the memory device 104; wherein the update data is used to indicate the update status of the system metadata during the process of writing the system metadata and the first user data to the memory device 104.

[0242] In summary, the storage system control method provided in this application, when a power failure occurs, first writes the system metadata cached in the memory controller 106 to the memory device 104 to ensure the integrity of the system metadata. After the system metadata is written, the first user data cached in the memory controller 106 is then written to the memory device 104. Because the system metadata is written to the memory device 104 in advance, the possibility of the storage system 102 failing to resume normal operation due to unsuccessful writing of system metadata to the memory device 104 is reduced, lowering the risk of the storage system 102 becoming unusable and thus reducing the impact on user services.

[0243] Indicative, Figure 9 This is an interactive flowchart of a control method for a storage system provided in an embodiment of this application. For example... Figure 9 As shown, the process includes the following steps 901 to 903.

[0244] In step 901, the memory controller 106 sends a second write request to the memory device 104 in response to the occurrence of a power failure event.

[0245] The second write request instructs the writing of system metadata to the memory device 104.

[0246] Optionally, in response to a power failure event, the memory controller 106 writes the address mapping data cached in the memory controller 106 into the memory device 104, the address mapping data including the address mapping relationship between physical addresses and logical addresses; in response to the completion of writing the address mapping data into the memory device 104, the system metadata is written into the memory device 104.

[0247] In some embodiments, in response to a power failure event, the memory controller 106 caches the logical address corresponding to user data that has not been written to the memory device 104, the user data that has not been written to the memory device 104 including first user data; in response to the completion of the logical address caching, the system metadata is written to the memory device 104.

[0248] In some embodiments, in response to a power failure event, the memory controller 106 sends a reset request to the memory device 104, the reset request being used to terminate the data erasure event in the memory device 104.

[0249] In step 902, memory device 104 processes the second write request.

[0250] That is, the memory device 104 performs the process of writing system metadata.

[0251] In step 903, in response to the completion of writing system metadata to memory device 104, memory controller 106 writes first user data to memory device 104.

[0252] In some embodiments, in response to the completion of the second write request processing, the memory device 104 sends a first write notification to the memory controller 106. The first write notification is used to indicate to the memory controller 106 that the system metadata has been written. That is, after the memory device 104 completes the writing process of the system metadata, it sends a first write notification to the memory controller 106. After receiving the first write notification, the memory controller 106 determines that the system metadata has been written to the memory device 104, and then writes the first user data to the memory device 104.

[0253] In other embodiments, the memory device 104 includes a status register; in response to the completion of the second write request processing, the status register generates a first level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the status register has undergone the first level change, and determines that the system metadata has been written to the memory device 104, then the first user data is written to the memory device 104. Optionally, the status register includes a flag bit for storing the level status data of the status register, and the memory controller 106 determines whether the status register has undergone the first level change by reading or listening to the level status data stored in the flag bit.

[0254] In some embodiments, in response to the completion of writing system metadata to memory device 104, memory controller 106 writes the verification information corresponding to the first user data to memory device 104.

[0255] In some embodiments, in response to the completion of writing the first user data to the memory device 104, the memory controller 106 writes updated data of the system metadata cached in the cache 601 of the memory controller 106 to the memory device 104; wherein the updated data is used to indicate the update status of the system metadata during the process of writing the system metadata and the first user data to the memory device 104.

[0256] Figure 10 This is an interactive flowchart of a control method for a storage system provided in an embodiment of this application. For example... Figure 10 As shown, the process includes steps 1001 to 1004.

[0257] Step 1001: The memory controller 106 sends a first write request to the memory device 104.

[0258] The first write request is a write request submitted to the memory device 104 before the power failure event occurs. The first write request indicates that second user data cached in the memory controller 106 be written to the memory device 104.

[0259] In step 1002, the memory controller 106 sends a second write request to the memory device 104 in response to the power failure event.

[0260] The second write request instructs the writing of system metadata to the memory device 104.

[0261] Step 1003: The memory device 104 processes the first write request and the second write request in parallel.

[0262] Indicatively, after a power failure event occurs, the memory controller 106 immediately sends a second write request to the memory device 104. The memory device 104 executes a write process for system metadata based on the second write request. At the same time, the memory device 104 continues to execute a write process for second user data.

[0263] In some embodiments, the memory device 104 and the memory controller 106 include multiple data transmission channels. Schematic, a memory controller 106 supporting four channels (data transmission channels) can communicate with the memory device 104 simultaneously via four independent data lines. Optionally, the channel priority for system metadata is higher than the channel priority for second user data, where channel priority refers to the priority of occupying the data transmission channel. Schematic, when the memory device 104 processes the second write request and the first write request in parallel, the number of data transmission channels for transmitting system metadata can be controlled to be greater than the number of data transmission channels for transmitting second user data.

[0264] Optionally, if the capacity of the backup capacitor is greater than or equal to the preset capacity, the second write request and the first write request are processed in parallel.

[0265] In step 1004, the memory controller 106 writes the first user data to the memory device 104 in response to the completion of the first write request processing of writing system metadata to the memory device 104 and submitting it to the memory device 104.

[0266] In some embodiments, the memory device 104 sends a first write notification to the memory controller 106 in response to the completion of the second write request processing. Illustratively, after the memory device 104 completes the write process for system metadata, it sends a first write notification to the memory controller 106, indicating to the memory controller 106 that the system metadata has been written successfully. In response to the completion of the first write request processing, the memory device 104 sends a second write notification to the memory controller 106. Illustratively, after the memory device 104 completes the write process for second user data, it sends a second write notification to the memory controller 106, indicating to the memory controller 106 that the second user data has been written successfully, i.e., the first write request submitted to the memory device 104 has been processed successfully. Upon receiving the first and second write notifications, the memory controller 106 determines that the system metadata has been written to the memory device 104 and the first write request submitted to the memory device 104 has been processed successfully, and then writes the first user data to the memory device 104.

[0267] In other embodiments, the memory device 104 includes a status register; in response to the completion of the second write request processing, the status register generates a first level change (e.g., from high to low or from low to high). In response to the completion of the first write request processing, the status register generates a second level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the second level change occurs after the first level change in the status register, and determines that the system metadata has been written to the memory device 104 and the first write request submitted to the memory device 104 has been completed, then the first user data is written to the memory device 104.

[0268] In some embodiments, in response to the completion of writing system metadata to memory device 104 and the completion of a first write request processing submitted to memory device 104, memory controller 106 writes an updated address mapping relationship to memory device 104; wherein the updated address mapping relationship includes the mapping relationship between the logical address and physical address of the second user data.

[0269] Figure 11 This is an interactive flowchart of a control method for a storage system provided in an embodiment of this application. For example... Figure 11 As shown, the process includes steps 1101 to 1111.

[0270] Step 1101: The memory controller 106 sends a first write request to the memory device 104.

[0271] The first write request is a write request submitted to the memory device 104 before the power failure event occurs. The first write request indicates that second user data cached in the memory controller 106 be written to the memory device 104.

[0272] In step 1102, in response to a power failure event, the memory controller 106 caches the logical address corresponding to the user data not written to the memory device 104.

[0273] Here, the logical address is the address used by the user or file system to access user data, and it is different from the actual physical address inside the memory device 104. In this application, when a power failure event occurs in the storage system 102, the memory controller 106 records the logical address of the user data that has not been written to the memory device 104, so that the user data can be correctly written to the correct location in the memory device 104 after power is restored.

[0274] Optionally, the user data not written to the memory device 104 includes the first user data.

[0275] Optionally, the user data not written to the memory device 104 also includes second user data.

[0276] In step 1103, the memory controller 106 writes the cached address mapping data into the memory device 104.

[0277] Address mapping data includes the address mapping relationship between physical addresses and logical addresses.

[0278] The physical address refers to the actual storage location of the memory device 104. Illustratively, the memory controller 106 stores an address mapping table in its register 601. This address mapping table records the address mapping relationship between physical addresses and logical addresses. In this application, when a power failure occurs in the storage system 102, the memory controller 106 writes the address mapping table into the memory device 104.

[0279] In step 1104, in response to the completion of writing the address-mapped data to the memory device, the memory controller 106 sends a second write request to the memory device 104.

[0280] The second write request instructs the writing of system metadata to the memory device 104.

[0281] In some embodiments, the memory device 104 sends a third write notification to the memory controller 106 in response to the completion of writing the address-mapped data. Illustratively, after the memory device 104 completes the write process of the address-mapped data, it sends a third write notification to the memory controller 106, indicating to the memory controller 106 that the address-mapped data has been written successfully. Upon receiving the third write notification, the memory controller 106 determines that the address-mapped data has been written to the memory device 104, and then sends a second write request to the memory device 104.

[0282] In other embodiments, the memory device 104 includes a status register; in response to the completion of writing address-mapped data, the status register generates a third level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the status register has undergone a third level change, and the memory controller 106 determines that the writing of address-mapped data into the memory device 104 is complete, it sends a second write request to the memory device 104.

[0283] Step 1105: The memory device 104 processes the first write request and the second write request in parallel.

[0284] Indicatively, after a power failure event occurs, the memory controller 106 immediately sends a second write request to the memory device 104. The memory device 104 executes a write process for system metadata based on the second write request. At the same time, the memory device 104 continues to execute a write process for second user data.

[0285] In step 1106, the memory controller 106 sends a reset request to the memory device 104 in response to the completion of the first write request processing of the system metadata being written to the memory device 104 and submitted to the memory device 104.

[0286] The reset request indicates the termination of a data erase event in the memory device 104.

[0287] In some embodiments, in response to the completion of a second write request, the memory device 104 sends a first write notification to the memory controller 106, indicating to the memory controller 106 that system metadata has been written successfully. In response to the completion of the first write request, the memory device 104 sends a second write notification to the memory controller 106, indicating to the memory controller 106 that the first write request has been completed. Upon receiving the first and second write notifications, the memory controller 106 determines that the system metadata has been written to the memory device 104 and that the first write request submitted to the memory device 104 has been completed, and then sends a reset request to the memory device 104.

[0288] In other embodiments, the memory device 104 includes a status register; in response to the completion of the second write request processing, the status register generates a first level change (e.g., from high to low or from low to high). In response to the completion of the first write request processing, the status register generates a second level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the second level change occurs after the first level change in the status register, and determines that the system metadata has been written to the memory device 104 and the first write request submitted to the memory device 104 has been processed, a reset request is sent to the memory device 104.

[0289] Step 1107, memory device 104 processes the reset request.

[0290] Upon receiving a reset request, memory device 104 terminates the data erase event. Illustratively, the data erase event is one of the fundamental operations of flash memory (such as NAND flash memory), its core objective being to reset the data in the storage block to its initial state (all 1s) so that new data can be written subsequently.

[0291] In step 1108, the memory controller 106 writes the updated address mapping relationship into the memory device 104.

[0292] The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data. In some embodiments, the updated address mapping relationship also includes the mapping relationship between the logical address and the physical address of system metadata.

[0293] In some embodiments, after the memory device 104 completes processing the reset request, it sends a reset completion notification to the memory controller 106. After receiving the reset completion notification, the memory controller 106 writes the updated address mapping relationship into the memory device 104.

[0294] In other embodiments, the memory device 104 includes a status register; after the memory device 104 has processed a reset request, the status register generates a fourth level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the status register has undergone a fourth level change and that the reset request has been completed, it writes the updated address mapping to the memory device 104.

[0295] In step 1109, in response to the completion of writing the updated address mapping relationship into the memory device 104, the memory controller 106 writes the first user data into the memory device 104.

[0296] In some embodiments, after the memory device 104 completes the write process of the updated address mapping relationship, it sends a fourth write notification to the memory controller 106. The fourth write notification is used to indicate to the memory controller 106 that the updated address mapping relationship has been written. After receiving the fourth write notification, the memory controller 106 determines that the updated address mapping relationship has been written to the memory device 104, and then writes the first user data to the memory device 104.

[0297] In other embodiments, the memory device 104 includes a status register; in response to the memory device 104 completing the write process of the updated address mapping, the status register generates a fifth level change (e.g., from high to low or from low to high). When the memory controller 106 determines that the status register has undergone a fifth level change, and the memory controller 106 determines that the write of the updated address mapping to the memory device 104 is complete, then the first user data is written to the memory device 104.

[0298] Step 1110: The memory controller 106 writes the verification information corresponding to the first user data into the memory device 104.

[0299] Optionally, the verification information can be implemented as a RAID checksum, which is generated through an XOR operation. Illustratively, the first user data includes at least two data blocks, and the verification information refers to the XOR result between these at least two data blocks. For example: Verification information = User data AX OR User data B; or Verification information = User data AX OR User data B XOR User data C.

[0300] In step 1111, the memory controller 106 writes the updated system metadata data to the memory device 104.

[0301] The update data indicates the update status of the system metadata during the process of writing system metadata and first user data into the memory device 104.

[0302] Schematic illustration: After the memory controller 106 successfully writes the first user data to the memory device 104, it writes the updated system metadata cached in the register 601 to the memory device 104. This updated data records the updates to the system metadata that occur throughout the entire process of writing the system metadata and the first user data to the memory device 104.

[0303] This application provides an electronic device, which includes a storage system 102 as described in any of the above embodiments, and a host 108 coupled to the storage system 102. The electronic device may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, etc.

[0304] This application provides a computer-readable storage medium storing at least one computer program. This computer program is loaded and executed by a processor to implement the control method of the storage system described in any of the above embodiments. Optionally, the computer-readable storage medium is a non-transitory-readable storage medium. Illustratively, at least one computer program is stored in the memory device 104 of a solid-state drive (SSD), runs in the TCM (Tightly Coupled Memory) of the SSD's memory controller 106 or in the cache of the memory controller 106, and is executed by the processor of the SSD's memory controller 106 to implement the control method of the storage system described in any of the above embodiments.

[0305] This application provides a computer program stored in a computer-readable storage medium. A processor reads the computer program from the computer-readable storage medium, causing the processor to load and execute it to implement the control method of the storage system provided in the above-described method embodiments.

[0306] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0307] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The above descriptions are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage system, characterized in that, The storage system includes: Memory devices, and A memory controller, which caches first user data and system metadata, is configured to: In response to a power failure event, the system metadata is written to the memory device; and In response to the completion of writing the system metadata to the memory device, the first user data is written to the memory device.

2. The system according to claim 1, characterized in that, The memory controller is configured to: In response to the completion of writing the system metadata to the memory device and the completion of the first write request processing submitted to the memory device, the first user data is written to the memory device; The first write request is a write request submitted to the memory device before the power failure event occurs, and the first write request indicates that second user data cached in the memory controller be written to the memory device.

3. The system according to claim 2, characterized in that, The memory controller is configured to: In response to the occurrence of the power failure event, a second write request is sent to the memory device, the second write request instructing the system metadata to be written to the memory device; The memory device is configured as follows: The second write request and the first write request are processed in parallel.

4. The system according to claim 2, characterized in that, The memory controller is configured to: Upon completion of the first write request submitted to the memory device, the updated address mapping is written to the memory device. The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

5. The system according to any one of claims 1 to 4, characterized in that, The memory controller is configured to: In response to the power failure event, the logical address corresponding to the user data that has not been written to the memory device is cached, and the user data that has not been written to the memory device includes the first user data; In response to the completion of the logical address caching, the system metadata is written to the memory device.

6. The system according to any one of claims 1 to 4, characterized in that, The memory controller is configured to: In response to the occurrence of the power failure event, a reset request is sent to the memory device, the reset request indicating the termination of the data erasure event in the memory device.

7. The system according to any one of claims 1 to 4, characterized in that, The memory controller is configured to: In response to the occurrence of the power failure event, the address mapping data cached in the cache of the memory controller is written into the memory device, the address mapping data including the address mapping relationship between physical addresses and logical addresses; In response to the completion of writing the address mapping data to the memory device, the system metadata is written to the memory device.

8. The system according to any one of claims 1 to 4, characterized in that, The memory controller is configured to: In response to the completion of writing the system metadata to the memory device, the verification information corresponding to the first user data is written to the memory device.

9. The system according to any one of claims 1 to 4, characterized in that, The memory controller is configured to: In response to the completion of writing the first user data to the memory device, the updated data of the system metadata cached in the cache of the memory controller is written to the memory device; The updated data indicates the update status of the system metadata during the process of writing the system metadata and the first user data into the memory device.

10. The system according to any one of claims 1 to 4, characterized in that, The storage system includes solid-state drives (SSDs).

11. The system according to any one of claims 1 to 4, characterized in that, The memory device includes a single-level storage cell (SLC).

12. A memory controller, characterized in that, include: The cache is configured to cache first user data and system metadata; One or more processors, said one or more processors being configured to: In response to a power failure event, the system metadata is written to the memory device; and In response to the completion of writing the system metadata to the memory device, the first user data is written to the memory device.

13. An electronic device, characterized in that, The electronic device includes: The storage system as described in any one of claims 1 to 11, and A host coupled to the storage system.

14. A control method for a storage system, characterized in that, The method includes: In response to a power failure event, the system metadata cached in the memory controller is written to the memory device; In response to the completion of writing the system metadata to the memory device, the first user data cached in the memory controller is written to the memory device.

15. The method according to claim 14, characterized in that, The step of writing the first user data cached in the memory controller to the memory device in response to the completion of writing the system metadata to the memory device includes: In response to the completion of writing the system metadata to the memory device and the completion of the first write request processing submitted to the memory device, the first user data is written to the memory device; The first write request is a write request submitted to the memory device before the power failure event occurs, and the first write request indicates that second user data cached in the memory controller be written to the memory device.

16. The method according to claim 15, characterized in that, The step of writing system metadata cached in the memory controller to the memory device in response to a power failure event includes: In response to the occurrence of the power failure event, a second write request is sent to the memory device, the second write request instructing the system metadata to be written to the memory device; The memory device is used to process the first write request and the second write request in parallel.

17. The method according to claim 15, characterized in that, The method further includes: In response to the completion of the first write request processing after the system metadata has been written to the memory device and submitted to the memory device, the updated address mapping relationship is written to the memory device. The updated address mapping relationship includes the mapping relationship between the logical address and the physical address of the second user data.

18. The method according to any one of claims 14 to 17, characterized in that, The step of writing system metadata cached in the memory controller to the memory device in response to a power failure event includes: In response to the power failure event, the logical address corresponding to the user data that has not been written to the memory device is cached, and the user data that has not been written to the memory device includes the first user data; In response to the completion of the logical address caching, the system metadata is written to the memory device.

19. The method according to any one of claims 14 to 17, characterized in that, The method further includes: In response to the power failure event, a reset request is sent to the memory device, the reset request being used to terminate the data erase event in the memory device.

20. The method according to any one of claims 14 to 17, characterized in that, The step of writing system metadata cached in the memory controller to the memory device in response to a power failure event includes: In response to the occurrence of the power failure event, the address mapping data cached in the memory controller is written into the memory device, the address mapping data including the address mapping relationship between physical addresses and logical addresses; In response to the completion of writing the address mapping data to the memory device, the system metadata is written to the memory device.

21. The method according to any one of claims 14 to 17, characterized in that, The method further includes: In response to the completion of writing the system metadata to the memory device, the verification information corresponding to the first user data is written to the memory device.

22. The method according to any one of claims 14 to 17, characterized in that, The method further includes: In response to the completion of writing the first user data to the memory device, the updated data of the system metadata cached in the cache of the memory controller is written to the memory device; The updated data is used to indicate the update status of the system metadata during the process of writing the system metadata and the first user data into the memory device.

23. The method according to any one of claims 14 to 17, characterized in that, The storage system includes solid-state drives (SSDs).

24. The method according to any one of claims 14 to 17, characterized in that, The memory device includes a single-level storage cell (SLC).

25. A computer-readable storage medium, characterized in that, The storage medium stores at least one computer program, which is loaded and executed by a processor to implement the control method of the storage system as described in any one of claims 14 to 24.

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