Processing unit, processor, system-on-chip, computing device and access control method

Abstract

This invention provides a processing unit, a processor, a system-on-a-chip, a computing device, and an access control method. The processing unit includes: an address partition register storing address partition information indicating multiple address blocks in physical memory space; an address permission register storing address permission information for multiple execution domains, wherein the address permission information indicates available address blocks for which each execution domain has access permissions; and an access unit that parses the address permission information and the address partition information to determine the available address blocks corresponding to the current execution domain where the processing unit is located, and performs an access operation for the current access object when the access address of the currently accessed object matches the available address blocks.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of processor chip technology, and in particular to a processing unit, processor, system-on-a-chip, computing device, and access control method. Background Technology

[0002] In some processor architectures, execution zones are used to manage resource access for processing units such as processors or processor cores. Processing units can run in different execution zones in a time-sharing manner. Each execution zone can have a given privilege mode, so that the code, memory, peripherals, I / O and other resources of one execution zone are not subject to unauthorized access by other execution zones.

[0003] In these processor architectures, the processing unit can support privileged modes such as machine mode (M-mode), (S-mode), and normal user mode (U-mode). In normal user mode, threads belonging to user applications run. Super user mode has higher privileges than normal user mode and runs threads belonging to the operating system. Machine mode has higher privileges than super user mode and includes PMP management privileges and access control management privileges. Typically, the Trusted Firmware (TF) unit is in machine mode.

[0004] Furthermore, the trusted firmware unit can manage the PMP register for different execution domains. For example, when the processing unit switches from the previous execution domain to the current execution domain, the trusted firmware unit can receive an interrupt instruction for execution domain switching, and disable the PMP entry corresponding to the previous execution domain and enable the PMP entry corresponding to the current execution domain in the PMP register to realize the switching of different PMP contexts.

[0005] In other words, during the switching between different PMP contexts (for example, in the case of execution domain context switching), the PMP entries in the PMP register need to be modified. Therefore, the process of modifying the partition information of the available address blocks of the current execution domain incurs a large time overhead, which affects the processing performance of the processing unit. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a processing unit, a processor, and an access control method to solve the above problems.

[0007] According to a first aspect of the present invention, a processing unit is provided, comprising: an address partition register storing address partition information, the address partition information indicating multiple address blocks of physical memory space; an address permission register storing address permission information for multiple execution domains, wherein the address permission information indicates available address blocks for which each execution domain has access permission among the multiple address blocks; and an access unit parsing the address permission information and the address partition information to determine the available address block corresponding to the current execution domain in which the processing unit is located, and performing an access operation for the current access object when the access address of the currently accessed object matches the available address block.

[0008] In another implementation of the present invention, the address permission information includes a plurality of consecutive permission segments, each of which corresponds to a plurality of address blocks in the physical memory space, and each permission segment indicates an execution domain that has access rights to the address block corresponding to that permission segment.

[0009] In another implementation of the present invention, each permission segment includes multiple fields corresponding to the plurality of execution domains, and each field indicates whether the execution domain corresponding to the field has access rights to the address block corresponding to the permission segment.

[0010] In another implementation of the present invention, the access unit is further configured to: sequentially parse multiple fields in each permission segment that correspond to the multiple execution domains respectively, and when the field corresponding to the current execution domain indicates that the current execution domain has access rights to the address block corresponding to the permission segment, determine the address block corresponding to the permission segment as an available address block.

[0011] In another implementation of the present invention, the access unit is further configured to: find the operation permission corresponding to the available address block, and perform an access operation on the current access object according to the operation permission, wherein the current access object is the current instruction or the current data, and the operation permission information includes at least one of read permission, write permission and execute permission.

[0012] In another implementation of the present invention, the processing unit further includes a permission configuration register, which stores operation permission information corresponding to the address partition information. The operation permission information indicates the operation permissions for the access objects in each address block. The access unit is further configured to: parse the operation permission information and determine the operation permissions corresponding to the available address blocks.

[0013] In another implementation of the present invention, the processing unit further includes a register management unit, which is used to configure the operation permission information corresponding to the plurality of address blocks into the permission configuration register.

[0014] In another implementation of the present invention, the register management unit is further configured to: when the processing unit switches from the previous execution domain to the current execution domain, configure the operation permission information corresponding to the available address block into the permission configuration register.

[0015] In another implementation of the present invention, the register management unit is further configured to: configure the address partition information to the address partition register, and configure the address permission information to the address permission register.

[0016] In another implementation of the present invention, the address permission information indicates that all of the plurality of address blocks are disabled address blocks. Accordingly, the register management unit is further configured to: configure the address partition information into the address partition register when the processing unit switches from the previous execution domain to the current execution domain.

[0017] According to a second aspect of the present invention, a processor is provided, the processor including a plurality of processing units, each processing unit being the processing unit described in the first aspect.

[0018] According to a third aspect of the present invention, a system-on-a-chip is provided, comprising: a processor according to the second aspect; and an on-chip network, wherein the plurality of processing units are interconnected via the on-chip network.

[0019] According to a fourth aspect of the present invention, a computing device is provided, comprising: memory, including physical memory space; and a system-on-a-chip according to a third aspect.

[0020] According to a fifth aspect of the present invention, an access control method is provided, comprising: when the access address of a currently accessed object is obtained, accessing address partitioning information in an access address partitioning register and address permission information for multiple execution domains in an address permission register, wherein the address partitioning information indicates multiple address blocks in physical memory space, and the address permission information indicates available address blocks in the multiple address blocks for which each execution domain has access rights; parsing the address permission information and the address partitioning information to determine the available address block corresponding to the current execution domain where the processing unit is located; and when the access address of the currently accessed object matches the available address block, performing an access operation for the currently accessed object.

[0021] In the embodiment of the present invention, the address partitioning information stored in the address partitioning register indicates multiple address blocks in the physical memory space, and the address permission information stored in the address permission register indicates the available address blocks that each execution domain has access to in the multiple address blocks. Therefore, the access unit can determine the available address blocks corresponding to the current execution domain where the processing unit is located by parsing the address partitioning information and the address permission information, thereby avoiding the modification of the address partitioning information of the available address blocks during the switching of the PMP context, thereby improving the processing performance of the processing unit. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0023] Figure 1 This is a schematic block diagram of a computing device applicable to some embodiments of the present invention.

[0024] Figure 2 for Figure 1 Schematic block diagrams of some examples of hardware and software configurations applicable to the processor architecture.

[0025] Figure 3 This is a schematic block diagram of a processing unit according to some embodiments of the present invention.

[0026] Figure 4 This is a schematic block diagram of an access control process according to other embodiments of the present invention.

[0027] Figure 5 This is a schematic diagram illustrating the steps of an access control method according to other embodiments of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0029] The specific implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0030] Figure 1A computing device applicable to some embodiments of the present invention is shown. For example... Figure 1 As shown, the computing device 100 comprises a processor including at least a processing unit 110, memory 120, and a bus 130. In the case of a single-core processor, the processor includes one processing unit 110; in the case of a multi-core processor, the processor includes multiple processing units 110, which are interconnected via an on-chip network (…). Figure 1 (Not shown in the diagram) Connections. Memory 120 includes, but is not limited to, storage media such as Dynamic Random Access Memory (DRAM), and the processor can access data or instructions in the physical memory space of memory 120 via a bus 130 such as a DDR bus. Further, the processing unit 110 includes an instruction fetch unit 10, an instruction decode unit 20, a trusted firmware unit 30, a data access unit 40, a memory management unit 50, and a control status register (CSR) 60, serving as an instruction function unit. It should be understood that... Figure 1 The processor architecture can be applied to single-core or multi-core processors. In the case of multi-core processors, the processor can include multiple processing units.

[0031] Specifically, the control status register 60 includes at least a privileged state register (e.g., the mstatus register) and a Physical Memory Protection (PMP) register. The privileged state register (e.g., the mstatus register) is used to track and control the privileged state of the processor. For example, the mpp field in the mstatus register indicates the current privileged mode, and the MPIE and MIE fields are used to control the interrupt enable state. During exception handling and context switching, the status values ​​of the privileged state registers are saved and restored to ensure proper switching of privileged states. In addition, the PMP register can store at least one PMP entry. The PMP register includes an associated address partition register (e.g., the PMP_addr register) and a permission configuration register (e.g., the PMP_cfg register). The PMP entry includes the status value of the address partition register and the status value of the permission configuration register. The status value of the address partition register indicates the physical address range of the available address block, and the permission configuration register and status value indicate the operation permissions of the access object (e.g., instruction or data) in the available address block. For example, operation permissions include, but are not limited to, read (R) permission, write (W) permission, execute (X) permission, etc.

[0032] In some processor architectures, execution zones are used to manage resource access for processing units such as processors or processor cores. Processing units can run in different execution zones in a time-sharing manner. Each execution zone can have a given privilege mode, so that the code, memory, peripherals, I / O and other resources of one execution zone are not subject to unauthorized access by other execution zones.

[0033] Accordingly, in these processor architectures, the processing unit can support privileged modes such as machine mode (M-mode), (S-mode), and normal user mode (U-mode). In normal user mode, threads belonging to user applications run. Super user mode has higher privileges than normal user mode and threads belonging to the operating system run in super user mode. Machine mode has higher privileges than super user mode. Machine mode management includes PMP management privileges and access control management privileges. Typically, the Trusted Firmware (TF) unit 30 is in machine mode.

[0034] In addition, the memory management unit 50 manages virtual memory, including address translation, page table management, and cache coherency. The memory management unit 50 translates virtual addresses into physical addresses, processes memory access requests, and manages memory protection and permissions. For example, the instruction fetch unit 10 fetches a sequence of program instructions, reads the instructions from the sequence according to the address specified by the program counter (PC), and sends them to the subsequent stage of the processing unit 110. During instruction fetching, the processor determines the privileged mode of the current execution domain (e.g., indicated by the privilege field in the mstatus register), and the memory management unit 50 uses an address mapping table corresponding to the privileged mode to translate virtual addresses into physical addresses. The instruction descriptor unit 20 converts the instructions fetched by the instruction fetch unit 10 from machine code into an internal format recognizable by the processing unit 110. The instruction decoder unit 20 parses the opcode used to determine the type of instruction and the operands for the execution unit to perform. Furthermore, for example, the data access unit 40 loads data from memory or other storage media for execution by the processing unit 110. During data access operations, the data access unit 40 performs address translation through the memory management unit 50, which uses the address mapping table corresponding to the privileged mode to translate the virtual address into a physical address.

[0035] Furthermore, in some processor architectures, before accessing physical memory, the instruction fetch unit 10 or the data memory access unit 40 needs to query the PMP register corresponding to the current execution domain to perform an access permission check. After the check is passed, the instruction or data access in physical memory is executed. The trusted firmware unit 30 can manage the PMP register for different execution domains.

[0036] like Figure 2 As shown, the trusted firmware unit can be trusted firmware unit 30, and the other hardware units shown below the trusted firmware unit can be instruction function units. The portion above the trusted firmware unit is the software configuration. In the software configuration, the areas separated by dashed lines can be considered as different PMP contexts (i.e., the same PMP table entry determines the same PMP context). Without loss of generality, the PMP contexts corresponding to different execution domains can be the same or different, and the execution domains corresponding to different PMP contexts are different. It should be understood that each execution domain can have at least one thread, and the instructions of the same thread belong to a specific execution domain. Threads in different execution domains can belong to the same process or different processes. In addition, in the areas separated by dashed lines, the areas separated by solid lines can be considered as different execution domain contexts within the same PMP context, such as privileged mode information. Typically, different execution domain contexts are maintained using different address mapping tables. It should also be understood that different execution domains can be in different execution domain contexts or in the same execution domain context, and different execution domain contexts correspond to different execution domains.

[0037] For example, processing units can be in different execution domains at different times, and kernel-mode threads S1, S2, ..., SN in different PMP contexts can represent the same or different operating systems. Furthermore, for the same PMP context, kernel-mode S1, user-mode U11, user-mode U12, and user-mode U13 can have different execution domain contexts; similarly, kernel-mode S2, user-mode U21, user-mode U22, and user-mode U23 can have different execution domain contexts, and kernel-mode SN, user-mode UN1, user-mode UN2, and user-mode UN3 can have different execution domain contexts.

[0038] In some examples, the trusted firmware unit 30 can manage the PMP register for different execution domains. For example, when the processing unit switches from the previous execution domain to the current execution domain, the trusted firmware unit 30 can receive an interrupt instruction for execution domain switching, and disable the PMP entry corresponding to the previous execution domain and enable the PMP entry corresponding to the current execution domain in the PMP register to achieve switching between different PMP contexts.

[0039] However, during the switching between different PMP contexts (e.g., in the case of execution domain context switching), it is necessary to modify the PMP entries in the PMP register. In other words, the process of modifying the partition information of the available address blocks of the current execution domain incurs a significant time overhead, which affects the processing performance of the processing unit. Various embodiments of the present invention can reduce the time overhead in the case of PMP context switching, thereby improving the processing performance of the processing unit.

[0040] Specifically, Figure 3 A processing unit 300 according to some embodiments of the present invention is shown. The processing unit 300 includes an address partition register 310, an address permission register 320, and an access unit 330.

[0041] Specifically, the address partition register 310 stores address partition information, which indicates multiple address blocks in the physical memory space.

[0042] It should be understood that address partitioning information is used to define the boundaries of different address regions in physical memory, enabling independent access control over these address regions. Multiple address blocks are non-overlapping address ranges; that is, at least two address blocks can form a contiguous address range, or multiple address blocks can be discrete address ranges in the physical memory space. Each address block can be used for different memory purposes, such as code segments, data segments, or device memory, thereby achieving fine-grained management of physical memory.

[0043] In addition, the address permission register 320 stores address permission information for multiple execution domains, wherein the address permission information indicates the available address blocks in the multiple address blocks that each execution domain has access to.

[0044] It should be understood that address permission information is set according to the system's security policy and the isolation requirements of execution domains, ensuring that each execution domain can only access its authorized memory areas. Address permission information includes multiple permission segments, which are based on the management granularity of address blocks, and each permission segment can also be based on the management granularity of execution domains.

[0045] Furthermore, the access unit 330 parses the address permission information and address partition information to determine the available address block corresponding to the current execution domain where the processing unit is located. When the access address of the currently accessed object matches the available address block, it executes an access operation for the currently accessed object. For example, the current accessed object can be the current instruction or the current data, and the operation permission information can include at least one of read permission, write permission, and execute permission.

[0046] It should be understood that the access unit can be implemented as Figure 1 In the example data access unit or instruction fetch unit, the access unit must comply with the permission rules defined by the PMP mechanism when accessing the current access object. For example, if the access address of the current access object exceeds the address range of the available address block, or the access operation exceeds the allowed operation permissions, the access unit will prevent the access operation or trigger an exception handling mechanism. Specifically, the address partition register 310 can be... Figure 1In the example, the PMP_addr register in the control status register, the permission configuration register can be the PMP_cfg register in the control status register, and the address permission register 320 can also belong to the control status register. Additionally, access unit 30 can be... Figure 1 In the example, the instruction fetch unit 10 or the data memory access unit 40. Additionally, the register management unit can be... Figure 1 Trusted firmware unit 30 in the example. Additionally... Figure 2 The processing unit may also include a memory management unit 50 and a dereference unit 20.

[0047] In the embodiment of the present invention, the address partitioning information stored in the address partitioning register indicates multiple address blocks in the physical memory space, and the address permission information stored in the address permission register indicates the available address blocks that each execution domain has access to in the multiple address blocks. Therefore, the access unit can determine the available address blocks corresponding to the current execution domain where the processing unit is located by parsing the address partitioning information and the address permission information, thereby avoiding the modification of the address partitioning information of the available address blocks during the switching of the PMP context, thereby improving the processing performance of the processing unit.

[0048] In some embodiments, the address partition register stores address partition information, where each address partition entry indicates the physical address start or physical address end of the corresponding address block. For example, the address partition information can be as shown in Table 1: the entry attributes of the address partition entry include at least the PMP address block identifier and the physical address range. In addition, the entry attributes may also include matching patterns, etc.

[0049] Table 1

[0050] PMP address block identifier Physical address range 1 0x00100000-0x001FFFFF 2 0x00300000-0x003FFFFF … …

[0051] It should be understood that in the above example, PMP address block 1 and PMP address block 2 can form a continuous physical address range or a non-contiguous physical address range.

[0052] Furthermore, the permission configuration register stores operation permission information. Each operation permission entry indicates the operation permission for the access object in the corresponding address block. For example, the entry attributes of an operation permission entry include at least the PMP configuration identifier, lock status, reserved segment, address matching mode, and operation permissions such as read permission, write permission, and execute permission. The PMP configuration identifier is a unique identifier used to distinguish different PMP entries. The lock status indicates whether the PMP entry is locked. When a PMP entry is locked, its configuration cannot be modified even in machine mode (M mode) until a hardware reset. The reserved segment refers to whether the memory area protected by the PMP entry is reserved for a specific purpose. Address matching modes define the address range matching method for the memory region protected by the PMP entry. Address matching modes include, but are not limited to: OFF: disabling the PMP entry; TOR (Top of Range): contiguous boundary mode, defining a memory region from the base address to the specified upper boundary; NA4 (Natural Aligned 4-byte): naturally aligned 4-byte region; NAPOT (Natural Aligned Power of Two): naturally aligned power of two region. Operation permissions define the access permissions for the memory region protected by the PMP entry, including read permission, write permission, and execute permission. Read permission (R) indicates that read operations are allowed on the memory region; write permission (W) indicates that write operations are allowed on the memory region; and execute permission (X) indicates that instruction execution operations are allowed on the memory region.

[0053] Table 2

[0054]

[0055] In other examples, the address permission register includes address permission information. Each permission segment in the address permission information may include multiple fields corresponding to multiple execution domains, or multiple table entries corresponding to multiple execution domains, based on the management granularity of the execution domain. The various permission segments of the address permission information can be shown in Table 3:

[0056] Table 3

[0057]

[0058] For example, permission segments 0-7 can represent the access permissions of the physical addresses in address blocks 0-7, respectively.

[0059] Furthermore, in the example where the management granularity of the permission segment is based on the execution domain and consists of multiple fields, the permission segment can be as shown in Table 4:

[0060] Table 4

[0061] Field 3 Field 2 Field 1 Field 0 0 0 0 1

[0062] For example, fields 0-3 respectively indicate whether execution domains 0-3 have access rights to the address blocks corresponding to the permission segment.

[0063] In other embodiments, Figure 4 Access control procedures according to other embodiments of the present invention are illustrated. For example... Figure 4 As shown, the execution domain register is used to manage execution domain status information. The different execution domain states indicated by the execution domain status information represent the processing unit handling multiple different execution domains, as well as the current execution domain among the multiple execution domains. It should be understood that different execution domains can have different execution domain contexts, or they can have the same execution domain context, and different execution domain contexts correspond to different execution domains. Figure 4 The example shown uses four execution domains—execution domain 0, execution domain 1, execution domain 2, and execution domain 3—as multiple execution domains. In different examples, the processor unit may have other numbers of execution domains.

[0064] In addition, the address partition register stores address partition information, which indicates multiple address blocks in the physical memory space. For example, the address partition information includes the identifiers of each of the multiple address blocks. Figure 4 An example is shown where four address blocks—address block 0, address block 1, address block 2, and address block 3—are used as multiple address blocks. Additionally, the operation permission memory stores operation permission information, which corresponds to the address partition information and indicates the operation permissions for the access objects within each address block. Figure 4 The example illustrates the operation permissions for four address blocks: address block 0, address block 1, address block 2, and address block 3. Specifically, the operation permission for address block 0 is RWX = 110, indicating that it has read and write permissions for the accessed object (e.g., instruction or data) in address block 0, but no execute permission; the operation permission for address block 1 is RWX = 110, indicating that it has read and write permissions for the accessed object (e.g., instruction or data) in address block 1, but no execute permission; the operation permission for address block 2 is RWX = 101, indicating that it has read and execute permissions for the accessed object (e.g., instruction or data) in address block 0, but no write permission; and the operation permission for address block 3 is RWX = 110, indicating that it has read and write permissions for the accessed object (e.g., instruction or data) in address block 3, but no execute permission.

[0065] In addition, the address permission register stores address permission information, which corresponds to both address partition information and execution domain status information. It is used to associate address partition information and execution domain status information, for example, to indicate the available address blocks that each execution domain in multiple address blocks has access to. Figure 4 The example shown includes permission segment 0 (0011), permission segment 1 (0010), permission segment 2 (0100), and permission segment 3 (1001), where each permission segment corresponds to a multiple address block. Without loss of generality, address permission information comprises multiple consecutive permission segments, each corresponding to a multiple address block in the physical memory space. Each permission segment indicates an execution domain with access rights to the address block it corresponds to. In other words, when multiple permission segments correspond to multiple address blocks in the physical memory space, address permission information and address partition information can be effectively matched, improving the encoding efficiency of address permission information and, consequently, the parsing efficiency of address permission information and address partition information.

[0066] Specifically, in Figure 4 In the example, each permission segment includes multiple fields corresponding to multiple execution domains, each field indicating whether the execution domain corresponding to that field has access rights to the address block corresponding to the permission segment. A permission segment can be represented as a bit sequence, and the fields within the permission segment can be represented as bits. Different bit values ​​can represent different permission states (i.e., available or disabled). For example, 1 represents an available state, and 0 represents a disabled state; alternatively, 1 represents a disabled state, and 0 represents an available state. For another example, bits from low to high can represent execution domain numbers from small to large; alternatively, bits from low to high can represent execution domain numbers from large to small, or there can be other specified correspondences between bits and execution domain identifiers (e.g., numbers). It should be understood that as long as multiple fields satisfy a one-to-one correspondence with multiple execution domains, it is within the scope of this embodiment. Without loss of generality, each permission segment includes multiple fields corresponding to multiple execution domains, each field indicating whether the execution domain corresponding to that field has access rights to the address block corresponding to the permission segment. In other words, multiple fields in the permission segment correspond to multiple execution domains, which further improves the encoding efficiency of address permission information, and thus improves the parsing efficiency of address permission information and address partition information.

[0067] Specifically, in Figure 4In the example, we'll use 1 to represent an available state and 0 to represent a disabled state. Permission segment 0 is 0011, indicating that execution domain 0 and execution domain 1 have access to the physical addresses in address block 0, while execution domain 2 and execution domain 3 do not. That is, address block 0 is an available address block for execution domains 0 and 1, and a disabled address block for execution domains 2 and 3. Permission segment 1 is 0010, indicating that execution domain 1 has access to the physical addresses in address block 1, while execution domains 0, 2, and 3 do not. That is, address block 1 is an available address block for execution domain 1, and a disabled address block for execution domains 0, 2, and 3. Permission segment 2 being 0100 indicates that execution domain 2 has access to the physical addresses in address block 2, while execution domains 0, 1, and 3 do not. In other words, address block 2 is a usable address block for execution domain 2, but a disabled address block for execution domains 0, 1, and 3. Permission segment 3 being 1001 indicates that execution domains 0 and 3 have access to the physical addresses in address block 3, while execution domains 1 and 2 do not. In other words, address block 3 is a usable address block for execution domains 0 and 3, but a disabled address block for execution domains 1 and 2.

[0068] In some embodiments, the access unit can sequentially parse multiple fields in each permission segment that correspond to multiple execution domains. Then, when a field corresponding to the current execution domain indicates that the current execution domain has access rights to the address block corresponding to the permission segment, the address block corresponding to the permission segment is determined as a usable address block. In other words, by using the encoding method of the permission segments, the parsing logic is simplified, thereby improving the verification efficiency of the PMP address range.

[0069] In some examples, when switching from execution domain 0 to execution domain 1, access units such as data memory access units or instruction fetch units parse address permission information for execution domain 1, determine that the available address block in execution domain 1 is address block 1, and the disabled address blocks are address block 0, address block 2, and address block 3. Accordingly, the access unit can determine the operation permissions corresponding to the available address areas. If the operation permission of address block 1 is RWX = 110, the access unit performs an access operation that conforms to the above operation permissions according to the access address of the currently accessed object.

[0070] In other examples, when switching from execution domain 1 to execution domain 2, access units such as data memory access units or instruction fetch units parse address permission information for execution domain 2, determine that the available address block in execution domain 2 is address block 2, and the disabled address blocks are address block 0, address block 1, and address block 3. Accordingly, the access unit can determine the operation permissions corresponding to the available address areas. If the operation permission of address block 2 is RWX = 101, the access unit performs an access operation that conforms to the above operation permissions according to the access address of the currently accessed object.

[0071] In other examples, when switching from execution domain 2 to execution domain 3, access units such as data memory access units or instruction fetch units parse address permission information for execution domain 3, determine that the available address block in execution domain 3 is address block 3, and the disabled address blocks are address block 0, address block 1, and address block 2. Accordingly, the access unit can determine the operation permissions corresponding to the available address areas. If the operation permission of address block 3 is RWX = 110, the access unit performs an access operation that conforms to the above operation permissions according to the access address of the currently accessed object.

[0072] In other examples, when switching from execution domain 3 to execution domain 0, access units such as data memory access units or instruction fetch units parse address permission information for execution domain 0, determine that the available address blocks in execution domain 0 are address block 0 and address block 1, and the disabled address blocks are address block 2 and address block 3. Accordingly, the access unit can determine the operation permissions corresponding to the available address areas. If the operation permission of address block 0 is RWX=110 and the operation permission of address block 1 is RWX=110, the access unit performs an access operation that conforms to the above operation permissions according to the available address block where the access address of the current accessed object is located.

[0073] Without loss of generality, the access unit can look up the operation permissions corresponding to the available address blocks and, based on these permissions, execute the access operation for the currently accessed object. In other words, when an available address block is matched, the access operation is executed based on the operation permissions corresponding to the physical address within that block, which is beneficial for compatibility with physical memory protection mechanisms. In some examples, the permission configuration register stores operation permission information corresponding to the address partition information, indicating the operation permissions for the accessed object in each address block. Accordingly, when looking up the operation permissions corresponding to an available address block, the access unit is further used to: parse the operation permission information to determine the operation permissions corresponding to the available address block. That is, by marking the operation permissions of the accessed object in each address block using the permission configuration register, compatibility with physical memory protection mechanisms is further enhanced.

[0074] In other embodiments, the register management unit can uniformly configure address partitioning information to the address partition register and address permission information to the address permission register before access operations corresponding to multiple execution domains. In other words, by adjusting the implementation logic of the register management unit, it can be enabled to configure both the address permission register and the address partition register.

[0075] In some examples, the register management unit can uniformly configure operation permission information corresponding to multiple address blocks in the permission configuration register before access operations corresponding to multiple execution domains. For example, the address partition register stores address partition information, and the address partition table entries in the address partition information indicate the physical address start or physical address end of the corresponding address block. The permission configuration register stores operation permission information corresponding to the address partition information, and the operation permission table entries in the operation permission information indicate the operation permissions for the access objects in the corresponding address blocks. The address partition table entries and operation permission table entries form PMP entries. The access unit can select the corresponding PMP entry by parsing the address permission information without managing the disabled or enabled state of the PMP entries, thus ensuring compatibility with the configuration process of the permission configuration register in the physical memory protection mechanism.

[0076] Alternatively, the register management unit can configure the operation permission information corresponding to the available address block into the permission configuration register when the processing unit switches from the previous execution domain to the current execution domain, so as to further be compatible with the timing of the configuration of the permission configuration register in the physical memory protection mechanism.

[0077] For example, when a processing unit switches from the previous execution domain to the current execution domain, the instruction fetch unit obtains an execution domain switching instruction (e.g., a privileged mode switching instruction). The instruction execution unit executes the execution domain switching instruction, marks the current execution domain in the execution domain register, marks the interrupt status in the mstatus register, and transfers execution privileges to the register management unit. Correspondingly, the register management unit reads the current execution domain marked in the execution domain register and configures the operation permission information corresponding to the available address blocks into the permission configuration register. For example, the permission configuration register pre-stores operation permission information corresponding to address partition information. Each operation permission entry in the operation permission information indicates the operation permission for the access object in the corresponding address block. The permission configuration register disables the operation permission entries corresponding to the previous execution domain and enables the operation permission entries corresponding to the current execution domain.

[0078] In other embodiments, address permission information indicates that multiple address blocks are disabled address blocks. Accordingly, the register management unit can configure address partitioning information into the address partition register when the processing unit switches from the previous execution domain to the current execution domain. For example, the register management unit can set multiple address blocks as available address blocks in at least one target execution domain. When the current execution domain is the target execution domain, there is no need to parse the address permission information to select the corresponding PMP table entry. The unit can continue to manage the disabled or enabled state of the PMP table entry, thus achieving high compatibility with the address partition register and address permission register in the physical memory protection mechanism.

[0079] The following will combine Figure 5 Access control methods according to other embodiments of the present invention are described. Specifically, Figure 5 Access control methods include:

[0080] S510: When the access address of the currently accessed object is obtained, the address partition information in the access address partition register and the address permission information in the address permission register for multiple execution domains, wherein the address partition information indicates multiple address blocks in the physical memory space, and the address permission information indicates the available address blocks in the multiple address blocks for which each execution domain has access rights;

[0081] S520: Parse address permission information and address partition information to determine the available address block corresponding to the current execution domain where the processing unit is located;

[0082] S530: When the access address of the currently accessed object matches the available address block, perform an access operation for the currently accessed object.

[0083] In the embodiment of the present invention, the address partitioning information stored in the address partitioning register indicates multiple address blocks in the physical memory space, and the address permission information stored in the address permission register indicates the available address blocks that each execution domain has access to in the multiple address blocks. Therefore, the access unit can determine the available address blocks corresponding to the current execution domain where the processing unit is located by parsing the address partitioning information and the address permission information, thereby avoiding the modification of the address partitioning information of the available address blocks during the switching of the PMP context, thereby improving the processing performance of the processing unit.

[0084] In other embodiments, the address permission information includes a plurality of consecutive permission segments, each of which corresponds to a plurality of address blocks in the physical memory space, and each permission segment indicates an execution domain that has access rights to the address block corresponding to that permission segment.

[0085] In other embodiments, each permission segment includes multiple fields corresponding to the plurality of execution domains, each field indicating whether the execution domain corresponding to the field has access rights to the address block corresponding to the permission segment.

[0086] In other embodiments, parsing address permission information and address partition information to determine the available address block corresponding to the current execution domain where the processing unit is located includes: sequentially parsing multiple fields in each permission segment that correspond to the multiple execution domains respectively, and when the field corresponding to the current execution domain indicates that the current execution domain has access permission for the address block corresponding to the permission segment, determining the address block corresponding to the permission segment as an available address block.

[0087] In other embodiments, when the access address of the currently accessed object matches the available address block, an access operation is performed on the currently accessed object, including: finding the operation permission corresponding to the available address block, and performing the access operation on the currently accessed object according to the operation permission, wherein the currently accessed object is the current instruction or the current data, and the operation permission information includes at least one of read permission, write permission and execute permission.

[0088] In other embodiments, the processing unit further includes a permission configuration register, which stores operation permission information corresponding to the address partition information. The operation permission information indicates the operation permissions for access objects within each address block. Finding the operation permissions corresponding to the available address block includes: parsing the operation permission information to determine the operation permissions corresponding to the available address block.

[0089] In other embodiments, the access control method further includes configuring operation permission information corresponding to the plurality of address blocks into the permission configuration register before obtaining the access address of the currently accessed object.

[0090] In other embodiments, the access control method further includes configuring operation permission information corresponding to the available address block into the permission configuration register when the processing unit switches from the previous execution domain to the current execution domain.

[0091] In other embodiments, the access control method further includes: configuring the address partition information into the address partition register and configuring the address permission information into the address permission register before configuring the operation permission information corresponding to the plurality of address blocks into the permission configuration register.

[0092] In other embodiments, the address permission information indicates that all of the plurality of address blocks are disabled address blocks. The access control method further includes configuring the address partition information into the address partition register when the processing unit switches from the previous execution domain to the current execution domain.

[0093] In other embodiments, the register management unit can uniformly configure address partitioning information to the address partition register and address permission information to the address permission register before access operations corresponding to multiple execution domains. In other words, by adjusting the implementation logic of the register management unit, it can be enabled to configure both the address permission register and the address partition register.

[0094] In some examples, the register management unit can uniformly configure operation permission information corresponding to multiple address blocks in the permission configuration register before access operations corresponding to multiple execution domains. For example, the address partition register stores address partition information, and the address partition table entries in the address partition information indicate the physical address start or physical address end of the corresponding address block. The permission configuration register stores operation permission information corresponding to the address partition information, and the operation permission table entries in the operation permission information indicate the operation permissions for the access objects in the corresponding address blocks. The address partition table entries and operation permission table entries form PMP entries. The access unit can select the corresponding PMP entry by parsing the address permission information without managing the disabled or enabled state of the PMP entries, thus ensuring compatibility with the configuration process of the permission configuration register in the physical memory protection mechanism.

[0095] Alternatively, the register management unit can configure the operation permission information corresponding to the available address block into the permission configuration register when the processing unit switches from the previous execution domain to the current execution domain, so as to further be compatible with the timing of the configuration of the permission configuration register in the physical memory protection mechanism.

[0096] For example, when a processing unit switches from the previous execution domain to the current execution domain, the instruction fetch unit obtains an execution domain switching instruction (e.g., a privileged mode switching instruction). The instruction execution unit executes the execution domain switching instruction, marks the current execution domain in the execution domain register, marks the interrupt status in the mstatus register, and transfers execution privileges to the register management unit. Correspondingly, the register management unit reads the current execution domain marked in the execution domain register and configures the operation permission information corresponding to the available address blocks into the permission configuration register. For example, the permission configuration register pre-stores operation permission information corresponding to address partition information. Each operation permission entry in the operation permission information indicates the operation permission for the access object in the corresponding address block. The permission configuration register disables the operation permission entries corresponding to the previous execution domain and enables the operation permission entries corresponding to the current execution domain.

[0097] In other embodiments, address permission information indicates that multiple address blocks are disabled address blocks. Accordingly, the register management unit can configure address partitioning information into the address partition register when the processing unit switches from the previous execution domain to the current execution domain. For example, the register management unit can set multiple address blocks as available address blocks in at least one target execution domain. When the current execution domain is the target execution domain, there is no need to parse the address permission information to select the corresponding PMP table entry. The unit can continue to manage the disabled or enabled state of the PMP table entry, thus achieving high compatibility with the address partition register and address permission register in the physical memory protection mechanism.

[0098] It should be understood that the specific implementation of each step in the access control method can be found in the description of the corresponding unit in the embodiment of the processing unit, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above access control method and steps can be referred to the corresponding process description in the aforementioned processing unit, and will not be repeated here.

[0099] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0100] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0102] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A processing unit, comprising: The address partition register stores address partition information, which indicates multiple address blocks in the physical memory space. The address permission register stores address permission information for multiple execution domains, wherein the address permission information indicates the available address blocks that each execution domain has access to in the multiple address blocks; The access unit parses the address permission information and the address partition information to determine the available address block corresponding to the current execution domain where the processing unit is located, and performs an access operation for the current access object when the access address of the current access object matches the available address block.

2. The processing unit according to claim 1, wherein, The address permission information includes multiple consecutive permission segments, each of which corresponds to multiple address blocks in the physical memory space. Each permission segment indicates an execution domain that has access rights to the address block corresponding to that permission segment.

3. The processing unit according to claim 2, wherein, Each permission segment includes multiple fields corresponding to the multiple execution domains, and each field indicates whether the execution domain corresponding to the field has access rights to the address block corresponding to the permission segment.

4. The processing unit according to claim 3, wherein, The access unit is further configured to: sequentially parse multiple fields in each permission segment that correspond to the multiple execution domains respectively, and when the field corresponding to the current execution domain indicates that the current execution domain has access rights to the address block corresponding to the permission segment, determine the address block corresponding to the permission segment as an available address block.

5. The processing unit according to claim 4, wherein, The access unit is further configured to: find the operation permissions corresponding to the available address block, and perform an access operation on the current access object according to the operation permissions, wherein the current access object is the current instruction or the current data, and the operation permission information includes at least one of read permission, write permission and execute permission.

6. The processing unit according to claim 5, wherein, The processing unit further includes a permission configuration register, which stores operation permission information corresponding to the address partition information. The operation permission information indicates the operation permissions for the access objects in each address block. The access unit is further configured to: parse the operation permission information and determine the operation permission corresponding to the available address block.

7. The processing unit according to claim 6, wherein, The processing unit further includes a register management unit, which is used to configure the operation permission information corresponding to the plurality of address blocks into the permission configuration register.

8. The processing unit according to claim 7, wherein, The register management unit is further configured to: when the processing unit switches from the previous execution domain to the current execution domain, configure the operation permission information corresponding to the available address block into the permission configuration register.

9. The processing unit according to claim 7, wherein, The register management unit is further configured to: configure the address partition information into the address partition register, and configure the address permission information into the address permission register.

10. The processing unit according to claim 9, wherein, The address permission information indicates that the multiple address blocks are all disabled address blocks. Accordingly, the register management unit is further configured to: configure the address partition information into the address partition register when the processing unit switches from the previous execution domain to the current execution domain.

11. A processor, comprising: Multiple processing units, each of which is a processing unit according to any one of claims 1-10.

12. A system-on-a-chip, comprising: The processor according to claim 11; An on-chip network, wherein the plurality of processing units are connected via the on-chip network.

13. A computing device, comprising: Memory, including the physical memory space; The system-on-a-chip according to claim 12.

14. An access control method, comprising: When the access address of the currently accessed object is obtained, the address partition information in the access address partition register and the address permission information in the address permission register for multiple execution domains are used. The address partition information indicates multiple address blocks in the physical memory space, and the address permission information indicates the available address blocks in the multiple address blocks for which each execution domain has access rights. Parse address permission information and address partition information to determine the available address blocks corresponding to the current execution domain where the processing unit is located; When the access address of the currently accessed object matches the available address block, an access operation is performed on the currently accessed object.

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