An EEPROM-based wear leveling method and system

Abstract

This invention discloses a wear leveling method and system based on EEPROM, relating to the fields of data storage and chip lifespan management. The method divides the EEPROM into contiguous wear leveling zones and employs an append-only versioned write mechanism. Each data update is constructed as a fixed-length entry containing a logical key, data value, global sequence number, and checksum, and written to different physical addresses. During reading, sequential scanning and verification are used to locate the latest value based on the logical key and the maximum sequence number. When a region is full, garbage collection is triggered, collecting the latest values ​​of all logical keys, erasing the entire region, compactly rewriting, and resetting the write pointer. This invention eliminates the need for complex address mapping tables and dynamic memory allocation, requiring only the maintenance of a single write pointer. It achieves uniform distribution of write operations with extremely low overhead, making it suitable for resource-constrained microcontroller systems. It can extend the overall lifespan of the EEPROM and provides excellent power-loss safety and data reliability.

Description

Technical Field

[0001] This invention relates to the field of data storage and chip lifespan management technology, and in particular to a wear leveling method and system based on EEPROM. Background Technology

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) has become the standard device in embedded systems for storing key parameters, configuration information, calibration data, and operational history due to its advantages such as byte-level programmability, non-volatility, high reliability, and simple interface. However, each memory cell of an EEPROM has a limited number of programming / erasing cycles, typically ranging from 10^5 to 10^6.

[0003] In applications requiring frequent data updates, such as recording cumulative values ​​for industrial sensors, calculating power consumption in smart meters, and storing status parameters for IoT terminals, improper software design leading to continuous write operations to the same physical address can cause that unit to rapidly reach its lifespan limit and fail. This premature failure of a localized unit can trigger system malfunctions, rendering the entire EEPROM chip unusable prematurely. This prevents the full utilization of its storage capacity, wasting hardware resources and severely reducing the long-term reliability of the system.

[0004] Wear leveling is a key technology for extending the lifespan of memory with limited erase / write cycles. Existing technologies mainly focus on flash memory (NAND / NORFlash), solid-state drives (SSDs), and new non-volatile memory (such as phase-change memory, PCM). These advanced wear leveling schemes typically involve complex logical-to-physical address mapping tables, dynamic metadata management, hot and cold data separation, concurrency control, or dedicated hardware acceleration. They have high algorithm complexity and place stringent demands on the system's RAM and CPU computing power.

[0005] Typical serial EEPROMs (such as the Microchip 24LC series and STM24 series) are used in resource-constrained microcontroller (MCU) systems, especially low-end 8-bit or 32-bit MCUs. Their RAM capacity is typically only a few KB to tens of KB, and their CPU frequency is only tens of MHz. Furthermore, the EEPROM itself only supports byte / page write operations and lacks internal block management or hardware address remapping capabilities. Directly porting the aforementioned complex flash memory wear leveling scheme to such lightweight platforms is impractical and would lead to system resource exhaustion and malfunction.

[0006] Currently, there is a lack of lightweight, low-overhead, and highly reliable software wear leveling algorithms specifically designed for small-capacity serial EEPROMs and resource-constrained MCU environments. Therefore, there is an urgent need for a simple and effective technical solution to address the problem of localized wear in EEPROMs and maximize their lifespan. Summary of the Invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a wear leveling processing method and system based on EEPROM.

[0008] In a first aspect, embodiments of the present invention provide a wear leveling method based on EEPROM, comprising:

[0009] S100. Divide the EEPROM storage space into continuous wear leveling dedicated areas, and initialize and scan the status of the wear leveling dedicated areas;

[0010] S200. When a data write request is received, the append write method is adopted to write the data entry containing key, value, sequence number and checksum formed by each data update into the new area, so that multiple updates of the same logical data are distributed across different physical addresses;

[0011] S300. When a data read request is received, the wear leveling area is scanned sequentially, each valid data entry is parsed and verified, and the latest value is located according to the key and the maximum sequence number;

[0012] S400. When a region is full, a garbage collection mechanism is triggered to collect the latest values ​​of all keys, erase the entire region, rewrite it compactly, and reset the write pointer, thus realizing garbage collection and space reorganization of the region.

[0013] Furthermore, the wear leveling area is initialized and its status is scanned. The specific method includes: sequentially scanning the wear leveling area, locating the write position of the last valid data entry according to the preset data entry format and verification rules, and setting the next free address as the current write pointer.

[0014] Furthermore, the data entry has a fixed-length structure, which includes, in sequence: a 1-byte logical key field for identifying the data body, a 2-byte numeric field for storing the data content, a 2-byte sequence number field for identifying the order in which the data was written, and a 1-byte checksum field for verifying data integrity. The checksum field is calculated by summing the value of the logical key field, the low byte of the numeric field, the high byte of the numeric field, and the 16-bit value of the sequence number field, and taking the lower 8 bits of the sum as the checksum.

[0015] Furthermore, the specific method for locating the write position of the last valid data entry is as follows: starting from the starting address of the wear leveling zone, read and verify each data entry one by one according to its length; if the current entry is successfully verified, record its sequence number and the address of the next entry; if the current entry fails to be verified or its content is a preset blank identifier, stop scanning and set the current address as the current write pointer.

[0016] Furthermore, in S200, an append-only write method is used to write each data update, resulting in a data entry containing a key, value, sequence number, and checksum, into a new area. Specific methods include:

[0017] Construct a new data entry, which includes at least the logical key, the data value to be written, an incrementing global sequence number, and a checksum calculated based on the aforementioned fields; append the new data entry to the physical address of the wear leveling zone pointed to by the current write pointer, and then update the current write pointer.

[0018] Furthermore, the global serial number is a 16-bit unsigned integer, generated in a cyclic increment manner. When the serial number reaches 0xFFFF, the next serial number starts again from 0x0000.

[0019] Furthermore, in S300, each valid data entry is parsed and verified, and the latest value is located based on the key and the maximum sequence number. Specific methods include:

[0020] The wear leveling area is scanned sequentially, each valid data entry is parsed and verified, entries whose logical keys match the request are selected, and the entry with the largest global sequence number is selected from these entries, and its data value is returned as the result.

[0021] Furthermore, in S400, the latest values ​​of all keys are collected, the entire area is erased and then rewritten compactly, and the write pointer is reset. Specific methods include:

[0022] S401. Collect valid data: Traverse the entire wear leveling zone, and for each logical key that has appeared, find the valid data entry with the largest global sequence number corresponding to it, and use it as the latest value of that key;

[0023] S402. Physically erase the region: Set all or part of the physical storage units of the wear leveling region to the erase state; the physical storage units of the wear leveling region are set to the erase state by cyclically writing data with a value of 0xFF to all addresses of the region;

[0024] S403. Perform compaction rewrite and state reset: Rewrite all the latest value data entries collected in S401 into a continuous space starting from the start address of the wear leveling zone, and reset the current write pointer.

[0025] Secondly, this invention also discloses a wear leveling system based on EEPROM, comprising: a region initialization and state scanning unit, a data writing unit, a data reading unit, and a garbage collection and space organization unit; wherein:

[0026] The region initialization and status scanning unit is used to divide a continuous wear leveling dedicated region in the EEPROM storage space, and to initialize and scan the status of the wear leveling dedicated region.

[0027] The data writing unit is used to append data to a new area when a data write request is received. This is done by writing each data update into a new area, which contains a key, value, sequence number and checksum. This allows multiple updates of the same logical data to be distributed across different physical addresses.

[0028] The data reading unit is used to sequentially scan the wear leveling area when a data reading request is received, parse and verify each valid data entry, and locate the latest value according to the key and the maximum sequence number;

[0029] The garbage collection and space reorganization unit is used to trigger the garbage collection mechanism when the area is full, collect the latest values ​​of all keys, erase the entire area and rewrite it compactly, and reset the write pointer to realize garbage collection and space reorganization of the area.

[0030] Thirdly, the present invention also discloses an electronic device, comprising:

[0031] One or more processors;

[0032] Memory, used to store one or more programs;

[0033] When the one or more programs are executed by the one or more processors, the one or more processors implement the processing method.

[0034] This invention discloses a wear leveling method and system based on EEPROM. The method divides the EEPROM into contiguous wear leveling zones and employs an append-only versioned write mechanism. Each data update is constructed as a fixed-length entry containing a logical key, data value, global sequence number, and checksum, and written to different physical addresses. During reading, sequential scanning and verification are used to locate the latest value based on the logical key and the maximum sequence number. When a region is full, garbage collection is triggered, collecting the latest values ​​of all logical keys, erasing the entire region, compactly rewriting, and resetting the write pointer. This invention eliminates the need for complex address mapping tables and dynamic memory allocation, requiring only the maintenance of a single write pointer. It achieves uniform distribution of write operations with extremely low software overhead, making it particularly suitable for resource-constrained microcontroller systems. It can extend the overall lifespan of the EEPROM by more than 300 times, while also possessing excellent power-loss safety and data reliability.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. Extremely Lightweight: The algorithm core only needs to maintain a write pointer and a few counters, requiring no dynamic memory allocation, complex mapping tables, or linked list structures. Memory usage is only a few tens of bytes, and CPU operations consist of simple addition, subtraction, and comparisons, making it extremely suitable for running on low-end 8-bit / 32-bit MCUs.

[0037] 2. High efficiency and balanced operation: The "append-write" strategy naturally distributes multiple updates to the same logical data across different physical addresses. The "garbage collection" process forces all valid data to be migrated to the head of the region, so that subsequent writes start the cycle from the head again, achieving an approximately uniform distribution of write operations in physical space and effectively avoiding "hot" addresses.

[0038] 3. High Reliability: Each data entry comes with its own checksum and global sequence number, providing dual protection for data integrity and version correctness. Even if the system loses power during the write process, the recovery mechanism based on checksum and sequential scanning ensures that the system can retrieve the latest valid values ​​of all logical keys, resulting in high data reliability.

[0039] 4. High versatility: The algorithm is implemented entirely in software, without relying on specific EEPROM models or hardware characteristics; only basic byte read / write drivers are required. It is easy to port and integrate into existing embedded software projects.

[0040] 5. Significantly Extended Lifespan: By distributing write operations across the entire reserved area, the overall lifespan of this area can theoretically be increased by approximately [number] times the area size / [number] times the size of data written per instance. For example, using a 128-byte area to store 5-byte entries, wear leveling can ideally be improved by more than 25 times. Attached Figure Description

[0041] Figure 1 A schematic flowchart of a wear leveling method based on EEPROM provided in an embodiment of the present invention;

[0042] Figure 2 A flowchart illustrating a wear leveling method based on EEPROM provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of the data structure and state scan of the wear leveling zone in an embodiment of the present invention;

[0044] Figure 4 This table compares the overall performance of the embodiments of the present invention with five existing wear leveling algorithms.

[0045] Figure 5 A structural block diagram of an EEPROM-based wear leveling system provided in an embodiment of the present invention;

[0046] Figure 6 This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions of the present invention, exemplary embodiments of the present invention are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0048] Where there is no conflict, the various embodiments of the present invention and the features thereof may be combined with each other.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0052] In the technical solution of this invention, the collection, storage, use, processing, transmission, provision, and disclosure of user personal information all comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example: appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely locating a specific individual.

[0053] To address at least one of the technical problems existing in the aforementioned related technologies, the present invention provides a wear leveling processing method and system based on EEPROM.

[0054] This implementation discloses a wear leveling method based on EEPROM, such as... Figure 1 and 2 ,include:

[0055] S100. Divide the EEPROM storage space into continuous wear leveling dedicated areas, and initialize and scan the status of the wear leveling dedicated areas; In S100 of this embodiment, the specific method for initializing and scanning the status of the wear leveling dedicated areas includes: sequentially scanning the wear leveling area, locating the write position of the last valid data entry according to the preset data entry format and verification rules, and setting the next free address as the current write pointer.

[0056] In this embodiment, the data entry is a fixed-length structure, which includes, in sequence: a 1-byte logical key field for identifying the data body, a 2-byte numeric field for storing the data content, a 2-byte sequence number field for identifying the order in which the data was written, and a 1-byte checksum field for verifying data integrity. The checksum field is calculated by summing the value of the logical key field, the low byte of the numeric field, the high byte of the numeric field, and the 16-bit value of the sequence number field, and taking the lower 8 bits of the sum as the checksum.

[0057] In this embodiment, the specific method for locating the write position of the last valid data entry is as follows: starting from the starting address of the wear leveling zone, read and verify each data entry one by one according to its length; if the current entry is successfully verified, record its sequence number and the address of the next entry; if the current entry fails to be verified or its content is a preset blank identifier, stop scanning and set the current address as the current write pointer.

[0058] For example, this embodiment uses an APM32F103 microcontroller and a 24LC16 (2KB) EEPROM. The entire 2048 bytes of the EEPROM are used as a wear leveling region. A data entry structure `wear_level_entry_t` is defined, containing a 1-byte key (0-255), a 2-byte value, a 2-byte sequence number (0-65535 repeating), and a 1-byte checksum.

[0059] Following the steps outlined in S100, after system power-on or reset, the microcontroller calls the EEPROM_WearLevel_Init function for initialization. This function performs the following steps:

[0060] Starting from the EEPROM start address (0x0000), data is read sequentially in steps of 6 bytes (one wear_level_entry_t entry).

[0061] For each 6 bytes of data read, the `CalculateChecksum` function is called to recalculate the checksum using the read key, value, and sequence fields. The calculated checksum is then compared to the `checksum` field stored in the entry.

[0062] If they match, the entry is considered valid. Its sequence number is recorded, and the next address (current address + 6) is temporarily considered a potential write location. If they do not match, or if all read data is 0xFF (blank state), an invalid entry or the end of a region is considered encountered, and scanning is stopped immediately. The last recorded "next address" is set as the current write pointer (s_current_write_pos). This pointer is stored in the MCU's RAM, indicating the physical address where the next write operation will occur.

[0063] S200. When a data write request is received, the append write method is adopted to write the data entry containing key, value, sequence number and checksum formed by each data update into the new area, so that multiple updates of the same logical data are distributed across different physical addresses;

[0064] In this embodiment, in S200, an append-only write method is used to write the data entry containing the key, value, sequence number, and checksum formed by each data update into the new area. The specific method includes:

[0065] A new data entry is constructed, which includes at least the logical key, the data value to be written, an incrementing global sequence number, and a checksum calculated based on the aforementioned fields. The new data entry is appended to the physical address of the wear leveling region pointed to by the current write pointer, and then the current write pointer is updated. The global sequence number is a 16-bit unsigned integer, generated in a circular incrementing manner; when the sequence number reaches 0xFFFF, the next sequence number starts again from 0x0000.

[0066] For example, this embodiment uses an APM32F103 microcontroller and a 24LC16 (2KB) EEPROM. When the application needs to update data, it calls the EEPROM_WearLevel_Write function. This function performs the following steps:

[0067] Check space: Determine if the current write pointer has reached or exceeded the end address of the EEPROM (0x07FF). If so, trigger the garbage collection process.

[0068] Constructing an entry: The passed-in key and value are combined with a globally incrementing 16-bit sequence number counter s_sequence, and the checksum is calculated by calling CalculateChecksum to form a complete new 6-byte entry.

[0069] Append to write: Call the underlying driver EEPROM_24LC16_Write to write this 6-byte entry to the EEPROM physical address pointed to by the current write pointer.

[0070] Update pointer: Increment the current write pointer by 6, pointing to the next free position. Increment the global write counter s_total_write_count by 1, completing this write operation.

[0071] S300. When a data read request is received, the wear leveling area is scanned sequentially, each valid data entry is parsed and verified, and the latest value is located according to the key and the maximum sequence number;

[0072] In S300 of this embodiment, each valid data entry is parsed and verified, and the latest value is located based on the key and the maximum serial number. The specific method includes: sequentially scanning the wear leveling area, parsing and verifying each valid data entry, filtering out entries whose logical keys match the request, selecting the entry with the largest global serial number from these entries, and returning its data value as the result.

[0073] For example, this embodiment uses an APM32F103 microcontroller and a 24LC16 (2KB) EEPROM. When the application needs to read data, it calls the EEPROM_WearLevel_Read function. This function performs the following steps:

[0074] Starting from the EEPROM start address (0x0000), sequentially scan each 6-byte entry.

[0075] Perform validation and verification on each entry (using the same method as the initialization process).

[0076] Among all valid entries, find the one whose key field matches the request.

[0077] Among these matching entries, their sequence fields are compared, and the entry with the largest value is selected. The value field of this entry is the latest valid data corresponding to that logical key, which is then returned to the application.

[0078] S400. When a region is full, a garbage collection mechanism is triggered to collect the latest values ​​of all keys, erase the entire region, rewrite it compactly, and reset the write pointer, thus realizing garbage collection and space reorganization of the region.

[0079] In S400 of this embodiment, the latest values ​​of all keys are collected, the entire area is erased and then rewritten compactly, and the write pointer is reset. The specific method includes:

[0080] S401. Collect valid data: Traverse the entire wear leveling zone, and for each logical key that has appeared, find the valid data entry with the largest global sequence number corresponding to it, and use it as the latest value of that key;

[0081] S402. Physically erase the region: Set all or part of the physical storage units of the wear leveling region to the erase state; the physical storage units of the wear leveling region are set to the erase state by cyclically writing data with a value of 0xFF to all addresses of the region;

[0082] S403. Perform compaction rewrite and state reset: Rewrite all the latest value data entries collected in S401 into a continuous space starting from the start address of the wear leveling zone, and reset the current write pointer.

[0083] After garbage collection is complete, the wear leveling area retains only the latest values ​​of all logical keys, freeing up the space occupied by all old version entries, allowing the system to continue with new write operations.

[0084] For example, this embodiment uses an APM32F103 microcontroller and a 24LC16 (2KB) EEPROM. Figure 3 As shown, when the EEPROM space is insufficient, the CompactWearLevelArea function is triggered to perform garbage collection to free up space.

[0085] Collect valid data:

[0086] like Figure 3 As shown on the left, the entire EEPROM (0x0000 to 0x07FF) is traversed. For each logic key (e.g., key=0x01, 0x02, 0x03), the sequence with the largest value among all valid entries is found using the above read logic and used as the unique latest value for that key. These latest value entries are temporarily stored in the MCU's RAM.

[0087] Erase the entire area:

[0088] By repeatedly calling the EEPROM_24LC16_Write operation, 0xFF is written to every address in the entire EEPROM address space (0x0000 to 0x07FF), restoring the entire chip to the "erase" state.

[0089] Compact rewrite and reset:

[0090] The latest value entry collected (e.g.) Figure 3 The latest values ​​of entries C, B, and E are rewritten sequentially, starting from the EEPROM start address (0x0000), according to the key order or any other order.

[0091] Assign new, consecutive sequence numbers (e.g., starting from 0) to these rewritten entries.

[0092] Based on the number of entries written, recalculate and set the current write pointer. For example... Figure 3 As shown on the right, the pointer is reset after the compact data and points to the beginning of the new free area.

[0093] To verify the performance advantages of this invention, we conducted standardized tests on the same hardware platform (APM32F103+24LC16) comparing this invention with five existing mainstream wear leveling algorithms (dynamic leveling, static leveling, block rotation, counter-assisted, and mapping table schemes). The test results are as follows: Figure 4 As shown.

[0094] The comprehensive performance comparison table (Figure 4) shows that the present invention performs best in terms of RAM usage, ROM usage, write amplification factor, write latency and power-down safety, with a theoretical lifespan extension of 341 times. It is currently the most suitable EEPROM wear leveling solution for resource-constrained embedded systems.

[0095] This embodiment of the invention discloses a wear leveling method and system based on EEPROM. The method divides the EEPROM into contiguous wear leveling zones and employs an append-only versioned write mechanism. Each data update is constructed as a fixed-length entry containing a logical key, data value, global sequence number, and checksum, and written to different physical addresses. During reading, sequential scanning and verification are used to locate the latest value based on the logical key and the maximum sequence number. When a region is full, garbage collection is triggered, collecting the latest values ​​of all logical keys, erasing the entire region, compactly rewriting, and resetting the write pointer. This invention eliminates the need for complex address mapping tables and dynamic memory allocation, requiring only the maintenance of a single write pointer. It achieves uniform distribution of write operations with extremely low software overhead, making it particularly suitable for resource-constrained microcontroller systems. It can extend the overall lifespan of the EEPROM by more than 300 times, while also possessing excellent power-loss safety and data reliability.

[0096] Based on the same inventive concept, embodiments of the present invention also provide an EEPROM-based wear leveling system, such as... Figure 5 It includes: a region initialization and status scanning unit, a data writing unit, a data reading unit, and a garbage collection and space organization unit; wherein:

[0097] The region initialization and status scanning unit is used to divide a continuous wear leveling dedicated region in the EEPROM storage space, and to initialize and scan the status of the wear leveling dedicated region.

[0098] The data writing unit is used to append data to a new area when a data write request is received. This is done by writing each data update into a new area, which contains a key, value, sequence number and checksum. This allows multiple updates of the same logical data to be distributed across different physical addresses.

[0099] The data reading unit is used to sequentially scan the wear leveling area when a data reading request is received, parse and verify each valid data entry, and locate the latest value according to the key and the maximum sequence number;

[0100] The garbage collection and space reorganization unit is used to trigger the garbage collection mechanism when the area is full, collect the latest values ​​of all keys, erase the entire area and rewrite it compactly, and reset the write pointer to realize garbage collection and space reorganization of the area.

[0101] The specific working methods of the region initialization and status scanning unit, data writing unit, data reading unit, and waste recycling and space organization unit have been described in detail in the above-mentioned wear leveling processing method based on EEPROM, and will not be repeated here in this embodiment.

[0102] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. Figure 6This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Figure 6 As shown, an embodiment of the present invention provides an electronic device including: one or more processors 101, a memory 102, and one or more I / O interfaces 103. The memory 102 stores one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement any of the methods described in the above embodiments; the one or more I / O interfaces 103 are connected between the processor and the memory, configured to enable information interaction between the processor and the memory.

[0103] The processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus).

[0104] In some embodiments, the processor 101, memory 102, and I / O interface 103 are interconnected via bus 104, and thus connected to other components of the computing device.

[0105] In some embodiments, the one or more processors 101 include a field-programmable gate array.

[0106] This invention also provides a computer-readable medium. The computer-readable medium stores a computer program, which, when executed by a processor, implements the steps of any of the methods described in the above embodiments. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0107] This invention also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the above-described method.

[0108] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0109] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0110] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0111] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0112] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0113] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0114] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0115] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0117] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A wear leveling method based on EEPROM, characterized in that, include: S100. Divide the EEPROM storage space into continuous wear leveling dedicated areas, and initialize and scan the status of the wear leveling dedicated areas; S200. When a data write request is received, the append write method is adopted to write the data entry containing key, value, sequence number and checksum formed by each data update into the new area, so that multiple updates of the same logical data are distributed across different physical addresses; S300. When a data read request is received, the wear leveling area is scanned sequentially, each valid data entry is parsed and verified, and the latest value is located according to the key and the maximum sequence number; S400. When a region is full, a garbage collection mechanism is triggered to collect the latest values ​​of all keys, erase the entire region, rewrite it compactly, and reset the write pointer, thus realizing garbage collection and space reorganization of the region.

2. The method according to claim 1, characterized in that, In S100, the wear leveling area is initialized and its status is scanned. The specific method includes: sequentially scanning the wear leveling area, locating the write position of the last valid data entry according to the preset data entry format and verification rules, and setting the next free address as the current write pointer.

3. The processing method according to claim 2, characterized in that, The data entry has a fixed-length structure, which includes, in sequence: a 1-byte logical key field for identifying the data body, a 2-byte numeric field for storing the data content, a 2-byte sequence number field for identifying the order in which the data was written, and a 1-byte checksum field for verifying data integrity. The checksum field is calculated by summing the value of the logical key field, the low byte of the numeric field, the high byte of the numeric field, and the 16-bit value of the sequence number field, and taking the lower 8 bits of the sum as the checksum.

4. The processing method according to claim 2, characterized in that, The specific method for locating the write position of the last valid data entry is as follows: starting from the starting address of the wear leveling zone, read and verify each data entry one by one according to its length; if the current entry is successfully verified, record its sequence number and the address of the next entry; if the current entry fails to be verified or its content is a preset blank identifier, stop scanning and set the current address as the current write pointer.

5. The processing method according to claim 1, characterized in that, In S200, an append-only write method is used to write each data update, resulting in a data entry containing a key, value, sequence number, and checksum, into a new area. Specific methods include: Construct a new data entry, which includes at least the logical key, the data value to be written, an incrementing global sequence number, and a checksum calculated based on the aforementioned fields; append the new data entry to the physical address of the wear leveling zone pointed to by the current write pointer, and then update the current write pointer.

6. The processing method according to claim 5, characterized in that, The global serial number is a 16-bit unsigned integer, generated in a cyclic increment manner. When the serial number reaches 0xFFFF, the next serial number starts again from 0x0000.

7. The processing method according to claim 1, characterized in that, In S300, each valid data entry is parsed and verified, and the latest value is located based on the key and the maximum sequence number. Specific methods include: The wear leveling area is scanned sequentially, each valid data entry is parsed and verified, entries whose logical keys match the request are selected, and the entry with the largest global sequence number is selected from these entries, and its data value is returned as the result.

8. The processing method according to claim 1, characterized in that, In S400, the latest values ​​of all keys are collected, the entire area is erased and then rewritten compactly, and the write pointer is reset. Specific methods include: S401. Collect valid data: Traverse the entire wear leveling zone, and for each logical key that has appeared, find the valid data entry with the largest global sequence number corresponding to it, and use it as the latest value of that key; S402. Physically erase the region: Set all or part of the physical storage units of the wear leveling region to the erase state; the physical storage units of the wear leveling region are set to the erase state by cyclically writing data with a value of 0xFF to all addresses of the region; S403. Perform compaction rewrite and state reset: Rewrite all the latest value data entries collected in S401 into a continuous space starting from the start address of the wear leveling zone, and reset the current write pointer.

9. A wear leveling system based on EEPROM, employing the processing method described in any one of claims 1-8, characterized in that, include: The system comprises a region initialization and status scanning unit, a data writing unit, a data reading unit, and a garbage collection and space management unit; among which: The region initialization and status scanning unit is used to divide a continuous wear leveling dedicated region in the EEPROM storage space, and to initialize and scan the status of the wear leveling dedicated region. The data writing unit is used to append data to a new area when a data write request is received. This is done by writing each data update into a new area, which contains a key, value, sequence number and checksum. This allows multiple updates of the same logical data to be distributed across different physical addresses. The data reading unit is used to sequentially scan the wear leveling area when a data reading request is received, parse and verify each valid data entry, and locate the latest value according to the key and the maximum sequence number; The garbage collection and space reorganization unit is used to trigger the garbage collection mechanism when the area is full, collect the latest values ​​of all keys, erase the entire area and rewrite it compactly, and reset the write pointer to realize garbage collection and space reorganization of the area.

10. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the processing method as described in any one of claims 1 to 8.

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