A memory hierarchical data cache intelligent scheduling method and system

Abstract

This invention relates to the field of intelligent chips and discloses a memory-layered data cache intelligent scheduling method and system, comprising: using a physical page hit signal generated by a conversion backup buffer to drive a historical state shift register associated with a page table entry to generate a physical displacement, generating a bitmap reflecting memory access activity, performing a logical AND operation on the bitmap with a preset intrinsic write cost constant of the medium, counting the number of high-level bits in the logical result through a physical group counting circuit and outputting a state parameter, adjusting the bypass multiplexer selection path based on the parameter, intercepting write instruction data blocks with low memory access activity at the static random access memory level, blocking the write path to the underlying non-volatile storage medium. This invention utilizes the physical evolution law of hardware bits to eliminate the microprocessor pipeline shadow delay caused by arithmetic scheduling logic, maintain low latency specifications for memory access paths, and effectively reduce the erase and write losses of the underlying medium.

Description

Technical Field

[0001] This invention relates to the field of intelligent chip technology, specifically to a memory hierarchical data cache intelligent scheduling method and system. Background Technology

[0002] Currently, the mainstream approach to balancing access latency and storage capacity is to construct a tiered storage architecture using high-speed static random access memory, dynamic random access memory, and non-volatile memory. This approach attempts to expand system capacity while ensuring memory access speed by scheduling data across different storage tiers. However, as the complexity of computational tasks increases, memory access request flows exhibit significant temporal clustering and spatial dispersion. Existing storage scheduling strategies typically make decisions based on access frequency or address span, assuming that the access cost is equal across all storage tiers. In actual operation, this approach leads to frequent occupancy of cache space by low-reusability data flows, causing cache thrashing and increasing bus bandwidth load. Furthermore, excessive erase and write operations on non-volatile memory reduce the overall reliability of the storage system.

[0003] To address these issues, the industry has attempted to introduce multi-dimensional feature weighting models or complex scheduling algorithms. However, cache hit determination needs to be completed within a short clock cycle, adding complex logical operations to the memory access path and generating processing latency. This latency causes pauses in the processor pipeline, and the resulting performance loss often offsets the throughput gains from strategy optimization. For example, Chinese invention patent CN120256340B discloses a hardware-based memory access pattern recognition device and method, which uses independent state machine logic and a confidence counter to recognize memory access patterns. The patented solution uses hardware circuitry to accelerate the identification process by identifying trace patterns. However, it relies on multi-level state machine transitions and confidence iteration calculations. The logic evolution incurs micro-clock cycle overhead during extremely high-frequency memory access windows, making it difficult to achieve zero-latency feature response. This technology focuses on memory access pattern identification to assist prefetching, without considering the physical differences in write cost, power consumption, and lifespan between heterogeneous storage media. When faced with high-frequency random write operations, it cannot accurately segment paths based on the intrinsic properties of the media. Due to the lack of real-time arbitration of the physical characteristics of the media, existing technologies cannot avoid the wear and tear of low-heat data on non-volatile storage media.

[0004] Therefore, how to utilize the native state of the underlying hardware to achieve low-overhead memory access feature extraction, and combine it with the characteristics of the storage medium to determine the data flow path, is the technical problem that this invention aims to solve. Summary of the Invention

[0005] To address the problems in the background technology, this invention proposes a hierarchical intelligent scheduling method for data caching in memory, comprising the following steps: Step S101: Obtain the physical page hit signal output by the translation backup buffer. The physical page hit signal represents the addressing hit status of the microprocessor for a specific physical page frame. Step S102: The physical page hit signal is used to directly drive the 16-bit history state shift register associated with the page table entry, so that the storage bits in the history state shift register are physically shifted in one direction to generate a bit map representing the memory access history pattern; wherein, the shift frequency of the history state shift register is controlled by the shift pulse signal generated by the system global clock frequency division circuit, and the shift operation and the address translation operation are completed synchronously at the physical level. Step S103: Perform a bitwise AND operation on the bitmap and the intrinsic write cost constant of the storage medium, which is pre-placed in the configuration register and represents the write loss weight of the storage medium. Use the hardware group counter to count the physical number of high-level bits in the parallel operation result and output the state parameter representing the memory access cluster density. Step S104: Adjust the selection path of the bypass multiplexer according to the state parameter. If the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory level, blocking the write path of the data block to the underlying non-volatile storage medium, thereby eliminating the microprocessor pipeline shadow delay caused by arithmetic scheduling logic by utilizing the physical evolution of hardware bit states.

[0006] Preferably, the historical state shift register and page table entries are physically bound one-to-one; the bitwise AND logic operation includes: performing bitmasking processing on the data bits in the high-level state of the bitmap and the intrinsic cost constant of the medium, accumulating the total number of high-level bits in the logic result bits through the hardware group counting circuit to generate quantized state parameters, so as to map the physical properties of the medium without calling the microprocessor arithmetic logic unit.

[0007] Preferably, the shift pulse signal is used to drive the historical state shift register in all active states to shift to the right; when the conversion backup buffer captures the addressing request and generates a physical page hit signal, the physical page hit signal is fed back to the most significant bit input of the historical state shift register through the logic circuit hard-wired, completing the physical setting of the latest memory access event, so as to simulate the natural decay of memory access heat over time through the one-way overflow of the bit.

[0008] Preferably, if the state parameter is less than the corresponding intrinsic write cost constant of the medium and the addressing request is a write instruction, the hardware comparator generates a low-level trigger signal to the selection control terminal of the bypass multiplexer, physically blocking the write link from the data bus to the cache layer, forcibly establishing a bypass data path, enabling the microprocessor to directly access the main memory controller or the underlying non-volatile memory, thereby preventing low-frequency write operations from crowding out hot cache lines.

[0009] Preferably, the method further includes step S105, which involves using a hardware group counter to read the high-level state bits in the historical state shift register in parallel and obtaining the memory access density. The calculation formula is: ;in, For memory access density; The first in the historical state shift register The value of the status bit; The preset decay weight coefficient is used to quantify the contribution of memory access behavior in different historical periods to the current scheduling weight.

[0010] Preferably, the method further includes step S106, which involves adjusting the memory access density. A logical comparison is performed with the preset bypass threshold; if the memory access density... If the current data stream is below the bypass threshold, it is determined to be a low-reuse data stream. Based on the determination result, the bypass multiplexer cuts off the write path of the data block to the first-level cache and the second-level cache, and establishes a direct data link between the microprocessor core and the main memory to avoid invalid pollution of the hierarchical cache by streaming data.

[0011] Preferably, the intrinsic write cost constant of the medium includes a weighted constant used to characterize the write latency, write power consumption and write lifetime of the non-volatile storage medium. The intrinsic write cost constant of the medium is stored in a read-only configuration register inside the microprocessor, and the output of the read-only configuration register is physically connected to a bit AND logic gate circuit to ensure that the parameters of the physical characteristics of the medium can participate in the logical arbitration of the hardware gating path in real time.

[0012] Preferably, if the state parameter is within the preset physical relocation range, the cache controller initiates background asynchronous migration logic to migrate the data block from the static random access memory (SRAM) level to the underlying dynamic random access memory (DRAM) level, and synchronously updates the media index bit in the page table entry. This asynchronous migration logic completes the relocation during the bus idle period, ensuring that the system maintains stable memory access timing specifications under high concurrency conditions. The heterogeneous storage media includes a first level composed of static random access memory, a second level composed of dynamic random access memory (DRAM), and a third level composed of non-volatile memory (NDRAM). Each level is interconnected by a bus matrix with independent gating logic. The gating terminal of the bus matrix is ​​directly controlled by the output level of the bypass multiplexer, thereby completing the adaptive routing of the data block between heterogeneous media.

[0013] Preferably, the status parameter includes priority information for different storage levels; based on the priority information, the remaining storage space capacity of each storage level is polled in a round-robin fashion. If the available capacity of a high-priority storage level is lower than a preset water level threshold, the data flow is directed to the next highest priority storage level. This ensures that the heterogeneous storage media maintains stable memory access hit performance and energy efficiency ratio through dynamic feedback adjustment of storage space.

[0014] A memory-level data cache intelligent scheduling system, used to implement a memory-level data cache intelligent scheduling method, includes: The conversion backup buffer module is used to obtain the address hit status and output the physical page hit signal; The history state representation module includes a 16-bit shift unit that corresponds one-to-one with page table entries. It is used to drive the shift unit to generate a unidirectional physical displacement using the physical page hit signal, thereby generating a bitmap that represents the memory access history pattern. The parameter configuration module is used to provide preset intrinsic writing cost constants of the medium; The state quantization evaluation module is connected to the historical state characterization module and the parameter configuration module respectively. It is used to perform bitwise AND logic operations on the bitmap and the intrinsic cost constant of the medium, and output the state parameters characterizing the memory access cluster density by statistically counting the physical number of high-level bits in the operation results. The bypass gating and scheduling module is deployed on the data path of a heterogeneous storage hierarchy that includes static random access memory, dynamic random access memory, and non-volatile memory. It is used to adjust the gating path according to the state parameter. When the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory hierarchy.

[0015] The beneficial effects of this invention are: 1. In the memory hierarchical data cache intelligent scheduling method, the memory access hit level signal generated by the processor's internal memory management unit directly drives the shift register mounted on the page table entry, so that the data access history capture process and address translation action are synchronized at the physical level. This feature extraction mechanism implemented through hardware interconnection does not occupy the operation cycle of the arithmetic logic unit, avoids the processing pauses induced by complex algebraic operations on the critical path of memory access, maintains the instruction advance frequency of the processor pipeline under high-speed operation, and resolves the physical conflict between the scheduling analysis logic and the low latency requirements of the cache.

[0016] 2. The memory access activity density determined by the hardware shift state is bitwise ANDed with the media write cost parameter preset in the register, and a gating control for different storage levels is established at the logic gate level. When a high-frequency write instruction pointing to non-volatile storage medium is detected, the determination circuit directly changes the gating state of the multiplexer, constraining the relevant data block in the higher-level cache with lower write overhead. This flow path based on hardware attribute mapping reduces the physical erase and write frequency of the underlying non-volatile medium, reduces the wear rate of storage components, and improves the overall reliability of the tiered storage system.

[0017] 3. The high-level status bits in the shift register are read in real time by a physical group counter, and the bypass control logic is combined to dynamically intercept the low-multiplexing data stream. When the memory access clustering of a specific memory macroblock is lower than a preset threshold, the bypass multiplexer physically cuts off the write path of the data block to the first and second level caches, forcibly establishing a direct data link between the processor core and main memory. This multi-mechanism collaborative control method blocks the crowding of hot instruction lines in the cache by streaming data, eliminates cache thrashing caused by invalid data movement, and increases the effective load ratio of the system bus bandwidth. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of the cache scheduling method based on hardware bit physical evolution and media cost mapping of the present invention; Figure 2 This is a diagram of the intelligent scheduling system architecture for bypass path selection and heterogeneous storage layer interconnection of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] A memory-based hierarchical data caching intelligent scheduling method includes the following steps: Step S101: Obtain the physical page hit signal output by the translation backup buffer. The physical page hit signal represents the addressing hit status of the microprocessor for a specific physical page frame. Step S102: The physical page hit signal is used to directly drive the 16-bit history state shift register associated with the page table entry, so that the storage bits in the history state shift register are physically shifted in one direction to generate a bit map representing the memory access history pattern; wherein, the shift frequency of the history state shift register is controlled by the shift pulse signal generated by the system global clock frequency division circuit, and the shift operation and the address translation operation are completed synchronously at the physical level. Step S103: Perform a bitwise AND operation on the bitmap and the intrinsic write cost constant of the storage medium, which is pre-placed in the configuration register and represents the write loss weight of the storage medium. Use the hardware group counter to count the physical number of high-level bits in the parallel operation result and output the state parameter representing the memory access cluster density. Step S104: Adjust the selection path of the bypass multiplexer according to the state parameter. If the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory level, blocking the write path of the data block to the underlying non-volatile storage medium, thereby eliminating the microprocessor pipeline shadow delay caused by arithmetic scheduling logic by utilizing the physical evolution of hardware bit states.

[0022] Preferably, the historical state shift register and page table entries are physically bound one-to-one; the bitwise AND logic operation includes: performing bitmasking processing on the data bits in the high-level state of the bitmap and the intrinsic cost constant of the medium, accumulating the total number of high-level bits in the logic result bits through the hardware group counting circuit to generate quantized state parameters, so as to map the physical properties of the medium without calling the microprocessor arithmetic logic unit.

[0023] Preferably, the shift pulse signal is used to drive the historical state shift register in all active states to shift to the right; when the conversion backup buffer captures the addressing request and generates a physical page hit signal, the physical page hit signal is fed back to the most significant bit input of the historical state shift register through the logic circuit hard-wired, completing the physical setting of the latest memory access event, so as to simulate the natural decay of memory access heat over time through the one-way overflow of the bit.

[0024] Preferably, if the state parameter is less than the corresponding intrinsic write cost constant of the medium and the addressing request is a write instruction, the hardware comparator generates a low-level trigger signal to the selection control terminal of the bypass multiplexer, physically blocking the write link from the data bus to the cache layer, and forcibly establishing a bypass data path from the microprocessor to the main memory controller or the underlying non-volatile memory, thereby preventing low-frequency write operations from crowding out hot cache lines.

[0025] Preferably, the method further includes step S105, which involves using a hardware group counter to read the high-level state bits in the historical state shift register in parallel and obtaining the memory access density. The calculation formula is: ;in, For memory access density; The first in the historical state shift register The value of the status bit; The preset decay weight coefficient is used to quantify the contribution of memory access behavior in different historical periods to the current scheduling weight.

[0026] Preferably, the method further includes step S106, which involves adjusting the memory access density. A logical comparison is performed with the preset bypass threshold; if the memory access density... If the current data stream is below the bypass threshold, it is determined to be a low-reuse data stream. Based on the determination result, the bypass multiplexer cuts off the write path of the data block to the first-level cache and the second-level cache, and establishes a direct data link between the microprocessor core and the main memory to avoid invalid pollution of the hierarchical cache by streaming data.

[0027] Preferably, the intrinsic write cost constant of the medium includes a weighted constant used to characterize the write latency, write power consumption and write lifetime of the non-volatile storage medium. The intrinsic write cost constant of the medium is stored in a read-only configuration register inside the microprocessor, and the output of the read-only configuration register is physically connected to a bit AND logic gate circuit to ensure that the parameters of the physical characteristics of the medium can participate in the logical arbitration of the hardware gating path in real time.

[0028] Preferably, if the state parameter is within the preset physical relocation range, the cache controller initiates background asynchronous migration logic to migrate the data block from the static random access memory (SRAM) level to the underlying dynamic random access memory (DRAM) level, and synchronously updates the media index bit in the page table entry. This asynchronous migration logic completes the relocation during the bus idle period, ensuring that the system maintains stable memory access timing specifications under high concurrency conditions. The heterogeneous storage media includes a first level composed of static random access memory, a second level composed of dynamic random access memory (DRAM), and a third level composed of non-volatile memory (NDRAM). Each level is interconnected by a bus matrix with independent gating logic. The gating terminal of the bus matrix is ​​directly controlled by the output level of the bypass multiplexer, thereby completing the adaptive routing of the data block between heterogeneous media.

[0029] Preferably, the status parameter includes priority information for different storage levels; based on the priority information, the remaining storage space capacity of each storage level is polled in a round-robin fashion. If the available capacity of a high-priority storage level is lower than a preset water level threshold, the data flow is directed to the next highest priority storage level. This ensures that the heterogeneous storage media maintains stable memory access hit performance and energy efficiency ratio through dynamic feedback adjustment of storage space.

[0030] A memory-based hierarchical data caching intelligent scheduling system includes: The conversion backup buffer module is used to obtain the address hit status and output the physical page hit signal; The history state representation module includes a 16-bit shift unit that corresponds one-to-one with page table entries. It is used to drive the shift unit to generate a unidirectional physical displacement using the physical page hit signal, thereby generating a bitmap that represents the memory access history pattern. The parameter configuration module is used to provide preset intrinsic writing cost constants of the medium; The state quantization evaluation module is connected to the historical state characterization module and the parameter configuration module respectively. It is used to perform bitwise AND logic operations on the bitmap and the intrinsic cost constant of the medium, and output the state parameters characterizing the memory access cluster density by statistically counting the physical number of high-level bits in the operation results. The bypass gating and scheduling module is deployed on the data path of a heterogeneous storage hierarchy that includes static random access memory, dynamic random access memory, and non-volatile memory. It is used to adjust the gating path according to the state parameter. When the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory hierarchy.

[0031] Example 1: In the operation of an integrated circuit containing heterogeneous storage layers including static random access memory, dynamic random access memory, and non-volatile memory, the memory access request stream generated by the processor core exhibits high-frequency fluctuations and non-linear distribution characteristics, and the proportion of write operation requests per unit time exceeds the preset memory scheduling threshold. Due to the physical performance differences between heterogeneous storage media, especially the difference in write latency and erase / write lifetime between the cache layer and the underlying non-volatile storage layer, if a scheduling algorithm involving complex feature weighting or algebraic operations is used on the memory access critical path, the resulting gate flip latency will cause the memory access response time to exceed the instruction wait limit of the processor pipeline, inducing computational pauses.

[0032] The translation-backup buffer inside the memory management unit hardware-binds a 16-bit history state shift register to each active page table entry, using a global clock divider circuit within the integrated circuit to generate a shift pulse signal. This shift pulse signal periodically drives all history state shift registers associated with active page table entries to perform a single right shift operation, simulating the physical decay of data access frequency over time through the natural overflow of hardware data bits. When the translation-backup buffer captures an addressing request from the processor core and outputs a hit level corresponding to a specific physical page frame, this hit level signal is fed back to the most significant bit input of the corresponding history state shift register via logic circuitry. The terminal triggers a 1 operation, ensuring that the address translation action and the capture of memory access history are synchronized at the physical level. The integrated circuit is equipped with a hard-wired gating circuit that is physically connected to the abnormal port of the backup buffer. When the microprocessor core triggers a physical page miss exception, the gating circuit intercepts the abnormal level, forcibly clamps and shuts down the shift pulse signal output from the system global clock divider circuit to the historical state shift register. All active historical state shift registers stop the right shift operation and maintain the existing physical distribution of storage bits until the memory management unit completes the page table roaming and pulls the hit level high again to prevent invalid low-level ticks from overwriting the real memory access history during the roaming cycle.

[0033] The hardware group counting circuit reads the total number of bits in the high-level state from the historical state shift register in parallel and uses this total number as a state parameter. Output to scheduling control logic, where The state parameter characterizing the physical page frame memory access heat; the scheduling control logic retrieves the preset intrinsic media write cost constant from the chip's read-only register. This constant is calibrated based on the physical erase / write limit latency of the target storage medium, where A constant is preset in the register to characterize the write loss cost of the target storage medium; the hardware comparator compares the state parameters in real time. With the intrinsic cost constant of the medium The magnitude relationship; to solve the problem of data structure attribute conflicts of a single constant in different processing nodes, the intrinsic write cost constant of the medium is deployed with a physically isolated dual-channel output architecture in the parameter configuration register. The first output channel penetrates to the mask array of the previous stage, specifically to convert and output the scalar constant into the corresponding 16-bit high-level mask word for consumption by the upstream bitmap bit and logic operations; the second output channel bypasses the previous stage array and directly feeds the original scalar count value of the constant to the reference level comparison terminal of the hardware comparator. This dual-channel physical current splitting mechanism ensures that when the same storage medium parameter participates in the mask truncation of the timing bitmap and the scalar comparison of the physical hit density, its mathematical dimension attribute can adaptively match the hardware interface of the corresponding stage, avoiding type dead loops in logic derivation. When the instruction write enable signal is valid and the status parameter is Less than the intrinsic writing cost constant of the medium At this time, the hardware comparator outputs a low-level strobe signal, which directly drives the bypass multiplexer at the front end of the buffer controller.

[0034] The bypass multiplexer switches the data flow direction based on a low-level strobe signal, physically blocking the write path from the data bus to the static random access memory (SRAM) level during the current clock cycle, establishing a bypass path from the processor core directly to the underlying memory controller. Simultaneously, for data blocks that are normally stored in the high-speed SRAM system without triggering the aforementioned low-level bypass condition, the scheduling logic incorporates a set of preset physical transfer intervals jointly defined by upper and lower limit address comparators. The tolerance boundary reference value of this interval is directly stripped from the engineering experience-based inflection point where the energy efficiency ratio experiences cross-attenuation during heterogeneous media performance calibration, and written into the configuration word. When the bus control center detects that the status parameter corresponding to the resident data block naturally drops over time, falling below the active access threshold but not yet reaching the direct discard limit, it precisely falls into the physical transfer interval. When the data is within the specified interval, the aforementioned background asynchronous migration logic is immediately activated. This logic acquires system idle control through the direct memory access controller and smoothly migrates and unloads data blocks with warm data characteristics to the lower-level dynamic random access memory during idle period periods such as the microprocessor pipeline's launch bubble. This scheduling mechanism, based on the physical evolution of hardware bits, avoids performing arithmetic and logical operations in the memory access path. This allows the system to intercept dirty data with low memory access activity and high write cost outside the cache level without generating logical delays, reducing the invalid erase and write frequency of non-volatile storage media. While maintaining high-frequency instruction propagation, the integrated circuit allocates storage resources through hardware-level path selection, making the read and write power consumption distribution of the memory system more balanced.

[0035] Example 2: On a smart chip verification platform integrating static random access memory, dynamic random access memory, and phase-change memory, a verification experiment was established to evaluate the real-time performance of cache scheduling and the effectiveness of media lifetime protection, targeting the spatiotemporal locality fluctuation mechanism exhibited by the memory access instruction stream. This verification platform was built based on a cycle-accurate instruction set simulator, with a time resolution set to 0.1 ns and a clock frequency set to 2.5 GHz. To simulate signal disturbances in real industrial conditions, random burst memory access noise, accounting for 15% of the total sample size, was injected into the address request sequence. This noise generated irregular... Regular address jumps were used to verify the stability of physically hardwired logic under fluctuating load conditions. In the experiment, the bit width of the historical state shift register was set to 16 bits. This setting was designed to balance the historical record depth with the area overhead of the integrated circuit logic array. When the bit width was less than 8 bits, the system could not capture the memory access characteristics of long-cycle cycles, causing the prediction accuracy to drop below 70%. When the bit width was greater than 32 bits, the power consumption of logic gate toggling increased by more than 45%, and no longer produced a significant hit rate improvement. The frequency of the shift pulse signal generated by the system's global clock divider circuit was also considered. It is set to 100MHz, and this frequency is calibrated based on the average reuse distance of the target workload.

[0036] The present invention's sample adopts a hardware architecture where the shift register is directly driven by the hit level of the conversion backup buffer, while the comparison sample uses a Least Recently Used algorithm running on the processor core. When the original input memory access stream enters the address translation stage, the hardware crowd counting circuit captures the physical bit distribution of the historical state shift register in real time. Within an observation period of 50,000 consecutive memory access requests, for data blocks with low memory access clustering, the state parameter output by the hardware crowd counting circuit... It remains in the low range of 2 to 4; due to the media intrinsic write cost constant preset in the register. Set to 5, the hardware comparator outputs a low-level signal to drive the bypass multiplexer, where... A state parameter characterizing the physical page frame access heat; This is a constant preset in the register to characterize the write loss cost of the target storage medium.

[0037] In state parameters Below the intrinsic writing cost constant of the medium Under normal operating conditions, the bypass multiplexer directly directs write requests to the underlying memory controller; the memory access response latency of the present invention's sample is stable at around 11.2ns, while the comparison sample incurs an additional computational overhead of over 25ns, with the total response latency climbing to 38.6ns; as memory access activity increases, when the state parameters... Crossing the performance inflection point When the value is greater than or equal to 6, the data enters the static random access memory (SRAM) level, and the cache hit rate increases from 62.4% to 88.5%; when When the value increases to above 15, the performance improvement curve tends to flatten out, indicating that the throughput capacity of the storage layer is approaching saturation, verifying the adaptive adjustment characteristics of this solution under different heat gradients. The experimental results show that, through the mechanism of direct mapping of the scheduling path by the hardware bitmap state, the processor pipeline maintains high clock frequency while suppressing the accumulation of shadow latency. The number of invalid erase / write operations on the underlying storage medium decreased by 32.8% in the 24-hour continuous operation test, proving the synergistic effect of hardware-level feature extraction in reducing access latency and extending media lifespan. This closed-loop feedback mechanism based on the laws of physical evolution makes the energy efficiency ratio distribution of the heterogeneous storage system tend to the optimal state.

[0038] Example 3: This example combines Figures 1 to 2 This paper describes a hierarchical data caching intelligent scheduling method and system for memory, such as... Figure 1 As shown, in step S101, the physical page hit signal output by the translation backup buffer is obtained. This physical page hit signal is used to characterize the addressing hit status of the microprocessor for a specific physical page frame. In step S102, the physical page hit signal is used to directly drive the 16-bit history state shift register associated with the page table entry. This causes the stored bits in the history state shift register to undergo unidirectional physical displacement under the control of the shift pulse signal generated by the system global clock frequency division circuit, thereby generating a bitmap characterizing the memory access history. Then, in step S103, this bitmap is compared with... The intrinsic write cost constant of the storage medium, which is pre-set in the configuration register and represents the write loss weight of the storage medium, is subjected to bitwise AND logic operations. The physical number of high-level bits in the operation result is counted in parallel using a hardware group counter, and a state parameter representing the memory access cluster density is output. Finally, step S104 is executed to adjust the selection path of the bypass multiplexer according to the state parameter. If the state parameter is lower than the intrinsic write cost constant of the storage medium, the data block pointed to by the write instruction is intercepted in the static random access memory level, blocking the write path of the data block to the underlying non-volatile storage medium.

[0039] like Figure 2As shown, the memory management unit physical subsystem is connected to the microprocessor core via a physical data bus. This physical subsystem integrates a translational backstop buffer, parameter configuration registers, a historical state shift register group, and a hardware group counter. After acquiring the address hit status, the translational backstop buffer outputs a physical page hit signal to the historical state shift register group, driving the register group to generate a bitmap data stream and transmit it to the hardware group counter. The hardware group counter outputs the quantized state parameters to the scheduling control hardware logic plane below. This scheduling control hardware logic plane includes a hardware comparator and a bypass multiplexer. The hardware comparator acquires the state parameters and performs logical judgment with a preset reference value, outputting a gating trigger signal to the bypass multiplexer. The bypass multiplexer performs path gating control on the heterogeneous storage physical hierarchy based on this signal. The heterogeneous storage physical hierarchy includes static random access memory, dynamic random access memory, and non-volatile memory interconnected by a bus matrix.

[0040] Example 4: In heterogeneous integrated circuits operating with massively parallel instruction streams, the integrated circuit includes a static random access memory (SRAM) level, a dynamic random access memory (DRAM) level, and a non-volatile memory (NRAM) level. Because the physical erase / write lifetime of NRAM is limited and its write latency is higher than that of SRAM, the system needs to complete the write path segmentation within a nanosecond-level memory access window to balance the cache hit rate gains with the wear and tear costs of the underlying media. This requires addressing the intrinsic write cost constant of the media. The settings employ a quantization calibration procedure based on the physical loss characteristics of the storage medium; this procedure extracts the baseline write latency of the non-volatile storage medium. Average read latency of static random access memory And according to the maximum rated erase / write life of the storage cell. Determine the conversion weights; intrinsic cost constant of the medium. The calculation formula is as follows: ,in, Write the intrinsic cost constant for the medium; This is the bus congestion adjustment factor, with a value ranging from 0.5 to 1.2; The duration of the write pulse for non-volatile storage media. Addressing latency of the static random access memory layer. To determine the rated erase / write lifetime of the storage medium, in the actual chip hardware signal processing path, considering that the original calculation result output by the above logarithmic and ratio product formula may span multiple orders of magnitude, in order to ensure that it can be physically aligned with the feature space of the finite-width shift register, the calculation engine implements a fixed hardware-level dimensionality reduction truncation before performing the rounding operation. Specifically, the original product output by the product unit is imported into a hard-wired shift array, forcing a division operation with a logical shift of eight bits to the right to achieve a constant scaling of division by 256. Based on this, when the parameters are under the following extreme load boundary conditions, the original product calculation value is approximately on the order of 1280. After this fixed dimensionality reduction mapping of division by 256 and rounding, the output is finally locked and outputs a limited calibration value of 5, thereby converging the macroscopic lifetime boundary specification to the characterization range of the microscopic hardware.

[0041] In a specific application scenario, when the non-volatile storage medium is a phase-change memory and its It is 150ns. It is 1ns. for At this time, the intrinsic writing cost constant of the medium is calculated using the above formula. The calibration value is 5; the hardware group counting circuit adopts an adder tree architecture composed of multi-stage full adders, the input of which is connected in parallel to the physical storage unit of the 16-bit history state shift register; it implements the attenuation weight coefficient without calling the microprocessor arithmetic logic unit. Memory access density quantization: the output of the 16-bit historical state shift register adopts an asymmetric fan-out topology routing. The hard-wired port representing the most significant bit of recent high-frequency memory access is split to multiple parallel input nodes in the adder tree architecture, and the number of physical terminals is multiplied to directly represent the equivalent state bits. Integer weighted product, state parameters are implemented through pure hardware cascading. In the weighted accumulation implementation, this asymmetric fan-out topology utilizes the spatial branch density of the metal wiring to solidify the corresponding attenuation weight coefficients. The most significant bit of the 16-bit historical state shift register, i.e., the physical pin carrying the latest memory access imprint, is directly split into multiple parallel sub-branches during copper routing, which are respectively connected to the inputs of multiple redundant full adders at the same level of the adder tree architecture. For example, if the weight coefficient corresponding to this node is set to a preset value of 4, its single physical pin will be split into four parallel inputs through the gold wire, so that the same high-level state is read in parallel and independently accumulated four times within one clock pulse. Similarly, the least significant bits of the shift register decrease the spatial branch fan-out number of their physical connections according to the time decay characteristics. The arithmetic multiplier call is abandoned, and the solidified weight decay curve is constructed solely by the geometric difference in the number of connected terminals. Within a single clock cycle after the output of the conversion backup buffer hits the level, the adder tree architecture counts the total number of bits in the high-level state through combinational logic operations and uses the result as a state parameter. The value is transmitted to the input of the hardware comparator; at the same time, the scheduling control logic transmits the calibration value 5 preset in the read-only register to the other input of the hardware comparator.

[0042] When the write enable signal issued by the microprocessor is synchronously valid with the hit signal of the translation backup buffer, the hardware comparator triggers a magnitude determination; if the status parameter corresponding to the current physical page frame... Since the value is 3, which is lower than the calibration value of 5, the hardware comparator immediately outputs a low-level drive signal to the selection terminal of the bypass multiplexer. After receiving the signal, the bypass multiplexer physically shuts down the write path from the data bus to the static random access memory within the current storage cycle, establishing a direct path for data flow to the underlying storage controller. This collaborative mechanism based on the physical evolution law of hardware bits and the pre-calibration of media characteristics enables the system to intercept low-hot dirty data without occupying the operation cycle of the arithmetic logic unit. This hardware-level scheduling and gating mechanism avoids the physical crowding of cache lines by low-frequency memory access data. While maintaining the instruction advance frequency of the computing node, it reduces the frequency of local hot spot write operations of non-volatile storage media by 28.5%, achieving the stability of heterogeneous storage architecture under real dynamic load.

[0043] Example 5: In the initial operating condition of the integrated circuit self-testing and booting to the firmware, the control status register in the memory management unit extracts the characteristic delay parameters of the target medium from the hardware description word based on the physical identifier of the underlying storage medium. Repair and write life benchmark Simultaneously, the bus monitoring circuit collects the idle background noise level of the current storage path to determine the initial congestion adjustment coefficient. The decision circuit substitutes the extracted feature parameters into the scheduling calculation logic to calculate the intrinsic write cost constant of the medium that matches the physical characteristics of the hardware. And write the intrinsic cost constant of the medium. The data is stored in a dedicated mask register inside the conversion backup buffer. Based on this, the clock divider circuit calculates the sampling window width according to the preset task sampling window width. With target main frequency The frequency of the shift pulse signal is adjusted by stepping through logic gates. It is locked at an order of magnitude that causes the historical state shift register to cover memory access cycles.

[0044] When an integrated circuit faces a memory access locality offset due to changes in its operating task attributes, the hardware performance counter acquires the instantaneous throughput rate of the data bus in real time and converts it into a normalized congestion offset. The transient hardware noise induced by periodic preemption of the direct memory access module and external bus master devices is eliminated. The hardware performance counter internally incorporates first-order infinite impulse response logic. The hardware shifter performs displacement reduction on the steady-state throughput rate of the previous cycle to obtain the historical attenuation amount. The difference operation between this value and the original throughput rate of the current clock cycle is performed by a full adder to filter out high-frequency fluctuation noise that deviates from the nominal bus bandwidth extreme value. The low-frequency steady-state baseline value is output as the conversion congestion degree offset. Input data, scheduling control logic is based on congestion offset Adjusting the feedback adjustment pin of the frequency divider circuit finely tunes the trigger period of the shift pulse signal without interrupting the address translation operation, ensuring that the bit movement speed in the 16-bit historical state shift register remains linearly synchronized with the instruction progression speed of the current task; the hardware comparator continuously monitors the status parameters. The polarity is reversed when the bus congestion offset is... When the preset dynamic stability threshold is exceeded and the write request hit rate drops to the saturation region boundary, the system updates the intrinsic write cost constant of the medium. The working position is maintained by the bypass multiplexer based on the refreshed comparison results to maintain the data path distribution state between heterogeneous storage layers.

[0045] Example 6: In the offline parameter optimization procedure of heterogeneous storage microarchitecture, the control logic is based on the nominal clock frequency of the processor core. In addition to the average memory access reuse span of the target workload, the division ratio parameter of the system global clock divider circuit is determined by a traversal search method. To adapt it to the memory access characteristics of specific industry workloads, this calibration procedure utilizes the performance monitoring unit inside the integrated circuit to statistically analyze the address access step size distribution within a preset cold start cycle, and maps the memory access feature vector to a frequency division lookup table stored in a read-only register. It then calculates and determines the shift pulse signal frequency that allows the 16-bit historical state shift register to cover the memory access lifetime. Frequency division ratio parameter The calculation formula is as follows: ,in, The frequency division ratio parameter, For processor core clock speed, The frequency of the shift pulse signal. The locality of access factor is used for memory access compensation, with a value ranging from 0.8 to 1.1. This hardware feedback-based calibration procedure ensures that the bitmap state generated by the 16-bit historical state shift register maintains the stability of physical latency at different operating frequencies.

[0046] When a compute node faces a memory access pattern shift caused by task load switching, the hardware group counting circuit adopts a three-level carry-storage adder tree architecture. During the write-back phase of the address translation pipeline, it synchronously reads the physical bit statistics of the 16-bit historical state shift register and sets the obtained state parameters... The data is directly latched at the input of the hardware comparator; to suppress scheduling bias caused by outdated historical data, the system deploys physical calibration logic based on XOR gates within the memory management unit. This logic is applied when a bus congestion offset is detected. Exceeding the dynamic stability threshold defined by the hardware hardwired and the state parameter When the system is in the saturation range for 10 consecutive cycles, the calibration logic triggers a forced clear of the 16-bit historical state shift register. The system global clock frequency divider circuit then regenerates a shift pulse sequence adapted to the current task characteristics. This fault-tolerant compensation mechanism based on the physical state of the circuit maintains the reliability of the cache scheduling path in non-ideal industrial environments by utilizing the evolution law of physical bits without changing the static random access memory write logic.

[0047] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hierarchical data caching intelligent scheduling method for memory, characterized in that, Includes the following steps: Step S101: Obtain the physical page hit signal output by the conversion backup buffer. The physical page hit signal represents the addressing hit status of the microprocessor for a specific physical page frame. Step S102: The physical page hit signal is used to directly drive the 16-bit history state shift register associated with the page table entry, so that the storage bits in the history state shift register are physically shifted in one direction to generate a bit map representing the memory access history pattern; wherein, the shift frequency of the history state shift register is controlled by the shift pulse signal generated by the system global clock frequency division circuit, and the shift operation and the address translation operation are completed synchronously at the physical level. Step S103: Perform bitwise AND logic operation between the bitmap and the intrinsic write cost constant of the storage medium, which is preset in the configuration register and represents the write loss weight of the storage medium. Use the hardware group counter to count the physical number of high-level bits in the parallel operation result and output the state parameter representing the memory access cluster density. Step S104: Adjust the selection path of the bypass multiplexer according to the state parameter. If the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory level, blocking the write path of the data block to the underlying non-volatile storage medium. In this way, the physical evolution of the hardware bit state is used to eliminate the microprocessor pipeline shadow delay caused by the arithmetic scheduling logic.

2. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, The historical state shift register is physically bound to each page table entry in a one-to-one correspondence. Bitwise AND logic operations include: performing bitmasking by combining the high-level data bits in the bitmap with the intrinsic cost constant of the medium; accumulating the total number of high-level bits in the logic result bits through a hardware group counting circuit to generate quantized state parameters, so as to map the physical properties of the medium without calling the microprocessor arithmetic logic unit.

3. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, The shift pulse signal drives the historical state shift register in all active states to shift to the right. When the conversion backup buffer captures the address request and generates a physical page hit signal, the physical page hit signal is fed back to the most significant bit input of the historical state shift register through the logic circuit hardwire, completing the physical setting of the latest memory access event, so as to simulate the natural decay of memory access heat over time through the one-way overflow of the bit.

4. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, If the state parameter is less than the corresponding intrinsic write cost constant of the medium and the addressing request is a write instruction, the hardware comparator generates a low-level trigger signal to the selection control terminal of the bypass multiplexer, physically blocking the write link from the data bus to the cache layer, and forcibly establishing a bypass data path from the microprocessor to the main memory controller or the underlying non-volatile memory, thereby preventing low-frequency write operations from crowding out hot cache lines.

5. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, It also includes step S105: using a hardware group counter to read the high-level state bits in the historical state shift register in parallel and obtain the memory access density. The calculation formula is: ;in, For memory access density; The first in the historical state shift register The value of the status bit; The preset decay weight coefficient is used to quantify the contribution of memory access behavior in different historical periods to the current scheduling weight.

6. The intelligent scheduling method for hierarchical data caching in memory according to claim 5, characterized in that, It also includes step S106, which sets the memory access density. A logical comparison is performed with the preset bypass threshold; if the memory access density... If the current data stream is below the bypass threshold, it is determined to be a low-reuse data stream. bypass The multiplexer cuts off the write path of the data block to the first-level cache and the second-level cache based on the judgment result, and establishes a direct data link between the microprocessor core and the main memory to avoid the invalid pollution of the hierarchical cache by streaming data.

7. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, The intrinsic write cost constant of the medium contains weighted constants used to characterize the write latency, write power consumption and write lifetime of the non-volatile storage medium. The intrinsic write cost constant of the medium is stored in the read-only configuration register inside the microprocessor, and the output of the read-only configuration register is physically connected to the bit AND logic gate circuit to ensure that the parameters of the physical characteristics of the medium can participate in the logic arbitration of the hardware gating path in real time.

8. The intelligent scheduling method for hierarchical data caching in memory according to claim 1, characterized in that, If the state parameter is within the preset physical relocation range, the cache controller initiates background asynchronous migration logic to migrate the data block from the static random access memory (SRAM) level to the underlying dynamic random access memory (DRAM) level, and synchronously updates the media index bit in the page table entry. This asynchronous migration logic completes the relocation during the bus idle period, ensuring that the system maintains stable memory access timing specifications under high concurrency conditions. The heterogeneous storage media includes a first level composed of static random access memory, a second level composed of dynamic random access memory (DRAM), and a third level composed of non-volatile memory (NDRAM). Each level is interconnected by a bus matrix with independent gating logic. The gating terminal of the bus matrix is ​​directly controlled by the output level of the bypass multiplexer, thereby completing the adaptive routing of data blocks between heterogeneous media.

9. The intelligent scheduling method for hierarchical data caching in memory according to claim 8, characterized in that, The status parameters include priority information for different storage tiers. Based on this priority information, the remaining storage space capacity of each storage tier is polled. If the available capacity of a high-priority storage tier is lower than a preset threshold, the data flow is directed to the next highest priority storage tier. Through dynamic feedback adjustment of storage space, the heterogeneous storage media maintain stable memory hit performance and energy efficiency ratio.

10. A memory hierarchical data cache intelligent scheduling system, used to implement the memory hierarchical data cache intelligent scheduling method according to claim 1, characterized in that, include: The conversion backup buffer module is used to obtain the address hit status and output the physical page hit signal; The history state representation module includes a 16-bit shift unit that corresponds one-to-one with page table entries. It is used to drive the shift unit to generate a unidirectional physical displacement using the physical page hit signal, thereby generating a bitmap that represents the memory access history pattern. The parameter configuration module is used to provide preset intrinsic writing cost constants of the medium; The state quantization evaluation module is connected to the historical state characterization module and the parameter configuration module respectively. It is used to perform bitwise AND logic operations on the bitmap and the intrinsic cost constant of the medium, and output the state parameters characterizing the memory access cluster density by statistically counting the physical number of high-level bits in the operation results. The bypass gating and scheduling module is deployed on the data path of a heterogeneous storage hierarchy that includes static random access memory, dynamic random access memory, and non-volatile memory. It is used to adjust the gating path according to the state parameter. When the state parameter is lower than the intrinsic write cost constant of the medium, the data block pointed to by the write instruction is intercepted in the static random access memory hierarchy.

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