Command sending method and apparatus, memory controller, and storage system

Abstract

This application discloses a command sending method, apparatus, memory controller, and storage system. In this method, the memory controller stores the same memory operation on multiple ranks of the memory in a single entry in the cache, eliminating the need to store the same memory operation on multiple ranks in different entries. This reduces the number of entries in the cache, lowers the usage of cache storage resources, and reduces the demand for cache storage capacity.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a command sending method, apparatus, memory controller, and storage system. Background Technology

[0002] The storage system includes a memory controller and a memory. The memory controller has multiple preset operating frequency levels, each of which is a frequency point. The memory controller can control the memory to switch between multiple frequency points.

[0003] Each frequency point has its own independent configuration parameters, and each configuration parameter can be configured by performing memory operations on the storage rank in the memory. Taking memory operations as an example of configuration operations, during the initialization phase, the memory controller stores each configuration parameter of each frequency point in the cache as entries. Each entry stores the configuration operation used to configure one configuration parameter. Before frequency switching, the memory controller reads the entries corresponding to the target frequency point from the cache and sends the configuration operations stored in each read entry to the memory to configure the corresponding configuration parameter.

[0004] However, as memory architectures become increasingly complex, the number of configuration parameters for each frequency point increases significantly, and the number of entries corresponding to each frequency point also rises, thereby increasing the occupation of storage resources in the cache and the demand for cache storage capacity. Summary of the Invention

[0005] This application provides a command sending method, apparatus, memory controller, and storage system, which can reduce the occupation of storage resources in the memory controller's cache and the demand for cache storage capacity. The technical solution of this application is as follows: According to a first aspect of the embodiments of this application, a command sending method is provided, applied to a memory controller, the method comprising: When multiple first entries in the cache meet the read condition, the multiple first entries in the cache are read. The first entries include description information of memory operations and enable flags corresponding to multiple storage ranks in the memory. The enable flags indicate that the memory operation is performed on the corresponding storage rank. For each first entry read, based on the enable flag and description information in the first entry, multiple commands are sent to the memory, the commands instructing the memory operation to be performed on the memory rank.

[0006] Optionally, the plurality of storage ranks correspond to the same channel between the memory controller and the memory.

[0007] Optionally, the channel includes multiple pseudo-channels, and the multiple storage ranks include the storage rank corresponding to each pseudo-channel among the multiple pseudo-channels.

[0008] Optionally, the channel corresponds to multiple pairs of parity storage ranks in the memory, the multiple storage ranks including at least two pairs of even storage ranks or odd storage ranks, and each pair of parity storage ranks includes one odd storage rank and one even storage rank.

[0009] Optionally, the plurality of storage ranks includes each storage rank corresponding to the channel.

[0010] Optionally, the first entry further includes a sending method identifier, which indicates the sending method of the plurality of commands; For each first entry read, based on the enable identifier and description information in the first entry, multiple commands are sent to the memory, including: For each first entry read, the plurality of commands are generated based on the enable identifier and the description information in the first entry; The plurality of commands are sent to the memory according to the sending method indicated by the sending method identifier.

[0011] Optionally, the plurality of storage ranks includes a first storage rank and a second storage rank, and the plurality of commands includes a first command and a second command, wherein the first command instructs the memory operation to be performed on the first storage rank, and the second command instructs the memory operation to be performed on the second storage rank; The transmission method is a serial transmission method; Sending the plurality of commands to the memory according to the sending method indicated by the sending method identifier includes: First, one of the multiple commands is sent to the memory. After a preset time period, the other of the multiple commands is sent to the memory.

[0012] Optionally, the memory operation is a configuration operation of the registers in the memory rank.

[0013] Optionally, the transmission method is a parallel transmission method; Sending the plurality of commands to the memory according to the sending method indicated by the sending method identifier includes: The multiple commands are sent to the memory in parallel.

[0014] Optionally, the memory operation is an operation on a memory cell in the memory rank.

[0015] Optionally, the first entry further includes an enable flag corresponding to the target scenario, the enable flag indicating that the memory operation corresponds to the target scenario; The step of reading the multiple first entries in the cache when the read condition is met includes: In response to the activation of the target scenario, the plurality of first entries in the cache are read.

[0016] According to a second aspect of the embodiments of this application, a command sending apparatus is provided, applied to a memory controller, the apparatus comprising: A read module is used to read the multiple first entries in the cache when the read condition is met. The first entries include description information of memory operations and enable flags corresponding to multiple storage ranks in the memory. The enable flags indicate that the memory operation is performed on the corresponding storage rank. The sending module is configured to send multiple commands to the memory based on the enable identifier and the description information in the first entry for each first entry read. The commands instruct the memory operation to be performed on the memory rank.

[0017] According to a third aspect of the embodiments of this application, a memory controller is provided, the memory controller including a cache and a control chip, the cache being used to cache a first entry, the first entry indicating the same memory operation to be performed on multiple memory ranks in the memory, and the control chip being used to execute the command sending method provided by the first aspect or any possible implementation of the first aspect.

[0018] According to a fourth aspect of the embodiments of this application, a storage system is provided, the storage system including a memory controller and a memory, the memory controller being configured to control the memory, and the memory controller being configured to execute the command sending method provided in the first aspect or any possible implementation thereof.

[0019] According to a fifth aspect of the embodiments of this application, a computer-readable storage medium is provided, which, when at least one instruction in the computer-readable storage medium is executed by a processor in a memory controller, enables the memory controller to perform the command sending method provided in the first aspect or any possible implementation thereof.

[0020] According to a sixth aspect of the embodiments of this application, a computer program product is provided, including one or more instructions, which can be executed by a processor in a memory controller, such that the memory controller can execute the command sending method provided in the first aspect or any possible implementation thereof.

[0021] In the command method provided in this application, the memory controller reduces the number of entries in the cache by storing the same memory operation on multiple Ranks of the memory in one entry in the cache, instead of storing the same memory operation on multiple Ranks in different entries, thereby reducing the occupation of storage resources in the cache and the demand for cache storage capacity.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0024] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an entry provided in an embodiment of this application; Figure 3 This is a flowchart of a command sending method provided in an embodiment of this application; Figure 4 This is a flowchart of another command sending method provided in an embodiment of this application; Figure 5 This is the structure of a command sending device provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0026] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0028] In response, it is used to indicate the conditions or states on which the operation performed depends. When the conditions or states on which it depends are met, one or more operations performed can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0029] In some embodiments, the meaning of A and / or B includes three cases: A and B, and A and B.

[0030] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application, such as... Figure 1 As shown, the storage system includes a memory controller 100 and a memory 200, wherein the memory 200 has at least one memory, and the memory controller 100 has at least one channel 11, each channel 11 being connected to at least one memory 200. Channel 11 can also be called a memory channel or storage channel. Channel 11 can be a Double Data Rate (DDR) bus, which includes a command bus and a data bus. Optionally, the DDR bus also includes an address bus, or the address bus and command bus are the same bus. Of course, channel 11 can also be other types of buses besides the DDR bus; however, this embodiment does not limit the type of channel 11.

[0031] Figure 1 This example illustrates a memory controller 100 having one channel 11 connected to one memory 200. In some embodiments, the memory controller 100 may have multiple channels 11, and each channel 11 may be connected to one or more memories 200. Here, this application embodiment does not limit the number of channels 11 of the memory controller 100 or the number of memories 200 connected to each channel 11.

[0032] Memory 200 is a storage device used for storing data. Memory 200 includes, but is not limited to, Dual In-line Memory Modules (DIMMs) and Multiplexed Registered Dual In-line Memory Modules (MRDIMMs). MRDIMMs are Dual In-line Memory Modules (DIMMs) with a Registered Dual In-line Memory Module (RDIMM) architecture, incorporating a Multiplexed Registering Clock Driver (MRCD) and a Multiplexed Data Buffer (MDB). RDIMMs are DDR memory modules with a Registering Clock Driver (RCD). A DIMM includes multiple Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) chips, where DDR SDRAM is the memory chip within the DIMM.

[0033] The memory 200 includes multiple memory ranks, also known as memory columns. Each rank includes multiple memory chips, which are memory chips used to store data. Memory chips include, but are not limited to, DDR SDRAM. All chips within the same rank share the same control signals, such as being controlled by the same chip select signal, and are simultaneously selected to work collaboratively. Each memory chip includes control circuitry and a memory array. The control circuitry is used to perform data read and write operations on the memory array. The control circuitry includes multiple registers used for configuring the memory 200. The memory array includes multiple memory cells arranged in an array, and each memory cell is used to store data.

[0034] In some embodiments, the chip select signal sequence can be used to perform parity encoding on the numbers of multiple Ranks in the memory 200, with odd-numbered Ranks referred to as odd Ranks and even-numbered Ranks referred to as even Ranks. For example, the memory 200 includes 4 Ranks, which, after parity encoding, are Rank0 to Rank3, where Rank1 and Rank3 are odd Ranks, and Rank0 and Rank2 are even Ranks. The memory 200 configures the multiple Ranks in the memory 200 into at least one pair of parity storage ranks (i.e., parity-even Ranks), with each pair consisting of one odd Rank and one even Rank. For example, Rank0 and Rank1 are a pair of parity-even Ranks, and Rank2 and Rank3 are a pair of parity-even Ranks.

[0035] A memory 200 is connected to a memory controller 100 via a channel 11. The same channel 11 of the memory controller 100 can be connected to at least one memory 200. The memory controller 100 is used to control the various memories 200 connected via the channel 11.

[0036] Channel 11 between memory 200 and memory controller 100 corresponds to multiple ranks in memory 200, and at least one memory 200 can be connected to the same channel 11. When at least one memory 200 is connected to the same channel 11, the channel 11 corresponds to each rank in that at least one memory 200, for example, the channel 11 corresponds to multiple pairs of odd and even ranks in memory 200. Each rank corresponding to the same channel 11 is called a rank within that channel 11. All ranks within the same channel 11 share the address / command bus in channel 11 and rely on independent chip select signals to distinguish addressing; all memory chips within each rank share a set of chip select signals and synchronously receive commands issued by memory controller 100 through channel 11. That is, memory controller 100 can access each rank within channel 11 through channel 11.

[0037] In some embodiments, channel 11 includes multiple pseudo-channels (PS), each corresponding to at least one Rank in the memory. Taking the memory as an MRDIMM as an example, in Mux Mode, the MRCD in the MRDIMM is connected to channel 11. The MRCD divides channel 11 into two pseudo-channels (PS), namely PS0 and PS1. Assuming that the MRDIMM has four Ranks, namely Rank0 to Rank3, PS0 corresponds to Rank0 and Rank1, and PS1 corresponds to Rank2 and Rank3. Each Rank corresponding to PS0 and PS1 corresponds to channel 11. The MRDIMM also supports Rank Mode, in which the MRDIMM does not divide channel 11 into multiple PSs.

[0038] In some embodiments, the Ranks within the same channel 11 support time-division serial access. Within one clock cycle, the memory controller 100 can only access one Rank within the same channel 11 and can only read and write data to that Rank. In this case, the memory 200 can be an MRDIMM, RDIMM, etc. Taking the memory 200 as an MRDIMM as an example, in multiplexing mode, the memory controller 100 serially accesses memory cells in multiple Ranks corresponding to the same PS. Taking accessing PS0 as an example, it first accesses the memory cells in Rank0 corresponding to PS0, and then accesses the memory cells in Rank1 corresponding to PS0. In multiplexing mode, the memory controller 100 can also serially access registers in Ranks corresponding to different PSs. For example, it first accesses the registers in Rank0 corresponding to PS0, and then accesses the registers in Rank2 corresponding to PS1. In Rank mode, the memory controller 100 can serially access memory cells in different Ranks. For example, it first accesses the memory cells in Rank0, and then accesses the memory cells in Rank1. In Rank mode, the memory controller 100 can access registers within different pairs of odd / even ranks serially. For example, the memory controller 100 can first access registers within the even rank of one pair of odd / even ranks, and then access registers within the even rank of another pair of odd / even ranks. Taking the memory 200 as an RDIMM as another example, the memory 200 cannot simultaneously access memory cells within different ranks of the RDIMM; it can only access memory cells within the same rank of the RDIMM at a time. That is, the memory 200 can access memory cells within different ranks of the RDIMM serially, but cannot access them in parallel. The memory 200 can access registers within all ranks of the RDIMM simultaneously, or it can access registers within a single rank individually. In other words, the memory 200 can access registers within different ranks of the RDIMM in parallel, or it can access them serially.

[0039] In some embodiments, each Rank within the same channel 11 supports time-division serial access. Within one clock cycle, the memory controller 100 can access multiple Ranks in the same channel 11 in parallel, and can perform data read and write operations on multiple Ranks in the same channel 11 in parallel. For example, when the memory 200 is an MRDIMM, the MRDIMM employs multiplexing technology (MRCD and MDB combination), allowing parallel reading and writing of data from two Ranks within one clock cycle, converting the double data rate of DDR to a quadruple data rate, thus doubling the bandwidth. For instance, in multiplexing mode, channel 11 includes PS0 and PS1. The memory controller 100 treats a Rank corresponding to PS0 and a Rank corresponding to PS1 as the same logical Rank, and accesses this logical Rank through channel 11. For example, within one clock cycle, the memory controller 100 can access (e.g., read and write) memory cells in two Ranks (including Rank1 corresponding to PS0 and Rank2 corresponding to PS1) in parallel through channel 11. Alternatively, in MRDIMM multiplexing mode, the memory controller 100 can also access registers in multiple ranks corresponding to the same PS in parallel, for example, accessing registers in Rank0 and Rank1 corresponding to PS0 in parallel. In RDIMM Rank mode, the memory controller 100 can access registers in two ranks within the same pair of odd and even ranks in parallel, for example, accessing registers in Rank0 and Rank1 in parallel.

[0040] Optionally, the memory controller 100 can be integrated into a host, which can be a server or a terminal, including but not limited to mobile phones, personal computers, laptops, desktop computers, wearable devices, vehicles, IoT devices, or smart home devices.

[0041] The memory controller 100 is connected to the central processing unit (CPU) in the host computer. The memory controller 100 manages the data stored in the memory 200 and is responsible for data scheduling between the memory 200 and the CPU. The memory controller 100 can issue memory operations to the memory 200, and the memory 200 is used to execute the issued memory operations. The memory controller 100 can implement memory operations by issuing commands instructing the memory 200 to perform memory operations. In some embodiments, the memory controller 100 can be referred to as a memory controller, the memory 200 can be referred to as memory, and the memory operation can also be referred to as a memory operation.

[0042] Memory operations refer to the control operations issued by the memory controller 100 to the memory 200. Memory operations include, but are not limited to, configuration operations, data read operations, data write operations, data erase operations, and configuration operations. Optionally, the memory controller 100 can also be used to manage various functions related to data stored or to be stored in the memory 200, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. The memory controller 100 can also perform any other suitable functions, such as formatting the memory.

[0043] like Figure 1 As shown, the memory controller 100 includes a cache 12 and a control chip 13, with the cache 12 connected to the control chip 13. The cache 12 includes, but is not limited to, Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). This embodiment does not limit the type of cache 12. The control chip 13 can be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), and Application Specific Integrated Circuit (ASIC). This embodiment does not limit the hardware implementation of the control chip.

[0044] Cache 12 is used to store at least one memory operation. In some embodiments, cache 12 may also be referred to as a memory operation (MOP) array.

[0045] The memory operations stored in cache 12 include configuration operations on registers in Rank. These configuration operations include at least one of Mode Register Write (MRW), Mode Register Read (MRR), and Multi-Purpose (MP) operations. MRW operations are used to configure parameters in registers, and the parameters configured in registers can be referred to as configuration parameters. MRR operations are used to read configuration parameters from registers. MP operations include, but are not limited to, interface initialization, bus training, electrical calibration, module configuration, and fault repair operations.

[0046] Optionally, the memory operations stored in cache 12 may also include operations on storage units in Rank, such as read / write operations, enable operations, or disable operations on storage units.

[0047] The operating scenarios of memory 200 include, but are not limited to, frequency switching scenarios, power mode switching scenarios, low-power operation scenarios, high-power operation scenarios, and data read / write scenarios. Frequency switching scenarios refer to controlling the memory 200 to switch between multiple frequency points. Memory 200 supports operation in multiple power modes. Power mode switching scenarios refer to controlling the memory 200 to switch between multiple power modes, such as switching the power mode of memory 200 from a high-power mode to a low-power mode, such as a light sleep mode. Low-power operation scenarios refer to scenarios where memory 200 operates in low-power mode. High-power operation scenarios refer to scenarios where memory 200 operates in high-power mode. Data read / write scenarios refer to scenarios where data is read from or written to memory 200.

[0048] In different working scenarios, the memory controller 100 requires the memory 200 to perform different memory operations. For example, in the frequency switching scenario, a large number of configuration operations need to be performed on the registers in Rank. In the power mode switching scenario, a small number of configuration operations need to be performed on the registers in Rank. In the low power operation scenario, a small number of configuration operations need to be performed on the registers in Rank. In the data read and write scenario, operations need to be performed on the storage cells in Rank.

[0049] The memory operation that needs to be stored in cache 12 and needs to be executed by memory 200 in the same working scenario is called the memory operation corresponding to the working scenario. The same working scenario can correspond to at least one memory operation. There are at least one memory operation of the same type corresponding to the same working scenario. For example, in the frequency switching scenario, if it is necessary to configure parameters in 50 registers in a certain Rank, then at least 50 write register operations are required, and each write register operation is used to configure parameters to a register.

[0050] Components of the same type and at the same position in different ranks (such as registers or storage units) are called the same component in different ranks. Components of the same type and at the same position in different ranks can be components with the same component identifier in different ranks. For example, register numbered 1 in Rank 0 and register numbered 1 in Rank 1 are the same register in Rank 0 and Rank 1, respectively.

[0051] In some embodiments, the same memory operation corresponding to the same working scenario includes such memory operations on multiple components (such as registers or memory cells) in multiple ranks. The memory operations on the same component in different ranks may be the same or different. The same memory operation on the same component in different ranks manifests as: writing the same data to the same component in different ranks, or reading data from the same location in the same component in different ranks. For example, if register P1 in Rank 0 and register P1 in Rank 1 are the same register in Rank 0 and Rank 1 respectively, and memory operation O1 writes data D0 to register P1 in Rank 0, and memory operation O2 writes data D0 to register P1 in Rank 1, then memory operation O1 and memory operation O2 are the same memory operations on the same component in Rank 0 and Rank 1.

[0052] In some embodiments, the same memory operation corresponding to the same working scenario includes such memory operations on multiple components (such as registers or storage units) in multiple ranks. The memory operations on the same component in different ranks may be the same or different. The same memory operations on the same component in different ranks manifest as: writing the same data to the same component in different ranks, or reading data from the same location in the same component in different ranks.

[0053] For any working scenario of the memory 200, before any working scenario is started, the control chip 13 can store the memory operation corresponding to the working scenario in the cache 12, so that when the working scenario is started, the control chip 13 can read the memory operation corresponding to the working scenario from the cache 12, convert the read memory operation into a command and send it to the memory 200.

[0054] Taking a frequency-switching scenario as an example, assuming the memory controller 100 is configured with multiple frequency points, the memory operation corresponding to the frequency-switching scenario is a configuration operation. That is, the frequency-switching scenario corresponds to multiple memory operations, including multiple memory operations corresponding to each of the multiple frequency points. Each memory operation corresponding to a frequency point is a configuration operation on a register in the Rank. In related technologies, the memory controller stores each memory operation corresponding to the frequency-switching scenario in its internal cache in the form of entries, thus storing multiple entries in the cache. Each entry includes a description of a memory operation, which describes the memory operation. The description of a memory operation can be an operation descriptor. The description of a memory operation includes the operation type, the location information of the target operation object, and the target time interval. The target operation object is the object targeted by the memory operation (i.e., the accessed object). Taking a configuration operation on a register in the Rank as an example, the target operation object is the register. The location information of the target operation object indicates the location of the target operation object in the storage system. This location information includes the identifier of the memory to which the target operation object belongs, the identifier of the target operation object in the Rank, and the identifier of the Rank to which the target operation object belongs. The identifier of the target operation object in the Rank can be the address or number of the target operation object. The target time interval is the waiting time required after reading an entry and before reading the next entry. In other words, it's the waiting time after reading the current memory operation and before reading the next memory operation. The current memory operation is the memory operation recorded in the entry containing the target time interval (i.e., the current entry). The next memory operation is the memory operation recorded in the entry following the current entry. When the memory operation is a write operation (such as a register write operation), the description information also includes the written data, which refers to the data to be written to the target operation object. When the memory operation is a configuration operation, the written data is the configuration parameters.

[0055] In related technologies, an entry only includes a description of a memory operation and no other information. In these technologies, each memory operation corresponding to a frequency-switching scenario requires an entry for storage. However, as memory architectures become increasingly complex, the configuration parameters for each frequency point increase significantly, leading to a greater number of storage operations for each frequency point. Consequently, the number of entries for each frequency point also rises, increasing the demand on cache storage resources and cache capacity.

[0056] Taking MRDIMM as an example, configuration operations on registers in a Rank include three types: MRW, MRR, and Multi-Purpose Command (MPC). When the memory controller issues these three configuration operations to the MRDIMM, it first converts the MRW, MRR, and MP operations into MRW, MRR, and MPC commands, respectively. Then, it sends these three commands to the MRDIMM via a channel. Upon receiving these commands, the MRCD in the MRDIMM sends them to the MDB in the MRDIMM via the Buffer Control Bus (BCOM Bus). The MDB then forwards these commands to the corresponding Rank. However, since the BCOM Bus is a serial bus, these three commands are transmitted serially and cannot be transmitted in parallel. Due to command length and MDB timing, the MRW command requires an 8-clock-cycle interval during transmission, the MRR command requires a 5-clock-cycle interval, and the MPC requires a 4-clock-cycle interval. Correspondingly, the memory controller needs to read the configuration operations corresponding to these three commands from the cache at certain intervals. Therefore, since each memory operation corresponding to the frequency switching scenario is a register configuration operation (such as MRW and MP operations), in the prior art, the memory controller stores each memory operation corresponding to the frequency switching scenario in the cache in the form of entries, with each memory operation occupying one entry. Before frequency switching, the memory controller reads the description information of the memory operation from the cache entry by entry, and based on the description information, converts the memory operation into an instruction and sends it to MRDIMM. However, due to the application of MRDIMM technology, the number of parameters that need to be configured for MRCD, MDB, and memory chips during frequency switching increases, resulting in a significant increase in the configuration parameters for each frequency point. The number of memory operations corresponding to each frequency point also increases accordingly, and the number of memory operations corresponding to the frequency switching scenario also surges. Consequently, the number of entries occupied by the memory operations corresponding to the frequency switching scenario also increases, thereby increasing the occupation of storage resources in the cache and the demand for cache storage capacity. For example, assuming MRDIMM supports 4 frequency points, the memory operations corresponding to the frequency switching scenario include memory operations for each frequency point. The memory operations for any given frequency point are those that need to be performed before switching to that frequency point. The memory operations for any given frequency point include the number of memory operations M1 required to configure the MRCD register, the number of memory operations M2 required to configure the MDB register, and the number of memory operations M3 required to configure the Rank register. Assuming M1=162, M2=495, M3=852, and MRDIMM supports 4 frequency points M0, then the number of memory operations corresponding to the frequency switching scenario is: Assuming each memory operation occupies one entry, the memory operations corresponding to the frequency switching scenario require a total of 6036 entries, which is a relatively large number of entries, thus increasing the occupation of storage resources in the cache and the demand for cache storage capacity.

[0057] Considering that multiple memory operations corresponding to any given work scenario may involve the same memory operation on different ranks, including the same memory operation on the same component in different ranks, this application stores the same memory operation on different ranks into the same entry to avoid storing the same memory operation on different ranks into multiple entries, thereby reducing the occupation of entries in the cache.

[0058] To enable the storage of the same memory operation on different ranks within the same entry, this application improves the data structure of entries in related technologies. For example, it adds an identifier corresponding to multiple ranks in memory to each entry, referring to the identifier corresponding to any rank as the first identifier. The first identifier indicates whether a memory operation is performed on the corresponding rank, and this memory operation is the memory operation described in the entry's descriptive information. The first identifier can be either an enabled identifier or a disabled identifier. When the first identifier is enabled, it indicates that a memory operation is performed on the corresponding rank; when the first identifier is disabled, it indicates that no memory operation is performed on the corresponding rank. The first identifier occupies 1 bit. Optionally, when the first identifier = 1, it is an enabled identifier; when the first identifier = 0, it is a disabled identifier. Alternatively, when the first identifier = 0, it is an enabled identifier; when the first identifier = 1, it is a disabled identifier.

[0059] by Figure 2 The schematic diagram of an entry provided in this application embodiment is shown as an example. Figure 2As shown, entry X indicates that a memory operation R is performed on at least one of a plurality of Ranks 21 in memory 200. The plurality of Ranks 21 are not shown in the figure. Entry X includes a description information X1 of the memory operation R and a first identifier X2 corresponding to each of the plurality of Ranks 21. Each Rank 21 corresponds to one first identifier X2, meaning entry X includes a plurality of first identifiers X2, each first identifier X2 corresponding to one Rank 21. Each first identifier X2 occupies 1 bit. The first identifier X2 corresponding to at least one Rank 21 is an enable identifier. If at least one Rank 21 is all of the plurality of Ranks 21, then entry X indicates that the memory operation R is performed on the plurality of Ranks 21. If at least one Rank 21 is a subset of the plurality of Ranks 21, then the Ranks 21 other than at least one Rank 21 are called the remaining Ranks. The first identifier X2 corresponding to the remaining Ranks are all disabled identifiers, thus enabling entry X to indicate that the memory operation R is performed on at least one Rank 21 and not on the remaining Ranks. Figure 2 This example illustrates a scenario where multiple Rank21 instances include two Rank21 instances, with the first identifier X2 corresponding to these two Rank1 instances being Flag0 and Flag1, respectively. However, the number of Rank21 instances in a set of multiple Rank21 instances is not limited to two; it can also be greater than two.

[0060] In this context, multiple Rank 21s correspond to the same channel 11 between the memory controller 100 and the memory 200. Multiple Rank 21s include all Ranks within that channel 11 in the memory 200, or may include a subset of Ranks within that channel 11 in the memory 200. This will be explained in detail below with reference to Case 1 and Case 2.

[0061] Case 1: Multiple Rank 21 includes some Ranks within channel 11. In some embodiments, the channel 11 between the memory controller 100 and the memory 200 includes a plurality of pseudo channels (PS), each of the plurality of PSs corresponding to a Rank in the memory 200, and the multiple Rank 21 includes the Rank corresponding to each of the plurality of PSs.

[0062] For example, the memory 200 is an MRDIMM, which includes four ranks, Rank 0 to Rank 3. When the MRDIMM operates in multiplexing mode, the channel 11 between the MRDIMM and the memory controller 100 includes two PSs, PS0 and PS1. PS0 corresponds to Rank 0 in the memory 200, and PS1 corresponds to Rank 2 in the memory 200. Therefore, the multiple Ranks 21 include Rank 0 and Rank 2. In this case, the multiple Ranks 21 include a portion of the ranks in the memory 200.

[0063] In the case where multiple Rank21s each correspond to one PS, optionally, each first identifier X2 in entry X corresponds to one PS in channel 11, and each PS corresponds to one Rank21, thus making each first identifier X2 in entry X correspond to one Rank21. Figure 2 For example, assuming channel 11 includes PS0 and PS1, Flag0 in entry X corresponds to PS0, Flag1 corresponds to PS1, PS0 corresponds to Rank0 in memory 200, and PS1 corresponds to Rank2 in memory 200. Based on the correspondence between PS and Rank, Flag0 corresponds to Rank0 corresponding to PS0, and Flag1 corresponds to Rank2 corresponding to PS1. Multiple Rank21 include Rank0 and Rank2.

[0064] In some embodiments, the channel 11 between the memory controller 100 and the memory 200 corresponds to multiple pairs of parity Ranks in the memory 200, and the multiple Ranks 21 include the even Ranks in at least two pairs of parity Ranks, or include the odd Ranks in at least two pairs of parity Ranks.

[0065] For example, memory 200 is an MRDIMM, which includes four ranks, namely Rank0 to 3. When the MRDIMM is working in Rank mode, Rank0 and Rank1 are a pair of odd and even ranks, Rank2 and Rank3 are another pair of odd and even ranks, and multiple Rank21 include Rank0 and Rank2. At this time, multiple Rank21 include a portion of the ranks in memory 200.

[0066] Case 2: Multiple Rank21s are all Ranks within channel 11 of memory 200. The multiple Rank 21s include each Rank within channel 11 of memory 200. Since all Ranks in memory 200 are located within channel 11, the multiple Rank 21s include all channels 11 in memory 200. Taking memory 200 as an RDIMM as an example, an RDIMM includes 4 Ranks, and the multiple Rank 21s include these 4 Ranks.

[0067] Memory operation R can be any type of memory operation. For example, memory operation R can be any configuration operation on registers in the Rank, such as an MRW operation, an MRR operation, or a multi-function operation. Alternatively, memory operation R can also be an operation on memory cells in the Rank, such as a read / write operation, a close operation, or an open operation on a memory cell. Description information X1 can also be considered as the memory operation R stored in entry X. Description information X1 is used to describe memory operation R, and description information X1 can be an operation descriptor for memory operation R. Similar to the description information stored in entries of related technologies, description information X1 includes the operation type of memory operation R, the location information of the target operation object, and the target time interval. When memory operation R is a write operation (such as an MRW operation or a write operation to a memory cell), the description information of the memory operation also includes the written data. Unlike the description information stored in entries of related technologies, the location information of the target operation object in description information X1 includes the identifier of the memory 200 to which the target operation object belongs and the identifier of the target operation object in the Rank, but does not include the identifier of the Rank to which the target operation object belongs.

[0068] In the case where multiple Rank 21s correspond to memory operations R (i.e., multiple memory operations R corresponding to multiple Rank 21s) in the memory operations corresponding to the work scenario, the memory controller 100 can store the multiple memory operations R corresponding to multiple Rank 21s into an entry X. For example, in entry X, a description information X1 of memory operation R is included, and the first identifier X2 corresponding to multiple Rank 21s in entry X is set as an enable identifier. This enables entry X to indicate that memory operation R is performed on all multiple Rank 21s. Since there should actually be multiple memory operations R corresponding to multiple Rank 21s, entry X can achieve the purpose of storing multiple memory operations R corresponding to multiple Rank 21s through a description information X1 of memory operation R and the enable identifier (i.e., the first identifier X2) corresponding to multiple Rank 21s. This avoids storing multiple memory operations R corresponding to multiple Rank 21s into multiple entries. Of course, if at least one of the multiple Rank21s corresponds to a memory operation R, the first identifier X2 corresponding to the at least one Rank21 in the entry X is set as an enable identifier, and the remaining first identifiers in the entry X are set as disable identifiers, so that the entry X can indicate that the memory operation R is performed on the at least one Rank21 and that the memory operation R is not performed on the Rank21 corresponding to the remaining first identifier.

[0069] It should be understood that the above entry X indicates memory operation R through description information X1, and indicates whether memory operation R is performed on the corresponding Rank 21 through the first identifier X2 corresponding to each Rank 21. Thus, one entry X indicates which Rank 21 among multiple Rank 21s will have memory operation R performed on, and which Rank 21 among multiple Rank 21s will not have memory operation R performed on.

[0070] The memory controller 100 converts memory operations R into commands and issues these commands to the memory 200 to implement the issuance of memory operations R. For ease of description, the commands converted from configuration operations on registers in the Rank are called configuration commands, and the commands converted from memory operations on memory cells in the Rank are called service commands. Configuration commands include, but are not limited to, MRW commands, MRR commands, and MPC commands. Service commands include, but are not limited to, write commands, read commands, enable commands, and disable commands. Write commands, read commands, enable commands, and disable commands are derived from write operations, read operations, disable operations, and enable operations on memory cells, respectively. Different commands may have different transmission methods when transmitted on different buses within the memory 200. Taking the memory 200 as an MRDIMM as an example, configuration commands are transmitted serially in the BCOM bus between the MRCD and MDB in the MRDIMM, while service commands are transmitted in parallel in the command parallel bus between the MRCD and MDB. The method by which the memory controller 100 sends commands to the memory 200 is called the command sending mode. The memory controller 100 supports multiple command sending modes, including serial sending mode and parallel sending mode. Serial sending mode refers to sending multiple commands to the memory 200 serially. For example, after sending one command to the memory 200, another command is sent to the memory 200 after a preset time interval. Serial sending mode can also be called interval sending mode. Parallel sending mode refers to sending multiple commands to the memory 200 in parallel; that is, sending multiple commands to the memory 200 simultaneously.

[0071] Based on this, in some embodiments, entry X further includes a transmission method identifier X3, which indicates the transmission method of multiple commands. Any command indicates the execution of a memory operation R on one of the multiple Ranks 21. This command is derived from the description information X1 of the memory operation R, meaning it is converted from the memory operation R. When the memory operation R is a configuration operation, all commands are configuration commands; when the memory operation R is an operation targeting a storage unit, all commands are service commands. It should be understood that the transmission method identifier X3 is only valid when multiple commands converted from multiple memory operations R need to be sent to the memory 200. It is invalid when only one command converted from one memory operation R needs to be sent to the memory 200. That is, the transmission method identifier X3 is valid when multiple first identifiers X2 in entry X are enable identifiers, and invalid when only one of the multiple first identifiers X2 in entry X is an enable identifier.

[0072] The transmission mode identifier X3 serves as both a serial transmission identifier and a parallel transmission identifier. The serial transmission identifier indicates a serial transmission mode; that is, when X3 is a serial transmission identifier, it indicates that multiple commands are transmitted serially. The parallel transmission identifier indicates a parallel transmission mode; that is, when X3 is a parallel transmission identifier, it indicates that multiple commands are transmitted in parallel. The transmission mode identifier X3 occupies 1 bit. In some embodiments, when X3=1, it is a serial transmission identifier; when X3=0, it is a parallel transmission identifier. Alternatively, when X3=0, it is a serial transmission identifier; when X3=1, it is a parallel transmission identifier.

[0073] Since configuration commands are transmitted serially in memory 200, when memory operation R is a configuration operation, the transmission mode identifier X3 is a serial transmission identifier, and the transmission mode indicated by transmission mode identifier X3 is the serial transmission mode. Since service commands can be transmitted in parallel in memory 200, when memory operation R is an operation targeting a memory cell, the transmission mode identifier X3 is a parallel transmission identifier, and the transmission mode indicated by transmission mode identifier X3 is the parallel transmission mode.

[0074] Therefore, a transmission flag is set according to the operation type of memory operation R, so that the subsequent control chip 13 can send the command converted by memory operation R according to the transmission method indicated by the transmission flag. There are multiple possible transmission flags, so that entry X can be applied to memory operations in various scenarios.

[0075] The storage operation corresponding to at least one working scenario of the memory 200 needs to be stored in the cache 12 in the form of an entry X. The at least one working scenario includes, but is not limited to, frequency switching scenario, power mode switching scenario, low power operation scenario, high power operation scenario, data read and write scenario, etc.

[0076] Figure 2 Taking an entry X with a length of 48 bits as an example, the transmission mode identifier X3 occupies the 47th bit, Flag0 and Flag1 occupy the 46th and 45th bits respectively, and the description information X1 has a total length of 45 bits, occupying bits 0 to 44. The length of the description information X1 is variable and not limited to 45 bits; correspondingly, the length of the 200-bit entry is also variable and can be set according to actual needs. Figure 2 The diagram illustrates one arrangement of the transmission method identifier X3, the first identifier X2, and the description information X1 in entry X, but is not limited to any particular arrangement. Figure 2This arrangement method can also be used in other ways.

[0077] To facilitate the controller chip 13 in distinguishing which entries X in the cache 12 store memory operations corresponding to which working scenario, in some embodiments, entry X further includes a second identifier corresponding to the at least one working scenario. Each working scenario corresponds to one second identifier; that is, entry X includes at least one second identifier, and each second identifier corresponds to one working scenario. The second identifier indicates whether the memory operation R corresponds to the working scenario corresponding to the second identifier. The second identifier is either an enabled identifier or a disabled identifier. An enabled identifier indicates that the memory operation R corresponds to the working scenario corresponding to the second identifier, while a disabled identifier indicates that the memory operation R does not correspond to the working scenario corresponding to the second identifier. The second identifier occupies 1 bit. Optionally, when the second identifier = 1, the first identifier is an enabled identifier; when the second identifier = 0, the first identifier is a disabled identifier. Alternatively, when the second identifier = 0, the first identifier is an enabled identifier; when the second identifier = 1, the first identifier is a disabled identifier.

[0078] For any operating scenario of memory 200, before any operating scenario is started, memory controller 100 can store the memory operations corresponding to that operating scenario in the form of entries X into cache 12. When storing memory operations in the form of entries X, if there are multiple identical memory operations of Rank 21 in the memory operations corresponding to that operating scenario, then the identical memory operations of multiple Rank 21 are stored in one entry X, thereby reducing the number of entries stored in cache 12. Different memory operations of different Rank 21 in the memory operations corresponding to the operating scenario need to be stored in a separate entry X, and the storage operations of registers of other components besides Rank 21 also need to be stored in a separate entry X.

[0079] For example, assuming there are M memory operations corresponding to this work scenario, when storing the memory operations corresponding to this work scenario in cache 12 as entries X, control chip 13 stores the M memory operations corresponding to this work scenario through N entries X, from entry 0 to entry N-1. Here, M is greater than N, and both M and N are integers.

[0080] Taking a frequency-switching scenario as an example, with memory 200 being an MRDIMM that supports four frequency points, as described above, the number of memory operations corresponding to the frequency-switching scenario is M=6035. The number of memory operations required to configure the MRCD register is M1=162, the number of memory operations required to configure the MDB register is M2=495, and the number of memory operations required to configure the Rank register is M3=852. In related technologies, each memory operation requires a separate entry. Therefore, the 162 memory operations for configuring the MRCD register require 162 entries, the 495 memory operations for configuring the MDB register require 495 entries, and the 852 memory operations for configuring the Rank register require 852 entries. In this application, assuming that memory operations for the two ranks corresponding to PS0 and PS1 share a single entry X, the 852 memory operations for configuring the Rank register require 432 entries X. That is, the number of entries required for configuring the Rank register is reduced from 852 to 432. Each memory operation for configuring the MRCD register occupies one entry X independently, and each memory operation for configuring the MDB register occupies one entry X independently. In other words, the number of entries required for configuring MRCD and MDB remains unchanged, and the final number of entries X required is [not specified]. This reduces the number of entries required for memory operations in frequency switching scenarios from 6035 to 4356, a reduction of approximately 27.8%. This reduces the amount of entries occupied in cache 12, the amount of storage space occupied in cache 12, and the amount of storage resources and storage capacity required in cache 12.

[0081] After storing the memory operations corresponding to the working scenario as entries X in cache 12, when the working scenario is activated, the control chip 13 can read the entries X corresponding to the working scenario one by one from cache 12. For each entry X read, the description information X1 is used to generate at least one command based on the description information X1, and the generated command is sent to memory 200. The following is in conjunction with Figure 3 This implementation method will be introduced.

[0082] Figure 3 This is a flowchart of a command sending method provided in an embodiment of this application. The method is applied to a memory controller, which controls the memory. Figure 1 Taking the memory controller 100 in the example, the memory is... Figure 1 The memory 200 in the memory. The method includes the following steps 301 and 302.

[0083] The memory supports at least one operating scenario, including but not limited to frequency switching scenario, power mode switching scenario, low-power operation scenario, high-power operation scenario, and data read / write scenario. Any one of these at least one operating scenario is referred to as the target scenario.

[0084] Before executing step 301, the memory controller generates N entries corresponding to the target scene based on M memory operations corresponding to the target scene, and stores these N entries in a cache. N is less than M, and both N and M are integers. This cache is a cache within the memory controller. Figure 1 Taking the memory controller 100 in the example, the cache is... Figure 1 Cache 12 in the middle.

[0085] Before performing step 301, the memory controller generates N entries corresponding to the target scene based on the M memory operations corresponding to the target scene, and stores the N entries corresponding to the target scene in the cache. N is less than M, and both N and M are integers.

[0086] The target scenario involves M memory operations, including memory operations (such as configuration operations) on registers in multiple ranks of the memory. There are multiple memory operations on registers in multiple ranks of the memory. Optionally, these multiple memory operations include configuration operations on registers in other modules of the memory besides the ranks. Taking the memory as MRDIMM and the target scenario as a frequency-switching scenario as an example, these multiple memory operations include 162 memory operations on registers in MRCD, 495 memory operations on registers in MDB, and 852 memory operations on registers in multiple ranks. The frequency-switching scenario corresponds to a total of 6036 memory operations, i.e., M=6036.

[0087] Optionally, the multiple memory operations corresponding to the target scenario also include operations on units stored in multiple Ranks, with at least one such operation.

[0088] The following describes the process of generating M entries corresponding to the target scenario based on M memory operations.

[0089] Each entry corresponding to the target scenario indicates that the same memory operation is performed on at least one target Rank among multiple Ranks in the memory. The target Rank is the Rank targeted by the memory operation among the multiple Ranks. The data format of each entry is similar to that of entry X described above. Taking the memory 200 mentioned above as an example, the multiple Ranks are the multiple Ranks 21 mentioned above, and each target Rank is one Rank 21. Each entry includes multiple first identifiers and a description of the memory operation. Each first identifier corresponds to a Rank in the memory, and different first identifiers correspond to different Ranks in the memory. The first identifiers corresponding to at least one target Rank in each entry are all enabled identifiers, while the first identifiers corresponding to other Ranks besides the target Rank are all disabled identifiers. This allows the entry to indicate that the memory operation described in the description information of the entry is performed on at least one target Rank.

[0090] Optionally, the N entries corresponding to the target scene include multiple first entries. Each first entry indicates performing the same memory operation on multiple target ranks among multiple ranks in the memory. In each first entry, the first identifiers corresponding to the multiple target ranks are all enable identifiers. That is, the first entry includes a description of the operation and enable identifiers corresponding to the multiple target ranks. The multiple target ranks are all or some of the ranks among the multiple ranks.

[0091] Optionally, the N entries corresponding to the target scenario further include at least one second entry. Each second entry indicates that a memory operation is performed on a target Rank among the multiple Ranks of the memory. Among the multiple first identifiers of each second entry, the first identifier corresponding to the target Rank is an enable identifier. That is, the first entry includes descriptive information describing the operation and the enable identifier corresponding to the target Rank. In this case, the target Rank is any Rank among the multiple Ranks.

[0092] For ease of description, the same memory operation on multiple target ranks of memory is referred to as a first memory operation, and different memory operations on memory are referred to as second memory operations. Any two different memory operations can be characterized by at least one difference in their operation type, target operation pair, and written data. The second memory operation can be any type of memory operation supported by the memory, including but not limited to memory operations on registers and memory operations on memory cells.

[0093] The memory operation described in the first entry is a first memory operation, and the memory operation described in the second entry is a second memory operation. That is, the first entry includes descriptions of the first memory operation, and the second entry includes descriptions of the second memory operation.

[0094] The following section describes the generation process of any entry corresponding to the target scene.

[0095] Taking the generation of any first entry as an example, if among the M memory operations corresponding to the target scene there is the same memory operation on multiple target ranks among multiple ranks of the memory, the memory controller takes the same memory operation on the multiple target ranks as the first memory operation, and generates a first entry based on the multiple target ranks and the first memory operation. The first entry includes multiple first identifiers and description information of the first memory operation, and the first identifiers corresponding to the multiple target ranks are all enable identifiers. For example, assuming the first memory operation is the memory operation R mentioned above, the memory is MRDIMM, and in multiplexing mode, the multiple ranks of the memory include Rank0 corresponding to PS0 and Rank2 corresponding to PS1. Figure 2 The entry X shown is the first entry. In entry X, the first identifiers corresponding to Rank0 and Rank2 are Flag0 and Flag1, respectively. Assuming that Rank0 and Rank2 are both target ranks, then Flag0 and Flag1 are both enable identifiers. In this case, memory operation R can be an operation on registers in the target rank (such as a configuration operation) or an operation on memory cells in the target rank. In other embodiments, MRDIMM is in Rank mode, where Flag0 and Flag1 correspond to either the odd rank or even rank in two pairs of odd and even rank pairs. For example, Flag0 and Flag1 correspond to Rank0 and Rank2, respectively, where Rank0 and Rank2 are target ranks, and memory operation R is an operation on registers in the target rank.

[0096] Among the M memory operations corresponding to the target scenario, there are multiple sets of first memory operations. Each set of first memory operations includes the same first memory operation for multiple target ranks. For each set of first memory operations, a first entry can be generated in a similar manner. The description information in the first entry and the enable flags corresponding to multiple target ranks indicate the same memory operation for multiple target ranks. This allows multiple memory operations for multiple target ranks to be stored in one entry, that is, multiple memory operations share the same entry, instead of using multiple entries to store each memory operation separately. This reduces the number of entries corresponding to the target scenario, and thus reduces the cache space occupied when storing entries corresponding to the target scenario in the cache, thereby reducing the consumption of cache storage resources and the demand for cache storage capacity. Taking the memory as MRDIMM and the target scenario as a frequency-switching scenario, 852 of the 6036 memory operations corresponding to the frequency-switching scenario are operations on registers in the Rank, using 432 registers. Figure 2 The entry X shown can store all 852 memory operations without using 852 entries to store them, thus reducing the number of entries required for memory operations in the frequency switching scenario from 6036 to 4356, where 6036 is M and 4356 is N.

[0097] Taking the generation of any second entry as an example, if any memory operation among the M memory operations corresponding to the target scene is different from the other memory operations among these multiple memory operations, then the memory controller takes this memory operation as the second memory operation. If the second memory operation is a configuration operation on a register in a certain Rank of the memory, then this Rank is taken as the target Rank. Based on the target Rank and the second memory operation, a second entry is generated. The second entry includes multiple first identifiers and a description of the second memory operation, and the first identifier corresponding to the target Rank among the multiple first identifiers is an enable identifier. For example, assuming the second memory operation is the aforementioned memory operation R, the memory is an MRDIMM, and in multiplexing mode, the multiple Ranks of the memory include Rank0 corresponding to PS0 and Rank2 corresponding to PS1. Figure 2The entry X shown is the second entry. In entry X, the first identifiers corresponding to Rank0 and Rank2 are Flag0 and Flag1, respectively. Assuming Rank0 is the target Rank and Rank2 is not, then Flag0 is the enable identifier and Flag1 is the disable identifier. In this case, memory operation R can be any type of memory operation. In other embodiments, MRDIMM is in Rank mode, where Flag0 and Flag1 correspond to different Ranks. The Ranks corresponding to Flag0 and Flag1 can belong to the same pair of odd / even Ranks or different pairs of odd / even Ranks. In this case, memory operation R can be any type of memory operation.

[0098] If the second memory operation is not a configuration operation on a register in a certain Rank of memory, the memory controller generates a second entry based on the target Rank. In this case, the second entry includes multiple first identifiers and a description of the second memory operation, and all of the multiple first identifiers are disabled identifiers.

[0099] In the M memory operations corresponding to the target scene, each memory operation other than the aforementioned multiple sets of first memory operations is a second memory operation. In the manner described above, a second entry corresponding to the target scene can be generated for each second memory operation.

[0100] The above describes the generation method of the first and second entries using MRDIMM as an example. When the memory is RDIMM, the first and second entries can also be generated according to the above generation method based on actual needs.

[0101] Optionally, each entry in the target scenario also includes a transmission method identifier. When multiple enable identifiers exist among the multiple first identifiers in any entry, the transmission method identifier in that entry is valid; that is, the transmission method identifier in the first entry is valid. The first memory operation described in the descriptive information of the first entry may be a configuration operation for registers in the target Rank, or it may be an operation for the memory in the target Rank.

[0102] For example, in an MRDIMM with the memory in multiplexed mode, if the first memory operation is a configuration operation on a register in the target Rank, the transmission mode identifier in the first entry is a serial transmission identifier; if the first memory operation is an operation on a memory cell in the target Rank, the transmission mode identifier in the first entry is a parallel transmission identifier. Thus, in multiplexed mode, the memory controller can serially access registers in different PS corresponding to different Ranks, or parallelly access memory cells in different PS corresponding to different Ranks, based on a single first entry. For example, suppose the first memory operation is the aforementioned memory operation R, where memory operation R is a configuration operation on a register in the Rank. Figure 2 The entry X shown is the first entry, and the transmission mode identifier X3 in entry X is the serial transmission identifier.

[0103] In some embodiments, when the memory is an MRDIMM in Rank mode, the first memory operation is a configuration operation on registers in the target Rank, and the transmit identifier in the first entry is a serial identifier. Thus, in Rank mode, the memory controller can serially access registers in different Ranks based on a single first entry.

[0104] When at most one enable flag exists among the multiple first flags of any entry, the transmission mode flag in that entry is invalid. That is, the transmission mode flag in the second entry is valid. The transmission mode flag in the second entry can be a serial transmission flag or a parallel transmission flag.

[0105] Optionally, each entry corresponding to the target scenario further includes a second identifier corresponding to at least one working scenario of the memory, wherein the second identifier corresponding to the target scenario in the at least one working scenario is an enable identifier. That is, each entry corresponding to the target scenario also includes an enable identifier corresponding to the target scenario. For example, the first entry includes an enable identifier corresponding to the target scenario, and the second entry also includes an enable identifier corresponding to the target scenario. In some embodiments, each entry corresponding to the target scenario may also not include the second identifier corresponding to the at least one second scenario.

[0106] The M memory operations corresponding to the above target scenario can be obtained based on the configuration file, which is configured by the user into the memory controller or sent to the memory controller by the host processor.

[0107] The process of generating N entries corresponding to the target scene based on the M memory operations described above, and storing these N entries in the cache, can be performed before the target scene is started. For example, during the initialization phase, the memory controller determines the M memory operations corresponding to the target scene based on the configuration file, generates N entries corresponding to the target scene based on these M memory operations, and stores these N entries in the cache. Subsequently, when the target scene is started, the memory controller reads the N entries corresponding to the target scene from the cache, generates M commands based on these N entries, and sends the M commands to the memory, thereby distributing the M memory operations to the memory. This implementation method is described below in conjunction with steps 301 and 302.

[0108] 301. When multiple first entries in the cache meet the read conditions, the memory controller reads multiple first entries in the cache. The first entry includes a description of the memory operation and an enable flag corresponding to multiple Ranks in the memory. The enable flag indicates that the memory operation is performed on the corresponding Rank.

[0109] This cache is an internal cache of the memory controller, such as cache 12 mentioned above. As described above, the first entry includes enable flags corresponding to multiple memory ranks in the memory; that is, the first entry includes multiple first flags, among which the first flags corresponding to multiple target ranks are enable flags. The memory operation described in the descriptive information of the first entry is a first memory operation, and all of these multiple ranks are target ranks.

[0110] In this context, multiple first entries each correspond to a target scenario, and the read condition for multiple first entries can include the target scenario being enabled. Accordingly, step 301 means that the memory controller, in response to the target scenario being enabled, reads multiple first entries from the cache. For example, the memory controller, in response to the target scenario being enabled, reads N entries in the cache corresponding to the target scenario, and these N entries include multiple first entries.

[0111] For example, the memory controller detects a target scene activation event and, in response, reads multiple entries corresponding to the target scene from the cache. The target scene activation event indicates that the target scene is activated. The multiple entries corresponding to the target scene include multiple first entries, or the multiple entries corresponding to the target scene also include at least one second entry. The multiple entries corresponding to the target scene can be all entries (i.e., N entries) or a subset of the entries. Taking a frequency-switching scene as an example, the N entries corresponding to the target scene include entries corresponding to multiple frequency points supported by the memory. Each frequency point corresponds to multiple entries, and each entry corresponding to a frequency point includes at least one first entry and at least one second entry. The memory operation recorded for each entry at any frequency point is the memory operation required for the memory to operate at that frequency point. The target scene activation event can be a frequency-switching instruction, which instructs the memory to switch its operating frequency point to the target frequency point. The target frequency point is any frequency point supported by the memory. After detecting the frequency-switching instruction, the memory controller, in response, reads each entry corresponding to the target frequency point from the cache.

[0112] The process of reading multiple entries corresponding to the target scenario from the cache includes: the memory controller reading each entry in the cache sequentially. For example, each entry contains a description information including a target time interval. For any entry among the multiple entries corresponding to the target scenario, except for the last one, the memory controller reads that entry from the cache. After the target time interval included in the description information of that entry has elapsed, the next entry among the multiple entries is read from the cache. This is to avoid subsequent commands generated based on that entry and commands generated based on the next entry competing for transmission resources.

[0113] 302. For each first entry read, the memory controller sends multiple commands to the memory based on the enable flag and description information in the first entry. The commands instruct the memory to perform the memory operation on Rank.

[0114] Among them, the multiple commands are commands generated based on the first entry.

[0115] For multiple entries corresponding to the target scene in the cache, each time an entry corresponding to the target scene is read from the cache, the memory controller generates at least one command based on that entry and sends the at least one command to the memory. The entry may be the first entry or the second entry. For ease of description, the command generated based on the first entry is referred to as the first command, and the command generated based on the second entry is referred to as the second command.

[0116] Taking the first entry as an example, each time an entry corresponding to the target scenario is read from the cache, if multiple enable identifiers exist among the multiple first identifiers of the entry, then the entry is the first entry. The Rank corresponding to the first identifiers that are enable identifiers in the entry are all target Ranks. The memory operation described in the description information of the entry is the first memory operation (i.e., the same memory operation for multiple target Ranks). Based on the description information of the first memory operation in the first entry and the enable identifiers corresponding to multiple target Ranks, the memory controller generates multiple first commands, thereby decoding the first entry into multiple first commands. The first command indicates that a first memory operation is performed on a target Rank. The description information includes the identifier of the target operation object of the first memory operation. The first command specifically indicates that a first memory operation is performed on the target operation object in the target Rank.

[0117] For example, for each enable identifier among multiple first identifiers, a first command is generated based on the target Rank corresponding to that enable identifier and the description information of the first memory operation. This first command instructs the execution of the first memory operation on the target Rank. Thus, the number of first commands generated corresponds to the number of first identifiers that are enable identifiers in the first entry.

[0118] The above-mentioned method can retrieve the first entry from the cache with a single read operation. Retrieving an entry from the cache is equivalent to retrieving an instruction from the cache. By performing a decoding operation on the retrieved first entry, multiple first commands can be obtained. Thus, a single instruction fetching and decoding operation on the first entry in the cache can achieve the effect of obtaining multiple commands. This reduces the number of cache accesses and the time spent in the process of retrieving the entry corresponding to the target scenario from the cache, thereby reducing the workload of the target scenario. Taking the target scenario as a frequency switching scenario as an example, it can reduce the time spent in the frequency switching process.

[0119] It should be understood that when the first memory operation is a configuration operation on a register in the target Rank, the first command is a configuration command. When the first memory operation is an operation on a storage cell in the target Rank, the first command is a service command.

[0120] If the first entry includes a transmission mode identifier, after generating multiple first commands based on a first entry, the memory controller sends the multiple first commands to the memory according to the transmission mode indicated by the transmission mode identifier in the first entry.

[0121] For example, assuming the transmission mode identifier is a serial transmission identifier, the memory controller sends the plurality of first commands to the memory according to the serial transmission mode indicated by the serial transmission identifier. For instance, it first sends one of the plurality of first commands to the memory, and after a preset time, sends another of the plurality of first commands to the memory. The preset time can be set according to the type of the first command or the operation type of the first memory operation. For example, if the first command is an MRW command, the preset time is 8 clock cycles; if the first command is an MRR command, the preset time is 5 clock cycles. Here, the embodiments of this application do not limit the preset time.

[0122] Assuming the transmission mode identifier is a parallel transmission identifier, the memory controller sends the multiple first commands to the memory according to the parallel transmission mode indicated by the parallel transmission identifier, for example, sending the multiple first commands to the memory in parallel.

[0123] If the first entry does not include a transmission mode identifier, the memory controller presets a prediction duration for each of the multiple command types supported by the memory. If the preset duration corresponding to the command type of the first command is 0, the memory controller sends multiple first commands to the memory in parallel. If the preset duration corresponding to the command type of the first command is not 0, the controller first sends one of the multiple first commands to the memory. After the preset duration corresponding to the command type of the first command has elapsed, the controller sends another of the multiple first commands to the memory.

[0124] Taking the read entry as the second entry as an example, each time an entry corresponding to the target scenario is read from the cache, if one of the multiple first identifiers of the entry is an enable identifier or there is no enable identifier, then the entry is the second entry. The memory operation described in the description information of the second entry is the second memory operation. This description information includes the identifier of the target operation object of the second memory operation. The memory controller generates a second command based on the second entry. The second command instructs the execution of the second memory operation on the target operation object in the memory. The target operation object may be located in a certain Rank in the memory, or it may be located in other modules in the memory besides a Rank. When the second memory operation is a configuration operation on a register in the target Rank, the second command is a configuration command. When the second memory operation is an operation on a storage unit in the target Rank, the second command is a service command.

[0125] For example, if an enable identifier exists among the multiple first identifiers in the second entry, then the Rank corresponding to the first identifier with the enable identifier is the target Rank, and the target operation object of the second memory operation is located in the target Rank. The memory controller generates a second command based on the target Rank and the description information of the second memory operation in the second entry, and the second command instructs the second memory operation to be performed on the target operation object in the target Rank. Alternatively, if no enable identifier exists among the multiple first identifiers in the second entry, then the memory controller generates a second command based on the description information of the second memory operation in the second entry, and the second command instructs the second memory operation to be performed on the target operation object.

[0126] After generating the second command based on the second entry, the memory controller sends the second command to the memory.

[0127] After sending all commands generated based on any read entry, the memory controller determines whether all entries corresponding to the target scene have been read. If not all entries have been read (i.e., there are unread entries among the multiple entries), after the target time interval of the entry, the next entry corresponding to the target scene is read from the cache, at least one command is generated based on the read next entry, and the at least one command is sent to the memory. This process continues until all entries corresponding to the target scene have been read, at which point reading entries from the cache is stopped, and the process ends.

[0128] Below, with Figure 4 Taking this as an example, we will introduce the process by which the memory controller converts multiple entries corresponding to the target scene in the cache into instructions and sends them to the memory.

[0129] like Figure 4 As shown, when or after the target scene is activated, the memory controller reads the first entry from multiple entries corresponding to the target scene in the cache, thereby fetching instructions. The memory controller decodes the read first entry to obtain at least one command, and sends the at least one command to the memory based on multiple first identifiers and / or transmission mode identifiers in the first entry.

[0130] Taking the first entry as Figure 2Taking entry X as an example, if both Flag0 and Flag1 in entry X are 1 (enable flags), it means that Rank0 corresponding to Flag0 and Rank2 corresponding to Flag1 are the target Ranks, and entry X is the first entry. Entry X is decoded into commands CMD1 and CMD2. Command CMD1 indicates that the first memory operation should be performed on Rank0 in memory, and command CMD2 indicates that the first memory operation should be performed on Rank2 in memory. At this time, both commands CMD1 and CMD2 are the first commands. When both Flag0 and Flag1 in entry X are 1, if the transmission mode flag in entry X is 1 (i.e., serial transmission flag), the memory controller first sends command CMD1 to the memory, and after a preset time, sends command CMD2 to the memory. Sending command CMD1 to the memory realizes that the command is sent to Rank0. If Rank0 corresponds to PS0, it also realizes that the command is sent to PS0. Sending the command CMD2 to the memory enables the command to be sent to Rank2. If Rank2 corresponds to PS1, then the command is sent to PS1. In this way, when Flag0, Flag1 and the sending method identifier in entry X are all 1, the command is first sent to Rank0 and then sent to Rank2.

[0131] If Flag0 and Flag1 in entry X are both 1, and the transmission mode identifier in entry X is 0 (i.e., parallel transmission identifier), then the memory controller sends commands CMD1 and CMD2 to the memory in parallel. This enables the commands to be sent to Rank0 and Rank2 simultaneously when Flag0 and Flag1 in entry X are both 1 and the transmission mode identifier is 0.

[0132] If Flag0 in entry X is 1 (enable flag) and Flag1 is 0 (disable flag), then entry X is the second entry, and Rank0 corresponding to Flag0 is the target Rank. The memory controller decodes entry X into a command CMD1, which is the second command. If Flag0 in entry X is 0 and Flag1 is 1, then entry X is the second entry, and Rank2 corresponding to Flag1 is the target Rank. The memory controller decodes entry X into a command CMD2, which is the second command. In this scenario, the transmission mode flag in entry X is invalid. The command is sent to the memory based on the enable flags in Flag0 and Flag1. For example, if entry X does not satisfy the condition that both Flag0 and Flag1 are 1 and the transmission mode flag is 0, if Flag0 is 0 and Flag1 is 1, the memory controller sends CMD2 to the memory, thus sending the command to Rank2; if Flag0 is 1 and Flag1 is 0, the memory controller sends CMD1 to the memory, thus sending the command to Rank0.

[0133] After sending the command generated based on the first entry to the memory, if the multiple entries corresponding to the target scene in the cache have not been read in time, the second entry corresponding to the target scene is read from the cache, the second entry is decoded into at least one command, and the at least one command is sent to the memory in the same manner as described above. This process continues until all the multiple entries corresponding to the target scene in the cache have been read in time, at which point the process ends.

[0134] In the above Figure 3 In the method provided in the embodiment, the memory controller reduces the number of entries in the cache by storing the same memory operation on multiple Ranks of the memory in one entry in the cache, thereby reducing the need to store the same memory operation on multiple Ranks in different entries, thus reducing the occupation of storage resources in the cache and the demand for cache storage capacity.

[0135] Optionally, Figure 3 The provided command sending method can be executed by the control chip in the memory controller, in order to Figure 1 Taking the memory controller 100 in the example, the control chip is the control chip 13.

[0136] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0137] Figure 5 This application provides a structure for a command sending device according to an embodiment. Figure 5The command sending device 500 shown is applied to the aforementioned memory controller. The command sending device 500 can be configured as the memory controller itself, or as a component within the memory controller (such as a control chip). Figure 5 As shown, the command sending device 500 includes: The reading module 501 is used to read the multiple first entries in the cache when the reading condition is met. The first entry includes description information of memory operation and enable flags corresponding to multiple storage ranks in the memory. The enable flags indicate that the memory operation is performed on the corresponding storage rank. The sending module 502 is configured to send multiple commands to the memory based on the enable identifier and the description information in the first entry for each first entry read, the commands instructing the memory operation to be performed on the memory rank.

[0138] Optionally, the plurality of storage ranks correspond to the same channel between the memory controller and the memory.

[0139] Optionally, the channel includes multiple pseudo-channels, and the multiple storage ranks include the storage rank corresponding to each pseudo-channel among the multiple pseudo-channels.

[0140] Optionally, the channel corresponds to multiple pairs of parity storage ranks in the memory, the multiple storage ranks including at least two pairs of even storage ranks or odd storage ranks, and each pair of parity storage ranks includes one odd storage rank and one even storage rank.

[0141] Optionally, the plurality of storage ranks includes each storage rank corresponding to the channel.

[0142] Optionally, the first entry further includes a sending method identifier, which indicates the sending method of the plurality of commands; The sending module includes: The generation unit is configured to generate the plurality of commands based on the enable identifier and the description information in the first entry for each first entry read. The sending unit is used to send the plurality of commands to the memory according to the sending method indicated by the sending method identifier.

[0143] Optionally, the plurality of storage ranks includes a first storage rank and a second storage rank, and the plurality of commands includes a first command and a second command, wherein the first command instructs the memory operation to be performed on the first storage rank, and the second command instructs the memory operation to be performed on the second storage rank; The transmission method is a serial transmission method; The sending unit is configured to first send one of the plurality of commands to the memory, and after a preset time period, send another of the plurality of commands to the memory.

[0144] Optionally, the memory operation is a configuration operation of the registers in the memory rank.

[0145] Optionally, the transmission method is a parallel transmission method; The sending unit is used to send the multiple commands to the memory in parallel.

[0146] Optionally, the memory operation is an operation on a memory cell in the memory rank.

[0147] Optionally, the first entry further includes an enable flag corresponding to the target scenario, the enable flag indicating that the memory operation corresponds to the target scenario; The step of reading the multiple first entries in the cache when the read condition is met includes: In response to the activation of the target scenario, the plurality of first entries in the cache are read.

[0148] Regarding the command sending device 500 in the above embodiments, the specific methods by which each module performs operations have been described in detail in the embodiments related to the command sending method, and will not be elaborated here.

[0149] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction, which can be executed by a processor in a memory controller to complete the command sending method in the above embodiments. Optionally, the computer-readable storage medium may be a non-transitory computer-readable storage medium, such as ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), optical data storage device, etc.

[0150] In an exemplary embodiment, a computer program product is also provided, including one or more instructions that can be executed by a processor in a memory controller to perform the command sending methods provided in the various embodiments described above.

[0151] The processor in the memory controller can be the control chip in the memory controller, or it can be a part of the control chip.

[0152] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0153] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A command sending method, characterized in that, Applied to a memory controller, the method includes: When multiple first entries in the cache meet the read condition, the multiple first entries in the cache are read. The first entries include description information of memory operations and enable flags corresponding to multiple storage ranks in the memory. The enable flags indicate that the memory operation is performed on the corresponding storage rank. For each first entry read, based on the enable flag and description information in the first entry, multiple commands are sent to the memory, the commands instructing the memory operation to be performed on the memory rank.

2. The method according to claim 1, characterized in that, The plurality of storage ranks correspond to the same channel between the memory controller and the memory.

3. The method according to claim 2, characterized in that, The channel includes multiple pseudo-channels, and the multiple storage ranks include the storage rank corresponding to each pseudo-channel among the multiple pseudo-channels.

4. The method according to claim 2, characterized in that, The channel corresponds to multiple pairs of parity storage ranks in the memory. The multiple storage ranks include at least two pairs of even storage ranks or odd storage ranks. Each pair of parity storage ranks includes one odd storage rank and one even storage rank.

5. The method according to claim 2, characterized in that, The plurality of storage ranks includes each storage rank corresponding to the channel.

6. The method according to claim 1, characterized in that, The first entry also includes a sending method identifier, which indicates the sending method of the plurality of commands; For each first entry read, based on the enable identifier and description information in the first entry, multiple commands are sent to the memory, including: For each first entry read, the plurality of commands are generated based on the enable identifier and the description information in the first entry; The plurality of commands are sent to the memory according to the sending method indicated by the sending method identifier.

7. The method according to claim 6, characterized in that, The plurality of storage ranks includes a first storage rank and a second storage rank, and the plurality of commands includes a first command and a second command, wherein the first command instructs to perform the memory operation on the first storage rank, and the second command instructs to perform the memory operation on the second storage rank; The transmission method is a serial transmission method; Sending the plurality of commands to the memory according to the sending method indicated by the sending method identifier includes: First, one of the multiple commands is sent to the memory. After a preset time period, the other of the multiple commands is sent to the memory.

8. The method according to claim 7, characterized in that, The memory operation is a configuration operation of the registers in the memory rank.

9. The method according to claim 6, characterized in that, The transmission method is a parallel transmission method; Sending the plurality of commands to the memory according to the sending method indicated by the sending method identifier includes: The multiple commands are sent to the memory in parallel.

10. The method according to claim 9, characterized in that, The memory operation is an operation on the memory cells in the memory rank.

11. The method according to claim 1, characterized in that, The first entry also includes an enable flag corresponding to the target scenario, the enable flag indicating that the memory operation corresponds to the target scenario; The step of reading the multiple first entries in the cache when the read condition is met includes: In response to the activation of the target scenario, the plurality of first entries in the cache are read.

12. A command sending device, characterized in that, Applied to a memory controller, the device includes: A read module is used to read the multiple first entries in the cache when the read condition is met. The first entries include description information of memory operations and enable flags corresponding to multiple storage ranks in the memory. The enable flags indicate that the memory operation is performed on the corresponding storage rank. The sending module is configured to send multiple commands to the memory based on the enable identifier and the description information in the first entry for each first entry read. The commands instruct the memory operation to be performed on the memory rank.

13. A memory controller, characterized in that, The memory controller includes a cache and a control chip. The cache is used to cache a first entry, which indicates the same memory operation to be performed on multiple memory ranks in the memory. The control chip is used to execute the command sending method according to any one of claims 1-11.

14. A storage system, characterized in that, The storage system includes a memory controller and a memory, the memory controller being used to control the memory, and the memory controller being used to execute the command sending method according to any one of claims 1-11.

15. A computer-readable storage medium, characterized in that, When at least one instruction in the computer-readable storage medium is executed by one or more processors in the memory controller, the memory controller is enabled to perform the command sending method as described in any one of claims 1-11.

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