A solid state disk life prediction method and device, electronic equipment and storage medium

Abstract

This application discloses a method, apparatus, electronic device, and storage medium for predicting the lifespan of a solid-state drive (SSD). It relates to the field of SSD technology and includes a method, apparatus, electronic device, and storage medium for predicting the lifespan of a SSD. The method selects a targeted degradation expert model based on the particle type. In the case of a hybrid SSD containing different particle types, the remaining lifespan prediction result of the SSD is determined based on the particle remaining lifespan output by the selected multiple targeted degradation expert models, thereby improving the accuracy of the remaining lifespan prediction result.

Description

Technical Field

[0001] This application relates to the field of solid-state drive technology, and in particular to a method, apparatus, electronic device and storage medium for predicting the lifespan of a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs) use NAND flash memory as their primary storage medium. NAND flash memory has a limited number of write cycles, making it prone to read / write errors or sudden failures near the end of its lifespan. Related technologies typically utilize machine learning models to analyze the degradation trends of SSDs in order to predict their remaining lifespan.

[0003] However, different types of NAND flash memory chips have different storage structures and degradation characteristics. It is difficult to effectively predict the degradation characteristics of different NAND types using a unified lifetime prediction model. In particular, for hybrid SSDs containing different types of NAND flash memory chips, the accuracy of SSD lifetime prediction results obtained by using a unified lifetime prediction model is low. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, and storage medium for predicting the lifespan of a solid-state drive (SSD), in order to at least solve the problem of low accuracy in predicting the lifespan of SSDs for different types of NAND flash memory in the related art.

[0005] This application provides a method for predicting the lifespan of a solid-state drive, including: Obtain multimodal degradation data, workload data, and flash memory chip type information from the flash memory chips in the solid-state drive; Based on multimodal degradation data and workload data, the degradation timing characteristics of solid-state drives were determined; Based on the type information, at least one target degradation expert model is selected from multiple preset degradation expert models; wherein, the multiple degradation expert models include expert models corresponding to multiple single particle types and expert models corresponding to mixed particle types; Based on at least one target degradation expert model, the remaining lifespan of the corresponding flash memory chip type is determined according to the degradation timing characteristics. The remaining lifespan prediction of the solid-state drive is determined based on the remaining lifespan of the particles obtained from at least one target degradation expert model.

[0006] This application also provides a solid-state drive lifespan prediction device, comprising: The acquisition module is used to acquire multimodal degradation data, workload data, and flash memory chip type information of the flash memory chips in the solid-state drive. The first determination module is used to determine the degradation timing characteristics of the solid-state drive based on multimodal degradation data and workload data; The filtering module is used to filter at least one target degradation expert model from multiple preset degradation expert models based on type information; wherein, the multiple degradation expert models include expert models corresponding to multiple single particle types and expert models corresponding to mixed particle types; The second determining module is used to determine the remaining lifespan of the corresponding flash memory chip type based on at least one target degradation expert model and according to the degradation timing characteristics. The prediction module is used to determine the predicted remaining lifespan of the solid-state drive based on the remaining lifespan of the particles obtained from at least one target degradation expert model.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described solid-state drive life prediction methods.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described solid-state drive life prediction methods.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described solid-state drive life prediction methods.

[0010] This application achieves the following: First, it obtains multimodal degradation data, workload data, and flash memory chip type information from the flash memory chips in the solid-state drive (SSD). Second, it determines the degradation timing characteristics of the SSD based on the multimodal degradation data and workload data. Third, it selects at least one target degradation expert model from multiple preset degradation expert models based on the type information. These multiple degradation expert models include expert models corresponding to various single chip types and expert models corresponding to mixed chip types. Fourth, based on the at least one target degradation expert model, it determines the remaining lifespan of the corresponding flash memory chip type according to the degradation timing characteristics. Finally, it determines the predicted remaining lifespan of the SSD based on the remaining lifespan of the chips obtained from the at least one target degradation expert model. This improves the accuracy of the remaining lifespan prediction by selecting a specific target degradation expert model based on the chip type. In the case of a mixed SSD containing different chip types, the remaining lifespan prediction is determined based on the remaining lifespan of the chips output by the selected multiple target degradation expert models. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating the solid-state drive lifespan prediction method provided in this application embodiment; Figure 2 A dynamic routing diagram illustrating the solid-state drive lifespan prediction method provided in this application embodiment; Figure 3 This is a schematic diagram of the solid-state drive life prediction device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] SSD lifespan prediction is a core technology in the storage field, its importance permeating the entire chain of data security, system operation, cost management, and technological iteration. In terms of data security, SSD NAND flash memory has a limited number of write cycles, making it prone to read / write errors or sudden failure near the end of its lifespan. Lifespan prediction can provide early warnings of these risks, buying valuable backup and migration time for important documents for individual users and business data for enterprises, preventing irreversible data loss at its source. Regarding system stability, in critical scenarios such as servers and data centers, SSD failure can lead to system crashes, service interruptions, user churn, and production stoppages. Lifespan prediction can identify aging devices in advance, allowing for replacement during off-peak hours and ensuring continuous business operation. In terms of cost control, accurate assessment of remaining lifespan avoids the resource waste of premature replacement and the emergency repair costs of delayed replacement, achieving a balance between cost and reliability in "on-demand replacement." From a user experience perspective, lifespan prediction can provide early warnings of performance degradation risks, helping to maintain system read / write speeds and operational efficiency. Furthermore, for data centers, predictive data can optimize storage resource allocation, matching SSDs with different remaining lifespans to appropriate tasks. For manufacturers, actual wear and tear data can inform R&D, optimizing flash memory processes and firmware algorithms, and driving upgrades to next-generation products. In summary, SSD lifespan prediction is a key support for ensuring data security, stable operation, cost control, and driving technological progress.

[0016] However, different types of NAND flash memory chips have different storage structures and degradation characteristics. It is difficult to effectively predict the degradation characteristics of different NAND types using a unified lifetime prediction model. In particular, for hybrid SSDs containing different types of NAND flash memory chips, the accuracy of SSD lifetime prediction results obtained by using a unified lifetime prediction model is low.

[0017] To address the aforementioned technical problems, this application provides a method, apparatus, electronic device, and storage medium for predicting the lifespan of a solid-state drive (SSD). By implementing the selection of a targeted degradation expert model based on particle type, in the case of a hybrid SSD containing different particle types, the remaining lifespan prediction result of the SSD is determined based on the particle remaining lifespan output by the selected multiple targeted degradation expert models, thereby improving the accuracy of the remaining lifespan prediction result.

[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] This application provides a method for predicting the lifespan of solid-state drives (SSDs), used to predict the lifespan of SSDs containing different types of flash memory chips. The execution subject of this application is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, or other electronic devices that can be used for SSD lifespan prediction.

[0020] like Figure 1 The diagram shown is a flowchart illustrating a solid-state drive lifespan prediction method provided in an embodiment of this application. The method includes: Step 101: Obtain multimodal degradation data, workload data, and flash memory chip type information from the flash memory chips in the solid-state drive.

[0021] Specifically, an integrated sensor array can monitor the physical degradation and environmental factors inside the SSD in real time, providing high-precision, multi-dimensional data (multimodal degradation data and workload data) for subsequent lifetime prediction. The sensor array includes a temperature sensor, a NAND SMART log read module, an LDPC decoder, a cache hit rate monitor, and a voltage drift monitor.

[0022] The temperature sensor monitors temperature changes in the NAND flash memory chip, as temperature directly affects the flash memory's write endurance and data retention capabilities. Specifically, it converts temperature changes into electrical signals based on thermistor or thermocouple effects. The sampling frequency is once per second. The NAND SMART log reading module reads the NAND flash memory's SMART (Self-Monitoring, Analysis and Reporting Technology) log to obtain key parameters such as write erasure cycles (PE), write amplification factor (WAF), and daily write volume (DWPD). Specifically, it communicates with the SSD controller via NVMe or SATA interfaces to extract predefined SMART attribute values. The sampling frequency is once per minute. The LDPC decoder monitors the raw bit error rate (RBER) to evaluate the read reliability of the NAND flash memory. During data reads, the LDPC (Low-Density Parity-Check) decoder records the number of corrected errors and calculates the RBER. The sampling frequency updates statistics after each read operation. The cache hit rate monitor monitors the SLC cache hit rate to evaluate data access patterns and cache efficiency. Specifically, it calculates the hit rate by statistically analyzing the number of cache accesses and hits. The sampling frequency is updated once per second. The voltage drift monitor is used to monitor the threshold voltage drift (ΔV) of NAND flash memory cells and evaluate voltage stability. Specifically, it calculates the voltage drift by periodically reading specific test pages and comparing the read voltage with a reference voltage. Sampling frequency: once per hour. The workload data includes the aforementioned DWPD and cache hit rate.

[0023] Specifically, the type information of the flash memory chips can be obtained by reading the chip type code returned by the ONFI protocol through the NAND ID parser. When the read code indicates a single chip type, it is directly identified as that type. When the read code indicates the presence of multiple chip types (e.g., a mix of SLC and QLC), it is further determined by combining the cache hit rate threshold. If the current cache hit rate is greater than the cache hit rate threshold, the current SSD is confirmed to be a hybrid chip architecture, and the flash memory chip type information is marked as Hybrid.

[0024] Step 102: Determine the degradation timing characteristics of the solid-state drive based on multimodal degradation data and workload data.

[0025] It should be noted that, due to the different acquisition frequencies of each sensor and the presence of noise in the raw data, preprocessing is required to construct degradation time-series features suitable for expert model input. Specifically, this includes: Data synchronization: Data with different sampling frequencies are aligned using timestamps so that data from different sources at the same time correspond on the timeline, forming a synchronized multidimensional data record.

[0026] Noise filtering: A Kalman filter is used to remove high-frequency noise from the temperature and voltage data. The Kalman filter can effectively estimate the true state of the system and reduce the impact of measurement noise on subsequent feature extraction.

[0027] Feature extraction: Statistical features are calculated within each time window. These features include: mean, which reflects the average level of the degradation index; variance, which reflects the severity of degradation fluctuations; and trend coefficient, which is obtained through linear fitting and reflects the rate of degradation change over time.

[0028] Sliding window reconstruction: The processed data is constructed into a time series feature matrix according to the preset window length and sliding step size, thus obtaining the degraded time series features.

[0029] Step 103: Based on the type information, select at least one target degradation expert model from a set of preset degradation expert models.

[0030] Among them, multiple degradation expert models include expert models corresponding to various single particle types and expert models corresponding to mixed particle types.

[0031] Specifically, multiple degradation expert models can be pre-built. By calling the sparse gated hybrid expert (MoE) architecture, the model can be dynamically routed to a dedicated sub-model based on the type information of the flash memory chips in the current solid-state drive. That is, at least one target degradation expert model that is specifically adapted to the type of flash memory chips in the current solid-state drive can be selected from the multiple pre-built degradation expert models.

[0032] Step 104: Based on at least one target degradation expert model, determine the remaining lifespan of the corresponding flash memory chip type according to the degradation timing characteristics.

[0033] Specifically, different target regression expert models determine the remaining lifespan of flash memory chips of different types based on the physical degradation mechanism of the chips and the degradation timing characteristics.

[0034] Step 105: Determine the predicted remaining lifespan of the solid-state drive based on the remaining lifespan of the particles obtained from at least one target degradation expert model.

[0035] Specifically, when only one target degradation expert model is selected, the remaining lifespan of the particles output by that model can be directly used as the prediction result of the remaining lifespan of the solid-state drive. When two or more target degradation expert models are selected, the remaining lifespan of the particles from each model is weighted and fused to obtain the prediction result of the remaining lifespan of the solid-state drive.

[0036] Specifically, in practical applications, the remaining lifetime prediction result (RUL) of the solid-state drive can be exposed (output) via NVMe-MI extended commands (latency <5ms). Hardware acceleration employs dynamic switching between ARM Cortex-M7 (SLC / MLC) and NPU (TLC / QLC / hybrid). DVFS adjustment targets include downclocking to 80% at temperatures >70°C and reducing power consumption by 37%. Through FP16 / INT8 quantization and Dynamic Voltage and Frequency Scaling (DVFS) technology, hardware acceleration and energy efficiency optimization of the model are achieved, ensuring real-time and low-power operation of the model on embedded devices, meeting the real-time prediction needs of data centers and enterprise-level storage systems.

[0037] Based on the above embodiments, as an implementable approach, in one embodiment, the flash memory chip type includes single-layer memory cell chips, the target degradation expert model includes an SLC model for predicting the remaining lifetime of single-layer memory cell chips, and based on at least one target degradation expert model, the remaining lifetime of chips of the corresponding flash memory chip type is determined according to degradation timing characteristics, including: Step 1041: Based on the SLC model and according to the degradation timing characteristics, determine the cumulative number of erase / write operations and the current temperature of a single-layer memory cell at the current moment. Step 1042: Determine the remaining lifespan of the single-layer storage cell based on the preset temperature acceleration coefficient, the maximum number of erase / write cycles of the single-layer storage cell, the cumulative number of erase / write cycles of the single-layer storage cell at the current moment, and the current temperature.

[0038] Specifically, the SLC model predicts the remaining lifetime of a single-level cell (SLC) by taking into account the effects of erase / write cycles and temperature on lifetime.

[0039] The input to the SLC model can be represented as: ,in, Indicates the current time The cumulative number of erase / write cycles, This represents the current temperature. The expression for the SLC model is as follows:

[0040] in, This indicates the remaining lifespan of the memory chips in a single-layer storage unit. This indicates the maximum number of erase / write cycles for a single-layer memory cell. and This represents the preset temperature acceleration factor, which can be calibrated using the Arrhenius equation.

[0041] It should be noted that the parameters involved in the calculations in the expressions of the various models provided in the embodiments of this application are all normalized parameters of the model, which are dimensionless parameters, and the expressions mainly express the basic principles of the model.

[0042] Based on the above embodiments, as an implementable approach, in one embodiment, the flash memory chip type includes dual-level memory cell chips, the target degradation expert model includes an MLC model for predicting the remaining lifetime of dual-level memory cell chips, and based on at least one target degradation expert model, the remaining lifetime of chips of the corresponding flash memory chip type is determined according to degradation timing characteristics, including: Step 1043: Based on the MLC model, extract the first time series features of the dual-layer memory cell particles from the degradation time series features; wherein, the first time series features include the cumulative number of erase / write operations, cross-cell coupling voltage, and write amplification factor of the dual-layer memory cell particles at the current time and within a preset historical period. Step 1044: Input the first time series features into the long short-term memory network layer of the MLC model to use the long short-term memory network layer to determine the nonlinear degradation time dependency of the two-layer storage unit particles in the preset historical period and obtain the first degradation state hidden vector. Step 1045: Input the first degraded state hidden vector into the multilayer perceptron layer of the MLC model, so as to perform nonlinear mapping on the first degraded state hidden vector through the multilayer perceptron layer to obtain the remaining lifetime of the dual-layer storage cell particles.

[0043] Specifically, the MLC model combines LSTM (Long Short-Term Memory) and MLP (Multi-Level Perceptron) layers to predict the remaining lifetime of a Multi-Level Cell (MLC) particle using first-time-series features (erasing / writing count, cross-cell coupling voltage, and write amplification factor).

[0044] The input to the Long Short-Term Memory (LSTM) network layer can be represented as: ,in, Indicates the current time The cumulative number of erase / write cycles, Indicates the cross-cell coupling voltage. This represents the amplification factor. The expression for the Long Short-Term Memory (LSTM) network layer is as follows:

[0045] in, express The first degenerate state hidden vector at time step 1.

[0046] Furthermore, the multilayer perceptron layer consists of a nonlinear mapping network composed of multiple fully connected layers and activation functions. In the MLC model, the MLP layer further maps the degraded state hidden vector output by the LSTM to the remaining lifetime value.

[0047] Specifically, in one embodiment, the flash memory chip type includes three-layer memory cell chips, and the target degradation expert model includes a TLC model for predicting the remaining lifetime of the three-layer memory cell chips. Based on the TLC model, a second time-series feature of the three-layer memory cell chips can be extracted from the degradation time-series features. The second time-series feature includes the cumulative number of erase / write operations, the cumulative original bit error rate caused by read interference, and the write amplification factor of the three-layer memory cell chips within the current time and a preset historical period. The second time-series feature is input into the bidirectional long short-term memory network layer of the TLC model to utilize the bidirectional long short-term memory network layer to process the second time-series feature along both the forward and reverse time sequences. Sequence features are encoded to determine the degradation time dependencies of the three-layer storage unit particles in both forward and backward directions, resulting in a second degradation state hidden vector for each time step. This second degradation state hidden vector is then input into the attention layer of the TLC model to calculate the attention weights for each time step. The second degradation state hidden vectors for each time step are then weighted and summed based on these attention weights to obtain a degradation context vector. The attention weights characterize the degree of influence of the degradation state at the corresponding time step on the remaining lifetime of the three-layer storage unit particles. Based on the degradation context vector, the remaining lifetime of the three-layer storage unit particles is determined.

[0048] Specifically, the TLC model combines bidirectional LSTM (Bi-LSTM) and an attention mechanism to predict the remaining lifetime of TLC particles using time-series features (number of erase / write cycles, cumulative raw bit error rate caused by read interference, and write amplification factor).

[0049] The second time series feature can be represented as: ,in, This represents the cumulative amount of raw bit error rate caused by read interference.

[0050] The expression for Bi-LSTM encoding is as follows:

[0051] in, This represents the time dependency of degradation of the three-layer memory cell granules in the forward direction. This represents the time dependency of degradation of the three-layer memory cell granules in the backward direction. Indicates time step The second degenerate state hidden vector has a time step range of 1 to L, where L represents the total number of time steps.

[0052] Furthermore, through the attention mechanism, the model can calculate a weight coefficient for each time step to characterize the degree of influence of the degradation state at that time step on the prediction result, and perform a weighted summation of the hidden vectors of each time step to obtain the degradation context vector. Finally, the degradation context vector is mapped to the remaining lifetime value.

[0053] The TLC model combines three types of features with different physical meanings—cumulative erase / write count, RBER accumulation, and write amplification factor—as input. Through a step-by-step nonlinear transformation using Bi-LSTM and attention layers, it can fully explore the interaction relationships between multi-dimensional features and adapt to the complex degradation mechanism of TLC particles.

[0054] Similarly, in one embodiment, the flash memory chip type includes four-layer memory cell chips, and the target degradation expert model includes a QLC model for predicting the remaining lifetime of the four-layer memory cell chips. Based on the QLC model, the multi-level voltage distribution entropy of the four-layer memory cell chips at multiple time steps within a preset historical period can be extracted from the degradation time-series features to obtain a third time-series feature; wherein, the multi-level voltage distribution entropy is used to characterize the degree of overlap of multiple level distributions in the four-layer memory cell chips; according to the third time-series feature, the input embedding vector corresponding to each time step is determined; a position encoding vector is added to the input embedding vector of each time step to obtain a time-series bit. An embedded vector sequence of location information is generated; where the location encoding vector is used to represent the temporal position of the corresponding time step within a preset historical period; the embedded vector sequence is input into the multi-head attention layer of the QLC model to perform multi-head self-attention calculation on the embedded vector sequence, determine the global degradation dependency relationship between the four-layer storage unit particles at different time steps, and obtain the attention output sequence; the attention output sequence is input into the feedforward network layer of the QLC model to perform nonlinear transformation on the attention output sequence to obtain the encoded feature sequence; based on the encoded feature sequence, the remaining lifetime of the four-layer storage unit particles is determined.

[0055] Specifically, the QLC model combines input embedding, multi-head attention mechanism and feedforward network in the Transformer architecture to predict the remaining lifetime of Quad-Level Cell (QLC) particles using time series features.

[0056] The input embedding vector maps the entropy value of the multi-level voltage distribution at each time step to a high-dimensional continuous vector for processing by the Transformer model. The embedding layer projects the scalar entropy value onto a vector space of a predetermined dimension through a linear transformation. The positional encoding vector represents the positional information of a time step within the sequence. Since the multi-head attention mechanism itself lacks sequence order awareness, a positional encoding needs to be explicitly added to each time step so that the model can utilize temporal order information. Positional encoding can employ sinusoidal positional encoding or learnable positional encoding.

[0057] Specifically, each attention head in the multi-head attention layer performs self-attention computation on the input embedding vector sequence, enabling direct dependency establishment between any two time steps in the sequence, thereby determining the global degradation association (global degradation dependency) between different time steps. The feedforward network layer consists of two fully connected layers and an activation function, performing position-by-position independent nonlinear transformations on the attention output sequence to improve the model's expressive power, obtaining the encoded feature sequence, and finally mapping the encoded feature sequence to the remaining lifetime value.

[0058] Specifically, the complex electrical degradation state of QLC particles is transformed into a single, computable statistical index through multi-level voltage distribution entropy, effectively extracting key degradation features that distinguish QLC particles from other particle types. The Transformer's multi-head self-attention mechanism enables direct correlation between any two time steps, overcoming the information forgetting problem of recurrent neural networks on long sequences and capturing long-term dependencies and abrupt changes in the QLC degradation process. Multi-head attention extracts degradation features in parallel from multiple representation subspaces, simultaneously focusing on degradation patterns at different time scales; the feedforward network layer further enhances nonlinear expressive power, enabling the model to adapt to the complex degradation patterns of QLC.

[0059] Specifically, in one embodiment, the flash memory chip type includes hybrid chips, and the target degradation expert model includes a hybrid model for predicting the remaining lifetime of the hybrid chips. Based on the hybrid model, the migration weight of data between each flash memory storage layer can be determined according to the degradation time sequence characteristics. Each flash memory storage layer corresponds to a different chip type, and data migrates between each flash memory storage layer according to a preset migration order. The remaining lifetime of the hybrid chips is determined based on the remaining lifetime of the chips corresponding to each flash memory storage layer and the impact of cross-flash memory storage layer data migration on the remaining lifetime of the chips, as represented by the migration weight.

[0060] For example, when the solid-state drive includes SLC and MLC particles, the selected target degradation expert model includes the SLC model, the MLC model, and the hybrid model; when the solid-state drive includes SLC, MLC, TLC, and QLC particles, the selected target degradation expert model includes the SLC model, the MLC model, the TLC model, the QLC model, and the hybrid model, and so on.

[0061] Specifically, the hybrid model world adopts Hybrid-Expert (hierarchical Markov coupling) to abstract the hybrid particle SSD as a four-state degenerate system, with each state corresponding to a particle type, and the state space... During state transitions, data migrates (or is written back in reverse) in the order SLC→MLC→TLC→QLC, forming a hierarchical Markov chain. Taking the migration from the SLC storage layer to the MLC storage layer as an example, the forward migration weight between the SLC and MLC storage layers can be expressed as: , This represents the time constant of heat decay. This indicates the degradation timing characteristics, specifically the access frequency of the solid-state drive (SSD). When data is re-marked as hot data, a write-back transition is triggered (e.g., QLC → SLC). , This indicates the threshold for judging hot data.

[0062] Since data migration incurs additional physical writes to the target storage layer, a higher migration weight results in greater write / erase overhead for the target storage layer within the same timeframe. This application's embodiments introduce a trans-state penalty factor. For the The base remaining lifetime of each storage layer is adjusted. The formula for calculating the transstate penalty factor is:

[0063] The remaining lifetime of the mixed particles is the system-level lifetime, governed by the shortest subsystem, and is expressed as follows:

[0064] This allows the impact of cross-layer data migration on lifetime to be quantified and coupled to the remaining lifetime of each storage layer, further improving the accuracy of remaining lifetime prediction results.

[0065] The hybrid model includes a real-time update mechanism: Online learning: Update state transition weights every Δt period Based on actual access frequency.

[0066] Adaptive threshold: dynamically adjusted To balance cache hit rate and cache lifespan.

[0067] For SSDs based on hybrid NAND flash memory, a hierarchical Markov process was established. By integrating the degradation states of the SLC cache layer and QLC data layer through the shortest subsystem dominance principle and introducing a cache failure penalty factor, system-level lifetime prediction for hybrid NAND flash memory SSDs was achieved. The impact of cache failure on overall lifetime was taken into account, and prediction results that are closer to reality were provided.

[0068] Based on the above embodiments, as an implementable approach, in one embodiment, the remaining lifespan prediction result of the solid-state drive is determined according to the remaining lifespan of the particles obtained from at least one target degradation expert model, including: Step 1051: Input the degradation time series features into the gating network, so as to use the gating network to calculate the fusion weights corresponding to each target degradation expert model according to the degradation time series features; Step 1052: Determine the predicted remaining lifespan of the solid-state drive based on the remaining lifespan of the particles output by the expert models for each target degradation and the corresponding fusion weights.

[0069] Specifically, such as Figure 2The diagram shown illustrates the dynamic routing of the solid-state drive lifetime prediction method provided in this application embodiment. It employs a sparse gated hybrid expert structure, dynamically selecting the most suitable expert model for prediction. Load balancing loss prevents gate collapse, improving the model's generalization ability and robustness, ensuring stable high-precision predictions under different workloads and particle types. The gated network (gating fusion mechanism) uses a sparse gated hybrid expert (MoE) structure, allocating weights to different expert models through a gating function, and finally fusing the prediction results of each expert to obtain the predicted remaining lifetime (RUL). Taking a solid-state drive with a mixture of SLC, MLC, TLC, and QLC particles as an example, the following is a detailed description of each part: Gating function:

[0070] Where K=5 (corresponding to SLC / MLC / TLC / QLC / Hybrid expert models).

[0071] Final prediction:

[0072] Regularization: Preventing gating crashes through load balancing losses.

[0073] in, g k (x) represents the fusion weight of the k-th back-to-back expert model. k and b k These are the weight vector and bias term corresponding to the k-th degenerate expert model, respectively. K=5, corresponding to the five degenerate expert models: SLC, MLC, TLC, QLC, and Hybrid. The summation term in the denominator is used to ensure that the sum of all weights is 1, i.e. RUL pred This is the final predicted remaining lifespan (the predicted remaining lifespan of the solid-state drive). RUL k This represents the remaining particle lifetime predicted by the k-th degradation expert model. The fusion weights of the regression expert models are calculated using a gating function. L aux It is an auxiliary loss function used for regularization. k P is the loading factor of the k-th degenerate expert model, used to balance the loading of each degenerate expert model. k It is the average weight of the k-th degenerate expert model, expressed as the expected value E[g]. k (x)] is calculated.

[0074] It should be further explained that the solid-state drive (SSD) lifespan prediction method provided in this application formalizes SSD lifespan prediction as a multimodal time-series regression problem, with the objective function being:

[0075] Where, x i Let Ω(θ) be the multidimensional degradation feature of the i-th SSD, and let Ω(θ) be the regularization term for cross-granular knowledge transfer. By introducing a late prediction penalty term, the penalty is increased for predicted values ​​that are greater than the true values; this effectively reduces the late prediction rate, improves the reliability of predictions, and avoids data loss and business interruption caused by prediction errors. Through cross-granular knowledge transfer technology, TLC / QLC models can be initialized using the parameters of already trained SLC / MLC models, reducing the need for training data, accelerating the model training process, reducing dependence on large-scale labeled data, and improving the practicality and scalability of the model.

[0076] The solid-state drive (SSD) lifespan prediction method provided in this application acquires multimodal degradation data, workload data, and flash memory chip type information of the SSD; determines the degradation timing characteristics of the SSD based on the multimodal degradation data and workload data; selects at least one target degradation expert model from a set of preset degradation expert models based on the type information; wherein the multiple degradation expert models include expert models corresponding to multiple single chip types and expert models corresponding to mixed chip types; based on the at least one target degradation expert model, determines the remaining lifespan of the corresponding flash memory chip type according to the degradation timing characteristics; and determines the predicted remaining lifespan of the SSD based on the remaining lifespan of the chips obtained from the at least one target degradation expert model. This method achieves the selection of a targeted degradation expert model based on chip type. In the case of a mixed SSD containing different chip types, the remaining lifespan prediction result of the SSD is determined based on the remaining lifespan of the chips output by the selected multiple target degradation expert models, thus improving the accuracy of the remaining lifespan prediction result.

[0077] Furthermore, a multimodal NAND-aware hierarchical-expert-fusion (HEF) framework was proposed, and dedicated expert models were designed for the heterogeneous degradation mechanisms of SLC, MLC, TLC, QLC, and hybrid NAND SSDs. Each expert model is optimized according to the physical degradation characteristics of NAND particles to ensure prediction accuracy, solving the problem of traditional models applying a one-size-fits-all approach when dealing with different types of NAND particles, and significantly improving prediction accuracy.

[0078] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0079] The embodiments of this application also provide a solid-state drive (SSD) lifespan prediction device for executing the SSD lifespan prediction method provided in the above embodiments.

[0080] like Figure 3 The diagram shown is a structural schematic of a solid-state drive (SSD) lifespan prediction device provided in an embodiment of this application. The SSD lifespan prediction device 30 includes: an acquisition module 301, a first determination module 302, a filtering module 303, a second determination module 304, and a prediction module 305.

[0081] The system includes: an acquisition module for acquiring multimodal degradation data, workload data, and flash memory chip type information of the solid-state drive (SSD); a first determination module for determining the degradation timing characteristics of the SSD based on the multimodal degradation data and workload data; a filtering module for selecting at least one target degradation expert model from a set of preset degradation expert models based on the type information; wherein the multiple degradation expert models include expert models corresponding to multiple single chip types and expert models corresponding to mixed chip types; a second determination module for determining the remaining lifespan of the corresponding flash memory chip type based on the degradation timing characteristics using at least one target degradation expert model; and a prediction module for determining the predicted remaining lifespan of the SSD based on the remaining lifespan of the chips obtained from at least one target degradation expert model.

[0082] Specifically, in one embodiment, the flash memory chip type includes single-layer memory cell chips, the target degradation expert model includes an SLC model for predicting the remaining lifetime of single-layer memory cell chips, and the second determining module is specifically used for: Based on the SLC model and the degradation timing characteristics, the cumulative number of erase / write operations and the current temperature of a single-layer memory cell at the current moment are determined. The remaining lifespan of a single-layer storage cell is determined based on the preset temperature acceleration factor, the maximum number of erase / write cycles for a single-layer storage cell, the cumulative number of erase / write cycles for a single-layer storage cell at the current moment, and the current temperature.

[0083] Specifically, in one embodiment, the flash memory chip type includes dual-level memory cell chips, the target degradation expert model includes an MLC model for predicting the remaining lifetime of dual-level memory cell chips, and the second determining module is specifically used for: Based on the MLC model, the first time series features of the dual-layer memory cell particles are extracted from the degradation time series features; wherein, the first time series features include the cumulative number of erase and write operations, cross-cell coupling voltage, and write amplification factor of the dual-layer memory cell particles at the current time and within a preset historical period. The first time series features are input into the long short-term memory network layer of the MLC model to determine the nonlinear degradation time dependency of the two-layer storage unit particles within a preset historical period, thereby obtaining the first degradation state hidden vector. The first degraded state hidden vector is input into the multilayer perceptron layer of the MLC model, and the multilayer perceptron layer performs a nonlinear mapping on the first degraded state hidden vector to obtain the remaining lifetime of the particles in the dual-layer storage unit.

[0084] Specifically, in one embodiment, the flash memory chip type includes three-layer memory cell chips, the target degradation expert model includes a TLC model for predicting the remaining lifetime of the three-layer memory cell chips, and the second determining module is specifically used for: Based on the TLC model, a second time series feature of the three-layer memory cell particles is extracted from the degradation time series features; wherein, the second time series feature includes the cumulative number of erase and write operations of the three-layer memory cell particles at the current time and within a preset historical period, the cumulative amount of the original bit error rate caused by read interference, and the write amplification factor; The second time series features are input into the bidirectional long short-term memory network layer of the TLC model. The bidirectional long short-term memory network layer encodes the second time series features in both forward and reverse time order, respectively, to determine the degradation time dependency of the three-layer storage unit particles in both forward and backward directions, and to obtain the second degradation state hidden vector at each time step. The second degraded state hidden vector at each time step is input into the attention layer of the TLC model to calculate the attention weights corresponding to each time step. The second degraded state hidden vectors at each time step are then weighted and summed according to the attention weights to obtain the degraded context vector. The attention weights are used to characterize the degree of influence of the degraded state at the corresponding time step on the remaining lifetime of the three-layer memory cell particles. The remaining lifetime of the three-level memory cell particles is determined based on the degradation context vector.

[0085] Specifically, in one embodiment, the flash memory chip type includes four-layer memory cell chips, the target degradation expert model includes a QLC model for predicting the remaining lifetime of the four-layer memory cell chips, and the second determination module is specifically used for: Based on the QLC model, the multi-level voltage distribution entropy of four-layer memory cell particles in multiple time steps within a preset historical period is extracted from the degradation time series features to obtain the third time series feature; among them, the multi-level voltage distribution entropy is used to characterize the degree of overlap of multiple level distributions in the four-layer memory cell particles. Based on the third time series features, determine the input embedding vector corresponding to each time step; Add a position encoding vector to the input embedding vector of each time step to obtain an embedding vector sequence with temporal position information; wherein, the position encoding vector is used to represent the temporal position of the corresponding time step within a preset historical period. The embedded vector sequence is input into the multi-head attention layer of the QLC model to perform multi-head self-attention calculation on the embedded vector sequence, determine the global degradation dependency of the four-layer storage unit granules at different time steps, and obtain the attention output sequence. The attention output sequence is input into the feedforward network layer of the QLC model, so that the feedforward network layer can perform a non-linear transformation on the attention output sequence to obtain the encoded feature sequence. Based on the encoded feature sequence, the remaining lifespan of the four-layer storage unit particles is determined.

[0086] Specifically, in one embodiment, the flash memory chip type includes hybrid chips, the target degradation expert model includes a hybrid model for predicting the remaining lifetime of the hybrid chips, and the second determining module is specifically used for: Based on the hybrid model, the migration weight of data between each flash memory storage layer is determined according to the degradation time sequence characteristics; where each flash memory storage layer corresponds to a different granularity type, and data is migrated between each flash memory storage layer according to a preset migration order; The remaining lifetime of hybrid NAND flash memory is determined based on the impact of cross-flash memory layer data migration on the remaining lifetime of NAND flash memory, characterized by the remaining lifetime of NAND flash memory corresponding to each flash memory layer and the migration weight.

[0087] Specifically, in one embodiment, the prediction module is specifically used for: The degradation time-series features are input into the gating network, and the gating network is used to calculate the fusion weights corresponding to each target degradation expert model according to the degradation time-series features. Based on the remaining lifetime of the particles output by the expert models for each target degradation and the corresponding fusion weights, the predicted remaining lifetime of the solid-state drive is determined.

[0088] For a description of the features in the embodiment corresponding to the solid-state drive life prediction device, please refer to the relevant description of the embodiment corresponding to the solid-state drive life prediction method, which will not be repeated here.

[0089] Embodiments of this application also provide an electronic device, such as... Figure 4The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to execute the steps in any of the above-described embodiments of the solid-state drive life prediction method.

[0090] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the solid-state drive life prediction method when it is run.

[0091] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0092] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the solid-state drive life prediction method.

[0093] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the solid-state drive lifetime prediction method.

[0094] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0095] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0096] The foregoing has provided a detailed description of a solid-state drive (SSD) lifespan prediction method, apparatus, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for predicting the lifespan of a solid-state drive, characterized in that, include: Obtain multimodal degradation data, workload data, and type information of the flash memory chips in the solid-state drive; Based on the multimodal degradation data and workload data, the degradation timing characteristics of the solid-state drive are determined; Based on the type information, at least one target degradation expert model is selected from a plurality of preset degradation expert models; wherein, the plurality of degradation expert models include expert models corresponding to a plurality of single particle types and expert models corresponding to mixed particle types; Based on the at least one target degradation expert model, the remaining lifespan of the corresponding flash memory chip type is determined according to the degradation timing characteristics. The remaining lifespan prediction result of the solid-state drive is determined based on the remaining lifespan of the particles obtained from the at least one target degradation expert model.

2. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The flash memory chip type includes single-layer memory cell chips, and the target degradation expert model includes an SLC model for predicting the remaining lifetime of single-layer memory cell chips. The step of determining the remaining lifetime of chips of the corresponding flash memory chip type based on the at least one target degradation expert model and according to the degradation timing characteristics includes: Based on the SLC model, and according to the degradation timing characteristics, the cumulative number of erase / write operations and the current temperature of the single-layer memory cell particle at the current moment are determined; The remaining lifespan of a single-layer storage unit particle is determined based on a preset temperature acceleration coefficient, the maximum number of erase / write cycles for a single-layer storage unit particle, the cumulative number of erase / write cycles for the single-layer storage unit particle at the current moment, and the current temperature.

3. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The flash memory chip type includes dual-level memory cell (MLC) chips, and the target degradation expert model includes an MLC model for predicting the remaining lifetime of MLC chips. The step of determining the remaining lifetime of chips of the corresponding flash memory chip type based on the at least one target degradation expert model and according to the degradation timing characteristics includes: Based on the MLC model, the first time series features of the dual-layer memory cell particle are extracted from the degradation time series features; wherein, the first time series features include the cumulative number of erase / write operations, cross-cell coupling voltage, and write amplification factor of the dual-layer memory cell particle at the current time and within a preset historical period. The first time series features are input into the long short-term memory network layer of the MLC model to determine the nonlinear degradation time dependency of the two-layer storage unit particles in the preset historical period, thereby obtaining the first degradation state hidden vector. The first degraded state hidden vector is input into the multilayer perceptron layer of the MLC model, so that the first degraded state hidden vector is nonlinearly mapped by the multilayer perceptron layer to obtain the remaining lifetime of the particle of the dual-layer storage unit.

4. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The flash memory chip type includes three-level memory cell chips, and the target degradation expert model includes a TLC model for predicting the remaining lifetime of three-level memory cell chips. The step of determining the remaining lifetime of chips of the corresponding flash memory chip type based on the at least one target degradation expert model and according to the degradation timing characteristics includes: Based on the TLC model, a second time series feature of the three-layer memory cell particle is extracted from the degradation time series feature; wherein, the second time series feature includes the cumulative number of erase / write operations of the three-layer memory cell particle at the current time and within a preset historical period, the cumulative amount of the original bit error rate caused by read interference, and the write amplification factor; The second time series feature is input into the bidirectional long short-term memory network layer of the TLC model, so that the bidirectional long short-term memory network layer encodes the second time series feature in forward and reverse time order respectively, determines the degradation time dependency of the three-layer storage unit particles in the forward and backward directions, and obtains the second degradation state hidden vector at each time step. The second degradation state hidden vector of each time step is input into the attention layer of the TLC model to calculate the attention weight corresponding to each time step. The second degradation state hidden vector of each time step is then weighted and summed according to the attention weight to obtain the degradation context vector. The attention weight is used to characterize the degree of influence of the degradation state of the corresponding time step on the remaining lifetime of the three-layer storage cell particles. The remaining lifetime of the three-layer storage cell particles is determined based on the degradation context vector.

5. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The flash memory chip type includes four-layer memory cell chips, and the target degradation expert model includes a QLC model for predicting the remaining lifetime of four-layer memory cell chips. The step of determining the remaining lifetime of chips of the corresponding flash memory chip type based on the at least one target degradation expert model and according to the degradation timing characteristics includes: Based on the QLC model, the multi-level voltage distribution entropy of the four-layer memory cell particles in multiple time steps within a preset historical period is extracted from the degradation time series features to obtain the third time series features; wherein, the multi-level voltage distribution entropy is used to characterize the degree of overlap of multiple level distributions in the four-layer memory cell particles; Based on the third time series features, determine the input embedding vector corresponding to each time step; A position encoding vector is added to the input embedding vector of each time step to obtain an embedding vector sequence with temporal position information; wherein, the position encoding vector is used to characterize the temporal position of the corresponding time step within the preset historical period. The embedded vector sequence is input into the multi-head attention layer of the QLC model to perform multi-head self-attention calculation on the embedded vector sequence, determine the global degradation dependency relationship of the four-layer storage unit granules at different time steps, and obtain the attention output sequence. The attention output sequence is input into the feedforward network layer of the QLC model to perform a nonlinear transformation on the attention output sequence using the feedforward network layer, thereby obtaining an encoded feature sequence. Based on the encoded feature sequence, the remaining lifespan of the particles in the four-layer storage unit is determined.

6. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The flash memory chip type includes hybrid chips, and the target degradation expert model includes a hybrid model for predicting the remaining lifetime of hybrid chips. The step of determining the remaining lifetime of chips corresponding to the flash memory chip type based on the at least one target degradation expert model and the degradation timing characteristics includes: Based on the hybrid model, the migration weight of data between each flash memory storage layer is determined according to the degradation time sequence characteristics; wherein, each flash memory storage layer corresponds to a different particle type, and data is migrated between the flash memory storage layers according to a preset migration order; The remaining lifetime of the hybrid particles is determined based on the remaining lifetime of the particles corresponding to each flash memory layer and the impact of cross-flash memory layer data migration on the remaining lifetime of the particles, as represented by the migration weight.

7. The solid-state drive lifespan prediction method according to claim 1, characterized in that, The step of determining the predicted remaining lifespan of the solid-state drive based on the remaining lifespan of the particles obtained from the at least one target degradation expert model includes: The degradation time-series features are input into a gating network, and the gating network is used to calculate the fusion weights corresponding to each target degradation expert model based on the degradation time-series features. The remaining lifespan prediction result of the solid-state drive is determined based on the particle remaining lifespan output by each target degradation expert model and the corresponding fusion weight.

8. A solid-state drive lifespan prediction device, characterized in that, include: The acquisition module is used to acquire multimodal degradation data, workload data, and type information of the flash memory chips in the solid-state drive. The first determining module is used to determine the degradation timing characteristics of the solid-state drive based on the multimodal degradation data and workload data. The filtering module is used to filter at least one target degradation expert model from a plurality of preset degradation expert models based on the type information; wherein, the plurality of degradation expert models include expert models corresponding to a plurality of single particle types and expert models corresponding to mixed particle types; The second determining module is used to determine the remaining lifespan of the corresponding flash memory chip type based on the at least one target degradation expert model and the degradation timing characteristics. The prediction module is used to determine the predicted remaining lifespan of the solid-state drive based on the remaining lifespan of the particles obtained from the at least one target degradation expert model.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the solid-state drive lifetime prediction method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the solid-state drive lifetime prediction method as described in any one of claims 1 to 7.

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