Method, system-on-chip, device, medium and program product for managing addresses

Abstract

A method, system-on-a-chip (SoC), device, medium, and program product for address management are provided, relating to the computer field. The SoC includes interconnect circuitry, a memory controller, and memory. The method includes: acquiring at least one faulty physical address of the memory and address mapping configuration information; converting the faulty physical address to a first local interconnect address based on the address mapping configuration information; determining a second local interconnect address from a first address range; configuring a remapping relationship between the first and second local interconnect addresses in the memory controller; receiving a memory access request; and in response to a third local interconnect address matching the first local interconnect address, remapping the third local interconnect address based on the second local interconnect address, and converting the remapped local interconnect address to a target physical address of the memory. This allows for hardware isolation of faulty pages via the memory controller and reduces software intervention and memory access processing overhead.

Description

Technical Field

[0001] The examples in this article generally relate to the computer field, and in particular to methods, systems-on-a-chip, devices, media, and program products for managing addresses. Background Technology

[0002] The physical location of a memory failure can occur during manufacturing, packaging, or operation. The number of redundant rows within a memory chip is typically limited by the memory bank structure, making it difficult to cover failures exceeding the internal redundancy capacity.

[0003] Some on-chip systems lack a memory management unit that manages address mapping via page tables. Further improvements are needed to isolate the physical location of faults without relying on page tables and to reduce runtime address processing overhead. Summary of the Invention

[0004] Some embodiments of this disclosure provide schemes for managing addresses with the aim of at least partially addressing one or more of the problems described above and other potential problems.

[0005] In a first aspect of this document, a method for managing addresses is provided. The method is applied to a system-on-a-chip (SoC), which includes interconnect circuitry, a memory controller, and memory. The method includes: acquiring at least one faulty physical address of the memory and address mapping configuration information, the address mapping configuration information describing the mapping relationship between a local interconnect address received by the memory controller and a physical address of the memory; converting the faulty physical address to a first local interconnect address based on the address mapping configuration information; determining a second local interconnect address from a first address range and configuring a remapping relationship between the first and second local interconnect addresses in the memory controller, the first address range being located in the local interconnect address space of the memory controller and not belonging to the allocation address range of service data; receiving a memory access request, the memory access request including a third local interconnect address; and in response to a match between the third local interconnect address and the first local interconnect address, remapping the third local interconnect address based on the second local interconnect address, and converting the remapped local interconnect address to a target physical address of the memory based on the address mapping configuration information to access the memory.

[0006] In a second aspect of this document, a system-on-a-chip (SoC) is provided. The SoC includes interconnect circuitry, a memory controller, and memory. The SoC further includes: an acquisition unit configured to acquire at least one faulty physical address of the memory and address mapping configuration information, the address mapping configuration information describing the mapping relationship between a local interconnect address received by the memory controller and a physical address of the memory; a conversion unit configured to convert the faulty physical address into a first local interconnect address based on the address mapping configuration information; a configuration unit configured to determine a second local interconnect address from a first address range and configure a remapping relationship between the first and second local interconnect addresses in the memory controller, the first address range being located in the local interconnect address space of the memory controller and not belonging to the allocation address range of service data; a receiving unit configured to receive a memory access request, the memory access request including a third local interconnect address; and an address processing unit configured to, in response to a match between the third local interconnect address and the first local interconnect address, remap the third local interconnect address based on the second local interconnect address, and convert the remapped local interconnect address into a target physical address of the memory based on the address mapping configuration information to access the memory.

[0007] In a third aspect of this document, an electronic device is provided. The electronic device includes at least one processing unit and at least one memory. The at least one memory is coupled to the at least one processing unit and stores instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the electronic device to perform the method of the first aspect.

[0008] In a fourth aspect of this document, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. The computer program can be executed by a processor to implement the method of the first aspect.

[0009] In a fifth aspect of this document, a computer program product is provided. This computer program product is tangibly stored in a computer storage medium and includes computer-executable instructions. When executed by a device, the computer-executable instructions cause the device to perform the method of the first aspect.

[0010] In this way, the memory controller can redirect accesses to faulty physical locations to available physical locations corresponding to reserved address ranges. This address processing does not rely on page tables and reduces software address lookups and branching during business operations.

[0011] It should be understood that the content described in this section is not intended to limit the key or important features of the examples in this article, nor is it intended to restrict the scope of the solution. Other features will become readily apparent from the following description. Attached Figure Description

[0012] The above and other features, advantages, and aspects of the various examples herein will become more apparent when taken in conjunction with the accompanying drawings and the following detailed description. In the accompanying drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic diagram of the example environment is shown; Figure 2 Flowcharts are shown for methods used to manage addresses in several scenarios; Figure 3 The diagram illustrates several scenarios of multi-memory address translation architectures; Figure 4 Block diagrams of on-chip systems for managing addresses are shown in some scenarios; Figure 5 A block diagram is shown of an electronic device capable of implementing one or more examples. Detailed Implementation

[0013] The examples in this document will now be described in more detail with reference to the accompanying drawings. While some examples are shown in the drawings, it should be understood that solutions can be implemented in various forms and should not be construed as limited to the examples presented herein. Rather, these examples are provided to provide a more thorough and complete understanding of the solutions. It should be understood that the drawings and examples in this document are for illustrative purposes only and are not intended to limit the scope of protection of the solutions.

[0014] It should be noted that the headings of any section / subsection provided herein are not restrictive. Various examples are described throughout this document, and examples of any type may be included under any section / subsection. Furthermore, examples described in any section / subsection may be combined in any way with any other examples described in the same section / subsection and / or different sections / subsections.

[0015] In the description of the examples in this document, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an example" or "the example" should be understood as "at least one example". The term "some examples" should be understood as "at least some examples". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0016] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, when implementing each example, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained through appropriate means, in accordance with relevant laws and regulations. The specific methods of notification and / or authorization can vary depending on the actual situation and application scenario; the scope of the solution is not limited in this regard.

[0017] In this manual and the examples, any solutions involving the processing of personal information will be processed only on the premise of a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0018] The term “System on Chip (SoC)” as used in this article refers to an integrated system that integrates processing devices, interconnect circuitry, memory controllers, and other functional circuitry, which can be implemented as a single chip or a combination of chips coupled together.

[0019] As used herein, the term "interconnect circuitry" refers to circuitry that transmits address, data, and control information between multiple functional components of a system-on-a-chip. Interconnect circuitry may include a network on chip (NoC), a bus, or a crossbar switch.

[0020] As used in this article, the term "memory controller" refers to the control circuit located between the interconnect circuitry and the memory, which performs address translation, request scheduling, and read / write control.

[0021] As used in this document, the term "memory" refers to a storage medium accessed via physical addresses. Memory may include Double Data Rate (DDR) memory, High Bandwidth Memory (HBM), or other Dynamic Random Access Memory (DRAM).

[0022] The term "fault physical address" as used in this article refers to the address of the fault storage location in the memory physical address field. The fault storage location can correspond to a fault line, a fault page, or a fault point within it.

[0023] The term "address mapping configuration information" as used in this article refers to information describing the correspondence between address bits of the local interconnect address and the memory physical address field. This information can be provided by the registers of the memory controller.

[0024] The term "local interconnect address" as used in this document refers to an address used in the local address space of a single memory controller. This address is received by the corresponding memory controller and further translated into a physical memory address.

[0025] The term “global interconnect address” as used in this article refers to an address used in the interconnect address space of an on-chip system and that can be routed to one of a number of memory controllers.

[0026] The term "remapping relationship" as used in this article refers to the address mapping relationship that directs the input address corresponding to the fault storage location to the output address corresponding to the repair storage location.

[0027] The term "first local interconnect address" as used in this document refers to the local interconnect address corresponding to the faulty storage location and used as the remapping input. The second local interconnect address is the local interconnect address corresponding to the repair storage location within the reserved interval. The third local interconnect address is the local interconnect address to be accessed carried in the memory access request.

[0028] As used in this article, the term "first address range" refers to a reserved range in the local interconnect address space of a single memory controller. The second address range is a reserved range in the system-on-chip global interconnect address space.

[0029] The term “address range for business data” as used in this article refers to the set of addresses that the on-chip system is allowed to use when allocating storage locations for business data, excluding address ranges reserved as repair resources.

[0030] The term "memory access request" as used in this article refers to a request to read or write data to memory, which carries at least the address to be accessed, and may also carry data, length, and read / write type.

[0031] The term "memory management unit" as used in this article refers to the hardware unit that manages processor access addresses through address translation structures such as page tables. The memory management unit can also be called the Memory Management Unit (MMU).

[0032] As used in this document, the term "configuration register" refers to a register in the memory controller that stores address mapping parameters or remapping parameters. Configuration registers may include the Control and Status Register (CSR).

[0033] The term "interleaving rule" as used in this article refers to the rule for allocating global interconnect addresses to different memory controllers according to one or more address bits or address ranges.

[0034] The term "address field" as used in this article refers to the field that constitutes the physical location of the memory, which may include chip select address, chip index address, row address, bank index address, bank group index address, column address, and data path address.

[0035] The term "remapping entry" as used in this article refers to a data structure that stores a remapping relationship, which may include input address, mask information, output address, and enable information.

[0036] The term "mask information" as used in this article refers to the information that identifies address bits that are not compared during address matching and address replacement and retain their original values.

[0037] The term "fault information" as used in this article refers to information that records the physical location of one or more faults according to the physical address field of the memory.

[0038] The term “non-volatile memory” as used in this article refers to a storage medium that retains fault information after power loss, and may include flash memory or other persistent storage devices.

[0039] The term "redundant row" as used in this article refers to a spare storage row inside memory used to replace a failed storage row.

[0040] The term “address processing pipeline” as used in this article refers to the hardware processing path in the memory controller that continuously performs local address matching, remapping, and physical address generation.

[0041] As mentioned above, memory chips can use internal redundant rows to replace faulty memory rows. This type of resource can be used for manufacturing repairs, post-packaging repairs, and runtime soft repairs. The number of redundant rows in a single memory bank is usually limited, and unused redundant rows may not be available for sharing with other memory banks.

[0042] Another approach involves using the page table of the memory management unit to isolate faulty physical pages. This method requires maintaining the page table and the physical page allocation status. For on-chip systems without a memory management unit, this page table path cannot directly isolate the fault location.

[0043] To supplement the repair resources within the memory chip, hardware remapping logic can be configured in the port address processing path of the memory controller. This logic uses repair address resources independent of the chip's redundancy lines and stores the address relationships through configuration registers.

[0044] Internal redundant rows and memory controller remapping can form a hierarchical processing mechanism. Internal redundant rows are repaired first at the granular level, and memory controller remapping then processes any faulty memory rows that have not been repaired. This increases the number of faulty rows that a single memory channel can handle and reduces the likelihood of large memory areas being unusable due to localized faults.

[0045] A scheme for address management is proposed. According to this scheme, the system-on-chip (SoC) obtains the faulty physical address and the mapping configuration between local interconnect addresses and memory physical addresses. Based on this configuration, the SoC reverse-engineers the first local interconnect address of the fault location and selects a second local interconnect address from a first address range not used by service data. Subsequently, the SoC configures the relationship between the two addresses in the memory controller. When a memory access request hits the first local interconnect address, the memory controller uses the second local interconnect address to perform a remapping and converts the remapped address to the target physical address.

[0046] Through the above scheme, the system-on-a-chip can redirect read / write accesses to fault locations to reserved, available locations without relying on page tables. Fault information and remapping configuration are processed by software only during the initialization or update phase, while address processing is handled by the memory controller hardware during the service memory access phase. This reduces the execution cycles required for processing devices to query mapping relationships on a request-by-request basis, and also reduces memory accesses used for page table traversal.

[0047] The following describes various examples of this scheme in further detail with reference to the accompanying drawings.

[0048] Figure 1 A schematic diagram of example environment 100 is shown. Example environment 100 includes system-on-chip 400. System-on-chip 400 may include processing device 110, interconnect network 130, first memory 121, second memory 122 and third memory 123.

[0049] Processing device 110 may include one or more processors, computing arrays, direct memory access circuitry, or firmware execution units. Processing device 110 may generate global interconnect addresses and initiate memory access requests via interconnect network 130. Processing device 110 may also read fault information and configure the memory controller during the initialization phase.

[0050] The interconnection network 130 can transfer address, data and control information between the processing device 110 and multiple memories. Figure 1 Each memory controller is not shown individually. Each memory controller is located between interconnect network 130 and its corresponding memory.

[0051] The first memory 121, the second memory 122, and the third memory 123 represent three example memories. The system-on-chip 400 may include more or fewer memories. Each memory may be a double data rate memory, a high-bandwidth memory, or other memory with addressable physical locations.

[0052] In some cases, the system-on-chip 400 may not include a memory management unit or may not have a memory management unit enabled. Address remapping may be entirely within the address processing path of the memory controller. Alternatively, even if the system-on-chip 400 includes a memory management unit, memory controller-level remapping may be located downstream of page table address translation to provide another layer of fault location isolation.

[0053] Fault information can be provided by manufacturing and inspection processes outside the System-on-Chip 400 (SoC), or by the memory self-test (WPS) process executed by the SoC. The WPS can be performed during power-up or during SoC runtime. Fault information obtained during power-up can be used to establish initial remapping relationships. New fault information obtained during runtime can be used to update existing configurations.

[0054] Processing device 110, interconnect network 130, memory controller, and various memories can be integrated into the same system-on-a-chip. Alternatively, one or more memories can be used as external memories for the system-on-a-chip 400. Requests can be transmitted between the interconnect network 130 and the memory controller via an on-chip interconnect interface.

[0055] It should be understood that the structure and function of the various elements in environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of the scheme.

[0056] The following description of the example will continue with reference to the accompanying drawings.

[0057] Figure 2 A flowchart of an example process 200 for managing addresses is shown, based on several scenarios. Process 200 can be implemented in... Figure 1 The on-chip system is located at 400. The configuration phase of process 200 can be executed collaboratively by the processing device 110 and the memory controller, while the memory access phase can be executed by the memory controller. See below for reference. Figure 2 To describe process 200.

[0058] like Figure 2 As shown in block 210, the system-on-chip 400 obtains at least one faulty physical address of the memory and address mapping configuration information, which describes the mapping relationship between the local interconnect address received by the memory controller and the physical address of the memory.

[0059] Fault information can be recorded separately for each memory, showing all known physical locations of faults. The recorded content may include, but is not limited to, the memory identifier and the chip select address, chip index address, row address, memory bank index address, memory bank group index address, column address, or data path address within that memory. Different fault locations may belong to either a service address range or a reserved address range.

[0060] The recording of the physical location of a fault is independent of whether the current address mapping configuration maps that location to the first address range. For example, even if a fault location is located within a reserved range under the current mapping, that fault location is still retained. This allows locations within the reserved range that are experiencing faults to be excluded when selecting a repair location.

[0061] In this way, local interconnect addresses can be recalculated using the same set of physical fault records even when the address mapping configuration changes. Functionally, there is no need to discard historical fault information due to changes in mapping bit order. In addition, it can reduce the read and write operations required to repeatedly perform full memory checks and reduce the processing overhead of rebuilding the fault list.

[0062] In some cases, fault information is stored in non-volatile memory. This non-volatile memory can be located internally within the system-on-chip 400 or provided by a storage device. This persistent record can be used to retain the physical location of each memory fault after power loss.

[0063] In box 220, the system-on-chip 400 translates the faulty physical address into a first local interconnect address based on address mapping configuration information.

[0064] This conversion is the reverse of the memory controller's regular forward address mapping. The System-on-Chip 400 reads each address field from the faulty physical address and configures the field values ​​to the local interconnect address bits specified in the address mapping configuration information.

[0065] In some cases, the memory physical address includes at least two of the following: chip select address, chip index address, row address, bank index address, bank group index address, column address, and data path address. Address mapping configuration information indicates the position of these address fields within the local interconnect address. Different address fields can be set consecutively or split across non-adjacent address bits.

[0066] A bank index address can be used to indicate a specific bank within a bank group, while a bank group index address can be used to indicate a specific bank group within the memory. The number of address bits occupied by the bank index address and the bank group index address can differ depending on the memory type or address organization method. In some memory organization methods, only the bank index address may be included, omitting the bank group index address.

[0067] Address mapping configuration information indicates the correspondence between each address field in the chip select address, chip index address, row address, bank index address, bank group index address, column address, and data path address and one or more address bits in the local interconnect address. For example, multiple bits of the row address can be located in the high-order region of the local interconnect address; multiple bits of the column address can be located in the low-order region, or they can be set between the address bits corresponding to the bank index address, bank group index address, or other address fields; the address bits corresponding to the bank index address and bank group index address can also be set in different positions according to the address mapping configuration. The bit order of address fields such as chip select address, chip index address, row address, bank index address, and bank group index address can be adjusted by the configuration register.

[0068] When converting a faulty physical address to a first local interconnect address, the system-on-chip 400 can read the corresponding address field in the faulty physical address and write the field value of each address field into the corresponding address bit in the local interconnect address according to the address mapping configuration information, thereby obtaining the first local interconnect address corresponding to the faulty physical address.

[0069] In a specific addressing example, the address mapping configuration information can specify that a portion of the address bits in the local interconnect address carries the column address, a portion carries the bank index address and bank group index address, a portion carries the row address, and one or more other address bits carry the chip select address or chip index address. If the obtained faulty physical address includes the corresponding chip select address, chip index address, row address, bank index address, bank group index address, and column address, then the processing device 110 can write the above address fields into the corresponding positions in the local interconnect address according to the bit order indicated by the address mapping configuration information to obtain the first local interconnect address. It should be understood that the bit width and position of each address field can be adjusted according to the actual address mapping configuration.

[0070] The mapping configuration can vary depending on the memory type, capacity organization, and access parallelism. The System-on-Chip 400 can also employ different mappings under different operating configurations. This allows the local interconnect address corresponding to the fault location to be obtained without a fixed physical address field arrangement.

[0071] In this way, the configuration phase can accurately locate the local interconnect address to be repaired based on the current memory address organization. Functionally, it can adapt to multiple physical address bit orders. In addition, there is no need to set up a fixed inverse calculation circuit for each bit order, thereby reducing the repeated implementation of address translation logic and reducing invalid remapping caused by misconfiguration.

[0072] In block 230, the system-on-chip 400 determines a second local interconnect address from a first address range and configures the remapping relationship between the first local interconnect address and the second local interconnect address in the memory controller. The first address range is located in the local interconnect address space of the memory controller and does not belong to the allocation address range of service data.

[0073] The service data allocator can mark the first address range as an unallocable range. Processing device 110 will not allocate this range to instructions, weights, feature data, or other service data for regular computing tasks. Therefore, the repair location pointed to by the second local interconnect address will not conflict with the allocation of regular service addresses.

[0074] In some cases, the System-on-Chip 400 does not include a memory management unit for managing memory address mappings via page tables. The remapping relationships are stored in configuration registers within the memory controller. These configuration registers directly provide parameters to the address comparison and replacement circuitry of the memory controller.

[0075] In this way, a system-on-a-chip without a memory management unit can still isolate faulty memory locations. Functionally, there is no need to create page tables or change the business data allocation interface. In addition, it avoids the processor cycles and memory accesses required for page table storage, page table traversal, and request-by-request software branching.

[0076] The memory controller can provide multiple remapping entries. As an example, the memory controller may include sixteen entries, each corresponding to a remapping resource with a specified row granularity. The number of entries, row granularity, and the number of memory banks sharing the entries can all be adjusted according to the memory organization method.

[0077] As a further example, sixteen memory banks can share sixteen memory controller-side repair resources. This shared pool does not require each memory bank to retain a fixed entry for its own use only. This allows repair capabilities not used by one memory bank to be allocated to other memory banks.

[0078] The number of fault remappings that a memory controller can support is limited by both the number of remapping table entries and the number of available candidate remapping locations in the first address range. A larger number of address bits in the first address range used to distinguish different candidate remapping locations provides more candidate remapping locations, but this also increases the required reserved address space. Conversely, increasing the number of remapping table entries allows for remapping of more fault locations, but it also increases the hardware resources used for address matching and address replacement in the memory controller, as well as the implementation overhead of address processing paths. Therefore, the supported number of fault remappings can be determined by combining the timing requirements of the memory controller, the number of remapping table entries, and the number of candidate remapping locations that the first address range can provide.

[0079] For example, if the first address range provides 16 sets of candidate row-level remapping locations and the memory controller includes 16 remapping table entries, up to 16 row-level remapping relationships can be established when all candidate remapping locations are available. If some candidate remapping locations in the first address range are indicated as fault locations by fault information, the corresponding candidate remapping locations can be excluded, and a second local interconnect address for establishing the remapping relationship can be determined from the remaining candidate remapping locations.

[0080] In some cases, the system-on-chip 400 writes the first local interconnect address, mask information, second local interconnect address, and enable information into the same remapping table entry. The first local interconnect address is used as the input address. The second local interconnect address is used as the output address.

[0081] The mask information indicates address bits that are not involved in address comparison and address substitution. The enable information indicates whether the entry participates in address matching. Entries that are not fully configured or have been released can be in a disabled state.

[0082] In this way, a single entry can provide the memory controller with a matching range, replacement target, and valid status. Functionally, each fault row mapping can be independently enabled or disabled. Furthermore, it reduces the number of accesses to multi-level software tables and allows the comparator circuitry to directly read fixed fields for address processing.

[0083] In some cases, the fault information acquired by the system-on-chip 400 includes at least one faulty physical location. The system-on-chip 400 traverses multiple memory physical locations corresponding to the first address range and excludes locations indicated as faulty by the fault information. Subsequently, the system-on-chip 400 determines the local interconnect address corresponding to a location that has not experienced a fault as the second local interconnect address.

[0084] If a repair location within the first address range subsequently fails, the System-on-Chip 400 can select another location that has not failed. The output address of the original entry can be replaced, or an entry pointing to the new location can be created.

[0085] In this way, the remapping target will not be occupied by unavailable locations already recorded in the fault information. Functionally, this reduces the probability of access redirecting to the fault location again. In addition, it can reduce duplicate configurations and duplicate memory accesses caused by invalid repair targets, and improve the effective utilization of limited table entries.

[0086] In some scenarios, after power-on, the System-on-Chip 400 reads fault information from non-volatile memory. Based on the currently used address mapping configuration information, the System-on-Chip 400 translates each fault physical location into a corresponding first local interconnect address. The System-on-Chip 400 then selects a repair location and writes the corresponding remapping relationship to the memory controller.

[0087] Address mapping configurations can change between different startup configurations. Each power-on performs a reverse translation based on the current configuration, instead of directly reusing the old local interconnect addresses. The remapping relationship can be configured once before service memory access begins.

[0088] In this way, fault location isolation can be restored even after a power outage, and the address bit order used at startup can be adapted. Functionally, there is no need for the software to regenerate the address on each access. In addition, concentrating the address translation overhead in the initialization phase can reduce the number of processor cycles and control path interactions during runtime.

[0089] In some cases, the system-on-chip 400 acquires new physical locations of faults during operation. Based on the new physical locations of faults, the system-on-chip 400 updates the persistent fault information and writes the corresponding remapping relationships into unused remapping table entries.

[0090] If the newly added fault location contains data that needs to be retained, the System-on-Chip 400 can attempt to copy the readable data to the new repair location before switching mappings. This copying is not a necessary condition for the remapping to take effect. Remapping configuration can be completed during periods of low access or after relevant requests have been paused.

[0091] If there are no unused entries or no available repair locations in the first address range, the System-on-Chip 400 can stop establishing new remapping relationships. The System-on-Chip 400 can also output a repair resource exhaustion status for handling by higher-level fault-tolerant processes.

[0092] In this way, newly added faults during runtime can be handled without restarting the System-on-Chip 400. This expands the applicable phases for remapping configurations. Furthermore, updating only the record corresponding to the newly added fault and one unused entry reduces the register operations required to rewrite the entire mapping table.

[0093] In some cases, the System-on-Chip 400 first uses redundant rows of memory to repair the faulty memory row. If the faulty memory row is not repaired by the redundant rows, the System-on-Chip 400 then configures a remapping relationship for that faulty memory row. Failure to repair may indicate that the redundant row resources have already been used, or that the granular-side repair did not cover the corresponding fault.

[0094] In this way, internal resources of the memory chip and shared resources with the memory controller can be used in a tiered manner. Functionally, the internal repair capabilities of the memory chip can be utilized first, and then the memory controller can handle the remaining faults. In addition, it can improve the availability of configured storage capacity and reduce the occurrence of entire memory channels being shut down due to insufficient redundant resources in a single memory bank.

[0095] In box 240, the system-on-chip 400 receives a memory access request, which includes a third local interconnect address.

[0096] The third local interconnect address can be obtained by interleaving and splitting the global interconnect address using interconnect network 130. The relevant global address to local address translation will be performed... Figure 3 Further details are provided below. The memory controller sends the third local interconnect address into the address processing pipeline before parsing read / write commands.

[0097] In block 250, in response to a third local interconnect address matching a first local interconnect address, the on-chip system 400 remaps the third local interconnect address based on the second local interconnect address, and converts the remapped local interconnect address into a target physical address of the memory based on address mapping configuration information, so as to access the memory.

[0098] In some cases, the address bits indicated by the mask information include column address bits. The comparator circuit ignores the masked bits in the third local interconnect address and the table entry address. The address replacement circuit retains the masked bits in the third local interconnect address and replaces the remaining address bits with the second local interconnect address.

[0099] For example, entries can match specific chip select addresses, chip index addresses, bank index addresses, bank set index addresses, and row addresses, without comparing column offsets within the same row. After remapping, the column offsets of the original memory access request remain unchanged. The replaced bank index address, bank set index address, and row address fields then point to the repaired rows within the reserved range.

[0100] In this way, a single entry can cover all column addresses in a faulty storage row. Functionally, it allows accesses at different offsets within a row to fall into the corresponding offsets in the repair row. Furthermore, it reduces the number of entries occupied by each column within a row and decreases the size of the parallel comparison circuitry.

[0101] In some cases, the memory controller includes multiple remapped entries. The comparison circuit compares the third local interconnect address with multiple entries indicated by the enable information for matching. Multiple comparisons can be performed in parallel.

[0102] If the third local interconnect address does not match any enabled entry, the memory controller retains the third local interconnect address. Disabled entries are not included in the comparison. Therefore, normal addresses that have not experienced a fault continue to access memory along their original address mapping path.

[0103] In this way, multiple faulty lines can share the same set of parallel comparison resources. Functionally, it can maintain multiple remapping relationships simultaneously and preserve the original access semantics of missed addresses. Furthermore, it can shorten the matching path compared to item-by-item software queries and reduce the additional control branches for normal requests.

[0104] The matching, remapping, and target physical address translation of the third local interconnect address are all performed by the memory controller. This execution is independent of the software's request-by-request lookup of the remapping relationships. The software can write entries during the configuration phase, but it does not need to read entries or participate in hit checks for each memory access request.

[0105] In this way, both read and write requests can transparently access the repair location. Functionally, there is no need to change the processing device or business process initiating the request. Furthermore, it reduces the number of software table lookups performed by the processor and decreases the amount of control messages between the processor and the memory controller.

[0106] Figure 3 A schematic diagram of a multi-memory address translation architecture 300 is shown, depending on several scenarios. Architecture 300 includes an interconnect network 130, a first memory controller 310, a second memory controller 315, a third memory controller 320, and first memories 121 to third memories 123. Figure 3 Using three channels as an example, the system-on-chip 400 can also include other numbers of memory controllers and memories.

[0107] Interconnect network 130 receives a global interconnect address and determines the memory controller corresponding to that global interconnect address based on a preset interleaving rule. The interleaving rule can use one or more address bits as memory controller selection bits. The corresponding request is routed to the first memory controller 310, the second memory controller 315, or the third memory controller 320.

[0108] The selected memory controller has its address bits used to identify it removed from the global interconnect address, resulting in a third local interconnect address. Removal can mean deleting the selection bit or compressing the remaining address bits into consecutive local address bits. The selection bit can be in the low, middle, or high position, determined by the interleaving rules.

[0109] Each memory controller can have an independent local interconnect address space starting from zero. The same local address value in different memory controllers points to their respective connected memories, thus preventing cross-channel address conflicts. Alternatively, each local address space can also use a non-zero base address.

[0110] Multi-memory interleaving allows consecutive data blocks to be distributed in parallel across different memory channels. The interleaving granularity can also be set based on the bus width and access burst length.

[0111] In this way, global interconnect addresses can form defined local addresses across multiple memory channels. Functionally, it can maintain contiguous address semantics and parallel access across channels. Furthermore, it can improve the parallel utilization of multiple memory controllers and reduce bandwidth bottlenecks caused by centralized access of continuous data to a single channel.

[0112] The first memory controller 310 further translates the third local interconnect address into the physical address of the first memory 121. The second memory controller 315 and the third memory controller 320 perform the same process to form the physical addresses of the second memory 122 and the third memory 123, respectively. This forward mapping uses... Figure 2 The reverse translation of box 220 uses the same address mapping configuration information.

[0113] In some cases, the System-on-Chip 400 sets up a second address range in the global interconnect address space. This second address range is a contiguous reserved range and does not fall within the allocation address range for service data. The service data allocator excludes this range from the allocatable set.

[0114] The system-on-chip 400 maps the second address range to the local interconnect address spaces of multiple memory controllers based on an interleaving rule. This results in the first address ranges corresponding to the first memory controller 310, the second memory controller 315, and the third memory controller 320. Each first address range can be independent of the others.

[0115] The length of the second address range can be set based on the resource requirements of multiple local reserved ranges. The global range only needs to be able to cover the local reserved resources required by each memory controller through interleaving mapping, and is not required to have the same length as any local reserved range.

[0116] In this way, the software can maintain a single reserved range in the global address space. Functionally, it eliminates the need to register multiple discrete channel ranges separately with the service allocator. Furthermore, it reduces the number of reserved range descriptors and range lookups, and lowers the address range configuration overhead during the initialization phase.

[0117] The first address range can be a contiguous address range, and must at least cover the value range of all column address bits corresponding to the memory in the local interconnect address. The contiguous range can start from address zero or any other local address. Similarly, the second address range does not necessarily need to start from address zero.

[0118] Covering all column address bits indicates that the first address range can accommodate the complete column offset range of a storage row to be remapped. In a specific mapping, the zeroth row of each memory bank can be reserved as a resource, or other rows can be selected.

[0119] In some cases, the first address range, in addition to covering the value range of all column address bits corresponding to the memory in the local interconnect address, may also cover at least a portion of the value range of one or more other address bits in the local interconnect address. These other address bits may include address bits corresponding to the bank index address, bank set index address, row address, chip select address, chip index address, or other memory physical address fields. Preferably, the other address bits include at least a portion of the address bits corresponding to the bank index address and the bank set index address.

[0120] With the first address interval covering all column address bits, for a given combination of other address bits, the first address interval can provide candidate remapping locations covering the complete column address range of a storage row. By further covering various different combinations of other address bits within the first address interval, multiple candidate remapping locations can be formed within the first address interval to serve as remapping targets for different faulty storage rows.

[0121] For example, in one address mapping configuration, the local interconnect address includes two address bits corresponding to the bank index address and two address bits corresponding to the bank group index address. The first address interval can cover all column address bits and further cover the entire value range of the aforementioned four address bits. When all possible combinations of the values ​​for the aforementioned four address bits are available, these four address bits have 16 different value combinations, thus the first address interval can provide 16 sets of candidate remapping positions. Each set of candidate remapping positions covers the entire value range of the column address bits, thereby maintaining the relative offset relationship between different column addresses within the remapped storage row.

[0122] It should be understood that the above four address bits and 16 candidate remapping positions are merely examples. The number and type of other address bits covered by the first address range, excluding the column address bits, can be set according to the specific memory address mapping method and the required fault recovery capabilities. For example, it can cover only one or more address bits corresponding to the bank index address, or it can cover one or more address bits corresponding to both the bank index address and the bank group index address.

[0123] The number of candidate remapping locations that the first address range can provide is limited. Increasing the number of other address bits covered by the first address range can increase the number of available candidate remapping locations, but it will also increase the reserved address space occupied by the first address range. Therefore, the size of the first address range and the other address bits covered by the first address range can be determined based on the number of faulty memory rows that need to be supported and the size of the allowed reserved address space.

[0124] The contiguousness of the first address range facilitates searching for repair locations that have not experienced faults in ascending address order. A row-level remapping entry can overwrite the same storage row while preserving column offsets. This eliminates the need to create a separate mapping for each column address of that row.

[0125] In this way, accesses to columns within a faulty row maintain their original relative offsets and are consistently directed to the repair row. Functionally, it can completely replace the entire storage row rather than a single point of failure. Furthermore, it reduces the number of remapped entries and address comparisons, and decreases the occupancy of entry registers.

[0126] Figure 3 The global interconnect address, local interconnect address, and memory physical address shown constitute a three-level address representation. Figure 2 Box 220 calculates the fault location in reverse order from the memory physical address to the local interconnect address. Figure 2 Box 250 completes the forward translation after remapping along the direction from local interconnect address to memory physical address.

[0127] A system-on-chip 400 for implementing the above methods or processes is also provided. Figure 4 Block diagrams of a system-on-chip 400 in several scenarios are shown. The system-on-chip 400 includes interconnect circuitry, a memory controller, and memory. The various units / components in the system-on-chip 400 can be implemented by hardware, software, firmware, or any combination thereof.

[0128] like Figure 4 As shown, the system-on-chip 400 includes an acquisition unit 410 configured to acquire at least one faulty physical address of the memory and address mapping configuration information, wherein the address mapping configuration information describes the mapping relationship between a local interconnect address received by the memory controller and a physical address of the memory; a conversion unit 420 configured to convert the faulty physical address into a first local interconnect address based on the address mapping configuration information; a configuration unit 430 configured to determine a second local interconnect address from a first address range and configure the remapping relationship between the first local interconnect address and the second local interconnect address in the memory controller, wherein the first address range is located in the local interconnect address space of the memory controller and does not belong to the allocation address range of service data; a receiving unit 440 configured to receive a memory access request, wherein the memory access request includes a third local interconnect address; and an address processing unit 450 configured to, in response to a match between the third local interconnect address and the first local interconnect address, remap the third local interconnect address based on the second local interconnect address and convert the remapped local interconnect address into a target physical address of the memory based on the address mapping configuration information, so as to access the memory.

[0129] In some cases, the system-on-a-chip does not include a memory management unit for managing memory address mappings via page tables; instead, the remapping relationships are stored in the configuration registers of the memory controller.

[0130] In some cases, the system-on-a-chip includes multiple memory controllers and multiple memories respectively connected to the multiple memory controllers, and the address processing unit 450 is further configured to: determine a first memory controller corresponding to a global interconnect address from the multiple memory controllers based on a preset interleaving rule; and remove the address bits used to determine the first memory controller from the global interconnect address to obtain a third local interconnect address.

[0131] In some cases, configuration unit 430 is also configured to: set a second address range in the global interconnect address space of the on-chip system, the second address range not belonging to the allocation address range of service data; and map the second address range to the local interconnect address spaces of multiple memory controllers based on interleaving rules to obtain the first address range corresponding to each memory controller.

[0132] In some cases, the first address range is a contiguous address range, and the first address range covers at least the range of values ​​for all column address bits in the local interconnect address corresponding to the memory.

[0133] In some cases, the physical address of the memory includes at least two of the following: chip select address, chip index address, row address, memory bank index address, memory bank group index address, column address, and data path address. The address mapping configuration information indicates the position of each address field of the physical address in the local interconnect address. Furthermore, the conversion unit 420 is configured to write each address field of the faulty physical address to the corresponding position in the local interconnect address based on the address mapping configuration information.

[0134] In some cases, configuration unit 430 is also configured to write a first local interconnect address, mask information, a second local interconnect address, and enable information into a remapping table entry of the memory controller, wherein the mask information indicates address bits that do not participate in address comparison and address substitution, and the enable information indicates whether the remapping table entry participates in address matching.

[0135] In some cases, the address bits indicated by the mask information include address bits corresponding to the column address of the memory; and the address processing unit 450 is further configured to: retain the address bits indicated by the mask information in the third local interconnect address, and replace the remaining address bits in the third local interconnect address based on the second local interconnect address.

[0136] In some cases, the memory controller includes multiple remapping entries, and the address processing unit 450 is further configured to: compare the third local interconnect address with each of the multiple remapping entries indicated by the enable information to participate in address matching; and keep the third local interconnect address unchanged in response to a mismatch between the third local interconnect address and all of the multiple remapping entries.

[0137] In some cases, the configuration unit 430 is further configured to: acquire fault information of the memory, the fault information including at least one faulty physical location in the memory; and determine, from a plurality of memory physical locations corresponding to a first address range, a memory physical location not indicated as a faulty physical location by the fault information, and determine the local interconnect address corresponding to the memory physical location as a second local interconnect address.

[0138] In some cases, the fault information records the physical location of each memory in the on-chip system, and records the physical location of the fault independently of whether the physical location of the fault is mapped to the first address range based on the current address mapping configuration information.

[0139] In some cases, configuration unit 430 is also configured to: read fault information from non-volatile memory in response to power-on of the on-chip system; convert the physical location of the fault in the fault information into the corresponding first local interconnect address based on the address mapping configuration information currently used by the on-chip system; and write the corresponding remapping relationship to the memory controller.

[0140] In some cases, configuration unit 430 is also configured to: acquire new physical locations of faults during on-chip system operation; update fault information based on the new physical locations of faults; and write the remapping relationship for the new physical locations of faults into unused remapping entries in the memory controller.

[0141] In some cases, configuration unit 430 is also configured to: repair faulty memory rows using redundant rows of memory; and configure remapping relationships for faulty memory rows in response to the failure of the faulty memory rows to be repaired by redundant rows.

[0142] In some cases, the matching, remapping, and translation of the third local interconnect address into the physical address of memory are performed by the memory controller, and the process of querying the remapping relationship is independent of the software.

[0143] The units in the System-on-Chip 400 can be implemented in various ways, including software, hardware, firmware, or any combination thereof. In some cases, one or more units can be implemented using machine-executable instructions stored on a storage medium. Additionally, some or all of the units can be implemented at least partially by one or more hardware logic components. Hardware logic components may include, for example, Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Hardware logic components may also include Application Specific Standard Parts (ASSPs) or Complex Programmable Logic Devices (CPLDs).

[0144] Figure 5 A block diagram of an electronic device 500 in which one or more examples may be implemented is shown. It should be understood that... Figure 5 The electronic device 500 shown is merely exemplary and should not be construed as limiting the functionality and scope of the examples described herein. Figure 5 The electronic device 500 shown can be used to implement the system-on-a-chip 400 as discussed above.

[0145] like Figure 5 As shown, electronic device 500 is in the form of a general-purpose electronic device. Components of electronic device 500 may include, but are not limited to, one or more processing units or processors 510, memory 520, storage devices 530, one or more communication units 540, one or more input devices 550, and one or more output devices 560. Processor 510 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 520. In a multiprocessor system, multiple processors execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 500.

[0146] Electronic device 500 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to electronic device 500, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 520 can be volatile memory, such as registers, caches, or random access memory (RAM). Memory 520 can also be non-volatile memory, such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 520 can also include combinations of the aforementioned memories. Storage device 530 can be a removable or non-removable medium and can include flash drives, disks, or other media capable of storing information or data and accessible within electronic device 500.

[0147] Electronic device 500 may further include additional removable or non-removable storage media, and may also include volatile or non-volatile storage media. Although not explicitly stated... Figure 5 As shown, a disk drive for reading from or writing to a removable non-volatile disk can be provided. An optical disc drive for reading from or writing to a removable non-volatile optical disc can also be provided. In these cases, each drive can be connected to a bus via one or more data media interfaces. Memory 520 may include computer program product 525. Computer program product 525 has one or more program modules configured to perform various example methods or actions.

[0148] The communication unit 540 enables communication with other electronic devices via a communication medium. Additionally, the component functions of the electronic device 500 can be implemented as a single computing cluster or multiple computing machines. Multiple computing machines can communicate via communication connections. Therefore, the electronic device 500 can operate in a networked environment using logical connections to one or more other servers, networked personal computers, or other network nodes.

[0149] Input device 550 can be one or more input devices, such as a mouse, keyboard, or trackball. Output device 560 can be one or more output devices, such as a monitor, speaker, or printer. Electronic device 500 can also communicate with one or more external devices via communication unit 540 as needed. External devices may include storage devices, display devices, devices that allow users to interact with electronic device 500, or devices that allow electronic device 500 to communicate with other electronic devices. Such communication can be performed via an input / output (I / O) interface.

[0150] A computer-readable storage medium is provided, on which computer-executable instructions are stored. The computer-executable instructions are executed by a processor to implement the methods described above. A computer program product is also provided. The computer program product is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions. The computer-executable instructions are executed by a processor to implement the methods described above.

[0151] Various aspects of the methods, systems-on-a-chip, devices, and computer program products of this disclosure are described herein with reference to flowcharts and block diagrams. It should be understood that each block of the flowcharts and block diagrams, as well as combinations of blocks, can be implemented by computer-readable program instructions.

[0152] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine. When executed by the processor, these instructions create means to perform the functions or actions specified in one or more blocks of a flowchart or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium. These instructions can cause a computer, programmable data processing apparatus, or other device to function in a particular manner. Therefore, a computer-readable medium storing the instructions can include an article of manufacture that performs the corresponding functions or actions.

[0153] Computer-readable program instructions can be loaded onto a computer, other programmable data processing device, or other equipment. By executing a series of operational steps, a computer-implemented process can be produced. When the corresponding instructions are executed by the device, they can perform the function or action specified in one or more blocks of a flowchart or block diagram.

[0154] The flowcharts and block diagrams in the accompanying figures illustrate possible architectures, functions, and operations of systems, methods, and computer program products under various scenarios. Each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction. This module, segment, or instruction portion contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the figures. For example, two consecutive blocks may be executed substantially in parallel or in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks, may be implemented by a dedicated hardware system performing the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0155] Various examples have been described above. The above descriptions are exemplary and not exhaustive, nor are they limited to the implementations already described. Many modifications and changes can be made by those skilled in the art without departing from the scope and spirit of the implementations. The terminology chosen herein is intended to explain the principles, practical applications, or improvements to related technologies of the implementations, and to enable others skilled in the art to understand the implementations described herein.

Claims

1. A method for managing addresses, applied to a system-on-a-chip, the system-on-a-chip including interconnect circuitry, a memory controller, and a memory, characterized in that, include: Obtain at least one faulty physical address and address mapping configuration information of the memory, wherein the address mapping configuration information describes the mapping relationship between the local interconnect address received by the memory controller and the physical address of the memory; Based on the address mapping configuration information, the faulty physical address is converted into a first local interconnect address; A second local interconnect address is determined from a first address range, and the remapping relationship between the first local interconnect address and the second local interconnect address is configured in the memory controller. The first address range is located in the local interconnect address space of the memory controller and does not belong to the allocation address range of service data. Receive a memory access request, the memory access request including a third local interconnect address; as well as In response to the third local interconnect address matching the first local interconnect address, the third local interconnect address is remapped based on the second local interconnect address, and the remapped local interconnect address is converted into the target physical address of the memory based on the address mapping configuration information, so as to access the memory.

2. The method according to claim 1, characterized in that, The system-on-a-chip does not include a memory management unit for managing the address mapping of the memory through page tables, and the remapping relationship is stored in the configuration register of the memory controller.

3. The method according to claim 1, characterized in that, The system-on-a-chip includes multiple memory controllers and multiple memories respectively connected to the multiple memory controllers, and the method further includes: Based on a preset interleaving rule, a first memory controller corresponding to the global interconnect address is determined from the plurality of memory controllers; and The third local interconnect address is obtained by removing the address bits used to determine the first memory controller from the global interconnect address.

4. The method according to claim 3, characterized in that, The method further includes: A second address range is set in the global interconnect address space of the on-chip system, wherein the second address range does not belong to the allocated address range of the service data; and Based on the interleaving rule, the second address range is mapped to the local interconnect address space of each of the plurality of memory controllers to obtain the first address range corresponding to each memory controller.

5. The method according to claim 4, characterized in that, The first address range is a continuous address range, and the first address range at least covers the value range of all column address bits corresponding to the memory in the local interconnect address.

6. The method according to claim 1, characterized in that, The physical address of the memory includes at least two of the following: chip select address, chip index address, row address, memory bank index address, memory bank group index address, column address, and data path address. The address mapping configuration information indicates the position of each address field of the physical address in the local interconnect address. The step of converting the faulty physical address into a first local interconnect address includes: writing each address field of the faulty physical address into the corresponding position in the local interconnect address based on the address mapping configuration information.

7. The method according to claim 1, characterized in that, The step of configuring the remapping relationship between the first local interconnect address and the second local interconnect address in the memory controller includes: The first local interconnect address, mask information, second local interconnect address, and enable information are written into a remapping table entry of the memory controller. The mask information indicates address bits that do not participate in address comparison and address replacement, and the enable information indicates whether the remapping table entry participates in address matching.

8. The method according to claim 7, characterized in that, The address bits indicated by the mask information include address bits corresponding to the column address of the memory; and The remapping of the third local interconnect address based on the second local interconnect address includes: retaining the address bits in the third local interconnect address indicated by the mask information, and replacing the remaining address bits in the third local interconnect address based on the second local interconnect address.

9. The method according to claim 7, characterized in that, The memory controller includes multiple remapping table entries, and the method further includes: The third local interconnect address is compared with multiple remapping entries indicated by the enable information to participate in address matching; and In response to the fact that the third local interconnect address does not match any of the plurality of remapping entries, the third local interconnect address remains unchanged.

10. The method according to claim 1, characterized in that, Determining the second local interconnect address from the first address range includes: Obtain fault information of the memory, the fault information including at least one physical location of the fault in the memory; and From the multiple memory physical locations corresponding to the first address range, determine the memory physical location that is not indicated as a fault physical location by the fault information, and determine the local interconnect address corresponding to the memory physical location as the second local interconnect address.

11. The method according to claim 10, characterized in that, The fault information records the physical location of each memory in the on-chip system, and records whether the physical location of the fault is mapped to the first address range based on the current address mapping configuration information, independent of whether the physical location of the fault is mapped to the first address range.

12. The method according to claim 11, characterized in that, The method further includes: In response to the power-on of the on-chip system, the fault information is read from the non-volatile memory; Based on the address mapping configuration information currently used by the on-chip system, the physical location of the fault in the fault information is converted into the corresponding first local interconnect address; and The corresponding remapping relationship is written to the memory controller.

13. The method according to claim 11, characterized in that, The method further includes: During the operation of the on-chip system, the physical location of newly added faults is acquired; and The fault information is updated based on the newly added physical location of the fault, and the remapping relationship for the newly added physical location of the fault is written into an unused remapping table entry in the memory controller.

14. The method according to claim 1, characterized in that, The method further includes: Repairing faulty memory rows using redundant rows of the memory; and In response to the failure of the faulty storage row to be repaired by the redundant row, the remapping relationship is configured for the faulty storage row.

15. The method according to claim 1, characterized in that, The matching, remapping, and translation of the third local interconnect address to the physical address of the memory are performed by the memory controller, and the execution is independent of the software query process for the remapping relationship.

16. A system-on-a-chip, characterized in that, The system-on-a-chip includes interconnect circuitry, a memory controller, and a memory. The system-on-a-chip also includes: The acquisition unit is configured to acquire at least one faulty physical address of the memory and address mapping configuration information, wherein the address mapping configuration information describes the mapping relationship between the local interconnect address received by the memory controller and the physical address of the memory; The conversion unit is configured to convert the faulty physical address into a first local interconnect address based on the address mapping configuration information; The configuration unit is configured to determine a second local interconnect address from a first address range and configure the remapping relationship between the first local interconnect address and the second local interconnect address in the memory controller. The first address range is located in the local interconnect address space of the memory controller and does not belong to the allocation address range of service data. A receiving unit is configured to receive a memory access request, the memory access request including a third local interconnect address; and The address processing unit is configured to, in response to the third local interconnect address matching the first local interconnect address, remap the third local interconnect address based on the second local interconnect address, and convert the remapped local interconnect address into a target physical address of the memory based on the address mapping configuration information, so as to access the memory.

17. An electronic device, characterized in that, include: At least one processing unit; as well as At least one memory, coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which, when executed by the at least one processing unit, cause the electronic device to perform the method according to any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the method according to any one of claims 1 to 15.

19. A computer program product, characterized in that, The computer program product is tangibly stored in a computer storage medium and includes computer-executable instructions that, when executed by a device, cause the device to perform the method according to any one of claims 1 to 15.

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