A division implementation device and FPGA

Abstract

This invention discloses a division implementation device and an FPGA. The device includes: a bit-width detection unit for receiving a binary dividend and divisor; calculating the actual effective bit width of the absolute value of the divisor; a path decision unit for generating a path selection signal based on a comparison between the actual effective bit width and a preset bit-width threshold; a low-bit-width processing unit for obtaining a first reciprocal of the absolute value of the divisor based on a reciprocal lookup table when the path selection signal indicates a low-bit-width bypass sub-path; a high-bit-width processing unit for obtaining a second reciprocal of the highest K significant bits of the absolute value of the divisor based on a reciprocal lookup table when the path selection signal indicates a high-bit-width Newton-corrected sub-path, and correcting the second reciprocal based on Newton's iteration method to obtain a third reciprocal; and a quotient multiplication unit for calculating the quotient based on the dividend and either the first or third reciprocal. This solution can achieve adaptive low-power, high-throughput division operations.

Description

Technical Field

[0001] This invention relates to the field of real-time signal processing technology, and more particularly to a division implementation device and an FPGA. Background Technology

[0002] In real-time signal processing systems implemented on FPGAs (Field Programmable Gate Arrays), division operations typically consume more logic, DSP (Digital Signal Processor), and on-chip memory resources than addition, shifting, and multiplication.

[0003] Existing FPGA division implementation schemes mostly use iterative algorithms to approximate the operation. Some schemes use table lookup to help generate the quotient value bit by bit to ensure the accuracy of the operation. Other methods integrate mature division circuits that can be directly called and reused.

[0004] However, existing methods using a single lookup table cannot directly cover 16-bit or higher bit widths. If a fixed high bit width path is used to process all inputs, unnecessary multiplication-level flips and dynamic power consumption will occur in low bit width divisor scenarios, and it is difficult to directly meet the requirements of high-throughput streaming processing. Summary of the Invention

[0005] This invention provides a division implementation device and an FPGA to achieve adaptive low-power, high-throughput division operations.

[0006] According to one aspect of the present invention, an embodiment of the present invention provides a division implementation apparatus, comprising: The bit width detection unit is used to receive the binary dividend and divisor; and to calculate the actual effective bit width of the absolute value of the divisor. The path decision unit is used to compare the actual effective bit width with a preset bit width threshold, and generate a path selection signal based on the comparison result. The path selection signal is used to indicate a low bit width bypass sub-path or a high bit width Newton correction sub-path. The low-bit-width processing unit is used to obtain the first reciprocal of the absolute value of the divisor based on the reciprocal lookup table when the path selection signal indicates a low-bit-width bypass sub-path, and input the first reciprocal into the quotient multiplication unit. A high-bit-width processing unit is used to, when the path selection signal indicates a high-bit-width Newton-corrected sub-path, obtain the second reciprocal of the highest K significant bits of the absolute value of the divisor based on a reciprocal lookup table, and correct the second reciprocal based on Newton's iteration method to obtain a third reciprocal; input the third reciprocal into the quotient multiplication unit; where K is equal to the preset bit-width threshold. The quotient multiplication unit is used to calculate the quotient of the dividend and the divisor based on the dividend and the input first reciprocal or the third reciprocal.

[0007] According to another aspect of the present invention, an FPGA is provided, the FPGA including the division implementation apparatus provided in any of the above embodiments.

[0008] In the technical solution of this invention embodiment, a bit width detection unit is used to receive a binary dividend and divisor; calculate the actual effective bit width of the absolute value of the divisor; a path decision unit is used to compare the actual effective bit width with a preset bit width threshold, and generate a path selection signal based on the comparison result, the path selection signal being used to indicate a low bit width bypass sub-path or a high bit width Newton correction sub-path; a low bit width processing unit is used to obtain the first inverse of the absolute value of the divisor based on a reciprocal lookup table when the path selection signal indicates a low bit width bypass sub-path. The first reciprocal is input into the quotient multiplication unit; the high-bit-width processing unit, when the path selection signal indicates a high-bit-width Newton correction sub-path, obtains the second reciprocal of the highest K significant bits of the absolute value of the divisor based on the reciprocal lookup table, and corrects the second reciprocal based on the Newton iteration method to obtain a third reciprocal; the third reciprocal is input into the quotient multiplication unit; the K is equal to the preset bit-width threshold; the quotient multiplication unit is used to calculate the quotient of the dividend and the divisor based on the dividend and the input first reciprocal or the third reciprocal. The above technical solution reduces invalid flips and dynamic power consumption by adaptively selecting low-bit-width paths and high-bit-width paths to process low-bit-width divisors and high-bit-width divisors respectively, and improves fixed-point accuracy and throughput by retaining sufficient fractional bit width and iterative approximation.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a division implementation device provided in Embodiment 1 of the present invention; Figure 2 A general architecture block diagram of a division implementation device is provided; Figure 3This is a schematic diagram of a division implementation device according to Embodiment 2 of the present invention; Figure 4 A schematic diagram illustrating the relationship between normalized reciprocal lookup table and fixed-point scaling is provided. Figure 5 This is a schematic diagram of a division implementation device provided according to Embodiment 3 of the present invention; Figure 6 A schematic diagram of the entire pipeline path and delay matching relationship in an adaptive mode is provided. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] Example 1 Figure 1 This is a schematic diagram of a division implementation device provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where division operations are used when processing signals using a DSP. The device can be implemented in hardware and can be configured within an FPGA chip. Figure 1 As shown, the device includes: The bit width detection unit 101 is used to receive the binary dividend and divisor; and to calculate the actual effective bit width of the absolute value of the divisor.

[0014] In this embodiment, the provided division implementation device can be configured on an FPGA chip and applied to various electronic devices equipped with digital arithmetic circuits. The chip may include a DSP, on-chip memory, a data interface, and arithmetic operation hardware units. The DSP can perform basic mathematical operations on digital signals, including addition, subtraction, and multiplication, but cannot perform division. The on-chip memory can be used to store intermediate data during the operation; for example, when using a reciprocal lookup table method, it can be used to store the lookup table.

[0015] As described above, the data interface uses a streaming interface to receive the system clock, reset signal, data valid signal, reverse voltage signal, dividend, and divisor, and outputs the data valid signal, reverse voltage signal, quotient, divisor-to-zero signal, and sign bit. If the system does not require reverse voltage, the input and output reverse voltage signals can be omitted, and the division implementation device can receive one task per clock cycle when the data is valid.

[0016] Among them, the streaming interface can be considered as the input / output interface in the hardware circuit that faces the continuous data stream. Data is continuously sent into the circuit with each clock cycle. A new set of data is transmitted with each clock cycle, without waiting for a whole frame of data to be received before starting the operation. The system clock can be considered as providing a unified timing reference for the entire device. The reset signal can be considered as being used to force all registers and intermediate operation variables inside the device to be restored to their initial default state.

[0017] The reverse pressure signal can be considered a handshake signal for a streaming interface. When the downstream circuit cannot process the data and cannot receive the current division output, the reverse pressure signal feeds pressure back to the upstream stage, pausing the reception of new input data to prevent data loss and overflow. The data valid signal can be used to mark that the current data is valid or to allow the path to start the operation. Disabling this signal means preventing new data from being sent to the high-bit-width Newton correction sub-path. This sub-path is determined to have no valid data and will not start iterative calculation.

[0018] The divisor-to-zero signal can be considered as detecting the divisor value during the operation. When the divisor is found to be equal to 0, this alarm signal is output to mark that the current input is an illegal operation condition. The sign bit can be considered as being used to mark the positive or negative attribute of the binary data of the dividend and divisor, and does not participate in the arithmetic operation of the numerical value.

[0019] To ensure output order, the device internally maintains the relative order of input tasks and sets the path selection signal, divisor-to-zero signal, and sign bit to move synchronously on the same pipeline as the dividend and divisor or the reciprocal of the divisor. This allows the division implementation device to output one result per cycle in the order of continuous valid inputs. The pipeline can be considered a parallel processing architecture in FPGA hardware that breaks down the complete computation process into multiple independent stages, processing a new set of data synchronously each clock cycle. Each stage is isolated and data is transferred between stages using delay registers.

[0020] As described above, the arithmetic operation hardware unit may include the division implementation device provided in this embodiment, which can call multiple basic operation units in the DSP to implement division operations.

[0021] In this embodiment, the actual effective bit width can be considered as the bit length reflecting the true numerical information after removing leading invalid zeros from the divisor in the division operation. Since the high-order bits of the input data often contain meaningless leading invalid zeros, a fixed-bit-width computation path would perform redundant calculations on invalid bits, resulting in wasted resources and power. By identifying the actual effective bit width, the computation path can be dynamically configured to perform subsequent operations only on the effective bits.

[0022] Among them, leading invalid zeros can be consecutive zero bits that do not carry numerical information before the most significant bit of binary data. When the data storage bit width is fixed, such zeros are often filled to make up the bit length.

[0023] Specifically, the bit width detection unit can be used for: It receives input binary data, including the dividend and divisor, and calculates the absolute values ​​of the dividend and divisor for subsequent division operations. It also calculates the actual effective bit width of the absolute value of the divisor using a leading zero detection circuit.

[0024] In one implementation, the bit width detection unit can be considered as follows: after receiving the binary dividend and divisor, for an unsigned divisor, if the divisor is not zero, the actual effective bit width can be equal to the highest non-zero bit index plus 1. For a signed divisor, the absolute value of the divisor can be taken first, and then the actual effective bit width can be calculated. This calculation can be implemented using binary tree logic. For example, for a 16-bit input, the actual effective bit width can be obtained by detecting the high 8 bits and low 8 bits separately.

[0025] The path decision unit 102 is used to compare the actual effective bit width with the preset bit width threshold, and generate a path selection signal based on the comparison result. The path selection signal is used to indicate a low bit width bypass sub-path or a high bit width Newton correction sub-path.

[0026] The preset bit width threshold is the address bit width of the reciprocal lookup table, which can be used to compare the actual effective bit width of the data to distinguish whether the data belongs to low bit width data or high bit width data.

[0027] The path selection signal can be considered as a control signal generated by the path decision unit based on the comparison between the actual effective bit width and the preset bit width threshold. Based on the path selection signal, an appropriate processing path can be adaptively selected for divisors of different bit widths, including low bit width bypass sub-paths and high bit width Newton correction sub-paths, in order to reduce invalid flips and dynamic losses caused when low bit width data is processed through high bit width Newton correction sub-paths.

[0028] The low-bit-width bypass sub-path can be considered as the branch being switched on by the path selection signal when the actual effective bit width is not greater than the preset bit width threshold, using fewer iterations and a small amount of DSP resources to complete the division operation; the high-bit-width Newton correction sub-path can be considered as the branch being switched on by the path selection signal when the actual effective bit width is greater than or equal to the preset bit width threshold, using multiple rounds of Newton iterations in conjunction with multiple levels of DSP to complete the convergence correction operation, forming two sets of split architectures with the low-bit-width bypass sub-path, improving the accuracy of high-bit-width calculation and the overall pipeline throughput.

[0029] In this division device, the division operation is broken down into pipeline stages such as table lookup, iterative correction, and post-processing, which can achieve continuous streaming data throughput and optimize the power consumption caused by DSP flip-flops while ensuring fixed operation latency.

[0030] The clock cycle is a driving signal provided by the FPGA system as a unified periodic timing reference. It is used to synchronize the actions of all registers and arithmetic units and determine when each stage of the pipeline receives, stores, and processes data. The delay register can be considered as the basic storage unit in the FPGA used to store data or delay the timing of data output. It can align the clock beats of signals at each stage of the pipeline to ensure data synchronization between modules. The delay register can ensure that the output frequency of the quotient is the same to compensate for the inherent operation delay of each stage of the arithmetic unit and ensure the stable operation of the pipeline.

[0031] As described above, DSP flipping can be considered as the phenomenon of the input bits of the DSP's internal registers constantly switching between high and low levels with the clock. Frequent bit flipping generates dynamic power consumption. Therefore, for low-bit-width divisors, dynamic power consumption can be reduced by controlling inactive DSP flipping.

[0032] Based on the above, this embodiment can further use the path decision unit for: Compare the actual effective bit width with the preset bit width threshold; If the actual effective bit width is not greater than the preset bit width threshold, a path selection signal indicating the low bit width bypass sub-path is generated. If the actual effective bit width is greater than the preset bit width threshold, a path selection signal indicating the high bit width Newton correction sub-path is generated.

[0033] The low-bit-width processing unit 103 is used to obtain the first reciprocal of the absolute value of the divisor based on the reciprocal lookup table when the path selection signal indicates a low-bit-width bypass sub-path, and input the first reciprocal into the quotient multiplication unit.

[0034] The first reciprocal can be the reciprocal obtained from the reciprocal lookup table, where the actual effective bit width is not greater than the preset bit width threshold.

[0035] In this embodiment, as described above, a path selection signal can be obtained by calculating the actual effective bit width of the divisor and comparing it with a preset bit width threshold, and different processing paths can be selected for divisors of different bit widths accordingly. In this embodiment, the low bit width processing unit can be considered as a low bit width bypass sub-path used to process divisors whose actual effective bit width is not greater than the preset bit width threshold.

[0036] In this embodiment, the low-bit-width processing unit can be considered as processing the divisor when the path decision unit determines that the actual effective bit-width is not greater than the preset bit-width threshold. The absolute value of the divisor is used to obtain the reciprocal of the absolute value of the divisor according to the reciprocal lookup table, which is taken as the first reciprocal and directly input into the quotient multiplication unit.

[0037] The reciprocal lookup table can be pre-stored in a memory unit, which can be implemented using BRAM, M18K, M20K, URAM, distributed RAM, or a register array. In FPGA division operations, the corresponding reciprocal can be quickly retrieved directly using the divisor as an index, eliminating the need for complex iterative calculations of finding the reciprocal in real time.

[0038] As described above, the quotient multiplication unit can be considered as performing multiplication operations based on the absolute value of the dividend and the reciprocal of the absolute value of the divisor to obtain the quotient of the dividend and the divisor.

[0039] The high bit-width processing unit 104 is used to obtain the second reciprocal of the highest K significant bits of the absolute value of the divisor based on the reciprocal lookup table when the path selection signal indicates a high bit-width Newton-corrected sub-path, and to correct the second reciprocal based on the Newton iteration method to obtain the third reciprocal; the third reciprocal is input into the quotient multiplication unit; K is equal to the preset bit-width threshold.

[0040] The second reciprocal can be considered as the initial value of the reciprocal directly read from the reciprocal lookup table after truncating the highest K significant digits of the absolute value of the divisor. It is the initial value of the lookup table without correction by Newton's iteration. The third reciprocal can be considered as the more accurate reciprocal value obtained by using the second reciprocal as the starting point of the iteration and correcting it with Newton's iteration method.

[0041] In this embodiment, as described above, a path selection signal can be obtained by calculating the actual effective bit width of the divisor and comparing it with a preset bit width threshold, and different processing paths can be selected for divisors of different bit widths accordingly. In this embodiment, the high bit width processing unit can be considered as a high bit width Newton correction sub-path used to process divisors whose actual effective bit width is greater than the preset bit width threshold.

[0042] The high-bit-width processing unit corrects the second reciprocal based on the scale compensation parameter and Newton's iteration method to obtain the third reciprocal. The scale compensation parameter is the difference between the actual effective bit width and the preset bit width threshold.

[0043] In this embodiment, the high-bit-width processing unit can be considered as the unit that processes the divisor when the path decision unit determines that the actual effective bit-width is greater than the preset bit-width threshold. Based on the preset bit-width threshold K, the unit obtains the highest K significant bits of the absolute value of the divisor and calculates its reciprocal as the second reciprocal. The second reciprocal is then corrected using Newton's iteration method to improve accuracy. This corrected second reciprocal is then used as the third reciprocal and input into the quotient multiplication unit to obtain the final quotient.

[0044] In this division device, the highest K valid bits can be considered as consecutive valid bits selected from the high-order bits of the binary data, with a preset bit width threshold K as the truncation length. By truncating the valid high-order bits according to K in the high-bit-width processing unit, the full-width data can be avoided from participating in the iteration, reducing DSP flipping and hardware resource consumption.

[0045] In one implementation, the high-bit-width processing unit can be considered as processing divisors whose actual effective bit-width is greater than a preset bit-width threshold to obtain a divisor with the highest K significant bits, which can be considered as shifting the divisor to the left by 's' bits. A reciprocal lookup table is then used to process the divisor with the highest K significant bits to obtain the second reciprocal. 'F' is set as the fixed-point decimal width of the reciprocal lookup table entry, used to define the proportion of the decimal part in the QF fixed-point format of the lookup table output data. The second reciprocal, carrying 'F' and 's', is then processed using Newton's iteration method to obtain the corrected third reciprocal.

[0046] Where F is the fixed-point decimal width of the entries in the reciprocal lookup table, and s is the value of the scale compensation parameter. The fixed-point decimal width can be considered as the number of binary bits occupied by the decimal part when the data in the reciprocal lookup table is stored in QF fixed-point format, which determines the precision of the initial value calculation.

[0047] QF fixed-point format can be a fixed-point encoding standard defined by a fixed-point decimal width F. The integer part only retains the sign bit and 1 integer bit, and the remaining F bits are used to store the decimal part. This format unifies the bit allocation rules for the initial value of the lookup table, supports fixed-point conversion throughout the Newton-Raphson iteration method, and performs scale compensation based on F in the later stages of the calculation to remove the decimal scaling factor and restore the true value.

[0048] The quotient multiplication unit 105 is used to calculate the quotient of the dividend and the divisor based on the dividend and the input first or third reciprocal.

[0049] The quotient multiplication unit calculates the quotient of the dividend and divisor based on the scale compensation parameter, the dividend, and the third reciprocal of the input.

[0050] In this embodiment, the quotient multiplication unit can be used to process the first or third reciprocal. Based on the corresponding dividend, the quotient of the dividend and divisor can be obtained through multiplication.

[0051] Based on the above, this embodiment can further use the quotient multiplication unit to: perform a multiplication operation on the absolute value of the dividend and its first reciprocal, shift the result of the multiplication operation to the right by F bits, and obtain the quotient of the dividend and divisor; or, Perform a multiplication operation on the absolute value of the dividend and its third reciprocal, shift the result of the multiplication operation to the right by F+s positions, and obtain the quotient of the dividend and divisor.

[0052] In one implementation, the quotient multiplication unit can be considered as obtaining the quotient of the dividend and divisor by performing multiplication operations based on the dividend and the first or third reciprocal, and improving the calculation accuracy by eliminating the fixed-point decimal places F and eliminating the normalized amplification s bits.

[0053] Eliminating fixed-point decimal places can be considered as a shifting process performed in fixed-point arithmetic to restore the true numerical scale. This operation is executed in the quotient multiplication unit. In this division implementation device, the entire iteration uses fixed-point format arithmetic with decimal places. After multiplying the dividend and its reciprocal to obtain the quotient, this operation is used to offset the offset caused by fixed-point scaling, outputting the final quotient result that conforms to the bit width specification, thus completing the data scale uniformity compensation of the entire pipeline.

[0054] The elimination of the s-bit normalization amplification can be considered as a shift operation that reverses the numerical amplification caused by the left shift of s bits performed in the preprocessing stage to complete the divisor normalization. In this division implementation device, this shift correction is performed after the iterative calculation is completed to offset the scaling bias introduced by the previous normalization operation. Combined with the elimination of fixed-point decimal places, this yields a final quotient with correct scaling.

[0055] To better understand the division implementation device proposed in this embodiment, Figure 2 A general architecture block diagram of a division implementation device is provided. Figure 2 This demonstrates the relationship between the streaming interface, divisor preprocessing, path decision unit, reciprocal lookup table, low-bit-width bypass sub-path, high-bit-width Newton correction sub-path, quotient multiplication unit, efficient pipeline control, low-power control, and delay matching. Figure 2 In this context, A can be considered the dividend, B can be considered the divisor, in_valid can be considered the valid input data signal, and W_real can be considered the actual valid bit width.

[0056] The first or second reciprocal can be obtained by searching the reciprocal lookup table: Where b can be considered as the non-zero address of the divisor. It can be considered a rounding function, taking the integer value closest to the value within the function. This can be considered a function that obtains the reciprocal using a reciprocal lookup table. When W_real≤K, the absolute value of the divisor B is directly used to look up the reciprocal lookup table to obtain the first reciprocal. When W_real>K, the absolute value of the divisor B is shifted to the right by s bits to obtain b_norm. b_norm can be considered as the normalized lookup table address of the high-bit-width Newton correction subpath. Then, b_norm is used to look up the reciprocal lookup table to obtain the second reciprocal.

[0057] Following the above description, Figure 2The MUX can be considered a multiplexer. The first reciprocal of the output from the low-bit-width bypass sub-path and the third reciprocal of the output from the high-bit-width Newton correction sub-path both arrive at the MUX. The MUX determines whether to input the first or third reciprocal into the quotient multiplication unit based on the path selection signal. Q can be considered the final quotient, and x_raw can be considered the output of the low-bit-width bypass sub-path or the high-bit-width Newton correction sub-path. Q=(A*x_raw)>>(F+s) can be considered as multiplying the dividend A by x_raw and shifting the product to the right by F+s bits to obtain the quotient, thus eliminating scale bias.

[0058] The divisor preprocessing can be considered as processing the divisor with a value of 0, the unsigned divisor, and the signed divisor separately to obtain the actual effective bit width of the divisor. Effective pipeline control refers to synchronously moving the path selection signal, the divisor-to-zero signal, the sign bit, and the dividend and divisor or the reciprocal of the divisor on the same pipeline, enabling the division implementation device to output one result per cycle in the input order when continuous inputs are valid. Low-power control can be considered as performing low-power control through the first and second gating processing units in the low-bit-width processing unit when W_real≤K; low-power control prevents DSP flipping in the low-bit-width bypass sub-path to reduce dynamic power consumption.

[0059] The technical solution in this embodiment dynamically selects two processing paths by calculating the actual effective bit width of the divisor. The low-bit-width bypass sub-path reduces DSP bit flipping and dynamic power consumption; the high-bit-width Newton correction sub-path truncates the highest K significant bits for computation, reducing the computational bit width and saving hardware resources. Accuracy correction is performed using the Newton iteration method, and the quotient value is solved via a quotient multiplication unit. Fixed-point decimal places are eliminated and shift deviations are compensated for sequentially in the quotient. This approach ensures the accuracy of the final quotient calculation while controlling resource overhead and power consumption.

[0060] Example 2 Figure 3 This is a schematic diagram of a division implementation device according to Embodiment 2 of the present invention. The embodiments of the present invention further refine the above-mentioned high-bit-width processing unit, such as... Figure 3 As shown, the unit includes: The first lookup table subunit 301 is used to obtain the second reciprocal of the highest K significant digits of the absolute value of the divisor based on the reciprocal lookup table.

[0061] In this embodiment, the first lookup table subunit can be considered as a divisor that is larger than the preset bit width threshold. It uses a reciprocal lookup table to look up the reciprocal of the absolute value of the divisor and obtains the second reciprocal with the highest K effective bits according to the preset bit width threshold K, which is then used as the input for the subsequent execution of the Newton iteration method.

[0062] The first Newton multiplication subunit 302 is used to perform multiplication operations on the absolute values ​​of the second reciprocal and the divisor, and to compensate the result of the multiplication operation based on the scale compensation parameter to obtain the multiplication compensation result.

[0063] In this embodiment, the first Newton multiplication subunit can be considered as multiplying the absolute value of the second reciprocal by the divisor, and then shifting and scaling the multiplication result to the right according to the scale compensation parameter. This is used to truncate the high-order bits and align the decimal point position of the entire Newton iteration method, finally obtaining the multiplication compensation result. Based on the above, this embodiment can specifically use the first Newton multiplication subunit to: perform a multiplication operation on the absolute value of the second reciprocal and the divisor, shift the result of the multiplication operation to the right by s bits, and obtain the multiplication compensation result; s is the value of the scale compensation parameter.

[0064] The first formula for obtaining the multiplication compensation result can be expressed as: , in, This can be considered as the result of the above multiplication compensation. Represents the absolute value of the divisor. It can be considered as being obtained from a reciprocal lookup table. The reciprocal of the highest K significant bits, It can be represented as .in, It can be considered as preserved. The divisor with the highest K significant digits, This can be represented as a rounding operation in fixed-point arithmetic, generally referring to rounding to the nearest integer. It can be a fixed-point decimal width. It can be considered as a scale compensation parameter.

[0065] The first formula can be considered a hardware-adapted expression for normalized divisor fixed-point conversion based on the QF fixed-point format. The formula internally completes the following: Fixed-point scaling conversion, then with the divisor Multiplication completes the fixed-point integer mapping of the first term of Newton's iteration method, adapts to the integer operation characteristics of FPGA hardware, avoids floating-point operation overhead, and sends the calculation result to the subsequent iteration link to complete the reciprocal precision correction. Then, it combines the scale compensation parameter to perform shifting and eliminate fixed-point decimal places to obtain the final quotient value.

[0066] The subtraction subunit 303 is used to extend the decimal width of 2 and perform a subtraction operation on the result of the decimal width extension and the result of the multiplication compensation to obtain the error correction result.

[0067] In this embodiment, the subtraction subunit can be considered as expanding the decimal width according to the fixed-point decimal width, subtracting the expanded result from the multiplication compensation result, and obtaining the error correction result. Based on the above, this embodiment can specifically use the subtraction subunit to perform multiplication operations on 2 and 2 to the power of F, and perform subtraction operations on the result of the multiplication operation and the multiplication compensation result to obtain the error correction result.

[0068] The second formula for obtaining the error correction result can be expressed as: , in, This can be considered as the result of error correction.

[0069] The second formula can be considered a fixed-point implementation of the Newton iteration correction term. This formula is used to complete one round of reciprocal update calculations using the Newton iteration method. Based on the mathematical derivation of the Newton iteration formula, the correction amount is calculated using the initial value of the reciprocal from the previous round, continuously approximating the true reciprocal of the divisor. The second formula can be considered as using this fixed-point conversion form, which can convert the original floating-point operations into integer operations that are easy to implement on FPGA, and complete the iterative convergence in conjunction with subsequent multiplications.

[0070] The Newton iteration correction term can be considered as an iterative update component derived from the formula of the Newton iteration method, used to gradually correct the initial value of the reciprocal so that the calculation result continuously converges to the true reciprocal of the divisor.

[0071] The second Newton multiplication subunit 304 is used to perform a multiplication operation on the second reciprocal and the error correction result to obtain the third reciprocal.

[0072] In this embodiment, the second Newton multiplication subunit can be considered as performing a multiplication operation on the second reciprocal and the error correction result according to the third formula to obtain the third reciprocal. Based on the above, this embodiment can specifically use the second Newton multiplication subunit to: perform a multiplication operation on the second reciprocal and the error correction result, and shift the result of the multiplication operation to the right by F bits to obtain the third reciprocal; F is the fixed-point decimal width of the entry in the reciprocal lookup table.

[0073] The third formula can be expressed as: , in, It can be considered the third to last.

[0074] The third formula can be considered as combining the Newton iteration correction term with the original reciprocal. Multiplying yields the updated reciprocal estimate, completing one round of Newton's iteration method. Through the operations of the first, second, and third formulas, a round of Newton's iteration method is performed on the reciprocal of the divisor, resulting in a more accurate reciprocal estimate. Still retained The composite metric is used to represent the third reciprocal relative to the divisor.

[0075] To better understand the division implementation device proposed in this embodiment, Figure 4 A schematic diagram illustrating the relationship between normalized reciprocal lookup table and fixed-point scaling is provided. Figure 4 This illustrates the normalized address generation, scale compensation, and fixed-point multiplication scaling relationships when the divisor passes through a high-bit-width Newton-corrected subpath. Figure 4 In this context, A_abs can be considered the absolute value of the dividend A, and B_abs can be considered the absolute value of the divisor B. t_1 can be considered as the result of multiplication compensation. t_2 can be considered as the error correction result. x_raw can be considered as the third reciprocal. .

[0076] Normalized address generation can be considered as shifting the binary bits of the divisor to the right by s bits, retaining the K most significant bits of the divisor, whose range falls into the K-bit non-zero address space, which can be represented as b_norm=B_abs>>s; scale compensation can be considered as applying scale compensation to the results of the Newton iteration method and the results of the quotient multiplication unit through the scale compensation parameter s; fixed-point multiplication scaling can be considered as scaling the intermediate results, the final result and the quotient through the fixed-point decimal width F during the Newton iteration method, which can eliminate numerical offset.

[0077] The technical solution of this embodiment obtains the divisor with the highest K significant bits by shifting the high-bit-width divisor and adapts the Newton iteration method formula to QF fixed-point integer arithmetic form, thus avoiding the hardware resource overhead caused by floating-point arithmetic. In addition, it completes the scale uniform conversion by using the preset fixed-point decimal bit width F and scale compensation parameter s. The iteration process can be adapted to the high-bit-width Newton correction sub-path, effectively reducing the DSP flip caused by high-bit-width full-precision arithmetic, realizing the rapid convergence of the reciprocal estimate, ensuring the calculation accuracy of the final quotient, and facilitating pipeline hardware timing design.

[0078] Example 3 Figure 5 This is a schematic diagram of a division implementation device according to Embodiment 3 of the present invention. The embodiments of the present invention further refine the aforementioned low-bit-width processing unit, such as... Figure 5 As shown, the unit includes: The second lookup table subunit 501 is used to obtain the first reciprocal of the absolute value of the divisor based on the reciprocal lookup table.

[0079] In this embodiment, the second lookup table subunit can be considered as the first reciprocal, which is used to directly obtain the reciprocal of the divisor whose actual effective bit width is not greater than the preset bit width threshold through the reciprocal lookup table.

[0080] The first gating processing subunit 502 is used to control the first Newton multiplication subunit to enter a low-power state.

[0081] In this embodiment, as described above, the first Newton multiplication subunit can be considered as performing multiplication calculations on the reciprocal of the absolute value of the divisor and the absolute value of the divisor. However, for low-bit-width divisors, the initial value of the reciprocal obtained directly from the reciprocal lookup table is already accurate enough to meet the system's computational requirements, eliminating the need for additional execution of the Newton iteration method. The Newton iteration method requires multiple multiplication operations, which consumes FPGA internal DSP resources, increases the number of signal toggles, raises dynamic power consumption, and lengthens computational latency.

[0082] Based on this, the first gating processing subunit can be considered as a low-power function for implementing the low-bit-width bypass sub-path. When the path decision unit selects the low-bit-width bypass sub-path for the divisor, the first gating processing subunit controls the first Newton multiplication subunit to enter a low-power state by preventing the data from flipping.

[0083] The low-power state can be considered the operating state of this division implementation device for low-bit-width divisors. In this state, the hardware does not start the Newton-Raphson iteration method for calculation, but directly obtains the reciprocal estimate through a lookup table, saving multiple rounds of multiplication operations. This state reduces the signal switching behavior of the DSP unit, reduces dynamic power consumption, and also reduces the occupation of logic resources.

[0084] The delay compensation subunit 503 is used to temporarily store the first countdown for a preset duration so that the processing delay of the high-width processing unit is the same as that of the low-width processing unit.

[0085] As described above, the low-bit-width processing unit bypasses the first Newton multiplication subunit, the subtraction subunit, and the second Newton multiplication subunit when processing divisors; therefore, its inherent output delay is less than that of the high-bit-width processing unit. To ensure that the outputs of the two units maintain the same timing when reaching the quotient multiplication unit and the final output port, this embodiment includes a delay compensation subunit.

[0086] The preset duration can be considered as a pre-configured fixed waiting period, corresponding to the number of clock cycles required for the high-bit-width Newton correction sub-path to complete table lookup and Newton iteration, determined by the cycle difference between the two processing paths; the processing delay can be considered as the number of clock cycles consumed from the entry of a set of input data into the processing path to the output of a valid reciprocal result. The low-bit-width processing unit only performs table lookup without iteration, resulting in a short delay; the high-bit-width processing unit includes multiple rounds of Newton iteration, resulting in a longer delay.

[0087] In this embodiment, the delay compensation subunit can be considered as setting a preset duration and caching the first reciprocal obtained by the second lookup table subunit for a preset duration, so that the processing delay of the high-bit-width processing unit is the same as that of the low-bit-width processing unit.

[0088] Based on the above, this embodiment can further optimize the delay compensation subunit to include at least one register or queue; the number of registers or queues is determined based on the access delay of the high-width processing unit.

[0089] In one implementation, the delay compensation subunit can be considered as having a lookup table access delay of 1 clock cycle, a subtraction unit delay of 1 clock cycle, and the first Newton multiplication unit, the second Newton multiplication unit, and the quotient multiplication unit are all independent DSPs. If each DSP is configured to output in 1 clock cycle, the total delay of the high-bit-width processing unit can be 5 clock cycles; the low-bit-width processing unit, by inserting a delay register of the corresponding number of stages, ensures that its quotient result is also output after the same 5 clock cycles.

[0090] Here, a clock cycle can be considered as a single clock cycle; a delay register can be considered as a hardware register used to temporarily buffer data or postpone the data output time. Each time a delay register is passed, the data output is delayed by one clock cycle.

[0091] The second gating processing subunit 504 is used to control the second Newton multiplication subunit to enter a low-power state.

[0092] In this embodiment, as described above, to reduce dynamic power consumption, the low-bit-width processing unit can directly obtain the reciprocal of the absolute value of the low-bit-width divisor without needing to perform Newton's iteration method. Based on this, the second gating processing subunit can be considered as implementing the low-power function of the low-bit-width bypass sub-path. When the path decision unit selects a low-bit-width bypass sub-path for the divisor, the second gating processing subunit controls the second Newton multiplication subunit to enter a low-power state.

[0093] Based on the above, this embodiment further refines the first gating processing subunit and the second gating processing subunit, specifically for: Disable the clock enable port of the corresponding Newton multiplication subunit; or, keep the input register of the corresponding Newton multiplication subunit from updating; or, block the valid data signal entering the high-width processing unit; or, clamp the input of the corresponding Newton multiplication subunit to a fixed value.

[0094] The clock enable port can be used to control whether the DSP hard core receives the clock to perform operations. When the port is turned off, the DSP will no longer respond to the clock and will pause multiplication and division arithmetic operations, reducing the dynamic power consumption of the circuit. The input register can be used to temporarily store the operation data sent to the DSP. Not updating the register means that the register latches the original data and no longer receives new input signals, avoiding the extra power consumption caused by frequent register toggling.

[0095] Clamping refers to forcibly locking the multiplier input to a fixed value, preventing the transmission of dynamically changing operation data, reducing the back-and-forth switching of signals within the multiplication path, and further reducing power consumption.

[0096] To better understand the division implementation device proposed in this embodiment, Figure 6 A schematic diagram of the entire pipeline path and delay matching relationship in an adaptive mode is provided. Figure 6 This shows that when the divisor passes through the low-width bypass sub-path, it bypasses the Newton-corrected multiplication stage and is sent to the quotient multiplication unit via the bypass delay register.

[0097] The adaptive mode can be considered as the division implementation device adaptively allocating a low-width bypass sub-path or a high-width Newton correction sub-path to the divisor based on the actual effective bit width of the divisor; the full pipeline path can be considered as including a low-width bypass sub-path, a high-width Newton correction sub-path, and a synchronous pipeline. The low-width bypass sub-path is delayed by a delay compensation unit so that both paths are mapped to the same fixed delay.

[0098] Figure 6 In this code, the LUT can be considered the basic programmable unit constituting the division logic; essentially, it's a small memory used to store the reciprocal lookup table. DSP1 and DSP2 can be considered chip units used to execute the relevant calculation operations of the first and second Newton multiplication subunits, respectively, on the high-bit-width Newton correction subpath. The quotient DSP can be considered a chip unit used to execute the relevant calculation operations of the quotient multiplication unit. Q_abs can be considered the absolute value of the quotient output by the quotient multiplication unit. out_valid can be considered the data validity signal of the output Q. Gated DSP1 and gated DSP2 can be considered chip units used to execute the low-power state control operations of the first and second gated processing subunits, respectively, to achieve low-power control of the high-bit-width Newton correction subpath.

[0099] The technical solution of this embodiment obtains the reciprocal result corresponding to the absolute value of the divisor by directly querying the reciprocal lookup table, thus obtaining the reciprocal estimate usable in low-bit-width scenarios. This allows low-bit-width data to skip iterative operations, reducing multiplication steps and DSP hardware resources. By gating the Newton multiplication unit, the multiplication unit in the non-operating state enters a low-power state, suppressing invalid signal flipping in the DSP unit and reducing the overall dynamic power consumption of the device.

[0100] By temporarily storing the reciprocal result of the low-bit-width path for a preset duration, the output data after timing matching is obtained, ensuring that the processing delays of the high-bit-width and low-bit-width processing paths are kept consistent, and preventing data misalignment or mismatch when the back-end pipeline receives data.

[0101] According to embodiments of the present invention, the present invention also provides a field-programmable gate array (FPGA), the FPGA including any of the division implementation devices described in the above embodiments.

[0102] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A division implementation device, characterized in that, The device includes: The bit width detection unit is used to receive the binary dividend and divisor; and to calculate the actual effective bit width of the absolute value of the divisor. The path decision unit is used to compare the actual effective bit width with a preset bit width threshold, and generate a path selection signal based on the comparison result. The path selection signal is used to indicate a low bit width bypass sub-path or a high bit width Newton correction sub-path. The low-bit-width processing unit is used to obtain the first reciprocal of the absolute value of the divisor based on the reciprocal lookup table when the path selection signal indicates a low-bit-width bypass sub-path, and input the first reciprocal into the quotient multiplication unit. A high-bit-width processing unit is used to, when the path selection signal indicates a high-bit-width Newton-corrected sub-path, obtain the second reciprocal of the highest K significant bits of the absolute value of the divisor based on a reciprocal lookup table, and correct the second reciprocal based on Newton's iteration method to obtain a third reciprocal; input the third reciprocal into the quotient multiplication unit; where K is equal to the preset bit-width threshold. The quotient multiplication unit is used to calculate the quotient of the dividend and the divisor based on the dividend and the input first reciprocal or the third reciprocal.

2. The apparatus according to claim 1, characterized in that, The path decision unit is specifically used for: Compare the actual effective bit width with the preset bit width threshold; If the actual effective bit width is not greater than the preset bit width threshold, a path selection signal indicating a low bit width bypass sub-path is generated. If the actual effective bit width is greater than the preset bit width threshold, a path selection signal indicating a high-bit-width Newton-corrected sub-path is generated.

3. The apparatus according to claim 1, characterized in that, The high bit-width processing unit corrects the second reciprocal based on the scale compensation parameter and Newton's iteration method to obtain the third reciprocal; The quotient multiplication unit calculates the quotient of the dividend and the divisor based on the scale compensation parameter, the dividend, and the input third reciprocal. The scale compensation parameter is the difference between the actual effective bit width and the preset bit width threshold.

4. The apparatus according to claim 3, characterized in that, The high-width processing unit includes: The first lookup table subunit is used to obtain the second reciprocal of the highest K significant digits of the absolute value of the divisor based on the reciprocal lookup table; The first Newton multiplication subunit is used to perform a multiplication operation on the absolute value of the second reciprocal and the divisor, and to compensate the result of the multiplication operation based on the scale compensation parameter to obtain a multiplication compensation result. The subtraction subunit is used to extend the decimal width of 2 and perform a subtraction operation between the result of the decimal width extension and the multiplication compensation result to obtain the error correction result; The second Newton multiplication subunit is used to perform a multiplication operation on the second reciprocal and the error correction result to obtain the third reciprocal.

5. The apparatus according to claim 4, characterized in that, The first Newton multiplication subunit is specifically used to: perform a multiplication operation on the absolute values ​​of the second reciprocal and the divisor, shift the result of the multiplication operation to the right by s positions, and obtain a multiplication compensation result; where s is the value of the scale compensation parameter; The subtraction subunit is specifically used to: perform multiplication operations on 2 and 2 to the power of F, and perform subtraction operations on the result of the multiplication operation and the multiplication compensation result to obtain the error correction result; The second Newton multiplication subunit is specifically used to: perform a multiplication operation on the second reciprocal and the error correction result, and shift the result of the multiplication operation to the right by F bits to obtain the third reciprocal; where F is the fixed-point decimal width of the entry in the reciprocal lookup table.

6. The apparatus according to claim 3, characterized in that, The quotient multiplication unit is specifically used for: Perform a multiplication operation on the absolute value of the dividend and its first reciprocal, shift the result of the multiplication operation to the right by F bits, and obtain the quotient of the dividend and the divisor; or, Perform a multiplication operation on the absolute value of the dividend and its third reciprocal, and shift the result of the multiplication operation to the right by F+s positions to obtain the quotient of the dividend and the divisor; Wherein, F is the fixed-point decimal width of the entry in the reciprocal lookup table, and s is the value of the scale compensation parameter.

7. The apparatus according to claim 4, characterized in that, The low-bit-width processing unit includes: The second lookup table subunit is used to obtain the first reciprocal of the absolute value of the divisor based on the reciprocal lookup table; The first gating processing subunit is used to control the first Newton multiplication subunit to enter a low-power state. The delay compensation subunit is used to temporarily store the first countdown for a preset duration so that the processing delay of the high-bit-width processing unit is the same as the processing delay of the low-bit-width processing unit. The second gating processing subunit is used to control the second Newton multiplication subunit to enter a low-power state.

8. The apparatus according to claim 7, characterized in that, The first gating processing subunit and the second gating processing subunit are specifically used for: Disable the clock enable port of the corresponding Newton multiplication subunit; or, keep the input register of the corresponding Newton multiplication subunit from updating; or, block the valid data signal entering the high-width processing unit; or, clamp the input of the corresponding Newton multiplication subunit to a fixed value.

9. The apparatus according to claim 7, characterized in that, The delay compensation subunit includes at least one register or queue; the number of the register or the queue is determined based on the access delay of the high-width processing unit.

10. The apparatus according to any one of claims 1-9, characterized in that, The preset bit width threshold is the address bit width of the reciprocal lookup table.

11. A field-programmable gate array (FPGA), characterized in that, The FPGA includes the division implementation device according to any one of claims 1-10.

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