Timing optimization method and device, chip, display device, electronic device and medium

Abstract

This disclosure relates to a timing optimization method and apparatus, chip, display device, electronic device, and medium. The method includes, within the current clock cycle, determining a first sign bit and a first reciprocal of the first data based on first and second data to be divided, under the condition of satisfying a first condition; and, within the next clock cycle, calculating the division result based on the first sign bit and the first reciprocal, under the condition of satisfying a second condition; wherein the first sign bit is used to indicate whether the division result is positive or negative. This disclosure splits the division operation into two clock cycles, with a moderate logic depth in each clock cycle. Each step can be completed while meeting timing constraints, resulting in simple and clear logic that can function normally without setting multi-cycle paths, significantly improving hardware resource utilization and greatly enhancing chip performance and processing power.

Description

Technical Field

[0001] This disclosure relates to the field of signal processing technology, and in particular to a timing optimization method and apparatus, chip, display device, electronic device and medium. Background Technology

[0002] Display driver ICs (DDICs) are the core components controlling screen imaging. Due to the instability of driving transistors and the aging of light-emitting materials, more complex compensation algorithms are required. Coupled with the demand for high refresh rates, timing optimization of DDICs is crucial. These algorithms involve numerous multiplication and division operations. The division unit design not only consumes area resources but is also prone to timing violations. Currently, most chip designs use " / " directly and implement division operations with the aid of synthesis tools. However, this approach has several problems. For example, to meet timing requirements, the multicycle path setting is demanding, requiring multiple cycles to complete a task, resulting in low throughput and low hardware utilization efficiency. Summary of the Invention

[0003] In view of this, the present disclosure proposes a timing optimization method and apparatus, a chip, a display device, an electronic device, and a medium.

[0004] According to one aspect of this disclosure, a timing optimization method is provided for a divider, the method comprising: within a current clock cycle, if a first condition is met, determining a first sign bit and a first reciprocal of the first data based on first data and second data to be divided; within the next clock cycle of the current clock cycle, if a second condition is met, calculating the division result based on the first sign bit and the first reciprocal; wherein the first sign bit is used to indicate whether the division result is a positive or negative number.

[0005] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data to be divided includes: determining the second sign bit of the first data and the third sign bit of the second data; performing an XOR operation on the second sign bit and the third sign bit to obtain the first sign bit; wherein the second sign bit is used to indicate whether the first data is positive or negative, and the third sign bit is used to indicate whether the second data is positive or negative.

[0006] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data used for division further includes: determining the first absolute value of the first data; and determining the first reciprocal corresponding to the first absolute value according to a preset mapping relationship; wherein the preset mapping relationship is used to indicate the correspondence between different values ​​and their reciprocals.

[0007] In one possible implementation, calculating the division result based on the first sign bit and the first reciprocal includes: performing a multiplication operation on the second absolute value of the second data and the first reciprocal to obtain a third absolute value; and determining the division result based on the first sign bit and the third absolute value.

[0008] In one possible implementation, the method further includes: determining a second absolute value of the second data within the current clock cycle, provided that the first condition is met.

[0009] In one possible implementation, the first condition includes: the first enable signal changing from a first level to a second level, and the second enable signal being at a third level; the second condition includes: the first enable signal being at a first level, and the second enable signal changing from a third level to a fourth level; wherein the first level is lower than the second level, and the third level is lower than the fourth level.

[0010] According to another aspect of this disclosure, a timing optimization apparatus is provided, the apparatus comprising: a first module, configured to determine a first sign bit and a first reciprocal of the first data based on first data and second data to be divided within a current clock cycle, provided that a first condition is met; and a second module, configured to calculate the division result based on the first sign bit and the first reciprocal within the next clock cycle of the current clock cycle, provided that a second condition is met; wherein the first sign bit is used to indicate whether the division result is positive or negative.

[0011] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data to be divided includes: determining the second sign bit of the first data and the third sign bit of the second data; performing an XOR operation on the second sign bit and the third sign bit to obtain the first sign bit; wherein the second sign bit is used to indicate whether the first data is positive or negative, and the third sign bit is used to indicate whether the second data is positive or negative.

[0012] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data used for division further includes: determining the first absolute value of the first data; and determining the first reciprocal corresponding to the first absolute value according to a preset mapping relationship; wherein the preset mapping relationship is used to indicate the correspondence between different values ​​and their reciprocals.

[0013] In one possible implementation, calculating the division result based on the first sign bit and the first reciprocal includes: performing a multiplication operation on the second absolute value of the second data and the first reciprocal to obtain a third absolute value; and determining the division result based on the first sign bit and the third absolute value.

[0014] In one possible implementation, the apparatus further includes a third module for: determining a second absolute value of the second data within the current clock cycle, provided that the first condition is met.

[0015] In one possible implementation, the first condition includes: the first enable signal changing from a first level to a second level, and the second enable signal being at a third level; the second condition includes: the first enable signal being at a first level, and the second enable signal changing from a third level to a fourth level; wherein the first level is lower than the second level, and the third level is lower than the fourth level.

[0016] According to another aspect of this disclosure, a chip is provided that includes the timing optimization apparatus described above.

[0017] According to another aspect of this disclosure, a display device is provided, including a plurality of display units and at least one of the aforementioned timing optimization devices.

[0018] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0019] According to another aspect of this disclosure, an electronic device is provided, including the display device described above.

[0020] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored in the memory.

[0021] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, which, when executed by a processor, implement the method described above.

[0022] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0024] Figure 1 A flowchart illustrating the timing optimization method provided in an embodiment of this disclosure is shown.

[0025] Figure 2 The timing diagrams of each signal in the timing optimization method provided in the embodiments of this disclosure are shown.

[0026] Figure 3 A schematic diagram of the timing optimization method provided in the embodiments of this disclosure is shown.

[0027] Figure 4 A block diagram of a timing optimization apparatus provided in an embodiment of this disclosure is shown. Detailed Implementation

[0028] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0029] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0030] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0031] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0032] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0033] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0034] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0035] To facilitate understanding of the technical solutions provided by the embodiments of this disclosure by those skilled in the art, the technical environment for implementing the technical solutions will be described below.

[0036] The display driver chip is the core component that controls screen imaging. It is responsible for converting the image signals sent by the processor into precise electrical signals, thereby controlling the brightness and color of each pixel on the screen, enabling text and images to be displayed. It is often referred to as the "brain" of the display panel.

[0037] Compared to liquid crystal display (LCD) screens, organic light-emitting semiconductor (OLED) screens require more complex compensation algorithms due to the instability of driving transistors and the aging of light-emitting materials. In addition, with the increasing demand for high refresh rates (120Hz, 144Hz, etc.), timing optimization of OLED display driver chips has become crucial.

[0038] Timing optimization of sequential circuits is a core aspect of chip design, aiming to resolve timing violations and balance constraints such as area and power consumption. Optimization needs to be carried out throughout the front-end (RTL design) and back-end (physical implementation) processes, and should be iteratively performed based on the timing analysis results from synthesis, placement, and routing stages.

[0039] In the RTL coding stage, the focus of optimization is to improve timing through algorithm reconstruction and structured design. For example, pipelining techniques can be used to decompose long paths into multi-level registers to reduce critical path latency, or resource sharing can be used to reduce the number of logical levels on the critical path. At the same time, parametric design and hierarchical coding facilitate tool optimization and avoid excessively long combinational logic.

[0040] To compensate for the instability and aging issues of OLED devices and achieve better visual effects, the image processing algorithms in OLED display driver chips are more complex, such as gradient compensation, mura compensation, and temperature compensation algorithms, all of which involve multiple addition, subtraction, multiplication, and division operations. Generally speaking, under the same conditions, the more complex the logic, the worse the timing of the circuit. The most complex of the above operations is the division unit design, which not only consumes a lot of area resources but is also prone to timing violations, making it difficult for the chip to run at higher frequencies.

[0041] Currently, in chip design, the division function is directly implemented by using " / ", and the logic is automatically synthesized by synthesis tools. For example, in SMIC 40nm process, under the clock constraint of 200MHz, the design includes a divider module that divides a 17-bit signed number by an 11-bit signed number to obtain a 17-bit signed quotient. The timing constraint setting and area result are as follows: (1) Without setting the multicycle path, the setup time margin (setupslack) is -1.04, which does not meet the timing requirements. The gate count is 6419, which consumes a lot of area resources; (2) Setting the multicycle path to 2 and the setup slack to 0 just meets the timing requirements. The gate count is 4890; (3) Setting the multicycle path to 3 and the setup slack to 0.22 meets the timing requirements. The gate count is 4513. Under normal circumstances, considering the additional path delay caused by the back-end placement and routing insert buffer, it is necessary to set the multicycle path to 3 to ensure that the chip can work stably for a long time. This means that using " / " directly to design a divider requires three clock cycles to process a division task, resulting in a three-cycle delay and a gate count of 4513. This method is the most convenient for designers, but it has many problems: (1) There is no specific logic optimization, which consumes a lot of area resources. (2) In order to meet the timing requirements, the multicycle path setting requirement is large, requiring multiple cycles to complete a task, resulting in low throughput and low hardware utilization efficiency. (3) The delay cycle number is large, the porch requirement is large (the blank time between the synchronization signal and the effective data is lengthened), which limits the application in actual projects.

[0042] To address the aforementioned technical problems, this disclosure provides a timing optimization method applicable to dividers. Now, in conjunction with... Figures 1 to 3 The timing optimization method provided in the embodiments of this disclosure is illustrated below. For example... Figure 1 As shown, the timing optimization method may include the following steps S101 to S102.

[0043] In step S101, within the current clock cycle, if the first condition is met, the first sign bit and the first reciprocal of the first data are determined based on the first data and the second data used for division.

[0044] like Figure 2 As shown, the clock signal is pulled high, initiating a new clock cycle. The clock signal provides a synchronous clock reference for the entire divider / the entire division operation. Being pulled high means the clock signal changes from a low level to a high level. High and low levels are essentially two states of voltage. A high level represents a higher voltage, typically corresponding to logic 1. A low level represents a lower voltage, typically corresponding to logic 0. The specific voltage values ​​for high and low levels depend on the actual circuit.

[0045] The first condition includes: the first enable signal changing from a first level to a second level, and the second enable signal being at a third level, wherein the first level is lower than the second level. That is, within the current clock cycle, when the first enable signal is pulled high, the first sign bit and the first reciprocal are determined.

[0046] The data required for division includes a first data point and a second data point. The first data point refers to the divisor involved in the division operation. For example, the first data point can be determined based on... Figure 2 The shown divisor[10:0] signal indicates that, in this example, the first data is an 11-bit signed number, b0. The second data refers to the dividend involved in the division operation. For example, the second data can be determined according to... Figure 2 The signal shown, divideend[16:0], indicates that, in this example, the second data is a 17-bit signed number, a0.

[0047] The first sign bit refers to the sign bit of the division result (i.e., the quotient), which is determined by the sign bits of the dividend and the divisor. The first sign bit is used to indicate whether the result of the division operation is positive or negative.

[0048] The first reciprocal refers to the reciprocal of the absolute value of the first data, i.e., the divisor. In this embodiment, since directly calculating the reciprocal incurs significant time overhead, a lookup table (LUT) is used to pre-store the reciprocals corresponding to each value, and the first reciprocal is quickly obtained by looking up the table.

[0049] In step S102, in the next clock cycle of the current clock cycle, if the second condition is met, the division result is calculated based on the first sign bit and the first reciprocal.

[0050] The second condition includes: the first enable signal is at the first level, and the second enable signal changes from the third level to the fourth level, where the third level is lower than the fourth level. In other words, the division result is calculated when the second enable signal is pulled high in the next clock cycle of the current clock cycle. It is important to note that the first and second enable signals are two non-overlapping enable signals; they will not both be high at the same time.

[0051] In this way, by splitting the division operation into two clock cycles, the logic depth within each clock cycle is moderate, and each step can be completed while meeting timing constraints. The logic is simple and clear, and it can work normally without setting up multi-cycle paths. Compared to the traditional method of directly using " / ", which requires three clock cycles to complete a division operation, this method only requires two clock cycles, reducing processing latency. At the same time, the two-stage pipelined design enables the divider to achieve fully pipelined operation, and a new division task can be started in each clock cycle. The throughput is increased from 1 / 3 of the traditional method to 1, significantly improving hardware resource utilization and greatly improving chip performance and processing power.

[0052] In step S101, determining the first sign bit and the first reciprocal of the first data based on the first and second data to be divided may include: a process for determining the first sign bit. This process may include: determining the second sign bit of the first data and the third sign bit of the second data; performing an XOR operation on the second sign bit and the third sign bit to obtain the first sign bit.

[0053] The second sign bit refers to the sign bit of the first data (e.g., ...). Figure 3 The sign bit (2) indicates whether the first data is positive or negative. The third sign bit indicates the sign bit of the second data (e.g., ...). Figure 3 The sign bit (1) in the second sign bit is used to indicate whether the second data is positive or negative. For signed numbers, the highest bit (MSB) is usually used as the sign bit, with 0 indicating a positive number and 1 indicating a negative number. For example, the second sign bit is divisor

[10] and the third sign bit is dividend

[16] .

[0054] The XOR operation refers to the logical XOR operation. It implements the sign rule of signed number division—"same sign equals positive, different sign equals negative"—using an XOR logic gate. When the two sign bits are the same, the XOR result is 0, indicating a positive quotient. When the two sign bits are different, the XOR result is 1, indicating a negative quotient.

[0055] For example, such as Figure 2As shown, when the first data b0 is positive and the second data a0 is negative, the XOR result of the second sign bit corresponding to b0 and the third sign bit corresponding to a0 is 1, thus the first sign bit is 1, which indicates that the quotient is negative.

[0056] In practical applications, the quotient_sign signal corresponding to the first sign bit (such as...) Figure 2 As shown, after the calculation is completed in the current clock cycle, it will be registered for a clock cycle (equivalent to a delay of one clock cycle) for the next clock cycle to calculate the result of the division operation.

[0057] In this way, the sign bit of the quotient is determined through a simple XOR logic operation, resulting in fewer logic levels and less latency. The calculation of the sign bit, the absolute value operation, and the reciprocal lookup are all completed in parallel within the same clock cycle, making full use of the computing resources within the clock cycle and avoiding the need to add an extra pipeline stage for sign calculation, which helps to achieve timing balance in a two-stage pipeline.

[0058] In step S101, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data used in the division operation may further include: a process for determining the first reciprocal. This process may include: determining the first absolute value of the first data; and determining the first reciprocal corresponding to the first absolute value according to a preset mapping relationship.

[0059] The first absolute value refers to the absolute value of the first data point. For example, such as... Figure 2 As shown, the first absolute value of the first data b0 can be determined by the corresponding divideend[15: 0] signal, i.e., c0.

[0060] Preset mapping relationships are used to indicate the correspondence between different numerical values ​​and their reciprocals. For example, preset mapping relationships can be stored in a lookup table (LUT), which is a pre-established data table used to store the correspondence between different numerical values ​​and their reciprocals. The LUT is pre-configured during the chip design phase. When the chip is working, it quickly looks up the corresponding reciprocal by inputting the first absolute value as the address index, and then outputs the first reciprocal, which is the reciprocal of the absolute value of the divisor, i.e., 1 / |divisor|.

[0061] In this way, obtaining the reciprocal of the divisor through a LUT table lookup avoids using complex divider logic to calculate the reciprocal, thus significantly reducing the level and area consumption of combinational logic. LUT tables offer fast access speed and fixed latency, which is beneficial for timing convergence. Compared to the traditional method of directly using the " / " operator, this solution transforms the reciprocal calculation into a table lookup operation and the division operation into a multiplication operation, significantly reducing the circuit implementation difficulty and area overhead, while maintaining essentially the same accuracy as the original divider, with an error not exceeding 1.

[0062] In step S102, calculating the division result based on the first sign bit and the first reciprocal may include: performing a multiplication operation on the second absolute value of the second data and the first reciprocal to obtain the third absolute value (e.g., Figure 3 (3) Based on the first sign bit and the third absolute value, determine the result of the division operation. The third absolute value is also the absolute value of the quotient. Combined with the sign bit of the quotient (i.e., the first sign bit), the third absolute value is converted into a signed number to obtain the result of the division operation, which is the quotient obtained by dividing the dividend by the divisor.

[0063] This approach replaces the complex logic of traditional dividers with multiplication operations, significantly reducing the depth and area consumption of combinational logic. Multipliers are mature and highly optimized basic arithmetic units in digital circuits, possessing excellent timing characteristics and easily meeting high-frequency clock constraints. This method, while maintaining essentially the same accuracy as the original divider, under the same process conditions, does not define a multicycle path, achieving a setup slack of 0.01, meeting timing requirements, and a gate count of 3222. Compared to the traditional " / " method, ensuring an error of no more than 1, it splits the division process into two steps, reducing the delay by one clock cycle (two pipeEn) and decreasing the gate count by 1290. Furthermore, the original design required a new task to start every three cycles, resulting in a throughput of 1 / 3; the current timing design enables full pipelined operation with a throughput of 1, greatly improving chip performance and processing power.

[0064] Furthermore, in the method, the second absolute value of the second data is determined when the first condition is met within the current clock cycle. That is, the second absolute value is determined when the first enable signal is pulled high within the current clock cycle.

[0065] like Figure 2 As shown, this method determines the first sign bit when the first enable signal is pulled high during the current clock cycle (see [link]). Figure 2 The quotient_sign signal in the first absolute value (see quotient_sign signal in the first absolute value in the second absolute value in the third absolute value in the fourth absolute value in the fifth absolute value in the sixth ... Figure 2 The dividend[15:0] signal in the middle) and the first reciprocal (see the first reciprocal) Figure 2 The `recip_divisor[9:0]` signal in the clock cycle. When the second enable signal is pulled high in the next clock cycle, the output quotient is determined (see...). Figure 2 (quotient[16:0] signal in the middle).

[0066] This method specifically targets the optimization of timing circuits in display driver chips, splitting the division operation into two steps: LUT table selection and multiplier. This method can reduce the area consumption of the divider while maintaining essentially the same accuracy as the original divider; optimize circuit timing, reducing the number of cycles required to complete the division function and improving throughput; reduce latency, decrease porch requirements, and lessen application limitations.

[0067] This disclosure also provides a timing optimization apparatus, the apparatus comprising: a first module, configured to determine a first sign bit and a first reciprocal of the first data based on first data and second data to be divided within the current clock cycle, provided that a first condition is met; and a second module, configured to calculate the division result based on the first sign bit and the first reciprocal within the next clock cycle of the current clock cycle, provided that a second condition is met; wherein the first sign bit is used to indicate whether the division result is positive or negative.

[0068] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data to be divided includes: determining the second sign bit of the first data and the third sign bit of the second data; performing an XOR operation on the second sign bit and the third sign bit to obtain the first sign bit; wherein the second sign bit is used to indicate whether the first data is positive or negative, and the third sign bit is used to indicate whether the second data is positive or negative.

[0069] In one possible implementation, determining the first sign bit and the first reciprocal of the first data based on the first data and the second data used for division further includes: determining the first absolute value of the first data; and determining the first reciprocal corresponding to the first absolute value according to a preset mapping relationship; wherein the preset mapping relationship is used to indicate the correspondence between different values ​​and their reciprocals.

[0070] In one possible implementation, calculating the division result based on the first sign bit and the first reciprocal includes: performing a multiplication operation on the second absolute value of the second data and the first reciprocal to obtain a third absolute value; and determining the division result based on the first sign bit and the third absolute value.

[0071] In one possible implementation, the apparatus further includes a third module for: determining a second absolute value of the second data within the current clock cycle, provided that the first condition is met.

[0072] In one possible implementation, the first condition includes: the first enable signal changing from a first level to a second level, and the second enable signal being at a third level; the second condition includes: the first enable signal being at a first level, and the second enable signal changing from a third level to a fourth level; wherein the first level is lower than the second level, and the third level is lower than the fourth level.

[0073] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0074] This disclosure also provides a chip including the timing optimization device described above.

[0075] This disclosure also provides a display device, including a plurality of display units and at least one of the above-described timing optimization devices.

[0076] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0077] Liquid crystal display (LCD) panels are a display technology that uses liquid crystal materials as its core. The liquid crystal molecules in an LCD panel do not emit light directly; instead, the alignment of the liquid crystal molecules is changed by applying voltage, thereby controlling the transmittance of light emitted by the backlight module. This, combined with color filters, enables the display of color images. Individual pixel units are extremely small (tens to hundreds of micrometers in size).

[0078] A light-emitting diode (LED) display panel is a display technology that uses light-emitting diodes (LEDs) as its core, typically referring to traditional LED displays. Individual light-emitting units are relatively large (hundreds of micrometers to millimeters in size), and they emit light directly through an LED array to create images.

[0079] Mini light-emitting diode (LED) display panels use micron-sized LEDs with dimensions ranging from 100μm to 500μm, a size between traditional LEDs and Micro-LEDs. By employing micron-sized LEDs as a backlight, a higher density of local dimming areas is achieved, thereby improving brightness, contrast, and energy efficiency.

[0080] Micro light-emitting diode (LED) display panels use micron-sized LEDs with dimensions of less than 100μm (or even 50μm). Each pixel includes self-emissive independent red, green, and blue micron-sized LEDs, eliminating the need for a backlight module.

[0081] Quantum dot light-emitting diode (LED) display panels display content by generating pure color light through the excitation of quantum dot materials (nanocrystals) under light, eliminating the need for a backlight. In some examples, a layer of quantum dot material is added in front of the LCD backlight, using blue LEDs to excite the quantum dots to improve color gamut and color accuracy.

[0082] Organic light-emitting diode (OLED) display panels are made by coating an organic material onto a transparent substrate such as glass. When an electric current passes through the organic material, it emits light spontaneously. Each pixel can be controlled independently, eliminating the need for backlighting.

[0083] A cathode ray tube display panel (CRT) is a display technology that uses a cathode ray tube (CRT) as its core imaging device. Its working principle involves heating the cathode to emit an electron beam, which, after being accelerated by high voltage and deflected by a magnetic field, bombards a phosphor coating on the inner surface of the screen, thereby exciting the phosphor to emit light and create an image.

[0084] Digital Light Processing Display Panel (DLP) is a projection display technology centered around a Digital Micromirror Device (DMD). Its working principle involves controlling millions of micrometer-sized micro-aluminum reflective mirrors on the DMD chip to rapidly switch the light emitted from the reflected light source, which is then projected through a lens or light absorber to form an image.

[0085] A field emission display panel (FET) is a display technology based on the field emission effect. Its basic principle involves creating numerous tiny field emission electron sources (cathodes) on a cathode panel. Under the influence of an electric field, electrons are directly "extracted" and bombarded with phosphors on the opposite anode panel, causing it to emit light and form an image.

[0086] Plasma display panels, also known as plasma display panels, are a display technology based on the principle of gas discharge. Their core light-emitting unit is a tiny plasma cavity, each filled with an inert gas (such as neon or xenon). When a voltage is applied, the gas inside the cavity undergoes plasma discharge, generating ultraviolet light, which in turn excites red, green, and blue phosphors within the cavity to emit visible light for imaging. They feature self-illumination, wide viewing angles, and high contrast.

[0087] Electrophoretic display panels are a type of reflective display technology based on electrophoresis. Their core principle is that charged pigment particles move under the influence of an electric field to display images. This technology itself does not emit light; it relies on ambient light reflection for imaging, offering a paper-like visual experience, ultra-low power consumption, and good visibility even in strong light.

[0088] Electro-wetting display panels are a type of reflective display technology based on the electro-wetting effect. The principle is to create an image by precisely driving the ink to shrink and spread using an electric field. Individual pixel units are small (micrometer-level), offering advantages such as high brightness, high contrast, fast response time (down to millisecond levels), and low power consumption.

[0089] Fine-pitch display panels refer to LED display panels with a pixel pitch of 2.5mm or less. Compared to traditional LED displays (where the pixel pitch is mostly 4mm or more), they significantly reduce the size of individual light-emitting units (tens to hundreds of micrometers), allowing more pixels to be integrated within a unit area, thus achieving higher resolution, closer viewing distance, and finer image quality.

[0090] This disclosure also provides an electronic device, including the display device described above.

[0091] This disclosure also provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing the instructions stored in the memory.

[0092] For example, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablets, and other common electronic devices that require multiple chips to be cascaded together to achieve driving.

[0093] For example, electronic devices can also be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: displays, smartphones or portable devices, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0094] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0095] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0096] Figure 4 A block diagram of a timing optimization apparatus provided in an embodiment of this disclosure is shown. For example, apparatus 1900 may be provided as a server or terminal device. (Refer to...) Figure 4 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0097] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0098] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0099] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0100] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0101] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0102] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0103] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0104] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0106] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A timing optimization method, characterized in that, Applied to a divider, the method includes: Within the current clock cycle, if the first condition is met, the first sign bit and the first reciprocal of the first data are determined based on the first data and the second data to be divided. In the next clock cycle of the current clock cycle, if the second condition is met, the division result is calculated based on the first sign bit and the first reciprocal. The first sign bit is used to indicate whether the result of the division operation is a positive or negative number.

2. The method according to claim 1, characterized in that, The step of determining the first sign bit and the first reciprocal of the first data based on the first and second data used in the division operation includes: Determine the second sign bit of the first data and the third sign bit of the second data; Perform an XOR operation on the second sign bit and the third sign bit to obtain the first sign bit; The second sign bit is used to indicate whether the first data is positive or negative, and the third sign bit is used to indicate whether the second data is positive or negative.

3. The method according to claim 1, characterized in that, The step of determining the first sign bit and the first reciprocal of the first data based on the first and second data used in the division operation further includes: Determine the first absolute value of the first data; Based on the preset mapping relationship, the first reciprocal corresponding to the first absolute value is determined; The preset mapping relationship is used to indicate the correspondence between different numerical values ​​and their reciprocals.

4. The method according to claim 1, characterized in that, The calculation of the division result based on the first sign bit and the first reciprocal includes: Multiply the second absolute value of the second data with the first reciprocal to obtain the third absolute value; The result of the division operation is determined based on the first sign bit and the third absolute value.

5. The method according to claim 4, characterized in that, The method further includes: Within the current clock cycle, if the first condition is met, the second absolute value of the second data is determined.

6. The method according to any one of claims 1 to 5, characterized in that, The first condition includes: the first enable signal changing from a first level to a second level, and the second enable signal being at a third level; The second condition includes: the first enable signal is at a first level, and the second enable signal changes from a third level to a fourth level; Wherein, the first level is lower than the second level, and the third level is lower than the fourth level.

7. A timing optimization device, characterized in that, The device includes: The first module is used to determine the first sign bit and the first reciprocal of the first data based on the first data and the second data to be divided within the current clock cycle, provided that the first condition is met. The second module is used to calculate the division result based on the first sign bit and the first reciprocal in the next clock cycle of the current clock cycle, provided that the second condition is met. The first sign bit is used to indicate whether the result of the division operation is a positive or negative number.

8. A chip, characterized in that, Includes the timing optimization apparatus as described in claim 7.

9. A display device, characterized in that, It includes multiple display units and at least one timing optimization device according to claim 7.

10. The display device according to claim 9, characterized in that, The display unit includes a display panel, which includes at least one of the following: liquid crystal display panel, micro light-emitting diode display panel, light-emitting diode display panel, mini light-emitting diode display panel, quantum dot light-emitting diode display panel, organic light-emitting diode display panel, cathode ray tube display panel, digital light processing display panel, field emission display panel, plasma display panel, electrophoretic display panel, electrowetting display panel, and small-pitch display panel.

11. An electronic device, characterized in that, Includes the display device according to claim 9 or 10.

12. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 6 when executing instructions stored in the memory.

13. A non-volatile computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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