Memory access scheduling method and device for vector processing and chip

Abstract

This application relates to the semiconductor field, providing a memory access scheduling method, apparatus, and chip for vector processing. The method includes: acquiring a vector memory access instruction; dividing the vector memory access instruction into multiple independently executable micro-operations based on the granularity of the instruction; scheduling the memory access issuance order of the multiple micro-operations according to the memory access characteristics of each micro-operation to determine the target micro-operation and initiate a memory access request; acquiring write-back load information fed back from the write-back side, and adjusting the memory access issuance order and / or issuance rate of subsequent micro-operations based on the write-back load information; and scheduling the write-back order of the memory access result after the memory access result is returned, based on the data characteristics and / or dependencies corresponding to the multiple micro-operations. This application can improve resource utilization, write-back efficiency, and overall processor execution efficiency in vector memory access scenarios.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically to a memory access scheduling method, apparatus, and chip for vector processing. Background Technology

[0002] In processors that support vector extensions, vector memory access instructions typically need to load or store data from multiple elements. Since a single vector memory access instruction often corresponds to multiple elements, the processor usually needs to perform operations such as address generation, memory access request initiation, data return, and result write-back during execution. This type of processing is widely used in high-performance computing, artificial intelligence, and data-intensive processing scenarios.

[0003] In related technologies, to execute vector memory access instructions, a single vector memory access instruction is typically divided into multiple execution units, and memory access processing and result writing are completed according to a preset order or fixed rules. This approach can meet basic execution requirements, but in situations with complex access patterns, uneven distribution of data effectively involved in processing, and limited internal resources, it is prone to issues such as decreased memory access efficiency, increased processing latency, and strain on backend resources. Especially in scenarios with a large number of vector memory accesses, frontend memory access requests and backend result processing may interfere with each other, thus adversely affecting the overall execution performance of the processor. Summary of the Invention

[0004] This application provides a memory access scheduling method, apparatus, and chip for vector processing, which addresses the problems of decreased memory access efficiency, increased processing latency, and insufficient backend resources in related technologies.

[0005] In a first aspect, embodiments of this application provide a memory access scheduling method for vector processing, applied to a processor that supports vector extension, the method comprising: Retrieve vector memory access instructions; Based on the granularity of the vector memory access instruction, the vector memory access instruction is broken down into multiple independently executable micro-operations; Based on the memory access characteristics of each micro-operation, the memory access issuance order of multiple micro-operations is scheduled to determine the target micro-operation and initiate a memory access request. Obtain write-back load information from the write-back side, and adjust the memory access and / or issue sequence and / or issue rate of subsequent micro-operations based on the write-back load information; After the memory access results are returned, the write-back order of the memory access results is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

[0006] Secondly, embodiments of this application provide a memory access scheduling apparatus for vector processing, which has the function of implementing the memory access scheduling method for vector processing corresponding to the first aspect described above. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function, and the modules can be software and / or hardware. In one embodiment, the memory access scheduling apparatus for vector processing includes: The processor core unit is configured to fetch vector memory access instructions; The vector execution unit is configured to break down the vector memory access instruction into multiple independently executable micro-operations according to the granularity of the vector memory access instruction. The memory access unit is configured to schedule the memory access issuance order of multiple micro-operations according to the memory access characteristics of each micro-operation, so as to determine the target micro-operation and initiate a memory access request. The write-back unit is configured to acquire write-back load information fed back from the write-back side, and adjust the memory access launch order and / or launch rate of subsequent micro-operations based on the write-back load information; after the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

[0007] Thirdly, embodiments of this application provide a chip including a processor coupled to a transceiver for executing the vector-oriented memory access scheduling method provided in the first aspect of this application. In one possible design, the chip can also be a dedicated hardware structure for implementing the technical solution provided in the first aspect above; for example, memory access scheduling involving vector-oriented processing can be implemented by a dedicated processor.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the memory access scheduling method for vector-oriented processing as described in the first aspect.

[0009] Fifthly, embodiments of this application provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the memory access scheduling method for vector-oriented processing described in the first aspect.

[0010] Compared to existing technologies, in this embodiment, after obtaining the vector memory access instruction, the instruction is divided into multiple independently executable micro-operations according to the granularity of the division. The memory access issuance order of these micro-operations is then scheduled based on their memory access characteristics. This allows micro-operations with higher address continuity, higher mask density, or higher memory access benefits to initiate memory access requests first, thereby reducing the memory resource occupation by low-benefit micro-operations, lowering the overall memory access waiting time, and improving memory access processing efficiency. Furthermore, by obtaining write-back load information from the write-back side and adjusting the memory access issuance order and / or issuance rate of subsequent micro-operations based on this information, the memory access side can adaptively schedule according to the resource status of the write-back side. This avoids excessive issuance by the memory access side leading to write-back path congestion and buffer resource accumulation, alleviating the scheduling pressure on backend resources. Furthermore, after the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations. This can prioritize the release of buffer resources and / or prioritize the satisfaction of data dependencies of subsequent instructions, thereby improving resource utilization, write-back efficiency and overall processor execution efficiency in vector memory access scenarios. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the memory access scheduling method for vector-oriented processing in an embodiment of this application. Figure 2 This is a flowchart illustrating the memory access scheduling method for vector-oriented processing according to an embodiment of this application. Figure 3 This is a schematic diagram of the structure of a computing device in an embodiment of this application.

[0012] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0013] This application provides a memory access scheduling method, apparatus, and chip for vector processing, applicable to processors, systems-on-a-chip, computing devices, or other hardware systems with vector processing capabilities that support RISC-V vector extensions. The hardware system may include an instruction decoding module, a vector memory access splitting module, a memory access issue scheduling module, a memory access module, and a data write-back scheduling module. The instruction decoding module identifies vector memory access instructions. The vector memory access splitting module splits the vector memory access instruction into multiple independently executable micro-operations. The memory access issue scheduling module determines the memory access issue order based on the memory access characteristics of each micro-operation. The memory access module executes the memory access request. The data write-back scheduling module provides write-back load information and schedules the write-back order of memory access results.

[0014] The solutions provided in this application involve technologies such as processor microarchitecture, RISC-V vector extension, vector memory access scheduling, and write-back resource scheduling, which are specifically illustrated through the following embodiments.

[0015] Processor microarchitecture refers to the hardware organization and control logic within a processor used to implement functions such as instruction fetching, instruction decoding, instruction execution, memory access, data write-back, and resource scheduling. In this application's embodiments, it is used to perform the splitting, scheduling, memory access, and write-back of vector memory access instructions in scenarios supporting vector processing.

[0016] Vector extension can be an extension mechanism in the RISC-V instruction set architecture used to support vector computation and vector memory access, allowing a single vector instruction to process multiple data elements in parallel or in batches. In this embodiment, the vector memory access instruction in the RISC-V vector extension can correspond to multiple elements and may involve information such as element width, number of elements, stride, and mask. The processor can use this information to break down the vector memory access instruction into multiple independently schedulable micro-operations.

[0017] Vector memory access scheduling refers to the control process by which a processor determines the issuing order, timing, and rate of memory access requests for vector memory access instructions or their decomposed micro-operations. In the embodiments of this application, vector memory access scheduling can be implemented based on the memory access characteristics of each micro-operation. These characteristics include at least one of step size range, address contiguity, effective mask density, and write-back resource occupancy information, prioritizing micro-operations with higher memory access benefits and less likelihood of causing write-back congestion.

[0018] Write-back resource scheduling refers to the process by which the processor allocates and controls resources such as the write-back queue, write-back buffer, write-back port, and write-back bandwidth after the memory access results are returned, and determines the write-back order of the memory access results. In the embodiments of this application, write-back resource scheduling is not only used to complete the write-back of returned data, but also to feed back write-back load information to the memory access launch scheduler. This allows the memory access launch scheduler to adjust the launch order and / or launch rate of subsequent micro-operations based on information such as the write-back queue occupancy rate, write-back buffer occupancy rate, or write-back port busy / idle status, thereby alleviating write-back congestion and improving resource utilization.

[0019] This application's embodiments can be applied to processors, chips, systems-on-a-chip, or computing devices that support vector extensions, and are particularly suitable for processor architectures that support RISC-V vector extensions. In scenarios such as high-performance computing, artificial intelligence inference, image and video processing, signal processing, and edge computing, processors typically need to execute a large number of vector memory access instructions. These instructions often correspond to multiple data elements and may involve access modes such as sequential memory access, straddle memory access, and masked memory access. Therefore, the processor needs to perform decomposition, memory access issuance, data return, and result write-back processing at the microarchitecture level. This application's embodiments introduce a cooperative scheduling mechanism among the vector memory access decomposition unit, memory access issuance scheduling unit, memory access unit, and write-back scheduling unit within the chip. Based on the memory access characteristics of micro-operations and write-back load information, the memory access issuance order and write-back order are dynamically adjusted, thereby improving the chip's memory access throughput, write-back resource utilization, and overall execution efficiency in vector memory access scenarios.

[0020] In related technologies, vector memory access instructions, after being broken down into multiple micro-operations, are typically issued and written back according to a preset order or fixed rules. This approach is relatively simple to implement, but in scenarios with complex element spans, mask control, or limited write-back resources, different micro-operations differ in terms of effective data volume, address continuity, resource consumption, and write-back pressure. A uniform scheduling method can easily lead to high-yield micro-operations not being executed first, increased overall memory access waiting time, congestion of the write-back path, and reduced resource utilization.

[0021] Compared to related technologies, this application embodiment breaks down vector memory access instructions into multiple independently executable micro-operations and schedules the memory access issuance order based on the memory access characteristics of each micro-operation, allowing micro-operations with higher memory access benefits to initiate memory access requests first. Simultaneously, by acquiring write-back load information from the write-back side, the memory access issuance order and / or issuance rate of subsequent micro-operations are adaptively adjusted to avoid excessive issuance on the memory access side leading to write-back congestion. Furthermore, after the memory access result is returned, the write-back order is scheduled based on the data characteristics and / or dependencies corresponding to the micro-operations, thereby improving resource utilization, write-back efficiency, and overall processor execution efficiency in vector memory access scenarios.

[0022] In some implementations, the vector-oriented memory access scheduling method provided in this application can be implemented by a processor system. The processor system may include a processor core unit, a vector execution unit, a memory access unit, and a write-back unit. The processor core unit acquires and decodes vector memory access instructions; the vector execution unit decomposes the vector memory access instructions and generates multiple micro-operations; the memory access unit executes the corresponding memory access request according to the memory access issue scheduling result; and the write-back unit provides feedback on write-back load information and completes the write-back of the memory access result according to the write-back scheduling result.

[0023] It should be noted that the computing devices involved in the embodiments of this application may be servers, terminal devices, embedded devices, edge computing devices, or other electronic devices configured with vector extension processors. The chips involved in the embodiments of this application may be processor chips, system-on-a-chip, accelerator chips, or application-specific integrated circuits including vector processing units.

[0024] Reference Figure 1 , Figure 1 This is a flowchart illustrating a memory access scheduling method for vector processing provided in an embodiment of this application. This method can be executed by a memory access scheduling device for vector processing. The method includes steps 101-105: Step 101: Obtain the vector memory access instruction.

[0025] In this embodiment, vector memory access instructions refer to instructions used to perform load or store operations on multiple vector elements. In RISC-V vector extensions, these instructions can be used to read multiple data elements from memory into a vector register, or to write multiple data elements from a vector register into memory. Compared to scalar memory access instructions, vector memory access instructions typically correspond to multiple elements, and are characterized by a larger number of elements, more complex access spans, and potential masking.

[0026] Further optionally, the vector memory access instruction includes a vector load instruction and / or a vector store instruction, and the memory access mode corresponding to the vector memory access instruction includes at least one of continuous memory access, straddle memory access, indexed memory access, and masked memory access.

[0027] Specifically, in step 101, obtaining the vector memory access instruction can refer to a processor supporting RISC-V vector extensions obtaining the vector memory access instruction to be executed during instruction execution. For example, the processor can identify whether the current instruction is a vector memory access instruction through the instruction decoding module, and after identifying the vector memory access instruction, send the vector memory access instruction to the vector memory splitting module.

[0028] In this embodiment, the vector memory access instruction may include a vector load instruction and / or a vector store instruction, used to perform data loading or data storage operations on multiple vector elements. The vector memory access instruction may carry or be associated with at least one of the following: element width, element quantity, step size information, mask information, memory access mode, source register information, and destination register information. Specifically, the element width characterizes the data width of each vector element, the element quantity characterizes the number of elements that the vector memory access instruction needs to process, the step size characterizes the interval between the memory access addresses of adjacent elements, the mask information indicates the valid elements participating in this memory access operation, and the memory access mode characterizes the memory access organization method corresponding to the vector memory access instruction. The above information can serve as the basis for subsequent splitting of the vector memory access instruction, memory access feature extraction, memory access issue scheduling, and write-back scheduling.

[0029] The aforementioned acquisition process includes retrieving the instruction from the instruction cache or memory, having the instruction decoding module identify that the instruction belongs to the vector memory access type, and sending the identified instruction to the vector memory access splitting module. This acquisition is not limited to a single hardware action and can also include one or more processing steps such as instruction fetching, decoding, dispatching, and enqueuing.

[0030] Step 102: Based on the granularity of the vector memory access instruction, the vector memory access instruction is divided into multiple independently executable micro-operations.

[0031] In this embodiment, the splitting granularity refers to the unit or scale used to divide a vector memory access instruction into multiple micro-operations. For example, the splitting granularity can be determined based on a single element, multiple consecutive elements, a fixed number of element groups, cache line boundaries, write-back port width, or memory access queue capacity. In this embodiment, the splitting granularity can be determined based on element width, element quantity, mask information, and step size information, so that the split micro-operations can independently participate in memory access scheduling and write-back scheduling.

[0032] Micro-operations are control units derived from vector memory access instructions and can be independently processed by the processor's internal scheduling logic. A micro-operation can correspond to one vector element or multiple vector elements. Each micro-operation can include information such as element number, element size, starting address, address span, mask valid bits, and target write-back flag, used to support subsequent memory access request issuance and result write-back.

[0033] Independent execution means that the decomposed micro-operations can independently participate in memory access launch scheduling when conditions such as address readiness, memory access queue availability, and no address conflicts are met, and independently participate in write-back scheduling after the memory access result is returned. Independent execution here does not require that there are no dependencies between micro-operations, but rather that they have the control attributes of independent scheduling, independent initiation of memory access requests, or independent write-back.

[0034] In related technologies, vector memory access instructions typically correspond to multiple data elements. If they are executed element by element in a fixed order or the entire instruction is executed as a whole, it is difficult to reflect the differences between different elements or groups of elements in terms of address continuity, mask validity, access span, and write-back resource consumption. Therefore, in this application, the vector memory access instruction is first divided into multiple micro-operations according to the granularity of the split, and then descriptive information that can be used for scheduling is established for each micro-operation, so that the subsequent memory access issue scheduling module can make differentiated selections based on the characteristics of different micro-operations.

[0035] For example, in a masked strafing vector load instruction, some elements may correspond to contiguous addresses with valid masks, while others may correspond to larger address spans or have invalid masks. If all elements are processed in a fixed order, it may result in low-value elements or low-return accesses consuming memory resources. After splitting in step 102, the processor can generate corresponding micro-operations from the set of elements with good address contiguity and high mask density, which will be prioritized for processing in subsequent scheduling, thereby improving memory access efficiency.

[0036] As an optional embodiment, in step 102, the vector memory access instruction is divided into multiple independently executable micro-operations according to the granularity of the vector memory access instruction, including: determining the element set corresponding to each micro-operation according to the element width, element number, mask information and step size information corresponding to the vector memory access instruction; and generating multiple micro-operations based on the element set.

[0037] Each micro-operation includes at least one of the following: element number, element size, starting address, address span, mask valid bits, and target write-back identifier.

[0038] As can be understood, an element set refers to the set of one or more vector elements covered by a micro-operation. The processor can divide multiple vector elements into several element sets based on the element width, element count, stride information, and mask information corresponding to the vector memory access instruction, and generate a corresponding micro-operation based on each element set. The element width represents the data bit width or byte length of each vector element, such as 8 bits, 16 bits, 32 bits, or 64 bits. The element width affects element address calculation, micro-operation data volume, write-back data volume, and write-back resource consumption. The element count represents the number of vector elements that the vector memory access instruction needs to process. The more elements there are, the more necessary it is to split the vector memory access instruction into multiple micro-operations to avoid a single instruction occupying hardware resources such as the memory access queue and write-back buffer for an extended period.

[0039] Mask information is used to indicate the elements in a vector memory access instruction that participate in the current memory access operation and those that do not. For masked vector memory access instructions, the number of valid elements in different micro-operations may vary; therefore, mask information can be used to determine the mask's valid bits, the number of valid elements, and the mask's valid density. Step information represents the address interval between the memory access addresses corresponding to adjacent vector elements. Step information can be used to determine whether memory access addresses are contiguous, the address span, and the memory access mode, thus affecting the micro-operation splitting method and subsequent memory access scheduling priority. The starting address refers to the memory access address of the first element or base element in the set of elements corresponding to the micro-operation. The processor can determine the starting address of the micro-operation based on the base address, element number, element width, and step information. Address span refers to the address range or address dispersion covered by the set of elements corresponding to the micro-operation. Address span reflects the concentration of memory access addresses for the micro-operation; a smaller or more regular address span is generally more conducive to memory merging, cache hits, or consecutive accesses.

[0040] The mask validity bit indicates whether each element in the element set participates in the current memory access operation. Elements with valid mask validity bits need to be loaded or stored, while elements with invalid mask validity bits may not initiate an actual memory access request or participate in write-back. Mask validity density represents the proportion of valid elements in a micro-operation to the total number of elements corresponding to that micro-operation. A higher mask validity density indicates a higher proportion of data actually participating in the memory access in that micro-operation, and generally results in higher memory access benefits.

[0041] The target write-back identifier is used to indicate the location or object where the memory access result of a micro-operation needs to be written back, such as the target vector register, target register segment, write-back queue entry, or other write-back target. The target write-back identifier can be used for subsequent write-back scheduling and dependency determination.

[0042] It is understood that in the above embodiments, the processor can first obtain the element width, element quantity, mask information, and step size information corresponding to the vector memory access instruction. The element width is used to determine the data size of each element, the element quantity is used to determine the overall range of elements to be processed, the mask information is used to determine whether each element is valid, and the step size information is used to determine the address relationship between adjacent elements.

[0043] Secondly, the processor can determine the set of elements corresponding to each micro-operation based on the above information. Specifically, multiple vector elements can be grouped according to a preset splitting granularity. For example, a fixed number of consecutive elements can be divided into one set of elements; elements with adjacent addresses or small address spans can be divided into one set of elements based on address continuity; and elements with a high concentration of valid elements can be grouped into the same set of elements in combination with mask information to reduce the memory access resource occupation by invalid elements.

[0044] Then, the processor can generate a corresponding micro-operation based on each set of elements. For each micro-operation, at least one of the following can be recorded: element number, element size, starting address, address span, mask valid bits, and target write-back identifier. The element number and element size represent the range of elements and data granularity covered by the micro-operation; the starting address and address span represent the range of memory access addresses corresponding to the micro-operation; the mask valid bits represent the elements actually involved in the memory access within the micro-operation; and the target write-back identifier represents the write-back target after the memory access result is returned.

[0045] Further optionally, in the above embodiments, generating multiple micro-operations based on the element set includes: determining the starting address and address span corresponding to the element set according to the element number, element size, mask valid bits, and step size information of each element in the element set; determining the number of valid elements corresponding to the element set according to the mask valid bits, and determining the mask valid density corresponding to the element set based on the number of valid elements; determining the target write-back identifier and expected write-back resource usage information corresponding to the element set according to the write-back target register and write-back data volume corresponding to the element set; and generating the micro-operations corresponding to the element set based on the starting address, address span, mask valid density, target write-back identifier, and expected write-back resource usage information.

[0046] Wherein, the starting address can be the memory access address corresponding to the first element or the reference element in the element set, the address span can be used to characterize the coverage or dispersion of the memory access addresses corresponding to each element in the element set, the mask effective density can be used to characterize the proportion of the number of effective elements in the element set to the total number of elements, the target write-back identifier can be used to indicate the write-back target after the memory access result is returned, and the expected write-back resource occupation information can be used to characterize the write-back queue, write-back buffer, write-back port or write-back bandwidth resources that the micro-operation may occupy in the write-back phase.

[0047] Therefore, the micro-operations obtained from the decomposition are not merely instruction fragments, but also carry the basic information required for memory access scheduling and write-back scheduling, enabling subsequent coordinated scheduling based on memory access characteristics and write-back load information. Micro-operations generated in this way can simultaneously carry memory access-side characteristics and write-back-side characteristics, allowing the memory access issue scheduling module to not only determine the memory access benefit of a micro-operation based on address continuity, step size range, and effective mask density, but also to estimate the write-back pressure that the micro-operation may cause based on the target write-back identifier and expected write-back resource occupancy information. Thus, the embodiments of this application can establish the correlation between micro-operations and memory access scheduling and write-back scheduling during the decomposition stage, improving the accuracy and effectiveness of subsequent coordinated memory access and write-back scheduling.

[0048] Step 103: Based on the memory access characteristics of each micro-operation, schedule the memory access issuance order of multiple micro-operations to determine the target micro-operation and initiate a memory access request.

[0049] In this embodiment, after the vector memory access instruction is broken down into multiple micro-operations, each micro-operation can enter the memory access issue scheduling module. The memory access issue scheduling module no longer initiates memory access requests solely according to the original or fixed order of the micro-operations. Instead, it performs differentiated scheduling of the issuance order of multiple micro-operations based on the memory access characteristics corresponding to each micro-operation. These memory access characteristics can be used to characterize the access patterns, effective data ratio, and impact on write-back resources of the micro-operations during the memory access phase. In this way, the processor can prioritize micro-operations with higher memory access benefits, more regular address access, a higher effective element ratio, and less likelihood of causing write-back congestion as target micro-operations, and initiate a memory access request to the memory access module when the target micro-operation meets the issuance conditions.

[0050] The target micro-operation can refer to a micro-operation selected from multiple pending micro-operations based on scheduling priority during the current scheduling cycle or window, used to initiate a memory access request. The memory access request can refer to a data read or write request issued by a memory access module, load memory unit, or memory access interface to a cache, on-chip memory, or external memory. By performing feature-driven scheduling before initiating a memory access request, the occupation of memory access resources by low-yield micro-operations can be reduced, and the probability of congestion on the subsequent write-back side can be lowered.

[0051] In this embodiment of the application, the memory access characteristics include at least one of the following: step size range, address continuity, effective mask density, and write-back resource occupancy information.

[0052] The step size range can be used to characterize the interval or variation range between the memory access addresses corresponding to each element in a micro-operation. For continuous memory access scenarios, the address interval between adjacent elements usually matches the element width; for multi-step memory access or scenarios with complex access spans, there may be a large address interval between adjacent elements. The step size range can be used to determine whether the memory accesses corresponding to the micro-operation are concentrated, regular, and whether they are likely to form continuous accesses, thus providing a basis for memory access issuance scheduling.

[0053] Address continuity can be used to characterize the degree of continuity between memory access addresses corresponding to multiple elements within a micro-operation, or between memory access addresses corresponding to adjacent micro-operations. Higher address continuity generally indicates that the memory access request corresponding to the micro-operation is more likely to utilize cache lines, bus burst transfers, or memory access merging mechanisms, thus the micro-operation usually has a higher memory access benefit. Address continuity can be determined based on the address difference between adjacent elements, whether the address ranges of adjacent micro-operations are contiguous, or whether the addresses of multiple elements fall into the same or adjacent cache lines.

[0054] Mask effective density characterizes the proportion of valid elements actually participating in memory access operations within a micro-operation, relative to the total number of elements corresponding to that micro-operation. In masked vector memory access scenarios, the number of valid elements corresponding to different micro-operations may vary significantly. A higher mask effective density indicates a higher proportion of actually valid data in the micro-operation, and the effective benefits generated by occupying memory access queues, memory access ports, and write-back resources are usually higher. Conversely, a lower mask effective density may indicate a larger number of invalid elements, and prioritizing the processing of such micro-operations can easily reduce resource utilization.

[0055] Write-back resource occupancy information can be used to characterize the write-back resources that a micro-operation may occupy after the memory access result is returned, such as the amount of data written back, the target write-back register, the write-back port occupancy period, the write-back buffer occupancy, and the number of write-back queue entries. This information enables the memory access launch scheduling module to estimate the pressure that the micro-operation will cause on the write-back side before launching the memory access request, thereby avoiding congestion of the write-back path caused by the memory access side pursuing only parallel launches.

[0056] Further optionally, memory access characteristics are extracted for each micro-operation, including: determining the step size range based on the starting address and address span corresponding to the micro-operation; determining address continuity based on the memory access addresses corresponding to adjacent micro-operations or adjacent elements; determining the effective mask density based on the ratio of the number of effective mask bits in the micro-operation to the number of elements corresponding to the micro-operation; and determining write-back resource usage information based on the data width, write-back target, and expected write-back port usage corresponding to the micro-operation.

[0057] Specifically, the processor can determine the memory access address corresponding to each element in a micro-operation based on the starting address, element number, element size, and step size information, and further determine the address interval between adjacent elements, thereby obtaining the step size range corresponding to the micro-operation. The processor can also determine address continuity based on the address distribution of multiple elements within a micro-operation, or based on the address interval relationship between the current micro-operation and adjacent micro-operations. For example, when the addresses of multiple elements increase consecutively according to their element widths, or when the address intervals corresponding to multiple micro-operations are adjacent, it can be determined that the micro-operation has high address continuity.

[0058] For mask effective density, the processor can count the number of elements with valid mask bits in a micro-operation and compare or calculate the ratio of this number to the total number of elements corresponding to that micro-operation to obtain the mask effective density. For write-back resource occupancy information, the processor can estimate the write-back resources that a micro-operation may occupy after the memory access result is returned, based on the data width, number of valid elements, target write-back register, write-back port width, and expected write-back cycle count. Through the above feature extraction process, each micro-operation can carry quantized or semi-quantized features that can be used for memory access issue scheduling, thereby supporting subsequent priority determination.

[0059] This allows for the identification of differences between micro-operations before they issue memory access requests, enabling memory access scheduling to no longer rely solely on a fixed order but to comprehensively consider address access patterns, effective data ratios, and write-back resource pressure, thereby improving the accuracy of memory access scheduling and resource utilization.

[0060] As an optional embodiment, in step 103, the memory access launch order of multiple micro-operations is scheduled according to the memory access characteristics of each micro-operation, including: determining the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information; selecting a target micro-operation from the micro-operations to be launched according to the scheduling priority; and initiating a memory access request corresponding to the target micro-operation when the target micro-operation satisfies the conditions of address readiness, memory access queue availability, and no address conflict.

[0061] The scheduling priority characterizes the degree to which a micro-operation to be launched is prioritized for launch within the current scheduling cycle or window. A higher scheduling priority makes the micro-operation more likely to be selected as a target micro-operation by the memory access launch scheduling module. A micro-operation to be launched refers to one that has been generated by the vector memory access splitting module and has entered the memory access launch scheduling module to await a memory access request. Address readiness means that the memory address corresponding to the micro-operation has been generated and is available for a memory access request; memory access queue availability means that the queue, buffer, or launch port used to store memory access requests has available resources; and no address conflict means that there is no conflict between the memory address of the micro-operation and other incomplete memory access requests that require blocking or waiting.

[0062] Specifically, the memory access issue scheduling module can first traverse or read multiple micro-operations in the launch queue and calculate or determine the scheduling priority based on the memory access characteristics of each micro-operation. Then, the module can sort the micro-operations according to their scheduling priorities, or select a higher-priority micro-operation as the target micro-operation using a priority selector or arbitrator. After selecting the target micro-operation, the module can further check whether it meets the launch conditions such as address readiness, memory access queue availability, and absence of address conflicts. If these conditions are met, a memory access request corresponding to the target micro-operation is sent to the memory access module. If the conditions are not met, the target micro-operation can be postponed, and a new target micro-operation can be selected from other micro-operations that meet the conditions.

[0063] By using the above method, the execution of the entire vector memory access instruction can be blocked due to a micro-operation address not being ready or an address conflict, allowing other micro-operations that have the conditions to be issued and have higher memory access benefits to be issued first, thereby reducing invalid waiting and improving memory access parallelism and memory access bandwidth utilization.

[0064] Further optionally, in the above embodiments, the scheduling priority of each micro-operation is determined based on the step size range, address continuity, mask effective density, and write-back resource occupancy information, including: A continuity priority component is determined based on the address continuity, wherein the higher the address continuity, the larger the continuity priority component; an effective density priority component is determined based on the mask effective density, wherein the higher the mask effective density, the larger the effective density priority component; a write-back pressure penalty component is determined based on the write-back resource occupancy information, wherein the higher the write-back resource occupancy represented by the write-back resource occupancy information, the larger the write-back pressure penalty component; and the scheduling priority of each micro-operation is determined based on the continuity priority component, the effective density priority component, and the write-back pressure penalty component, wherein the scheduling priority is positively correlated with the continuity priority component and the effective density priority component, and negatively correlated with the write-back pressure penalty component.

[0065] In this embodiment, the continuity priority component can be used to characterize the positive contribution of address continuity to scheduling priority. When the memory access addresses corresponding to a micro-operation are more continuous, the micro-operation is more likely to have a higher cache hit rate, lower access overhead, or better memory merging effect, and therefore can be assigned a larger continuity priority component. The effective density priority component can be used to characterize the positive contribution of mask effective density to scheduling priority. When the proportion of effective elements in a micro-operation is high, the effective data processing benefit generated by the micro-operation using the same amount of hardware resources is higher, and therefore can be assigned a larger effective density priority component.

[0066] The write-back pressure penalty component can be used to characterize the negative impact of micro-operations on write-back resources. When the micro-operation corresponds to a large data width, a large number of valid elements, a long write-back port occupancy period, or a high write-back buffer occupancy, the micro-operation may cause significant pressure on the write-back side after the memory access result is returned. Therefore, a larger write-back pressure penalty component can be assigned to it, and its probability of being prioritized can be reduced when determining scheduling priority. This can prevent a large number of micro-operations with high write-back loads from returning in a short period of time and occupying the write-back path.

[0067] In one example, scheduling priority can be determined by weighting a continuity priority component, an effective density priority component, and a write-back pressure penalty component. For example, the continuity priority component and the effective density priority component are used as positive factors, while the write-back pressure penalty component is used as a negative factor. It should be noted that the embodiments of this application do not limit the specific calculation formula, nor do they limit the specific weight of each component. In actual implementation, it can be configured according to the processor architecture, memory access queue capacity, number of write-back ports, or application scenario.

[0068] By incorporating factors affecting memory access efficiency and factors affecting write-back congestion into the scheduling priority, memory access efficiency can be improved while suppressing write-back pressure, resulting in a more balanced memory access and launch scheduling.

[0069] Further optionally, in the above embodiments, determining the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information further includes: Based on the step size range, address continuity, and effective mask density, the memory access benefit information of the micro-operation is determined; based on the write-back resource occupancy information and the write-back load information fed back from the write-back side, the write-back pressure information of the micro-operation is determined; based on the memory access benefit information and the write-back pressure information, joint scheduling parameters are determined, wherein the joint scheduling parameters are positively correlated with the memory access benefit information and negatively correlated with the write-back pressure information; multiple micro-operations are sorted according to the joint scheduling parameters, and the scheduling priority of each micro-operation is determined based on the sorting result.

[0070] The memory access benefit information can be used to characterize the potential improvement in memory access efficiency after a micro-operation is prioritized for issuance. In other words, the memory access benefit information can characterize the expected degree of improvement in memory access efficiency after a micro-operation is prioritized for issuance. The memory access benefit information can be related to the step size range, address continuity, and effective mask density. Further, based on the step size range, address continuity, and effective mask density corresponding to the micro-operation, step size benefit components, continuity benefit components, and effective density benefit components can be determined, and the memory access benefit information of the micro-operation can be determined based on these components. Specifically, the smaller the step size range or the more stable the access pattern, the larger the step size benefit component; the higher the address continuity, the larger the continuity benefit component; and the higher the effective mask density, the larger the effective density benefit component. It is understood that micro-operations with smaller step size ranges or stronger access patterns, higher address continuity, and higher effective mask density have higher memory access benefit information.

[0071] For example, the calculation process for determining the memory access benefit information of micro-operations based on step size range, address continuity, and effective mask density can be expressed as the following formula: .

[0072] in, Indicates micro-operations The overall retention rate score. Indicates micro-operations Step size gain component. It is usually positively correlated with the inverse of the step size range or regularity. For example, if the step size is 1 (continuous) or 2, 4, 8 (regular step). Take the higher value. If the step size is a random large number, Take the lower value. If a step size is detected. It is a constant and satisfies ( If the number of elements corresponds to the width of the cache line (e.g., 16), it is determined to be a rule-based access and assigned a high score. If the step size is 0 (broadcast) or If the number is a large prime number (which may cause cache conflicts), then assign a low score. In quantization calculations, it can be set that... This reflects the principle that the smaller the step size and the stronger the regularity, the higher the return.

[0073] Indicates micro-operations The continuity component measures the degree of address contiguousness within a micro-operation or between adjacent micro-operations. If a complete cache line can be filled... Take the maximum value. Calculate the micro-operations. The alignment of the memory access address range [Addrstart, Addrend] with the cache line boundary. If Addrstart is aligned with the beginning address of the cache line and the access length covers the complete N cache lines, then... =1. If the access span is too large or misaligned, resulting in additional cache line splitting, then It decreases proportionally. Specifically, It can be expressed as the ratio of the effective cache line bandwidth to the theoretical maximum bandwidth.

[0074] Indicates micro-operations The effective density gain component is equal to the effective mask density. The number of valid elements. This is the width of the vector register or the maximum number of elements in the micro-operation. When When the return exceeds a preset threshold (e.g., 50%), it is considered a high-yield micro-operation.

[0075] Indicates micro-operations The write-back pressure penalty (corresponding to the write-back resource usage information mentioned earlier) can be the expected write-back bandwidth or buffer size. This is based on the data width and number of valid elements in the micro-operation. The estimated number of entries and cycles in the reorder buffer / writeback queue used by the returned data is calculated. This can be quantified as the expected proportion of write-back port bandwidth used.

[0076] , , , These are preset weighting coefficients, satisfying... , , , The sum is 1. These coefficients can be configured according to the specific processor microarchitecture (such as cache size and write-back queue depth).

[0077] Write-back pressure information can be used to characterize the load pressure that a micro-operation may cause on the write-back side after the memory access result is returned. Write-back pressure information can be related to write-back resource usage information and write-back load information fed back by the write-back side. For example, when the micro-operation itself is expected to have high write-back resource usage, and the current write-back queue occupancy rate or write-back buffer occupancy rate is high, the corresponding write-back pressure information for that micro-operation can be large.

[0078] Joint scheduling parameters can be used to comprehensively characterize whether a micro-operation is suitable for priority issuance under the current scheduling state. These parameters reflect both the memory access benefit and the potential write-back pressure of the micro-operation. A positive correlation exists between the joint scheduling parameters and memory access benefit information, indicating that micro-operations with higher memory access benefits are more likely to be scheduled first. A negative correlation exists between the joint scheduling parameters and write-back pressure information, indicating that micro-operations with higher write-back pressure are more likely to be scheduled later. Through these joint scheduling parameters, coordinated control between the memory access side and the write-back side can be achieved.

[0079] In one possible implementation, the memory access launch scheduling module can periodically or upon event triggering update the joint scheduling parameters of each micro-operation. These events may include a new micro-operation entering the launch queue, a change in write-back side load, memory access queue release, address conflict resolution, or memory access request completion. The memory access launch scheduling module can sort the micro-operations to be launched according to the updated joint scheduling parameters and prioritize the micro-operation with higher joint scheduling parameters as the target micro-operation. If multiple micro-operations have the same or similar joint scheduling parameters, secondary arbitration can be performed based on element number order, enqueue time order, address order, or target write-back identifier.

[0080] Therefore, by unifying memory access benefits and write-back pressure into a single scheduling decision process through joint scheduling parameters, the problem of memory access issue scheduling focusing only on memory access parallelism while ignoring write-back capacity can be avoided. When the write-back load is high, the scheduling module can reduce the issuance priority of micro-operations with high write-back pressure. When the write-back load is low, more micro-operations with higher memory access benefits can be issued first. This improves memory access bandwidth utilization while alleviating write-back congestion, thereby improving the overall processor execution efficiency.

[0081] Step 104: Obtain the write-back load information fed back from the write-back side, and adjust the memory access and / or issue sequence and / or issue rate of subsequent micro-operations based on the write-back load information.

[0082] In this embodiment, the write-back side can refer to the hardware resources in the processor used to receive memory access return results and write them to a target register, write-back buffer, or other target memory structure. For example, the write-back side includes, but is not limited to, write-back queues, write-back buffers, write-back ports, write-back arbitration logic, and data write-back paths. Write-back load information can be used to characterize the current or predicted resource occupancy status of the write-back side, such as whether the write-back queue is nearing full load, whether the write-back port is continuously busy, and whether there are too many micro-operations waiting for write-back.

[0083] In this embodiment, the memory access launch scheduling module does not determine the launch order of micro-operations solely based on the memory access side status. Instead, it further obtains write-back load information fed back from the write-back side and uses this write-back load information to adjust the memory access launch order and / or launch rate of subsequent micro-operations. Therefore, the pressure on the write-back side after the memory access result is returned can be considered in advance before the memory access request is initiated, avoiding excessive pursuit of parallelism by the memory access side that could lead to write-back path congestion.

[0084] As an optional embodiment, it is assumed that the write-back load information fed back by the write-back side includes at least one of the following: write-back queue occupancy rate, write-back buffer occupancy rate, write-back port busy / idle status, number of micro-operations waiting to be written back, write-back bandwidth occupancy information, and write-back blocking status.

[0085] The write-back queue occupancy rate can be used to characterize the ratio between the number of occupied entries in the write-back queue and the total number of entries in the write-back queue. A higher write-back queue occupancy rate indicates that there are already a lot of memory access results or data waiting to be written back. If a large number of micro-operations that will generate write-back data continue to be issued, it may further cause the write-back queue to overflow or backpressure.

[0086] Write-back buffer occupancy rate can be used to characterize the ratio of occupied storage space in the write-back buffer to the total storage space. The write-back buffer is used to temporarily store memory access return data, write-back data, or result data to be committed. A high write-back buffer occupancy rate indicates that the space available on the write-back side to receive subsequent memory access return results is reduced. In this case, it is necessary to appropriately reduce the transmit priority or transmit rate of subsequent high write-back load micro-operations.

[0087] The write-back port's busy / idle status indicates whether the write-back port is currently available for write-back operations, or how busy the write-back port is over multiple consecutive cycles. The write-back port is the hardware pathway for writing data to the target register, vector register file, or other target memory structures. If the write-back port remains busy, it indicates that the write-back capability has approached or reached its bottleneck.

[0088] The number of micro-operations awaiting write-back can be used to characterize the number of micro-operations that have completed memory access or have received memory access data but have not yet completed write-back. The larger this number, the more severe the backlog on the write-back side, and subsequent memory access launches should be more cautious to avoid further increasing the write-back pressure.

[0089] Write-back bandwidth occupancy information can be used to characterize the write-back bandwidth used or remaining in a unit of time. For example, if the write-back path has been heavily occupied in the current or recent scheduling cycles, the memory access launch scheduling module can reduce the launch of micro-operations that are expected to generate a large amount of write-back data.

[0090] Write-back blocking status can be used to characterize whether the write-back side is blocked due to reasons such as a full write-back queue, a full write-back buffer, a write-back port conflict, an unwritable destination register, or unavailability of subsequent pipeline resources. If the write-back side is in a blocked state, the memory access issue side can reduce the issue intensity of related micro-operations to prevent the blockage from spreading further to the memory access queue and the front-end pipeline.

[0091] By feeding back the write-back load information to the memory access launch scheduling module, the memory access scheduler can be made aware of the resource status on the write-back side, thereby forming a coordinated control between memory access launch and result write-back.

[0092] Based on this, in step 104, adjusting the memory access launch order and / or launch rate of subsequent micro-operations based on the write-back load information includes: if the write-back load information meets the congestion condition, reducing the launch priority of micro-operations that are expected to increase write-back pressure, and / or reducing the number of micro-operations allowed to be launched per unit scheduling cycle; if the write-back load information does not meet the congestion condition, increasing the launch priority of micro-operations with higher memory access benefits, and / or increasing the number of micro-operations allowed to be launched per unit scheduling cycle.

[0093] Among these, congestion conditions can be used to determine whether the write-back side is under high load, near saturation, or experiencing blockage. Micro-operations expected to increase write-back pressure can refer to those that will consume significant write-back resources after the memory access result is returned, such as those involving large write-back data volumes, long target write-back port occupancy periods, a large number of valid elements requiring write-back, contention in the target write-back register, or micro-operations expected to consume a large write-back buffer. The transmit rate can be used to characterize the number of micro-operations allowed to initiate memory access requests per scheduling cycle, and can also be used to characterize the transmit rhythm or transmit intensity of the memory access transmit module across multiple scheduling cycles.

[0094] If the write-back load information meets the congestion conditions, it indicates that the current capacity of the write-back side is limited. In this case, if the memory access side continues to issue a large number of micro-operations expected to generate a significant amount of write-back data, it may lead to the inability to write back the memory access results in a timely manner, resulting in write-back queue backlog, write-back buffer fullness, and back pressure on the processor pipeline. Therefore, the memory access issue scheduling module can reduce the issuance priority of high write-back pressure micro-operations, temporarily suspending their issuance. Simultaneously, it can reduce the number of micro-operations allowed to be issued per scheduling cycle, thereby reducing the overall impact of memory access return data on the write-back side. For example, for micro-operations with a large expected write-back data volume or a long expected write-back port occupancy period, its write-back pressure penalty component can be increased, or its joint scheduling parameters can be reduced; for micro-operations with low write-back pressure and ready addresses, they can be prioritized as target micro-operations. Furthermore, the memory access issue scheduling module can reduce the number of micro-operations allowed to be issued in the current scheduling cycle, or reduce the memory access issue rate over several cycles.

[0095] If the write-back load information does not meet the congestion conditions, it indicates that the write-back side still has sufficient write-back capacity. In this case, the memory access issue scheduling module can focus more on memory access benefits, such as prioritizing the issuance of micro-operations with higher address contiguity, higher mask effective density, smaller step size, or higher memory access merging benefits. Simultaneously, the number of micro-operations allowed to be issued per scheduling cycle can be increased to improve memory access bandwidth utilization and overall execution efficiency. For example, micro-operations with higher address contiguity, higher mask effective density, or smaller step size can be prioritized for issuance, and the issuance rate can be increased when memory access queues and memory access resources are available.

[0096] Therefore, the embodiments of this application can dynamically adjust the memory access and issuance strategy according to the real-time or near-real-time load state of the write-back side, so as to form a backpressure control relationship between the memory access side and the write-back side and avoid the write-back side becoming a performance bottleneck.

[0097] Further optionally, the congestion condition includes at least one of the following: the write-back queue occupancy rate is greater than a first threshold; the write-back buffer occupancy rate is greater than a second threshold; the number of consecutive cycles in which the write-back port is busy is greater than a third threshold; and the number of micro-operations waiting to write back is greater than a fourth threshold.

[0098] The first threshold can be used to determine if the write-back queue is close to full load; the second threshold can be used to determine if the write-back buffer is close to saturation; the third threshold can be used to determine if the write-back port is continuously busy; and the fourth threshold can be used to determine if there is a backlog of micro-operations to be written back. These thresholds can be fixed or dynamically configured based on the processor's operating mode, current vector length, number of write-back ports, write-back queue depth, power consumption strategy, or runtime load.

[0099] For example, when the write-back queue occupancy rate exceeds the first threshold, it can be assumed that there are already many entries waiting to be written back in the queue, and continuing to issue high-pressure micro-operations for write-back may further congest the queue. When the write-back buffer occupancy rate exceeds the second threshold, it can be assumed that the remaining space in the write-back buffer is insufficient, and the memory access results may not be cached in a timely manner. When the number of consecutive cycles in which the write-back port is busy exceeds the third threshold, it can be assumed that the write-back port has become the current processing bottleneck. When the number of micro-operations waiting for write-back exceeds the fourth threshold, it can be assumed that there is a significant backlog on the write-back side.

[0100] In one possible implementation, the write-back load information is deemed to meet the congestion condition as long as any one of the above conditions is satisfied. In another possible implementation, the write-back load information is deemed to meet the congestion condition when multiple conditions are met simultaneously, or when the weighted result of multiple conditions exceeds a preset congestion threshold. This application does not limit this approach.

[0101] By setting the above congestion conditions, the memory access and launch scheduling module can identify the congestion status on the write-back side with low complexity and adjust the launch sequence and / or launch rate of subsequent micro-operations in a timely manner.

[0102] In this way, the load status on the write-back side can be fed back to the memory access issue scheduling module in a timely manner. This allows the memory access issue scheduling module to reduce the issue priority or issue rate of high write-back pressure micro-operations when the write-back side load is high, and to increase the issue priority or issue rate of high memory access benefit micro-operations when the write-back side load is low. Therefore, while improving memory access bandwidth utilization, it can alleviate write-back path congestion, reduce write-back queue and write-back buffer backlog, and improve the overall processor execution efficiency.

[0103] Further optionally, after a micro-operation enters the memory access launch schedule, the memory access characteristics of the micro-operation are updated according to the write-back load information fed back from the write-back side to obtain the updated memory access characteristics; and the scheduling priority of the micro-operation is re-determined according to the updated memory access characteristics.

[0104] Specifically, when a micro-operation enters the memory access issue scheduling module, it can carry initial memory access characteristics such as step size range, address continuity, effective mask density, and write-back resource occupancy information. Since the write-back queue occupancy rate, write-back buffer occupancy rate, and write-back port busy / idle status on the write-back side change dynamically with the processor's operating state, the memory access issue scheduling module can update the micro-operation's write-back resource occupancy information, write-back pressure information, or joint scheduling parameters based on the write-back load information fed back from the write-back side, and re-determine the micro-operation's scheduling priority based on the updated memory access characteristics. When the write-back side load is high, the scheduling priority of micro-operations expected to increase write-back pressure can be reduced. When the write-back side load is low, the scheduling priority of micro-operations with higher memory access benefits can be increased. Thus, micro-operations already in the scheduling queue can be dynamically reordered according to the write-back side resource status, avoiding a mismatch between the memory access side issue decision and the write-back side resource status, thereby alleviating write-back congestion and improving overall memory access scheduling efficiency. In addition, it can avoid the problem that fixed priority or one-time priority calculation cannot adapt to changes in write-back load, thereby alleviating write-back congestion, reducing invalid waits, and improving the overall execution efficiency in vector memory access scenarios.

[0105] Alternatively, during memory access launch scheduling, micro-operations whose addresses are not ready, have address conflicts, or whose memory access queues are unavailable are temporarily deferred. Once the address is ready, the address conflict is resolved, or the memory access queue becomes available, the micro-operation is re-enlisted in memory access launch scheduling. This approach avoids blocking other executable micro-operations due to address generation, address conflicts, or memory access queue resource limitations imposed by a single micro-operation, allowing qualified and higher-priority micro-operations to be launched first, thereby reducing unnecessary waiting and improving memory access scheduling efficiency.

[0106] Further, optionally, when multiple micro-operations have the same scheduling priority, the launch order among the multiple micro-operations is determined based on at least one of the following: the element number order corresponding to the micro-operation, the time order of entry into the scheduling queue, the address order, or the target write-back identifier. This method provides a deterministic secondary arbitration rule when multiple micro-operations have the same or similar priorities, avoiding scheduling jitter caused by uncertain launch order, and taking into account factors such as element order, queuing fairness, address access continuity, and write-back target conflicts.

[0107] Step 105: After the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

[0108] In this embodiment, the memory access result can refer to the data or execution result returned after the memory access module processes the memory access request corresponding to the micro-operation. For vector loading micro-operations, the memory access result can include data read from the cache, on-chip memory, or external memory. For vector storage micro-operations, the memory access result can include storage completion status, exception status, or execution confirmation information. The write-back order can refer to the order in which multiple memory access results are written to the target vector register, target register segment, write-back buffer, or other target memory structure.

[0109] In this embodiment of the application, after the memory access result is returned, the data write-back scheduling module can determine the write-back order by combining the data characteristics and / or dependencies corresponding to multiple micro-operations, rather than writing back in the order of micro-operation issuance, return, or fixed order.

[0110] As an optional embodiment, in step 105, after the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations, including: determining the write-back priority corresponding to each micro-operation based on the buffer resource occupancy, write-back data volume and subsequent instruction dependencies corresponding to each micro-operation; and writing back the memory access result according to the write-back priority.

[0111] The write-back priority characterizes the degree to which memory access results are prioritized during the write-back phase. A higher write-back priority means the memory access result corresponding to that micro-operation is written to the target register or target memory structure more preferentially through the write-back port. In one possible implementation, the data write-back scheduling module can write the returned result to a write-back queue or write-back buffer after the memory access result is returned, and maintain a write-back priority field for each micro-operation to be written back. This write-back priority field can be determined based on buffer resource usage, the amount of data to be written back, and subsequent instruction dependencies.

[0112] For example, when the memory access result of a micro-operation occupies a large amount of write-back buffer space, and the write-back will release a significant amount of buffer resources, the write-back priority of that micro-operation can be increased. When the memory access result of a micro-operation is directly dependent on by subsequent instructions, the write-back priority of that micro-operation can be increased so that subsequent instructions can obtain the required data as quickly as possible. When a micro-operation writes back a large amount of data, but there are no urgent subsequent instructions that depend on it, and write-back resources are relatively scarce, the write-back priority of that micro-operation can be appropriately reduced to prevent it from occupying the write-back port for an extended period and affecting the write-back of other more urgent memory access results.

[0113] In one specific implementation, the data write-back scheduling module can receive memory access results from multiple micro-operations and determine the corresponding write-back priority based on the target write-back identifier, write-back data volume, buffer resource usage, and dependency identifier for each micro-operation. Subsequently, the data write-back scheduling module can select the target write-back micro-operation from the pending write-back micro-operations according to the write-back priority, and write the memory access result corresponding to the target write-back micro-operation to the target vector register or other target storage structure through the write-back port. If multiple micro-operations have the same or similar write-back priorities, secondary arbitration can be performed based on return time, element number order, target write-back identifier, or enqueue time order.

[0114] Optionally, the write-back priority for each micro-operation can be determined, including: increasing the write-back priority of memory access results corresponding to micro-operations that can release buffer resources; increasing the write-back priority of memory access results corresponding to micro-operations that have data dependencies on subsequent instructions; and decreasing the write-back priority of memory access results corresponding to micro-operations whose write-back resource occupancy exceeds the occupancy condition and has no urgent dependency. Thus, a micro-operation that can release buffer resources can refer to a micro-operation whose memory access result, after being written back, can release the write-back queue entry, the return data buffer, the memory access result buffer, or other temporary storage resources. Prioritizing the write-back of this type of micro-operation helps reduce buffer resource accumulation and provides space for subsequent memory access result returns.

[0115] Micro-operations that have data dependencies on subsequent instructions can be those whose memory access results are data required for the execution of subsequent instructions. For example, if a subsequent vector calculation instruction needs to read the target vector register segment written back by this micro-operation, then this micro-operation has a data dependency on the subsequent instruction. Increasing the write-back priority of such micro-operations can satisfy the data read requirements of subsequent instructions in advance, reducing the blocking of subsequent instructions.

[0116] Micro-operations that exceed the write-back resource usage threshold and have no urgent dependencies can refer to those with large write-back data volumes, long write-back port usage periods, strong contention for target write-back resources, or significant write-back bandwidth requirements, but whose memory access results are not yet urgently needed by subsequent instructions. For such micro-operations, if current write-back resources are scarce, their write-back priority can be lowered, allowing limited write-back resources to prioritize micro-operations that can release buffer resources or eliminate dependencies on subsequent instructions.

[0117] The occupancy conditions can be determined based on thresholds such as write-back data volume, write-back port occupancy period, write-back buffer occupancy, or write-back bandwidth occupancy. Urgent dependencies can be determined based on information such as whether subsequent instructions have entered a waiting state, the distance of dependent instructions from the current execution position, and whether the target register has been read by an upcoming instruction. This application does not limit the specific methods for determining occupancy conditions and urgent dependencies.

[0118] Through the above methods, the embodiments of this application can continue to perform differentiated scheduling based on micro-operation granularity during the write-back phase, so that write-back resources are given priority to memory access results that can release buffer resources or eliminate the dependence of subsequent instructions, avoiding write-back buffer accumulation, inefficient occupation of write-back ports and waiting for subsequent instructions caused by fixed-order write-back, thereby improving the utilization rate of write-back resources and the overall execution efficiency of the processor.

[0119] In this embodiment, by dividing the acquired vector memory access instructions into multiple independently executable micro-operations at a granularity, and scheduling the memory access issuance order of these micro-operations based on their memory access characteristics, micro-operations with higher address continuity, higher mask effective density, or higher memory access benefits can be prioritized for memory access requests. This reduces invalid waiting caused by fixed-order issuance and improves memory resource utilization. Furthermore, by acquiring write-back load information from the write-back side and adjusting the memory access issuance order and / or issuance rate of subsequent micro-operations based on this information, the memory access issuance scheduling process can be aware of the resource occupancy status on the write-back side, preventing excessive issuance on the write-back side from causing congestion in the write-back queue, write-back buffer, or write-back port. After the memory access result is returned, scheduling the write-back order of the memory access result based on the data characteristics and / or dependencies corresponding to the multiple micro-operations can prioritize writing back memory access results that can release buffer resources or satisfy the dependencies of subsequent instructions, thereby alleviating write-back congestion, reducing subsequent instruction waiting, and improving the overall execution efficiency of the processor in vector memory access scenarios.

[0120] The above describes a memory access scheduling method for vector processing in the embodiments of this application. The memory access scheduling device for vector processing that executes the above method will be described below.

[0121] See Figure 2 ,like Figure 2 The diagram shows a structural schematic of a memory access scheduling device for vector processing. The memory access scheduling device for vector processing in this embodiment can achieve the above-described... Figure 1 The steps of the vector-oriented memory access scheduling method executed in the corresponding embodiments are described above. The functionality of the vector-oriented memory access scheduling device can be implemented in hardware or by executing corresponding software within hardware. The hardware or software includes one or more modules corresponding to the above functions, and these modules can be software and / or hardware. The vector-oriented memory access scheduling device may include multiple units, the functional implementation of which can be referred to... Figure 1 The operations performed in the corresponding embodiments are not described in detail here. In one embodiment, the memory access scheduling device for vector processing includes the following units: The processor core unit is configured to fetch vector memory access instructions; The vector execution unit is configured to break down the vector memory access instruction into multiple independently executable micro-operations according to the granularity of the vector memory access instruction. The memory access unit is configured to schedule the memory access issuance order of multiple micro-operations according to the memory access characteristics of each micro-operation, so as to determine the target micro-operation and initiate a memory access request. The write-back unit is configured to acquire write-back load information fed back from the write-back side, and adjust the memory access launch order and / or launch rate of subsequent micro-operations based on the write-back load information; after the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

[0122] In some implementations, the vector execution unit is specifically configured to: determine the element set corresponding to each micro-operation based on the element width, element number, mask information, and step size information corresponding to the vector memory access instruction; and generate multiple micro-operations based on the element set, wherein each micro-operation includes at least one of element number, element size, starting address, address span, mask valid bits, and target write-back identifier.

[0123] In some implementations, when the vector execution unit generates multiple micro-operations based on the element set, it is specifically configured to: determine the starting address and address span corresponding to the element set according to the element number, element size, mask valid bits, and step size information of each element in the element set; determine the number of valid elements corresponding to the element set according to the mask valid bits, and determine the mask valid density corresponding to the element set based on the number of valid elements; determine the target write-back identifier and expected write-back resource usage information corresponding to the element set according to the write-back target register and write-back data volume corresponding to the element set; and generate the micro-operations corresponding to the element set based on the starting address, address span, mask valid density, target write-back identifier, and expected write-back resource usage information.

[0124] In some implementations, when the memory access unit schedules the memory access issuance order of multiple micro-operations based on the memory access characteristics of each micro-operation, it is specifically configured to: determine the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information; select a target micro-operation from the micro-operations to be issued based on the scheduling priority; and, if the target micro-operation satisfies the conditions of address readiness, memory access queue availability, and no address conflict, initiate a memory access request corresponding to the target micro-operation.

[0125] In some implementations, when the memory access unit determines the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information, it is specifically configured to: determine a continuity priority component based on the address continuity, wherein the higher the address continuity, the larger the continuity priority component; determine an effective density priority component based on the mask effective density, wherein the higher the mask effective density, the larger the effective density priority component; determine a write-back pressure penalty component based on the write-back resource occupancy information, wherein the higher the write-back resource occupancy represented by the write-back resource occupancy information, the larger the write-back pressure penalty component; and determine the scheduling priority of each micro-operation based on the continuity priority component, the effective density priority component, and the write-back pressure penalty component, wherein the scheduling priority is positively correlated with the continuity priority component and the effective density priority component, and negatively correlated with the write-back pressure penalty component.

[0126] In some implementations, when the memory access unit determines the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information, it is further configured to: determine the memory access benefit information of the micro-operation based on the step size range, address continuity, and mask effective density; determine the write-back pressure information of the micro-operation based on the write-back resource occupancy information and the write-back load information fed back from the write-back side; determine joint scheduling parameters based on the memory access benefit information and the write-back pressure information, wherein the joint scheduling parameters are positively correlated with the memory access benefit information and negatively correlated with the write-back pressure information; sort multiple micro-operations based on the joint scheduling parameters, and determine the scheduling priority of each micro-operation based on the sorting result.

[0127] In some implementations, the write-back load information fed back by the write-back side includes at least one of the following: write-back queue occupancy rate, write-back buffer occupancy rate, write-back port busy / idle status, number of micro-operations waiting to be written back, write-back bandwidth occupancy information, and write-back blocking status.

[0128] When the write-back unit adjusts the memory access launch order and / or launch rate of subsequent micro-operations based on the write-back load information, it is specifically configured to: reduce the launch priority of micro-operations that are expected to increase write-back pressure and / or reduce the number of micro-operations allowed to be launched per unit scheduling cycle if the write-back load information meets the congestion conditions; and increase the launch priority of micro-operations with higher memory access benefits and / or increase the number of micro-operations allowed to be launched per unit scheduling cycle if the write-back load information does not meet the congestion conditions.

[0129] In some implementations, the memory access unit is further configured to: after a micro-operation enters the memory access issue schedule, update the memory access characteristics of the micro-operation based on the write-back load information fed back from the write-back side to obtain updated memory access characteristics; and redetermine the scheduling priority of the micro-operation based on the updated memory access characteristics.

[0130] The memory access scheduling device for vector processing provided in this application embodiment obtains vector memory access instructions through the processor core unit, decomposes the vector memory access instructions into multiple independently executable micro-operations using the vector execution unit, and schedules the memory access issuance order of the multiple micro-operations according to the memory access characteristics of each micro-operation to determine the target micro-operation and initiate a memory access request. Simultaneously, the write-back unit obtains write-back load information fed back from the write-back side and adjusts the memory access issuance order and / or issuance rate of subsequent micro-operations based on the write-back load information. After the memory access result is returned, the write-back order of the memory access result is scheduled again according to the data characteristics and / or dependencies corresponding to the multiple micro-operations. Therefore, this application embodiment can achieve coordinated control between memory access issuance and result write-back, reduce invalid waiting caused by fixed-order issuance and fixed-order write-back, alleviate write-back side congestion, improve resource utilization, and thus improve the overall execution efficiency of the processor in vector memory access scenarios.

[0131] The memory access scheduling device for vector processing in this application embodiment has been described above from the perspective of modular functional entities. The memory access scheduling device for vector processing in this application embodiment will be described below from the perspective of hardware processing.

[0132] This application also relates to a chip system including at least one processor and an interface circuit. The processor includes a plurality of vector storage units. The processor is used to perform instruction and / or data interaction through the interface circuit, causing the chip system to perform the methods of any of the above embodiments.

[0133] In one possible implementation, the chip system may also directly include memory storing computer programs or computer instructions. For example, the memory may be volatile or non-volatile, or may include both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM).

[0134] This application also relates to a processor, which includes a plurality of storage units for calling computer programs or computer instructions stored in the memory to cause the processor to execute the methods described in any of the above embodiments.

[0135] For example, in the embodiments of this application, the processor is an integrated circuit chip with signal processing capabilities. For instance, the processor may be an FPGA, a general-purpose processor, a DSP, an ASIC, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, a SoC, a CPU, a network processor (NP), a microcontroller unit (MCU), a PLD, or other integrated chips, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. In one possible implementation, the embodiments of this application also provide a computer-readable storage medium storing program code, which, when executed on the computer, causes the computer to perform the above-described method embodiments.

[0136] It should be noted that, in addition to the processor, Figure 2 The physical device corresponding to the illustrated device may also include transceivers, radio frequency circuits, communication modules, and input / output (I / O) interfaces.

[0137] This application provides a computing device, such as a server. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of a computing device structure provided in an embodiment of this application. The computing device 1100 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1122 (e.g., one or more processors) and a memory 1132, and one or more storage media 1130 (e.g., one or more mass storage devices) for storing application programs 1142 or data 1144. The memory 1132 and storage media 1130 can be temporary or persistent storage. The program stored in the storage media 1130 may include one or more modules (not shown in the figure), each module including a series of instruction operations on a server. Furthermore, the CPU 1122 may be configured to communicate with the storage media 1130 and execute the series of instruction operations in the storage media 1130 on the server 1100. Server 1100 may also include one or more power supplies 1126, one or more wired or wireless network interfaces 1150, one or more input / output interfaces 1158, and / or one or more operating systems 1141, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. The steps performed by the server in the above embodiments can be based on this... Figure 3 The structure of server 1100 is shown. For example, in the above embodiment, it consists of... Figure 2 The steps performed by the memory access scheduling device for vector-oriented processing shown can be based on this Figure 3 The server structure is shown. For example, the central processing unit 1122 performs the following operations by calling instructions from memory 1132: Obtain vector memory access instructions through input / output interface 1158; The central processing unit 1122 further divides the vector memory access instruction into multiple independently executable micro-operations according to the granularity of the vector memory access instruction; schedules the memory access issuance order of multiple micro-operations according to the memory access characteristics of each micro-operation to determine the target micro-operation and initiate a memory access request; obtains the write-back load information fed back from the write-back side, and adjusts the memory access issuance order and / or issuance rate of subsequent micro-operations based on the write-back load information; The write-back order of the memory access results can also be scheduled after the memory access results are returned, based on the data characteristics and / or dependencies corresponding to multiple micro-operations, through the input / output interface 1158.

[0138] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0139] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0140] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0141] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0143] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, it generates, in whole or in part, the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0144] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A memory access scheduling method for vector processing, characterized in that, The method is applied to a processor that supports vector extension, and the method includes: Retrieve vector memory access instructions; Based on the granularity of the vector memory access instruction, the vector memory access instruction is broken down into multiple independently executable micro-operations; Based on the memory access characteristics of each micro-operation, the memory access issuance order of multiple micro-operations is scheduled to determine the target micro-operation and initiate a memory access request. Obtain write-back load information from the write-back side, and adjust the memory access and / or issue sequence and / or issue rate of subsequent micro-operations based on the write-back load information; After the memory access results are returned, the write-back order of the memory access results is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

2. The memory access scheduling method for vector processing according to claim 1, characterized in that, The step of breaking down the vector memory access instruction into multiple independently executable micro-operations based on the granularity of the vector memory access instruction includes: Based on the element width, element quantity, mask information, and step size information corresponding to the vector memory access instruction, determine the element set corresponding to each micro-operation; Multiple micro-operations are generated based on the set of elements, wherein each micro-operation includes at least one of element number, element size, starting address, address span, mask valid bits, and target write-back identifier.

3. The memory access scheduling method for vector processing according to claim 2, characterized in that, The generation of multiple micro-operations based on the set of elements includes: Based on the element number, element size, mask valid bits, and step size information of each element in the element set, determine the starting address and address span corresponding to the element set; The number of valid elements corresponding to the element set is determined based on the valid bits of the mask, and the effective density of the mask corresponding to the element set is determined based on the number of valid elements. Based on the write-back target register and write-back data volume corresponding to the element set, determine the target write-back identifier and expected write-back resource usage information corresponding to the element set; Based on the starting address, address span, effective mask density, target write-back identifier, and expected write-back resource usage information, generate the micro-operations corresponding to the element set.

4. The memory access scheduling method for vector processing according to claim 1, characterized in that, The step of scheduling the memory access sequence of multiple micro-operations based on their memory access characteristics includes: Based on the step size range, address continuity, effective mask density, and write-back resource occupancy information, the scheduling priority of each micro-operation is determined; Select the target micro-operation from the micro-operations to be launched according to the scheduling priority; If the target micro-operation satisfies the conditions that the address is ready, the memory access queue is available, and there is no address conflict, then the memory access request corresponding to the target micro-operation is initiated.

5. The memory access scheduling method for vector processing according to claim 4, characterized in that, The step of determining the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information includes: A continuity priority component is determined based on the address continuity, wherein the higher the address continuity, the larger the continuity priority component. The effective density priority component is determined based on the effective mask density, wherein the higher the effective mask density, the larger the effective density priority component. The write-back pressure penalty component is determined based on the write-back resource occupancy information, wherein the higher the write-back resource occupancy represented by the write-back resource occupancy information, the greater the write-back pressure penalty component. The scheduling priority of each micro-operation is determined based on the continuity priority component, the effective density priority component, and the write-back pressure penalty component, wherein the scheduling priority is positively correlated with the continuity priority component and the effective density priority component, and negatively correlated with the write-back pressure penalty component.

6. The memory access scheduling method for vector processing according to claim 4, characterized in that, The step of determining the scheduling priority of each micro-operation based on the step size range, address continuity, mask effective density, and write-back resource occupancy information also includes: Based on the step size range, address continuity, and effective mask density, the memory access benefit information of the micro-operation is determined; Based on the write-back resource usage information and the write-back load information fed back from the write-back side, the write-back pressure information of the micro-operation is determined; The joint scheduling parameters are determined based on the memory access benefit information and the write-back pressure information, wherein the joint scheduling parameters are positively correlated with the memory access benefit information and negatively correlated with the write-back pressure information. Multiple micro-operations are sorted according to the joint scheduling parameters, and the scheduling priority of each micro-operation is determined based on the sorting results.

7. The memory access scheduling method for vector processing according to claim 1, characterized in that, The write-back load information fed back by the write-back side includes at least one of the following: write-back queue occupancy rate, write-back buffer occupancy rate, write-back port busy / idle status, number of micro-operations waiting to be written back, write-back bandwidth occupancy information, and write-back blocking status; The adjustment of the memory access issue order and / or issue rate of subsequent micro-operations based on the write-back load information includes: If the write-back load information meets the congestion conditions, reduce the transmit priority of micro-operations that are expected to increase write-back pressure, and / or reduce the number of micro-operations allowed to be transmitted per unit scheduling cycle. If the write-back load information does not meet the congestion conditions, increase the launch priority of micro-operations with higher memory access benefits, and / or increase the number of micro-operations allowed to be launched per unit scheduling cycle.

8. The memory access scheduling method for vector processing according to claim 1, characterized in that, The method further includes: After a micro-operation enters the memory access launch schedule, the memory access characteristics of the micro-operation are updated based on the write-back load information fed back from the write-back side, resulting in the updated memory access characteristics. The scheduling priority of the micro-operation is re-determined based on the updated memory access characteristics.

9. A memory access scheduling device for vector processing, characterized in that, The apparatus is used in a processor that supports vector extension, and the apparatus includes: The processor core unit is configured to fetch vector memory access instructions; The vector execution unit is configured to break down the vector memory access instruction into multiple independently executable micro-operations according to the granularity of the vector memory access instruction. The memory access unit is configured to schedule the memory access issuance order of multiple micro-operations according to the memory access characteristics of each micro-operation, so as to determine the target micro-operation and initiate a memory access request. The write-back unit is configured to acquire write-back load information fed back from the write-back side, and adjust the memory access launch order and / or launch rate of subsequent micro-operations based on the write-back load information; after the memory access result is returned, the write-back order of the memory access result is scheduled according to the data characteristics and / or dependencies corresponding to multiple micro-operations.

10. A chip, characterized in that, The chip includes a processor coupled to a transceiver for executing the memory access scheduling method for vector-oriented processing as described in any one of claims 1-8.

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