Watchdog circuit for embedded systems and method of operation thereof

Abstract

This application relates to a watchdog circuit and its operating method for embedded systems, applicable to the field of embedded application technology. The circuit includes a general-purpose watchdog timer, a tri-state gate, a D flip-flop, and a CPU. The general-purpose watchdog timer is used for undervoltage monitoring and watchdog timeout reset monitoring. The tri-state gate is used for WDI state control and feed signal access control of the general-purpose watchdog timer. The D flip-flop is used for trigger control of the tri-state gate's enable signal pin OE. The CPU's feed pin IO is connected to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate. The CPU's reset pin nRST is connected to the output pin WDO of the general-purpose watchdog timer. This invention effectively solves the problem of excessively long microprocessor startup time causing watchdog timeout triggering reset, resulting in repeated system restarts and failure to complete startup normally.

Description

Technical Field

[0001] This invention belongs to the field of embedded application technology, specifically relating to a watchdog circuit suitable for embedded systems and its working method. Background Technology

[0002] Watchdog circuits and power monitoring and reset circuits are crucial components in embedded systems to ensure normal system operation. Insufficient CPU power supply, coupled with voltage fluctuations exceeding the CPU's operating range, can lead to serious system malfunctions. When the power supply falls below the limits set by the power monitoring and reset circuit, the monitoring circuit continuously outputs a reset signal to prevent the CPU from operating under low voltage until the power supply returns to normal. In the watchdog circuit, the timeout period is a core parameter. If the watchdog circuit fails to detect a valid feed signal within the timeout period, it outputs a reset signal, forcing the connected CPU and its system to restart. When system software vulnerabilities cause the CPU to enter abnormal states such as software crashes, interrupt freezes, or infinite loops, the CPU cannot feed the watchdog on time; in this case, the watchdog circuit will reset the CPU and restart the system. Typically, watchdog circuits and power monitoring and reset circuits are integrated within a single chip.

[0003] The timeout period for watchdog circuits is typically fixed at 1.6 seconds. Embedded operating systems like Linux are more complex, requiring several seconds to boot—far exceeding the watchdog timeout—and cannot output a feed signal during the boot phase. Therefore, systems running embedded Linux cannot implement watchdog and power monitoring / reset functions using conventional chip methods. The current solution is: (1) A programmable monitoring chip is used. After the system starts, the CPU communicates to configure the watchdog timeout and enables the watchdog function. Such chips are expensive, complex to operate, and consume a lot of resources. (2) A switching circuit can be added to the conventional watchdog chip. The input of the switching circuit is connected to the WDO signal output by the watchdog, the output of the switching circuit is connected to the CPU's reset signal, and the enable signal of the switching circuit is connected to the CPU's IO. For example, the method mentioned in patents CN201310078877.8 and CN201810106714.9. When the CPU is powered on, the control switching circuit is turned off by default, blocking the reset signal between the CPU and the watchdog. After the CPU starts up, the control switch is turned on, enabling the reset signal between the CPU and the watchdog. In this way, in addition to configuring an IO output to feed the watchdog signal, the CPU also needs to configure other IO resources. (3) Alternatively, a switching circuit can be added by taking advantage of the characteristics of some watchdog chips (i.e., when the watchdog's WDI feed pin is in a high-impedance state, the watchdog reset function does not run). The output of the switching circuit is connected to the watchdog's WDI, the input of the switching circuit is connected to the CPU's IO1 for feeding the watchdog, and the enable signal of the switching circuit is connected to the CPU's IO2. When the CPU is powered on, the IO defaults to controlling the switching circuit to be open, so that the watchdog chip's WDI is in a high-impedance state. After the CPU starts up, it controls the switch to be turned on, connecting the WDI signal between the CPU's IO1 and the watchdog, enabling the watchdog function and feeding the watchdog. This method also requires additional IO resources of the CPU and requires the watchdog chip to have the above characteristics. Summary of the Invention

[0004] The technical problem this invention aims to solve is that embedded systems require a watchdog circuit to ensure normal system operation, but conventional watchdog circuits cannot be adapted to embedded systems with long startup times. Current solutions are costly, complex to operate, and consume a lot of resources. Therefore, a low-cost, simple-to-operate, and resource-efficient watchdog circuit is needed to match the embedded system.

[0005] The present invention proposes a watchdog circuit and its working method suitable for embedded systems, which can effectively solve the problem that the watchdog timer timeout triggers a reset due to the excessively long microprocessor startup time, resulting in repeated system restarts and failure to complete the startup normally.

[0006] To address the above problems, this invention provides a watchdog circuit suitable for embedded systems, comprising a general-purpose watchdog, a tri-state gate, a D flip-flop, and a CPU. The general-purpose watchdog is used for power undervoltage monitoring and watchdog timeout reset monitoring. Its feed pin WDI is connected to the output pin Y of the tri-state gate, and its output pin WDO is connected to the CPU's reset pin nRST and the asynchronous clear pin CLR of the D flip-flop. The tri-state gate is a high-level enabled tri-state buffer used for the WDI state control and watchdog signal access control of the general watchdog. The input signal pin A is connected to the CPU's watchdog pin IO and the clock pin CLK of the D flip-flop. The enable signal pin OE of the tri-state gate is connected to the output signal pin Q of the D flip-flop. When the enable signal pin OE is high, it can connect the CPU's watchdog pin IO and the general watchdog's watchdog pin WDI. The D flip-flop is used for triggering control of the tri-state gate enable signal pin OE, and its input signal pin D is fixed at a high level; The CPU's watchdog pin IO is connected to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate, and the CPU's reset pin nRST is connected to the output pin WDO of the general-purpose watchdog.

[0007] The present invention also provides a method for operating the above-mentioned watchdog circuit suitable for embedded systems, comprising the following steps: During the power supply voltage VCC rise process, the general-purpose watchdog chip monitors the power supply undervoltage. When VCC is lower than the undervoltage reset threshold, the output pin WDO of the general-purpose watchdog continuously outputs a low-level reset signal. The digital circuit composed of a tri-state gate and a D flip-flop sets the feed pin WDI of the general-purpose watchdog to a high-impedance state, thus disabling the watchdog function. After VCC rises above the undervoltage reset threshold, the CPU starts up. During the startup process, the watchdog function of the general watchdog is disabled, while the voltage monitoring function is normal. After the CPU boots up, the watchdog function is restored through a digital circuit composed of tri-state gates and D flip-flops to continuously monitor the system's operating status.

[0008] Preferably, after VCC rises above the undervoltage reset threshold, the general-purpose watchdog will still maintain a reset pulse for a certain duration (see chip reset pulse width for details) before releasing the reset signal, allowing the CPU to enter the startup process.

[0009] Preferably, when VCC is below the undervoltage reset threshold and the output pin WDO of the general watchdog outputs a low-level reset signal, the asynchronous clear pin CLR of the D flip-flop connected to the output pin WDO is synchronously set low. At this time, the output signal pin Q of the D flip-flop outputs a low level, which in turn makes the enable signal pin OE of the connected tri-state gate go low, the output channel of the tri-state gate is turned off, and its output pin Y is in a high-impedance state.

[0010] Preferably, during CPU startup, the output signal pin Q of the D flip-flop will continuously output a low level until the clock pin CLK of the D flip-flop receives a rising edge signal.

[0011] Preferably, after the CPU completes system initialization, the CPU's watchdog feed pin IO periodically outputs a watchdog feed signal to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate. When the clock pin CLK of the D flip-flop receives a rising edge signal, the D flip-flop latches the high level of the input signal pin D to the output signal pin Q, causing the output signal pin Q to flip from low level to high level. This high-level signal is synchronously sent to the tri-state gate enable signal pin OE, enabling the tri-state gate to pass-through buffer mode. Its output pin Y follows the level state of the input pin A in real time. At this time, the general-purpose watchdog feed pin WDI connected to the output pin Y is out of the high-impedance state and can normally receive the watchdog feed signal output by the CPU through the watchdog feed pin IO. The watchdog monitoring function of the general-purpose watchdog is restored, and it can continuously monitor the operating status of the entire system in real time.

[0012] In summary, compared with the prior art, the present invention has the following technical advantages and beneficial effects: (1) Effectively solves the problem of repeated restarts during the startup process of embedded systems: The circuit of this invention only disables the watchdog function during the power-on startup phase (while retaining the chip power undervoltage monitoring and reset function), and does not need to output a watchdog signal during the startup phase. This effectively solves the problem of repeated restarts caused by the long startup time of complex embedded systems from the hardware level.

[0013] (2) No additional general IO resources are occupied: the microprocessor only needs to be configured with one IO output dog feed signal, without the need to add other IO resource allocation. For embedded systems with many peripherals and IO resources that are close to saturation, the adaptability of the present invention is higher.

[0014] (3) Strong compatibility: Only simple digital circuits are added at the hardware level, without modifying the existing software design. This invention is applicable to a variety of embedded system application scenarios. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the watchdog circuit of the present invention applicable to embedded systems; Figure 2 This is a flowchart illustrating the working method of the watchdog circuit applicable to embedded systems according to the present invention. Detailed Implementation

[0016] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0017] like Figure 1 The present invention relates to a watchdog circuit suitable for embedded systems, comprising a general-purpose watchdog, a tri-state gate, a D flip-flop, and a CPU.

[0018] Specifically, the general-purpose watchdog is used for power undervoltage monitoring and watchdog timeout reset monitoring. Its feed pin WDI is connected to the output pin Y of the tri-state gate, and its output pin WDO is connected to the CPU's reset pin nRST and the asynchronous clear pin CLR of the D flip-flop. In addition, the general-purpose watchdog's pin MR can be connected to a manual reset button as needed.

[0019] Specifically, the tri-state gate is a high-level enabled tri-state buffer used for the WDI state control and watchdog signal access control of the general-purpose watchdog. The input signal pin A is connected to the CPU's watchdog pin IO and the clock pin CLK of the D flip-flop. The enable signal pin OE of the tri-state gate is connected to the output signal pin Q of the D flip-flop. When the enable signal pin OE is high, it can connect the CPU's watchdog pin IO and the general-purpose watchdog pin WDI.

[0020] Specifically, the D flip-flop is used for triggering control of the tri-state gate enable signal pin OE, and its input signal pin D is fixed at a high level.

[0021] Specifically, the CPU's watchdog pin IO is connected to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate, and the CPU's reset pin nRST is connected to the output pin WDO of the general-purpose watchdog.

[0022] The above-mentioned watchdog circuit operation method applicable to embedded systems is as follows: Figure 2 As shown, it includes the following steps: During the power-on voltage VCC rise process, the general-purpose watchdog chip monitors for undervoltage. When VCC falls below the undervoltage reset threshold, the watchdog's output pin WDO continuously outputs a low-level reset signal. This, along with a digital circuit composed of a tri-state gate and a D flip-flop, sets the watchdog's feed pin WDI to a high-impedance state, disabling the watchdog function. While VCC is below the undervoltage reset threshold and the watchdog's output pin WDO outputs a low-level reset signal, the asynchronous clear pin CLR of the D flip-flop connected to WDO is synchronously set low. At this time, the D flip-flop's output signal pin Q outputs a low level, causing the connected tri-state gate's enable signal pin OE to go low, shutting down the tri-state gate's output channel, and its output pin Y becomes high-impedance. This high-impedance signal, when connected to the watchdog's feed pin WDI, disables the watchdog function internally, the internal counting unit stops working, and no watchdog reset signal is generated.

[0023] After VCC rises above the undervoltage reset threshold, the general-purpose watchdog will still maintain a reset pulse for a certain duration (see chip reset pulse width for details), and then release the reset signal, allowing the CPU to enter the startup process; the CPU starts up, during which the watchdog function of the general-purpose watchdog is disabled, and the voltage monitoring function is normal.

[0024] After the CPU boots up, the watchdog function is restored through a digital circuit composed of a tri-state gate and a D flip-flop, continuously monitoring the system's operating status. After the CPU completes system initialization, the CPU's watchdog feed pin (IO) periodically outputs a watchdog signal. When the D flip-flop's clock pin (CLK) receives a rising edge signal, the D flip-flop latches the high level of the input signal pin (D) to the output signal pin (Q), causing the output signal pin (Q) to flip from low to high. This high-level signal is synchronously sent to the tri-state gate's enable signal pin (OE), enabling the tri-state gate's pass-through buffer mode. Its output pin (Y) follows the level state of the input pin (A) in real time. At this time, the general-purpose watchdog feed pin (WDI) connected to the output pin (Y) is removed from the high-impedance state and can normally receive the watchdog signal output by the CPU through the watchdog feed pin (IO). The general-purpose watchdog's watchdog monitoring function is restored, allowing continuous real-time monitoring of the entire system's operating status.

[0025] The following example illustrates this.

[0026] Assuming the system supply voltage is 3.3V, the typical undervoltage reset threshold of the general watchdog is 2.93V, the watchdog timeout is 1.6s, and the reset pulse width is 200ms; the CPU startup time is 5s, and the CPU watchdog feeding cycle after startup is 300ms.

[0027] After the system is powered on, the power supply voltage VCC gradually rises. The general-purpose watchdog chip monitors for undervoltage. When VCC drops below 2.93V, the watchdog chip's WDO pin continuously outputs a low-level reset signal. The asynchronous clear input CLR of the D flip-flop connected to this pin is synchronously set low. At this time, the Q pin of the D flip-flop outputs a low level, which in turn causes the output enable input OE of the connected tri-state gate to go low, turning off the tri-state gate's output channel, and its Y pin becomes high-impedance. After this high-impedance signal is connected to the watchdog chip's WDI pin, the internal watchdog function is disabled, and the internal counting unit stops working. Even if the startup time exceeds 1.6 seconds, the watchdog will not generate a reset signal.

[0028] Once VCC rises above 2.93V, the watchdog chip will maintain a 200ms reset pulse before releasing the reset signal. The CPU then enters the startup process. During startup, the watchdog chip can monitor undervoltage, and the output signal pin Q of the D flip-flop will continuously output a low level until the clock pin CLK of the D flip-flop receives a rising edge signal.

[0029] After the CPU boots up, its I / O pins output a watchdog signal every 300ms. When the CLK pin of the connected D flip-flop receives a rising edge signal, the D flip-flop latches the high level of the D pin to its output Q, causing Q to flip from low to high. This high-level signal is synchronously sent to the tri-state gate's output enable pin OE, enabling the tri-state gate's pass-through buffer mode. Its output pin Y follows the level state of the input pin A in real time. At this time, the watchdog chip's watchdog feed pin WDI, connected to pin Y, is no longer in a high-impedance state and can normally receive the watchdog signal output by the CPU through the I / O pins. The watchdog monitoring function of the watchdog chip is restored, allowing continuous real-time monitoring of the entire system's operating status.

[0030] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape, principle and application direction of this application should be covered within the scope of protection of this application.

Claims

1. A watchdog circuit suitable for embedded systems, characterized in that, This includes a general-purpose watchdog timer, tri-state gates, D flip-flops, and a CPU; The general-purpose watchdog is used for power undervoltage monitoring and watchdog timeout reset monitoring. Its feed pin WDI is connected to the output pin Y of the tri-state gate, and its output pin WDO is connected to the CPU's reset pin nRST and the asynchronous clear pin CLR of the D flip-flop. The tri-state gate is a high-level enabled tri-state buffer used for the WDI state control and watchdog signal access control of the general watchdog. The input signal pin A is connected to the CPU's watchdog pin IO and the clock pin CLK of the D flip-flop. The enable signal pin OE of the tri-state gate is connected to the output signal pin Q of the D flip-flop. When the enable signal pin OE is high, it can connect the CPU's watchdog pin IO and the general watchdog's watchdog pin WDI. The D flip-flop is used for triggering control of the tri-state gate enable signal pin OE, and its input signal pin D is fixed at a high level; The CPU's watchdog pin IO is connected to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate, and the CPU's reset pin nRST is connected to the output pin WDO of the general-purpose watchdog.

2. The watchdog circuit for embedded systems according to claim 1, characterized in that, The MR pin of the general-purpose watchdog can be connected to a manual reset button as needed.

3. A method for operating a watchdog circuit suitable for embedded systems as described in claim 1 or 2, characterized in that, Includes the following steps: During the power supply voltage VCC rise process, the general-purpose watchdog chip monitors the power supply undervoltage. When VCC is lower than the undervoltage reset threshold, the output pin WDO of the general-purpose watchdog continuously outputs a low-level reset signal. The digital circuit composed of a tri-state gate and a D flip-flop sets the feed pin WDI of the general-purpose watchdog to a high-impedance state, thus disabling the watchdog function. After VCC rises above the undervoltage reset threshold, the CPU starts up. During the startup process, the watchdog function of the general watchdog is disabled, while the voltage monitoring function is normal. After the CPU boots up, the watchdog function is restored through a digital circuit composed of tri-state gates and D flip-flops to continuously monitor the system's operating status.

4. The operating method of the watchdog circuit for embedded systems according to claim 3, characterized in that, After VCC rises above the undervoltage reset threshold, the general-purpose watchdog will maintain a reset pulse for a certain duration before releasing the reset signal, allowing the CPU to enter the startup process.

5. The operating method of the watchdog circuit for embedded systems according to claim 4, characterized in that, When VCC is below the undervoltage reset threshold and the output pin WDO of the general watchdog timer outputs a low-level reset signal, the asynchronous clear pin CLR of the D flip-flop connected to the output pin WDO is synchronously set low. At this time, the output signal pin Q of the D flip-flop outputs a low level, which in turn makes the enable signal pin OE of the connected tri-state gate go low, the output channel of the tri-state gate is turned off, and its output pin Y is in a high-impedance state.

6. The operating method of the watchdog circuit for embedded systems according to claim 5, characterized in that, During CPU startup, the general-purpose watchdog timer can monitor undervoltage, and the output signal pin Q of the D flip-flop will continuously output a low level until the clock pin CLK of the D flip-flop receives a rising edge signal.

7. The operating method of the watchdog circuit for embedded systems according to claim 6, characterized in that, After the CPU completes system initialization, the CPU's watchdog feed pin IO periodically outputs a watchdog feed signal to the clock pin CLK of the D flip-flop and the input signal pin A of the tri-state gate. When the clock pin CLK of the D flip-flop receives a rising edge signal, the D flip-flop latches the high level of the input signal pin D to the output signal pin Q. This high level signal is synchronously sent to the tri-state gate enable signal pin OE, enabling the tri-state gate to pass-through buffer mode. Its output pin Y follows the level state of the input pin A in real time. At this time, the general-purpose watchdog feed pin WDI, which is connected to the output pin Y, is out of the high-impedance state and can normally receive the watchdog feed signal output by the CPU through the watchdog feed pin IO. The watchdog monitoring function of the general-purpose watchdog is restored, and it can continuously monitor the operating status of the entire system in real time.

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