Memory device, memory controller, and method of operating a memory device

Abstract

This disclosure provides a storage device, a storage controller, and a method of operating the storage device. The storage device includes: at least one first pin; a plurality of second pins; a storage interface circuit configured to obtain control information from at least one control signal received from the at least one first pin, obtain data from a plurality of data signals received from the plurality of second pins, and obtain command and parity information from the control information by parsing a header included in the control information; a storage cell array configured to store the data; an error correction code (ECC) decoder circuit configured to correct errors in the command based on the parity information to generate an error-corrected command; and a control circuit configured to control the storage device based on the error-corrected command in a reset state of a failure flag.

Description

Technical Field

[0001] This disclosure relates to a storage device, a storage controller for controlling the storage device, and a method for operating the storage device. Background Technology

[0002] Storage devices can send and receive input / output signals to and from the storage controller via predetermined pins. For example, a storage device can send and receive data to and from the storage controller via data input / output pins, and can send and receive control signals to and from the storage controller via control signal input / output pins that are different from the data input / output pins. When data and control signals are sent and received through different input / output pins, data can be sent simultaneously with the control signals, thereby improving data transmission efficiency.

[0003] However, in order to further improve data transmission efficiency as the data transmission speed increases, the transmission speed of the control signal should also be increased accordingly. Summary of the Invention

[0004] An example implementation provides a storage device, a storage controller, and a method for operating the storage device, wherein the command failure rate can be reduced even when the transmission rate of control signals is increased.

[0005] According to an example embodiment, a storage device includes: at least one first pin; a plurality of second pins; a memory interface circuit that obtains control information from at least one control signal received from the at least one first pin, obtains data from a plurality of data signals received from the plurality of second pins, and obtains command and parity information from the control information by parsing a header included in the control information; a storage cell array that stores the data; an error correction code (ECC) decoder circuit that uses the parity information to correct errors in the command to generate an error-corrected command; and a control circuit that controls the storage device based on the error-corrected command in a reset state of a failure flag.

[0006] According to an example implementation, a storage controller includes: at least one first pin; a plurality of second pins; a processor configured to generate commands for controlling a storage device; a first error correction code (ECC) circuit configured to perform error correction coding on the commands to generate first parity information; and a controller interface circuit configured to provide at least one control signal including the commands and the first parity information to the storage device via the at least one first pin, input data signals to and output data signals from the storage device via the plurality of second pins, receive a failure signal from the storage device indicating that the at least one control signal has failed, and perform training on the at least one control signal based on the failure signal.

[0007] According to an example implementation, a method of operating a storage device includes: receiving at least one control signal from a controller via at least one control signal line, including a command, an address, and parity information; performing error correction code (ECC) decoding on the command and the address using the parity information; setting a failure flag and generating failure information based on error correction failure of at least one of the command and the address; providing a response including the failure information via the at least one control signal line and resetting the failure flag in response to a status read command from the controller; and receiving a training command from the controller and providing a response via the at least one control signal line. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a diagram illustrating an example of a storage system according to some implementation methods.

[0010] Figure 2 It is a timing diagram of control signals and data signals.

[0011] Figure 3 This is a diagram illustrating an example of a storage system according to some implementation methods.

[0012] Figure 4 This is a diagram illustrating examples of storage devices according to some embodiments.

[0013] Figure 5 This is a flowchart illustrating an operational example of a storage device according to some embodiments.

[0014] Figure 6 This is a timing diagram of example control signals according to some implementation methods.

[0015] Figure 7 This is a timing diagram of example control signals and example failure flag signals according to some implementation methods.

[0016] Figure 8 This is a flowchart illustrating an operational example of a storage device according to some embodiments.

[0017] Figure 9 This is a timing diagram of examples of control signals and failure flag signals according to some implementation methods.

[0018] Figure 10 This is a diagram illustrating an example interaction between a storage controller and a storage device according to some implementations. Detailed Implementation

[0019] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0020] Figure 1 This is a diagram illustrating a storage system according to some example implementations.

[0021] refer to Figure 1 The storage system 10 may include a storage device group 100 and a storage controller 200. The storage system 10 may support multiple channels CH1-CHm, and the storage device group 100 and the storage controller 200 may be connected via multiple channels CH1-CHm. For example, the storage system 10 may be implemented as a storage system such as a solid-state drive (SSD).

[0022] The memory device group 100 may include a plurality of memory devices MD11-MDmn. Each of the plurality of memory devices MD11-MDmn may be a flash memory device. However, this disclosure is not limited thereto, and each of the plurality of memory devices MD11-MDmn may include: non-volatile memory, such as resistive random access memory (RRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), thyristor random access memory (TRAM), or magnetic random access memory (MRAM); or volatile memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0023] Each memory device MD11-MDmn can be connected to one of the multiple channels CH1-CHm via a corresponding path. For example, memory devices MD11-MD1n can be connected to the first channel CH1 via paths W11-W1n, and memory devices MD21-MD2n can be connected to the second channel CH2 via paths W21-W2n. In some example embodiments, each memory device MD11-MDmn can be implemented as an arbitrary memory cell that can be operated according to a single control signal from the memory controller 200. For example, each memory device MD11-MDmn can be implemented as a chip or a die, but this disclosure is not limited thereto.

[0024] The storage controller 200 can send and receive signals to and from the storage device group 100 via multiple channels CH1-CHm. For example, the storage controller 200 can send control signals CTR1a-CTRLm and data signals to the storage device group 100 via channels CH1-CHm, and receive data signals DATAa-DATAm from the storage device group 100. The control signals may include commands and may also include addresses.

[0025] The storage controller 200 can select one storage device connected to the corresponding channel for each channel and send and receive signals with the selected storage device. For example, the storage controller 200 can select storage device MD11 from the storage devices MD11-MD1n connected to the first channel CH1. The storage controller 200 can send control signal CTR1a and data signal DATAa to the selected storage device MD11 through the first channel CH1, and receive data DATAa from the selected storage device MD11.

[0026] The storage controller 200 can send and receive signals in parallel with the storage device group 100 through different channels. For example, the storage controller 200 can send a control signal CTRLb to the storage device group 100 through a first channel CH1 while simultaneously sending a control signal CTRL1 to the storage device group 100 through a second channel CH2. Similarly, the storage controller 200 can receive a data signal DATAa from the storage device group 100 through a first channel CH1 while simultaneously receiving a data signal DATAb from the storage device group 100 through a second channel CH2.

[0027] The storage controller 200 can control the overall operation of the storage device group 100. The storage controller 200 can control the individual storage devices MD11-MD1n connected to channels CH1-CHm by sending signals to channels CH1-CHm. For example, the storage controller 200 can control one selected storage device among the storage devices MD11-MD1n by sending a control signal CTRLa to the first channel CH1.

[0028] Each storage device MD11-MDmn can operate under the control of the storage controller 200. For example, storage device MD11 can be programmed with data according to the control signal CTR1a and the data signal DATAa provided to the first channel CH1. For example, storage device MD21 can read data according to the control signal CTRLb provided to the second channel CH2 and send the read data to the storage controller 200 as the data signal DATAb.

[0029] exist Figure 1 In this diagram, the memory device group 100 is shown communicating with the memory controller 200 via m channels, and the memory device group 100 includes n non-volatile memory devices corresponding to each channel. However, the number of channels and the number of non-volatile memory devices connected to a channel can be varied in various ways.

[0030] A channel may include control signal lines for sending and receiving control signals, and data signal lines for sending and receiving data signals. Control signals and data signals can be sent and received in parallel via the control signal lines and data signal lines.

[0031] Figure 2 It is a timing diagram of control signals and data signals.

[0032] refer to Figure 1 The described storage controller 200 and storage device MD (MD11-MDmn) can send and receive one or more control signals CA[X:0] via one or more control signal lines, and can send and receive multiple data signals DQ[Y:0] via multiple data lines.

[0033] For example, the memory controller 200 and the memory device MD can send and receive control signals CA[1:0] via two control signal lines and data signals DQ[7:0] via eight data pins. Hereinafter, some exemplary embodiments will be described using the case of sending and receiving multiple control signals between the memory controller 200 and the memory device MD as an example. However, this disclosure does not exclude the case where the memory controller 200 and the memory device MD send and receive a single control signal via a single control signal line, or a single data signal via a single data line.

[0034] The storage device MD can receive the control signal CA[X:0] during the first time period T11 and obtain the first control information CTRL1 from the control signal CA[X:0]. For example, the first control information CTRL1 may include a command and an address. The storage device MD can obtain the first data DATA1 from the data signal DQ[Y:0] based on the first control information CTRL1 obtained in the first time period T11, or output the first data DATA1 stored in the storage device MD as the data signal DQ[Y:0].

[0035] For example, when the command is a programming command, the storage device MD can obtain the first data DATA1 in the second time period T12, and when the command is a read command, the storage device MD can output the first data DATA1 in the second time period T12.

[0036] The storage device MD can receive the control signal CA[X:0] during the second time period T12 and obtain the second control information CTRL2 from the control signal CA[X:0]. For example, the storage device MD can obtain the second control information CTRL2 through a control signal line different from the data signal line while simultaneously inputting / outputting the first data DATA1. Since the input / output paths of data and control information are different, the storage device MD can input / output data while obtaining control information, and the data input / output efficiency can be improved.

[0037] To further improve data input / output efficiency, the speed at which control information is received may also need to increase in response to the increased data input / output speed. The size of the control information can be smaller than the size of the data, and the speed at which the control information is received can be slower than the data input / output speed. For example, to prevent failure of the storage device MD, the control information may require a higher level of integrity than the data. Therefore, the storage controller 200 can provide sufficient timing margin for the sampling control signal by sending control signals at a frequency lower than the data signal frequency.

[0038] However, if the time period for receiving the control signal including the second control information CTRL2 is longer than the time period for inputting / outputting the data signal including the first data DATA1, the data signal based on the second control information CTRL2 may not be input / output before the control signal reception is complete, even after the first data DATA1 has been received. Therefore, data input / output efficiency may be reduced.

[0039] If the frequency of control signals is increased to improve data input / output efficiency, timing margin may decrease, and the failure rate of commands or addresses included in the control information may increase. Command or address failure refers to a state where a command cannot be executed correctly due to incorrect bits in the received command or address. If the failure rate increases, the likelihood of memory device (MD) failure may also increase.

[0040] According to some example implementations, the control information may include not only commands and addresses, but also parity checks of the commands and addresses (e.g., parity information). The storage device can receive a control signal CA[X:0] including parity checks via a control signal line. The storage device can obtain commands, addresses, and parity checks from the control signal CA[X:0], and can use parity checks to detect and correct errors in commands and addresses, thereby reducing the failure rate.

[0041] Furthermore, when errors in the control information are not corrected, the storage device can prevent malfunctions by setting a failure flag and ignoring the control information. When the failure flag is set, the storage device can respond to a status read command received via the control line by outputting a failure message via the control line.

[0042] The following text will refer to Figures 3 to 10 A detailed description of a storage system including storage devices according to some example embodiments.

[0043] Figure 3 This is a diagram illustrating a storage system according to some example implementations.

[0044] refer to Figure 3 The storage system 20 may include a storage device 300 and a storage controller 400. The storage device 300 may be connected to a reference... Figure 1 The description corresponds to any of the storage devices MD (MD11-MDmn), and the storage controller 400 can be associated with the reference. Figure 1 The storage controller 200 described corresponds to this.

[0045] The storage device 300 may include first pins P11 to fourth pins P14, a memory interface circuit 310, an ECC decoder circuit 320, a control circuit 330, and a storage cell array 340.

[0046] The memory interface circuit 310 can send and receive one or more control signals CA[X:0], control clock signal CA_CLK, multiple data signals DQ[Y:0] and data strobe signal DQS through the first pin P11 to the fourth pin P14.

[0047] Specifically, the memory interface circuit 310 can obtain control information from the control signal CA[X:0] received through the first pin P11. The number of first pins P11 can be equal to the number of control signals.

[0048] According to some example implementations, the control information may include at least a command and a parity check, and may also include an address. For example, when the control information includes a command, an address, and a parity check, the parity check may include a first parity check obtained by performing error correction coding on the command, and a second parity check obtained by performing error correction coding on the address. However, this disclosure is not limited thereto, and the parity check may be a parity check obtained by performing error correction coding on the entire command and address.

[0049] The memory interface circuit 310 can obtain control information by sampling the control signal CA[X:0] based on the control clock signal CA_CLK received through the second pin P12. The control clock signal CA_CLK can remain in a static state such as high or low during periods when the control signal CA[X:0] is not received, and can switch between high and low levels during periods when the control signal CA[X:0] is received.

[0050] Furthermore, the memory interface circuit 310 can send a control signal CA[X:0] to the memory controller 400, which includes control information such as a response to a status read command. The memory interface circuit 310 can generate a control clock signal CA_CLK and send the control signal CA[X:0] to the memory controller 400 based on the generated control clock signal CA_CLK.

[0051] The memory interface circuit 310 can obtain data DATA from the data signal DQ[Y:0] received through the third pin P13, or generate a data signal DQ[Y:0] including data DATA. The number of third pins P13 can be the same as the number of data signals DQ[Y:0].

[0052] The memory interface circuit 310 can obtain data DATA from the data signal DQ[Y:0] via the data strobe signal DQS received from the memory controller 400 via the fourth pin P14. Furthermore, the memory interface circuit 310 can generate the data strobe signal DQS and send a third signal SIG3 containing the data DATA to the memory controller 400 based on the generated data strobe signal DQS.

[0053] In some example implementations, the frequencies of the data signal DQ[Y:0] and the data strobe signal DQS can be higher than the frequencies of the control signal CA[X:0] and the control clock signal CA_CLK.

[0054] ECC decoder circuit 320 can perform error detection and correction on the control information CTRL obtained from memory interface circuit 310. ECC decoder circuit 320 can correct errors in commands and addresses included in the control information CTRL by performing error correction decoding using parity included in the control information CTRL, and output command / address CMD / ADDR with corrected errors.

[0055] According to some example implementations, the control information CTRL received from the storage controller 400 may include parity checking, and the ECC decoder circuit 320 may use parity checking to correct errors in commands and addresses.

[0056] The control circuit 330 can control the overall operation of the storage device 300. The control circuit 330 can receive commands / addresses (CMD / ADDR) from the ECC decoder circuit 320. Based on the received commands / addresses (CMD / ADDR), the control circuit 330 can generate internal signals for controlling other components of the storage device 300. For example, the control circuit 330 can generate various internal signals for programming data DATA into or reading data DATA from the memory cell array 340.

[0057] According to some example implementations, if the ECC decoder circuit 320 fails to correct at least some errors in the command and address, the control circuit 330 may set a failure flag (that is, set the failure flag to a set state). The control circuit 330 may ignore received command / address CMD / ADDR after the failure flag is set, except for status read commands.

[0058] The control circuit 330 can provide failure information to the storage controller 400 in response to a status read command when the failure flag is set, and reset the failure flag (that is, put the failure flag in a reset state). According to some example implementations, the failure information can be sent via the first pin P11.

[0059] The storage cell array 340 can store data DATA obtained from the memory interface circuit 310 under the control of the control circuit 330. The storage cell array 340 can also output the stored data DATA to the memory interface circuit 310 under the control of the control circuit 330.

[0060] The storage cell array 340 may include a plurality of storage cells. For example, the plurality of storage cells may be flash memory cells. However, this disclosure is not limited thereto, and the storage cells may be non-volatile storage cells or volatile storage cells. Hereinafter, implementations will be described based on some example implementations in which the storage cells are NAND flash memory cells.

[0061] The storage controller 400 may include first pins P21 to fourth pins P24, host interface circuit 410, controller interface circuit 420, processor 430, buffer memory 440, data ECC circuit 451 and control ECC circuit 452.

[0062] The host interface circuit 410 can send and receive data packets with the host. Data packets sent from the host to the host interface circuit 410 may include commands or data to be written to the storage device 300, and data packets sent from the host interface circuit 410 to the host may include responses to commands or data read from the storage device 300.

[0063] Pins P21 to P24 can correspond to pins P11 to P14 of the storage device 300. Pins P11 and P21 can be connected via control signal lines, and pins P12 and P22 can be connected via control clock signal lines. Pins P13 and P23 can be connected via data signal lines, and pins P14 and P24 can be connected via data strobe signal lines.

[0064] The controller interface circuit 420 can send control signals CA[X:0] and control clock signals CA_CLK to the storage device 300 and receive control signals CA[X:0] and control clock signals CA_CLK from the storage device 300 through the first pin P21 to the fourth pin P24. It can also send data signals DQ[Y:0] and data strobe signals DQS to the storage device 300 and receive data signals DQ[Y:0] and data strobe signals DQS from the storage device 300.

[0065] Specifically, the controller interface circuit 420 can send the control signal CA[X:0] through the first pin P21 and send the control clock signal CA_CLK for sampling the control signal CA[X:0] through the second pin P22. Alternatively, the controller interface circuit 420 can receive the control signal CA[X:0] through the first pin P21 and receive the control clock signal CA_CLK through the second pin P22.

[0066] Furthermore, the controller interface circuit 420 can send the data signal DQ[Y:0] via the third pin P23 and send the data strobe signal DQS for sampling the data signal DQ[Y:0] via the fourth pin P24. Alternatively, the controller interface circuit 420 can receive the data signal DQ[Y:0] via the third pin P23 and receive the data strobe signal DQS via the fourth pin P24.

[0067] The processor 430 can control the overall operation of the storage controller 400 by executing firmware such as the flash translation layer (FTL). For example, the processor 430 can perform various functions such as address mapping, wear leveling, and garbage collection.

[0068] Processor 430 can generate commands and addresses to control storage device 300. For example, processor 430 can generate commands such as programming commands, read commands, and erase commands, as well as addresses corresponding to the storage areas where the commands will be executed. Furthermore, processor 430 can generate status read commands to request the status of storage device 300.

[0069] The buffer memory 440 can store data to be programmed into the storage device 300, data read from the storage device 300, and metadata such as mapping data. The buffer memory 440 can be located within the storage controller 400, or it can be located outside the storage controller 400.

[0070] The data ECC circuit 451 can perform error detection and correction functions on the data read from the storage device 300. Specifically, the data ECC circuit 451 can generate parity checks for the programming data to be programmed into the storage device 300. The generated parity checks can be stored in the storage device 300 along with the programming data. Furthermore, the data ECC circuit 451 can use the parity checks read from the storage device 300 along with the read data to correct errors in the read data and output the corrected read data.

[0071] The control ECC circuit 452 can generate parity checks for commands and addresses sent to the storage device 300. As a first example, the control ECC circuit 452 can generate a parity check including a first parity check for the command and a second parity check for the address. As a second example, the control ECC circuit 452 can generate a parity check by performing error correction coding on the command and address.

[0072] In some example implementations, different error correction codes can be applied to the data ECC circuit 451 and the control ECC circuit 452. For example, the size of the data can be larger than the size of the command and the address. Therefore, the error correction code applied to the data ECC circuit 451 can support error correction coding of codewords with larger size than the error correction code applied to the control ECC circuit 452.

[0073] In some example implementations, host interface circuitry 410 may include host direct memory access (HDMA) 411, which controls data transmission and reception between host memory and buffer memory 440. Furthermore, controller interface circuitry 420 may include flash direct memory access (FDMA) 421, which controls data transmission and reception between buffer memory 440 and memory interface circuitry 310. HDMA 411 and FDMA 421 can transmit data without intervention from processor 430.

[0074] According to some example implementations, the storage controller 400 can protect commands and addresses from errors and reduce the failure rate of control signals by sending control signals with parity checks to the storage device 300. In response to the trend of high-speed data input / output, the failure rate of control signals can be reduced even if the transmission rate of control signals is high. As a result, data input / output efficiency can be improved.

[0075] Furthermore, the storage controller 400 can resend control signals, including the failed command or address, in response to failed data from the storage device 300. In some example embodiments, the storage controller 400 can reduce the frequency of the control signals to increase the timing margin of the control signals, and can also perform a recovery operation to retrain the control signal lines. Therefore, the reliability of the storage system 20 can be improved.

[0076] Before describing the operation of the storage system according to the example implementation in detail below, refer to Figure 4 Describe the structure of the storage device in more detail.

[0077] Figure 4 This is a diagram illustrating a storage device according to an example embodiment.

[0078] Figure 4 This is an example block diagram illustrating a non-volatile storage device. (Reference) Figure 4 The non-volatile memory 500 may include control circuitry 530, a memory cell array 540, a page buffer 550, a voltage generator 560, and a line decoder 570. Although not explicitly stated... Figure 4 As shown, but the non-volatile memory 500 may also include, for example, a reference. Figure 3 The circuits described are the memory interface circuit 310 and the ECC decoder circuit 320, and may also include column logic, pre-decoder, temperature sensor, command decoder, address decoder, etc.

[0079] The control circuit 530 can generally control various operations within the non-volatile memory 500. The control circuit 530 can output various internal signals in response to commands CMD and / or addresses ADDR received by the memory interface circuit and corrected by the ECC decoder circuit. For example, the control circuit 530 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0080] The memory cell array 540 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 540 may be connected to the page buffer 550 via the bit line BL, and may be connected to the line decoder 570 via the word line WL, the serial select line SSL, and the ground select line GSL.

[0081] In some example embodiments, the memory cell array 540 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. Examples of the memory cell array 540 when implemented as a three-dimensional memory cell array are described in U.S. Patent Publications Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648, the contents of which are incorporated herein by reference in their entirety. In some example embodiments, the memory cell array 540 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0082] Page buffer 550 may include multiple page buffers PB1-PBn (n is an integer of 3 or greater), and the multiple page buffers PB1-PBn may be connected to the memory cell via multiple bit lines BL. Page buffer 550 may select at least one bit line in the bit lines BL in response to column address Y-ADDR. Page buffer 550 may be used as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer 550 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer 550 may detect the data stored in the memory cell by detecting the current or voltage of the selected bit line.

[0083] Voltage generator 560 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 560 can generate programming voltage, read voltage, programming verification voltage, erase voltage, etc., as word line voltage VWL.

[0084] The line decoder 570 can select a word line from multiple word lines (WL) and a string select line from multiple string select lines (SSL) in response to the line address X-ADDR. For example, during a programming operation, the line decoder 570 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the line decoder 570 can apply a read voltage to the selected word line.

[0085] In the following text, refer to Figures 5 to 9 The description specifically describes the operation of the storage device according to some example implementations.

[0086] Figure 5 This is a flowchart illustrating the operation of a storage device according to some example embodiments.

[0087] In operation S11, the storage device (e.g., Figure 3 The memory interface circuit 310 can receive control signals CA[X:0] from the memory controller. (See reference...) Figure 3 The storage device can receive the control clock signal CA_CLK together with the control signal CA[X:0].

[0088] In operation S12, the memory interface circuit 310 can obtain control information including command CMD, address ADDR, and parity check. For example, the memory device can obtain control information including multiple bits by sampling the control signal CA[X:0] using the control clock signal CA_CLK.

[0089] Furthermore, control information does not necessarily include addresses. For example, a status read command may not require an address. Therefore, storage devices can obtain control information that includes only the command CMD and parity check.

[0090] In operation S13, the storage device (e.g., Figure 3 The ECC decoder circuit 320 can perform error correction decoding on commands and addresses and determine whether the error correction decoding is successful.

[0091] If the error correction decoding passes ("Yes" in operation S13), then the storage device (e.g., Figure 3 The control circuit 330 can perform operations in operation S14 based on the error-corrected command CMD and the error-corrected address ADDR.

[0092] If error correction decoding fails (No in operation S13), the control circuit 330 can set a failure flag in operation S15. Specifically, the control circuit 330 can set a failure flag even if error correction decoding of command CMD or address ADDR fails.

[0093] In operation S16, control circuitry 330 can generate failure information for command CMD or address ADDR. In some example implementations, the failure information can indicate which control information has failed. Furthermore, when parity checking includes parity checking for each command CMD and address ADDR, the failure information can include information indicating whether error correction decoding of command CMD or address ADDR has failed.

[0094] Before describing the signal timing of control signals and failure flags below, please refer to [reference needed]. Figure 6 Describe in detail the method for sending control signals.

[0095] Figure 6 This is a timing diagram of control signals based on some example implementations.

[0096] exist Figure 6 In the example, the method of sending control signals is described by taking the case of receiving control information through two control signals CA[1:0].

[0097] The storage device can receive control signals CA[1:0] in parallel. While the control signals CA[1:0] are being received, the storage device can receive the switching control clock signal CA_CLK. The storage device can obtain control information from the control signals CA[1:0] based on the control clock signal CA_CLK.

[0098] For example, the storage device can obtain two bits within one cycle CY of the control clock signal CA_CLK by sampling the control signal CA[1:0] on the rising edge of the control clock signal CA_CLK. The storage device can obtain control signals including multiple bits within multiple time periods T21-T25.

[0099] The period for receiving control signals can be divided into multiple time units T21-T25. Each time unit can correspond to one or more cycles CY of the control clock signal CA_CLK. Figure 6 In the example, a unit time period can correspond to four cycles of the control clock signal CA_CLK. The storage device can obtain an 8-bit signal from the control signals CA[1:0] received in the unit time period. However, the number of control signals received in parallel and the number of cycles CY included in a time period are not limited to this.

[0100] The storage device can obtain commands, addresses, and parity checks from control signals received over multiple time periods. Control signals may include a header and a body following the header. The body may be any of a command, address, or parity check. The header may include information indicating whether the body is a command, address, or parity check.

[0101] exist Figure 6 In the example, the header can be received in the first time period T21. For example, the header can include header bits (H[7:0]) received in the first time period T21. The header can indicate whether the control signal CA[1:0] received in a unit time period after the first time period T21 is a command, address, or parity check. However, the length of the header is not limited to 8 bits.

[0102] The text received during the second time period T22 to the fifth time period T25 may include commands, addresses, or parity checks. For example, the text may include the text bits (B1[7:0], B2[7:0], B3[7:0], and B4[7:0]) received during the second time period T22 to the fifth time period T25.

[0103] In some example implementations, the sizes of the command, address, and parity check can be different from each other. The storage device can obtain the command, address, or parity check from control signals CA[1:0] received within several unit time periods determined based on the header.

[0104] Figure 7 It is a timing diagram of control signals and failure flag signals according to some example implementations.

[0105] refer to Figure 7 The storage device can receive the control signal CA[X:0] and generate a failure flag. The failure flag can remain in a reset state until a failure of the control signal is detected, and can be set when a failure of the control signal is detected.

[0106] Specifically, the storage device may receive control signals CA[X:0] during the first time period T31. For example, the control signals CA[X:0] received during the time period may include command header CMD_H, command CMD, address header ADDR_H, address ADDR, parity header PAR_H, and parity PAR.

[0107] The storage device can perform error correction on commands and addresses in the second time period T32. For example, refer to Figure 3 The described memory interface circuit 310 can obtain the command CMD, address ADDR, and parity PAR based on the headers CMD_H, ADD_H, and PAR_H of the control signal CA[X:0]. Furthermore, refer to... Figure 3The described ECC decoder circuit 320 can perform error correction on command CMD and address ADDR based on parity check (PAR).

[0108] The failure flag can remain reset during the first time period T31 and the second time period T32. If the command and address error correction passes (ECC pass), the failure flag can remain reset even after the second time period T32. However, if the command or address error correction fails (ECC fail), the storage device can set the failure flag after the second time period T32.

[0109] In the following text, refer to Figure 8 and Figure 9 The operation of the storage device will be described in detail when the failure flag is set.

[0110] Figure 8 This is a flowchart illustrating the operation of a storage device according to some example embodiments.

[0111] In operation S21, the storage device (e.g., reference) Figure 3 The memory interface circuit 310 described can receive control signals CA[X:0] from the memory controller.

[0112] In operation S22, the memory interface circuit 310 can obtain control information including command CMD, address ADDR, and parity check. For example, the memory interface circuit 310 can obtain control information including multiple bits by sampling the control signal CA[X:0] using the control clock signal CA_CLK.

[0113] In operation S23, the storage device (e.g., Figure 3 The ECC decoder circuit 320 can perform error correction decoding on the control information and determine whether the error correction decoding is successful.

[0114] If the error correction decoding fails (No in operation S23), then the storage device (e.g., Figure 3 The control circuit 330 can ignore the command CMD in operation S24.

[0115] If the error correction decoding passes (Yes in operation S23), the control circuit 330 can determine in operation S25 whether the command CMD is a status read command.

[0116] If the command CMD is not a status read command ("No" in operation S25), the control circuit 330 can ignore the command CMD in operation S24. For example, the control circuit 330 can discard the command without performing the operation indicated by the command CMD.

[0117] If the command CMD is a status read command ("Yes" in operation S25), the control circuit 330 can output failure data as a response to the status read command through the memory interface circuit 310 in operation S26.

[0118] In some example implementations, failure data may include a failure flag value. In some example implementations, failure data may also include a reference. Figure 5 The description refers to the failure information generated in operation S16.

[0119] In operation S27, control circuit 330 can reset the failure flag.

[0120] Figure 9 It is a timing diagram of control signals and failure flag signals according to some example implementations.

[0121] refer to Figure 9 The storage device can send and receive control signals CA[X:0] and control clock signals CA_CLK with the storage controller. Furthermore, the storage device can generate a failure flag.

[0122] exist Figure 9 In the example, the first time period T41, the second time period T42, and the third time period T43 are shown in chronological order.

[0123] With the failure flag set, the storage device can receive a status read command (Status read CMD) during the first time period T41. For example, the storage device can sequentially receive the command header CMD_H, the command CMD, the parity header PAR_H, and the parity PAR during the first time period T41. The storage device can obtain the command CMD and the parity PAR based on the headers CMD_H and PAR_H, and perform error correction decoding on the command using the parity PAR after the first time period T41.

[0124] If error correction decoding of the control signal received in the first time period T41 fails, or if the command included in the control signal is not a status read command, the storage device may ignore the command. However, if error correction decoding is successful and the command is a status read command, the storage device may provide a response to the status read command to the storage controller in the second time period T42.

[0125] According to some example implementations, storage devices (e.g., references) Figure 3The described control circuit 330 can output a response to a status read command via a control signal line that sends a control signal CA[X:0]. For example, the response may include status information (Status) and failure data (Fail_D). The status information may indicate the state of the storage device, such as whether the storage device is busy or ready. The failure data (Fail_D) may include a set failure flag value and failure information.

[0126] However, this disclosure is not limited thereto. For example, the control circuit 330 may include a failure flag value in the reserved bits of the 8-bit status information (Status) transmitted per unit time period.

[0127] According to some example implementations, the storage device can be accessed via a reference. Figure 3 The first pin, P11, is described as transmitting failure data. For example, the control signal line can support bidirectional communication between the memory controller and the memory device. The memory device can output a control signal CA[X:0] including the response via the first pin P11, and simultaneously output a control clock signal CA_CLK via the second pin P12.

[0128] Therefore, the storage device can notify the storage controller of whether there is a failure and the failure information through the first pin P11 without adding a separate signal pin for the failure alarm. This eliminates the need for excessive design changes to the storage device and saves the area occupied by the signal pin.

[0129] The storage device can reset the failure flag after the second time period T42. If the error correction decoding of the control signal CA[X:0] received after the failure flag is reset is successful, the storage device can execute the command included in the control signal CA[X:0].

[0130] For example, the storage device may sequentially receive the command header CMD_H, the command CMD, the parity header PAR_H, and the parity PAR during the third time period T43. If the error correction decoding of the control signal CA[X:0] received by the storage device during the third time period T43 is successful, the storage device may execute the command CMD included in the control signal CA[X:0].

[0131] For example, the storage controller can determine which control information has failed based on the failure information received from the storage device, and can resend the failed control information to the storage device.

[0132] On the other hand, if a control signal received by the storage device fails, there is a high probability that subsequent control signals will also fail. For example, if the timing of the control signal CA[X:0] and the control clock signal CA_CLK is misaligned, causing the control signal to fail, there is a high probability that subsequent control signals will also fail.

[0133] In some example implementations, the memory controller can improve the timing margin of the control signal CA[X:0] by reducing the frequency of the control signal CA[X:0] and the control clock signal CA_CLK. However, if the frequency of the control signal CA[X:0] is reduced, the transmission period of the control signal CA[X:0] may become longer, and consequently, the input / output efficiency of the data signal may decrease.

[0134] According to some example implementations, the memory controller can perform control signal training in response to a failure flag received from the memory device before retransmitting the control signal that has failed. Control signal training can refer to operations used to improve timing margins in the control signal bus. For example, the memory controller can delay the control clock signal CA_CLK such that the rising edge of the control clock signal CA_CLK is in the middle of the eye diagram of the control signal. For example, control signal training can be performed by, as referenced... Figure 3 The processor 430 is used for control.

[0135] In some example implementations, the memory controller can initiate training by sending a control signal CA[X:0] including a training command (Training CMD) to the memory device in the third time period T43. The training command (Training CMD) includes a command header CMD_H, a command CMD, a parity header PAR_H, and a parity check PAR. The memory controller can send the training command to the memory device, then send a predetermined signal to the memory device via the control signal line, receive a response to the predetermined signal from the memory device via the control signal line, and control the delay of the control clock signal CA_CLK based on the response.

[0136] In some example implementations, the storage controller (e.g., Figure 3 The processor 430 can control the second frequency of the control signal CA[X:0] and the control clock signal CA_CLK sent in the third time period T43 to be lower than the first frequency of the control signal CA[X:0] and the control clock signal CA_CLK sent in the first time period T41 and the second time period T42. Figure 9 In the example, the second period CY2 of the control clock signal CA_CLK sent in the third time period T43 can be longer than the first period CY1 of the control clock signal CA_CLK sent in the first time period T41 and the second time period T42.

[0137] By lowering the second frequency, even if the timing is misaligned, the timing margin can be increased, and the probability of the training command being successfully sent to the storage device can also be increased. Once the training command is successfully sent, the processor 430 can restore the second frequency to the first frequency and execute the training.

[0138] Furthermore, if the control signal fails, the status read command sent to the storage device may also fail. If the storage device does not receive the status read command normally, it may be difficult to send failure information.

[0139] According to some example implementations, the storage controller can detect that the storage device is not receiving a status read command normally, reduce the frequency of the control signal and the control clock signal, and obtain the failure information by resending the status read command.

[0140] Figure 10 This is a diagram illustrating the interaction between a storage controller and storage devices according to some example implementations.

[0141] Figure 10 The storage device can be used with the reference Figure 3 The described storage device 300 corresponds to, and Figure 10 The storage controller can be compared with the reference Figure 3 The storage controller 400 described corresponds to this.

[0142] In operation S31, the storage controller can send control signals to the storage device. These control signals can be sent in parallel via control signal lines, which are different from the data signal lines. According to some example implementations, the control signals may include at least a command CMD and a parity check for the command. The control signals may include a command CMD, an address ADDR, and parity checks for both the command and the address.

[0143] In operation S32, the storage device can receive control signals and perform error correction decoding via control signal lines. For example, the storage device can use parity checks included in the control signals to detect and correct errors in commands CMD and addresses ADDR.

[0144] If error correction fails for at least one of the commands CMD and ADDR, the storage device can set a failure flag and store the failure information in operation S33. Then, the storage device can ignore the control signals received in operation S31.

[0145] Even if a failure flag is set in the storage device, the storage controller may not be able to detect whether a failure has occurred in the storage device before the failure information is sent to the storage controller.

[0146] In operation S34, the storage controller can send control signals to the storage device. The storage device can perform error correction decoding on the control signals, but if the error correction decoding fails or the command that succeeds in the error correction decoding is not a status read command, the control signal can be ignored.

[0147] In operation S35, the storage controller can detect a state where there is no response to the control signal sent in operation S31 and subsequent control signals. For example, the storage controller can detect a timeout state where no response is received after a predetermined period of time following the sending of a control signal.

[0148] In operation S36, the storage controller can send control signals, including a status read command and parity check, to the storage device. If the storage device receives the status read command normally, it can send failure data to the storage controller in response to the status read command. However, if error correction decoding based on the control signals fails, the storage device can ignore the control signals.

[0149] In operation S37, the storage controller (e.g., Figure 3 The processor 430 can detect a timeout state after sending a control signal that includes a status read command.

[0150] In operation S38, the processor 430 can reduce the frequency of the control signal and the control clock signal. Furthermore, in operation S39, the processor 430 can resend control signals, including status read commands, to the memory device.

[0151] If the storage device receives the status read command normally, the storage device can proceed as per the reference. Figure 8 and Figure 9 As a response to the status read command, failure data is sent to the storage controller.

[0152] As described above, according to some example implementations, the storage device can detect commands, addresses, and parity from control signals received from the storage controller, and can use parity to perform error detection and correction on commands and addresses. Therefore, even if the transmission speed of control signals received from the storage controller is increased, the command failure rate can be reduced.

[0153] According to some example implementations, the storage device can respond to a status read command received via a control signal input / output pin by outputting failure information of the control signal via the control signal input / output pin. Therefore, failure information can be provided to the storage controller without requiring a design change to add separate input / output pins.

[0154] According to some example implementations, the storage controller can perform training on the control signals in response to failure information received via control signal input / output pins to repair faults in the control signal lines and reduce the command failure rate.

[0155] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular implementations of a particular invention. Certain features described in the context of individual embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination can be removed from the combination in certain circumstances, and combinations may involve sub-combinations or variations of sub-combinations.

[0156] While exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A storage device, the storage device comprising: At least one first pin; Multiple second pins; A memory interface circuit configured to: obtain control information from at least one control signal received from at least one first pin; obtain data from a plurality of data signals received from a plurality of second pins; and obtain command and parity information from the control information by parsing a header included in the control information; A storage cell array configured to store the data; An error correction code decoder circuit is configured to use the parity information to correct errors in the command to generate an error-corrected command. as well as A control circuit configured to control the storage device based on the error-corrected command in a failed flag reset state.

2. The storage device according to claim 1, wherein, The control circuit is also configured to set the failure flag to a set state based on the error correction failure of the command.

3. The storage device according to claim 2, wherein, The control circuit is further configured to: ignore commands for which error correction has failed based on the failure flag being placed in the set state; and ignore the corrected command based on the fact that the corrected command includes a command different from the status read command.

4. The storage device according to claim 2, wherein, The control circuit is further configured to, based on the failure flag being placed in the set state, generate status information including the failure flag in response to a status read command, and The memory interface circuit is also configured to output at least one additional control signal, including the status information, through the at least one first pin.

5. The storage device according to claim 1, wherein, The memory interface circuit is also configured to obtain an address from the control information based on the header. The error-correcting code decoder circuit is further configured to generate an error-corrected address by using the parity information to correct errors in the address, and The control circuit is also configured to use the error-corrected address to control the memory cell array.

6. The storage device according to claim 5, wherein, The control circuit is also configured to set the failure flag to a set state based on the error correction failure of at least one of the command and the address.

7. The storage device according to claim 6, wherein, The control circuit is further configured to: generate failure information indicating that error correction has failed based on the failure flag being set to the setting state; and output a response including the failure information through the at least one first pin based on the status read command.

8. The storage device according to claim 7, wherein, The control circuit is also configured to reset the failure flag after the failure information is output.

9. The storage device according to claim 1, wherein, The frequency of at least one control signal is lower than the frequency of the plurality of data signals.

10. A storage controller, the storage controller comprising: At least one first pin; Multiple second pins; A processor configured to generate commands for controlling storage devices; A first error correction code circuit is configured to perform error correction coding on the command to generate first parity information. as well as A controller interface circuit is configured to: provide at least one control signal, including the command and the first parity information, to the storage device via at least one first pin; and input data signals to and output data signals from the storage device via the plurality of second pins. Receive a failure signal from the storage device indicating that the at least one control signal has failed; and perform training on the at least one control signal based on the failure signal.

11. The storage controller of claim 10, wherein, The processor is also configured to: After the at least one control signal is output, a status read command is provided to the storage device through the at least one first pin; as well as Based on the status read command, the failure signal is received through at least one first pin.

12. The storage controller of claim 11, wherein, The processor is also configured to: Based on receiving a response to the status read command after a predetermined time period, the frequency of the signal output to the at least one first pin is changed from a first frequency to a second frequency, wherein the second frequency is lower than the first frequency; and The status read command is resent to the storage device via at least one first pin.

13. The storage controller according to claim 10, wherein, The processor is also configured to resend the failed command via the at least one first pin based on the failure signal and the completion of the training.

14. The memory controller of claim 10, further comprising a third pin configured to output a first clock signal. in, The processor is also configured to: Change the frequency of the at least one control signal and the first clock signal from a first frequency to a second frequency lower than the first frequency; Training commands are provided to the storage device via the at least one first pin; Training is performed by changing the frequency of the at least one control signal and the first clock signal from the second frequency to the first frequency, based on the first response of the storage device to the training command. A predetermined signal is sent to the storage device via at least one first pin; A second response to the predetermined signal is received from the storage device via the at least one first pin; as well as The delay of the first clock signal is controlled based on the second response.

15. The storage controller of claim 10, wherein, The processor is also configured to generate an address associated with the command. The first error-correcting code circuit is further configured to generate second parity information by performing error-correcting encoding on the address, and The at least one control signal also includes the address and the second parity information.

16. The storage controller of claim 10, further comprising a second error correction code circuit configured to perform error correction coding and error correction decoding on data included in the data signal.

17. A method of operating a storage device, the method comprising: Receive at least one control signal, including command, address and parity information, from the controller via at least one control signal line; The parity information is used to perform error correction code decoding on the command and the address; A failure flag is set and failure information is generated based on the error correction failure of at least one of the command and the address; In response to a status read command from the controller, a response including the failure information is provided via the at least one control signal line and the failure flag is reset; as well as The controller receives training commands and provides responses via at least one control signal line.

18. The method of claim 17, further comprising ignoring commands other than the status read command when the failure flag is set.

19. The method according to claim 17, wherein, The parity information includes first parity information for the command and second parity information for the address, and The failure information includes information indicating that error correction for a command or address has failed.

20. The method of claim 17, further comprising obtaining the command, the address, and the parity information based on a plurality of headers included in the at least one control signal.

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