Analog method for testing interrupt function, testing method and related device

Abstract

This application discloses a method, testing method, and related apparatus for simulating interrupt functions, relating to the field of software testing. The method includes: initializing an interrupt control thread in a virtual embedded platform used for testing interrupt functions; storing a first mapping relationship and a second mapping relationship in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates interrupt functions at least based on the first and second mapping relationships. This application uses an interrupt control thread that stores the first and second mapping relationships consistent with the target embedded platform, and configures the test execution unit and the execution unit's configuration information to be consistent, as well as the virtual processor core and the processor core's configuration information to be consistent. The virtual embedded platform stores interrupt functions from the target embedded platform, thus eliminating the need for on-board testing. The interrupt functions in the target embedded platform can be simulated using the virtual embedded platform and the interrupt control thread, improving the testing efficiency of interrupt functions.

Description

Technical Field

[0001] This application relates to the field of software testing technology, and in particular to a method for simulating interruption functions, a testing method, and related apparatus. Background Technology

[0002] Interrupt functionality allows the processor to suspend its current task and handle unexpected events occurring in external devices or threads. Once the event is resolved, the suspended task can resume execution. Interrupt functionality ensures system reliability and operating speed. Testing the interrupt functionality verifies its effectiveness.

[0003] In embedded platforms, the aforementioned interrupt functionality is executed by the Generic Interrupt Controller (GIC) within the embedded platform. This necessitates on-board testing within the embedded platform during interrupt functionality testing. On-board testing requires frequent compilation and flashing, resulting in low testing efficiency. Summary of the Invention

[0004] In view of the above problems, this application provides a method for simulating interrupt functions, a testing method, and related apparatus to improve the testing efficiency of interrupt functions. The specific solution is as follows:

[0005] The first aspect of this application provides a method for simulating an interrupt function, comprising:

[0006] An interrupt control thread is initialized in a virtual embedded platform used for testing interrupt functionality. A first mapping relationship and a second mapping relationship are stored in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates interrupt functionality based at least on the first mapping relationship and the second mapping relationship. The first mapping relationship is the mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core controlling the execution unit. The second mapping relationship is the mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform. The configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform. The interrupt function in the target embedded platform is stored in the virtual embedded platform.

[0007] In one possible implementation, the method for simulating the interrupt function further includes:

[0008] A preset interrupt number queue is initialized in the virtual embedded platform. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform, and is used by the interrupt control thread to extract the interrupt numbers.

[0009] A second aspect of this application provides a method for testing interruption functions, including:

[0010] After obtaining the interrupt number sent by the target test execution unit running on the virtual embedded platform, the interrupt control thread of the virtual embedded platform performs an interrupt test based on the interrupt number. The interrupt test includes: the interrupt control thread determining at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calling the virtual processor core to perform interrupt processing based on an interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed using the interrupt function simulation method as described in the first aspect or any implementation of the first aspect.

[0011] In one possible implementation, after obtaining interrupt numbers sent by multiple target test execution units, the interrupt control thread of the virtual embedded platform performs interrupt testing based on the interrupt numbers, including:

[0012] After receiving interrupt numbers from multiple target test execution units, the interrupt control thread of the virtual embedded platform performs the interrupt test sequentially based on each interrupt number in descending order of interrupt number priority.

[0013] In one possible implementation, the invocation of the virtual processor core to perform interrupt handling based on an interrupt function having a second mapping relationship with the interrupt number includes:

[0014] The interrupt control thread controls the virtual processor core to suspend the currently executing task and controls the virtual processor to execute the interrupt function;

[0015] Upon detecting that the virtual processor has completed executing the interrupt function, the interrupt control thread controls the virtual processor core to resume the execution of the suspended currently executing task.

[0016] In one possible implementation, obtaining the interrupt number sent by the target test execution unit running on the virtual embedded platform includes:

[0017] The interrupt control thread polls the preset interrupt number queue, and if it detects that there is at least one newly added interrupt number in the preset interrupt number queue, it extracts the newly added interrupt number. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform, and the target test execution unit is any one of the test execution units.

[0018] A third aspect of this application provides a simulation system for interrupt functionality, comprising:

[0019] A mapping relationship storage unit is used to initialize an interrupt control thread in a virtual embedded platform used for testing interrupt functions, and to store a first mapping relationship and a second mapping relationship in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates interrupt functions based at least on the first mapping relationship and the second mapping relationship. The first mapping relationship is a mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core controlling the execution unit; the second mapping relationship is a mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform; the configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform; and the interrupt functions of the target embedded platform are stored in the virtual embedded platform.

[0020] In one possible implementation, the simulation system for the interrupt function further includes:

[0021] A queue initialization unit is used to initialize a preset interrupt number queue in the virtual embedded platform. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform and to extract the interrupt numbers by the interrupt control thread.

[0022] The fourth aspect of this application provides a test system for interruption functions, comprising:

[0023] An interrupt control thread is configured to perform an interrupt test based on an interrupt number sent by a target test execution unit running on a virtual embedded platform after obtaining the interrupt number. The interrupt test includes: the interrupt control thread determining at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calling the virtual processor core to perform interrupt processing based on an interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed using the interrupt function simulation method as described in the first aspect of this application or any implementation thereof.

[0024] In one possible implementation, the interrupt control thread is configured to perform an interrupt test based on the interrupt number as follows:

[0025] After receiving interrupt numbers from multiple target test execution units, the interrupt control thread of the virtual embedded platform performs the interrupt test sequentially based on each interrupt number in descending order of interrupt number priority.

[0026] In one possible implementation, the interrupt control thread is configured to: When calling the virtual processor core to perform interrupt handling based on an interrupt function that has a second mapping relationship with the interrupt number.

[0027] The interrupt control thread controls the virtual processor core to suspend the currently executing task and controls the virtual processor to execute the interrupt function;

[0028] Upon detecting that the virtual processor has completed executing the interrupt function, the interrupt control thread controls the virtual processor core to resume the execution of the suspended currently executing task.

[0029] In one possible implementation, the interrupt control thread is set to:

[0030] The interrupt control thread polls the preset interrupt number queue, and if it detects that there is at least one newly added interrupt number in the preset interrupt number queue, it extracts the newly added interrupt number. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform, and the target test execution unit is any one of the test execution units.

[0031] A fifth aspect of this application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:

[0032] The memory is used to store computer programs;

[0033] The processor is configured to execute the computer program to enable the electronic device to implement the interrupt function simulation method as described in the first aspect or any implementation thereof, or the interrupt function testing method as described in the second aspect or any implementation thereof.

[0034] The sixth aspect of this application provides a computer storage medium carrying one or more computer programs, which, when executed by an electronic device, enable the electronic device to implement a method for simulating an interrupt function as described in the first aspect or any implementation thereof, or a method for testing an interrupt function as described in the second aspect or any implementation thereof.

[0035] By employing the above technical solution, this application provides a method for simulating, testing, and related apparatus for interrupt functionality. This involves initializing an interrupt control thread in a virtual embedded platform used for testing interrupt functionality, and storing the first mapping relationship between the interrupt numbers of each execution unit in the target embedded platform and the processor cores of the control execution units, as well as the second mapping relationship between each interrupt number in the target embedded platform and its corresponding interrupt function, in the interrupt control thread. This ensures that the virtual embedded platform stores the same first and second mapping relationships as the target embedded platform. Furthermore, since the configuration information of the test execution units in the virtual embedded platform is consistent with that of the execution units in the target embedded platform, the virtual embedded platform... The virtual processor core has the same configuration information as the processor core in the target embedded platform, and the interrupt function in the virtual embedded platform is the same as the interrupt function in the target embedded platform. Therefore, this application utilizes the test execution unit, virtual processor core, interrupt function, first mapping relationship and second mapping relationship in the virtual embedded platform that are consistent with the target embedded platform. Without on-board testing, the above-mentioned test execution unit and virtual processor core can be used to simulate the hardware function of the target embedded platform. Furthermore, the interrupt control thread uses the above-mentioned interrupt function, first mapping relationship and second mapping relationship to simulate the real interrupt function in the target embedded platform in the virtual embedded platform, thereby improving the testing efficiency of interrupt function. Attached Figure Description

[0036] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0037] Figure 1 A flowchart of a method for simulating an interrupt function provided in this application;

[0038] Figure 2 This application provides a schematic diagram of the structure of a virtual embedded platform;

[0039] Figure 3 A flowchart of a test method for interrupt function provided in this application;

[0040] Figure 4 This application provides a flowchart of an interrupt control thread performing interrupt tests sequentially based on each interrupt number;

[0041] Figure 5 A flowchart illustrating a test method for the interrupt function of a virtual embedded platform provided in this application;

[0042] Figure 6 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0043] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0044] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0045] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0046] The first aspect of this application provides a method for simulating interrupt functionality, such as... Figure 1 As shown, the simulation method for this interrupt function includes:

[0047] S101. Initialize the interrupt control thread in the virtual embedded platform used for testing interrupt functions, and store the first mapping relationship and the second mapping relationship in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates the interrupt function at least based on the first mapping relationship and the second mapping relationship. The first mapping relationship is the mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core of the control execution unit. The second mapping relationship is the mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform. The configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform. The interrupt function in the target embedded platform is stored in the virtual embedded platform.

[0048] It should be noted that, in practical application scenarios, the aforementioned target embedded platform can be a computing system integrating hardware and software. Examples include Electronic Control Units (ECUs) and Transmission Control Units (TCUs) in the automotive field, and Programmable Logic Controllers (PLCs) in the industrial automation field.

[0049] It should be noted that in practical application scenarios, the aforementioned virtual embedded platform can be a virtual platform deployed on a server or personal computer to simulate the real architecture and functions of the target embedded platform, such as Linux or Windows.

[0050] It should be noted that in practical application scenarios, the interrupt control thread is built in a virtual embedded platform and is used to perform the same function as the interrupt control unit in the target embedded platform.

[0051] It should be noted that, in practical application scenarios, the execution unit in the aforementioned target embedded platform can be an external device within the target embedded platform.

[0052] It should be noted that in practical applications, the aforementioned Interrupt Request (IRQ) is an identifier used to uniquely identify the execution unit that initiated the interrupt request. For the execution unit in the target embedded platform, if the execution unit is an external device (such as a control chip or in-vehicle device in the automotive field), its interrupt number is set at the factory. Therefore, when the execution unit is an external device, its interrupt number can be directly sent to the interrupt control unit via a signal line.

[0053] It should be noted that, in practical application scenarios, the execution unit in the aforementioned target embedded platform can also be the program code within the target embedded platform. Since the program code is written manually by developers, in order to trigger the interrupt, the developers will set up API interface calling logic for the program code during the development process, and set the interrupt request ID corresponding to that API interface as the interrupt number of the program code.

[0054] It should be noted that in practical applications, the processor core mentioned above is the computing engine (kernel) in a multi-core processor, which is used to execute arithmetic, logical, or control operations to be performed by the assigned execution unit.

[0055] It should be noted that, in practical application scenarios, the aforementioned interrupt service routine (ISR) is a special function used to respond to external interrupt events (triggered by hardware interrupts or program interrupts) and to process external interrupt events.

[0056] It should be noted that, in practical application scenarios, the test execution unit and virtual processor core in the aforementioned virtual embedded platform can be threads built within the virtual embedded platform. By configuring the attribute configuration information of the test execution unit and the execution unit to be consistent, and configuring the configuration information of the virtual processor core in the virtual embedded platform to be consistent with the processor core in the target embedded platform, it is possible to simulate the function of the control unit using the test execution unit and the function of the processor core using the virtual processor core in the virtual embedded platform without configuring the actual control unit and processor core in the target embedded platform.

[0057] It should be noted that in practical application scenarios, the interrupt functions in the aforementioned virtual embedded platform, as well as the first and second mapping relationships, can be obtained by parsing the project files imported into the target embedded platform. Since existing interrupt control units implement interrupt functionality based on the mapping relationship between interrupt numbers and interrupt functions, this application ensures that the interrupt control thread can realistically simulate the interrupt function of the interrupt control unit in the target embedded platform by storing the first and second mapping relationships in the interrupt control thread of the virtual embedded platform and configuring the virtual processor core in the virtual embedded platform to be consistent with the configuration information of the processor core in the target embedded platform.

[0058] It should be noted that, in practical application scenarios, this application ensures architectural consistency between the virtual embedded platform and the target embedded platform by configuring the test execution unit in the virtual embedded platform to have the same configuration information as the execution unit in the target embedded platform, the virtual processor core in the virtual embedded platform to have the same configuration information as the processor core in the target embedded platform, and the interrupt function in the virtual embedded platform to have the same interrupt function in the target embedded platform. Subsequently, by configuring the interrupt control thread of the virtual embedded platform to store the aforementioned first and second mapping relationships, when the virtual embedded platform tests the interrupt function, the interrupt control thread can locate the processor core of the control execution unit based on the interrupt number sent by the execution unit, and determine the interrupt function based on the second mapping relationship, thereby controlling the processor to perform interrupt function testing based on the interrupt function.

[0059] This application initializes an interrupt control thread in a virtual embedded platform used for testing interrupt functions, and stores the first mapping relationship between the interrupt numbers of each execution unit in the target embedded platform and the processor core of the control execution unit, as well as the second mapping relationship between each interrupt number in the target embedded platform and its corresponding interrupt function, in the interrupt control thread. This ensures that the virtual embedded platform stores the same first and second mapping relationships as the target embedded platform. Since the configuration information of the test execution units in the virtual embedded platform is consistent with that of the execution units in the target embedded platform, the configuration information of the virtual processor cores in the virtual embedded platform is consistent with that of the processor cores in the target embedded platform, and the interrupt functions in the virtual embedded platform are consistent with those in the target embedded platform, this application utilizes the test execution units, virtual processor cores, interrupt functions, first mapping relationships, and second mapping relationships in the virtual embedded platform that are consistent with those in the target embedded platform. Without requiring on-board testing, the hardware functions of the target embedded platform can be simulated using the aforementioned test execution units and virtual processor cores. Furthermore, the interrupt control thread simulates the real interrupt functions of the target embedded platform in the virtual embedded platform based on the aforementioned interrupt functions, first mapping relationships, and second mapping relationships, thereby improving the testing efficiency of interrupt functions.

[0060] In one possible implementation, the method for simulating the interrupt function provided in the first aspect of this application further includes:

[0061] A preset interrupt number queue is initialized in the virtual embedded platform. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform and is used by the interrupt control thread to extract the interrupt numbers.

[0062] It should be noted that in practical application scenarios, the execution units in the target embedded platform can be external devices or program code within the target embedded platform. For external devices, since the purpose of hardware interrupt triggering is to inform the processor core controlling the hardware to respond quickly—for example, when a button on the console is pressed, the processor core needs to quickly respond to the corresponding function—the interrupt number sent by the external device is usually sent directly to the interrupt controller, which then controls the corresponding processor core to execute the interrupt function corresponding to the interrupt number, ensuring the response speed of the target embedded system. For program code, since program interrupt triggering involves complex logical execution sequences and system call sequences, this application initializes a preset interrupt number queue in the virtual embedded platform and uses this queue to store the interrupt numbers sent by each test execution unit in the virtual embedded platform. This fulfills the interrupt triggering requirements for both types of test execution units, improving the universality of the interrupt function simulation method provided in this application.

[0063] To facilitate understanding of the method for simulating an interrupt function provided by the first aspect and any implementation thereof of this application, a possible implementation of this application is described hereby:

[0064] like Figure 2 The diagram illustrates the structure of a virtual embedded platform obtained after processing using a simulation method for interrupt functionality provided by the first aspect and any implementation thereof of this application. The virtual embedded platform includes Test Execution Unit A, Test Execution Unit B, Test Execution Unit C, an interrupt control thread, and multiple virtual processor cores. Test Execution Unit A is a Universal Asynchronous Receiver / Transmitter Thread (UART Thread) used to simulate external devices in the target embedded platform. Test Execution Unit B is a Controller Area Network Thread (CAN Thread) used to simulate the communication thread executing CAN bus communication tasks in the target embedded platform. Test Execution Unit C is a thread used to simulate user soft interrupts in the target embedded platform. The aforementioned interrupt control thread is configured with a preset interrupt number queue, interrupt number mapping processing functions that can call first and second mapping relationships, and an affinity processing unit. The preset interrupt number queue receives interrupt numbers sent by test execution units A, B, and C. The interrupt number mapping processing function determines the virtual processor cores with the first mapping relationship to the interrupt number and the interrupt functions with the second mapping relationship. The affinity processing unit is a virtual unit that determines the runtime requirements of the virtual processor cores and interrupt functions based on the interrupt number mapping processing function and selects the interrupt mode. The interrupt mode includes: when there are many virtual processor cores with the first mapping relationship to an interrupt number and / or the runtime requirements of the interrupt functions are high, a global interrupt mode is executed, suspending the current task executed by all virtual processor cores; when there are few virtual processor cores with the first mapping relationship to an interrupt number and / or the runtime requirements of the interrupt functions are low, a local core interrupt mode is executed, suspending the current task executed by the virtual processor core with the first mapping relationship to that interrupt number. Given a virtual processor core, interrupt function, and interrupt mode, the interrupt control thread is used to control the determined virtual processor core to suspend the execution of the current task and execute the interrupt function (Handler) that has a second mapping relationship with the interrupt number.

[0065] In one possible implementation, the preset interrupt number queue, the interrupt number mapping processing function that can call the first mapping relationship and the second mapping relationship configured in the interrupt control thread are only for the sake of description. In actual application scenarios, the preset interrupt number queue, the interrupt number mapping processing function that can call the first mapping relationship and the second mapping relationship and the affinity processing unit can all be implemented by editing the program code of the interrupt control thread.

[0066] The second aspect of this application provides a method for testing interruption functions, such as... Figure 3 As shown, the test method for this interrupt function includes:

[0067] S301. After obtaining the interrupt number sent by the target test execution unit running on the virtual embedded platform, the interrupt control thread of the virtual embedded platform performs an interrupt test based on the interrupt number. The interrupt test includes: the interrupt control thread determines at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calls the virtual processor core to perform interrupt processing based on the interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed by the interrupt function simulation method as described in the first aspect of this application or any implementation of the first aspect.

[0068] It should be noted that, in practical application scenarios, this application configures the interrupt control thread in the virtual embedded platform processed by the interrupt function simulation method as described in the first aspect or any implementation thereof. After obtaining the interrupt number sent by the target test execution unit running on it, the interrupt test is performed based on the interrupt number. Compared with the prior art, this application avoids frequent compilation and flashing by eliminating the need for on-board testing, thus improving the testing efficiency of the interrupt function. Furthermore, since the first and second mapping relationships stored in the interrupt control thread of the virtual embedded platform processed by the interrupt function simulation method as described in the first aspect or any implementation thereof are consistent with those in the target embedded system, the interrupt control thread is configured to determine at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calls the virtual processor core to perform interrupt processing based on the interrupt function that has a second mapping relationship with the interrupt number, thereby improving the testing accuracy of the interrupt function.

[0069] In one possible implementation, after obtaining interrupt numbers sent by multiple target test execution units, the interrupt control thread of the virtual embedded platform performs interrupt testing based on the interrupt numbers, including:

[0070] After receiving interrupt numbers from multiple target test execution units, the interrupt control thread of the virtual embedded platform performs interrupt tests sequentially based on each interrupt number, in descending order of interrupt number priority.

[0071] It should be noted that in real-world applications, there may be situations where multiple interrupt numbers sent by target test execution units are obtained within a short period. The resources required by the interrupt functions corresponding to different interrupt numbers, as well as the number of virtual machine cores corresponding to each interrupt number, vary significantly. If interrupt tests are performed on all interrupt numbers simultaneously, there is a risk of data corruption, excessive processor usage, and virtual embedded platform crashes. Therefore, this application configures the interrupt control thread of the virtual embedded platform to perform interrupt tests sequentially based on the interrupt number priority from high to low after obtaining multiple interrupt numbers sent by target test execution units. This avoids the aforementioned risks and improves the operational stability and reliability of the virtual embedded platform's interrupt testing.

[0072] In one possible implementation, the virtual processor core is invoked to perform interrupt handling based on an interrupt function that has a second mapping relationship with the interrupt number, including:

[0073] The interrupt control thread controls the virtual processor core to suspend the currently executing task and controls the virtual processor to execute interrupt functions;

[0074] Upon detecting that the virtual processor has completed executing the interrupt function, the interrupt control thread controls the virtual processor core to resume the currently suspended task.

[0075] It should be noted that in practical applications, after obtaining interrupt numbers sent by multiple target test execution units, there are several ways to perform interrupt tests sequentially based on each interrupt number. Here, one example is provided:

[0076] like Figure 4 The diagram shows a flowchart of an interrupt control thread performing interrupt tests sequentially based on each interrupt number. The specific operation steps are as follows:

[0077] Step S401: Obtain the interrupt numbers sent by multiple target test execution units. This triggers step S402.

[0078] Step S402: Determine if there is at least one interrupt number among the obtained interrupt numbers that has not undergone interrupt testing. If yes, then trigger step S403; otherwise, trigger step S408.

[0079] Step S403: Determine the interrupt number with the highest priority among at least one interrupt number as the current interrupt number. Then trigger step S404.

[0080] Step S404: Determine at least one virtual processor core with a first mapping relationship to the current interrupt number, and determine the interrupt function with a second mapping relationship to the current interrupt number. Then trigger step S405.

[0081] Step S405: Control the virtual processor core determined in step S404 to suspend the currently executing task, and control the virtual processor core to execute the interrupt function determined in step S404. Then trigger step S406.

[0082] Step S406: Determine whether the virtual processor core has finished executing the interrupt function. If yes, trigger step S407; otherwise, trigger step S406.

[0083] Step S407: Control the virtual processor core to resume the currently executed task that was suspended, and add an identifier indicating that an interrupt test has been performed to the current interrupt number. Then trigger step S402.

[0084] Step S408, end the process.

[0085] In one possible implementation, the interrupt number sent by the target test execution unit running on the virtual embedded platform is obtained, including:

[0086] The interrupt control thread polls the preset interrupt number queue and extracts the newly added interrupt number if it detects that there is at least one new interrupt number in the preset interrupt number queue. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform. The target test execution unit is any one of the test execution units.

[0087] In one possible implementation, the interrupt control thread can poll the preset interrupt number queue by configuring a timed polling statement in the interrupt control thread's program code.

[0088] In another possible implementation, the interrupt control thread can also be configured to use the test execution unit of program code type to call the interrupt request interface as a trigger condition to trigger the interrupt control thread to query the preset interrupt number queue.

[0089] To facilitate understanding of the interrupt function testing method provided in the second aspect of this application, a possible implementation of this application is described below:

[0090] like Figure 5 The diagram shown is a flowchart illustrating a test method for running interrupt functions on a virtual embedded platform after processing according to the first aspect of this application and any possible implementation thereof.

[0091] Assume that the current virtual embedded platform is configured with a first test execution unit, a second test execution unit, a preset interrupt number queue, and an interrupt control thread.

[0092] The first test execution unit responds to the user-defined simulated interrupt by calling a preset API interface to add interrupt number 1 to the preset interrupt number queue. The second test execution unit responds to the user-defined simulated interrupt by calling a preset API interface to add interrupt number 2 to the preset interrupt number queue.

[0093] The interrupt control thread is awakened by the API call signal and checks if there is a newly added interrupt number in the preset interrupt number queue. If not, it resumes sleep mode; if so, it performs interrupt tests on each newly added interrupt number in descending order of priority.

[0094] A third aspect of this application provides a simulation system for interrupt functionality, comprising:

[0095] The mapping relationship storage unit is used to initialize the interrupt control thread in the virtual embedded platform used for testing interrupt functions, and to store the first mapping relationship and the second mapping relationship in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates the interrupt function based at least on the first mapping relationship and the second mapping relationship. The first mapping relationship is the mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core of the control execution unit, and the second mapping relationship is the mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform, the configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform, and the interrupt function in the target embedded platform is stored in the virtual embedded platform.

[0096] In one possible implementation, the simulation system for the interrupt function provided in the third aspect of this application further includes:

[0097] The queue initialization unit is used to initialize a preset interrupt number queue in the virtual embedded platform. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform.

[0098] The fourth aspect of this application provides a test system for interruption functions, comprising:

[0099] An interrupt control thread is used to perform interrupt testing based on the interrupt number sent by the target test execution unit running on the virtual embedded platform after obtaining the interrupt number. The interrupt testing includes: the interrupt control thread determining at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calling the virtual processor core to perform interrupt processing based on the interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed by the interrupt function simulation method as described in the first aspect of this application or any implementation of the first aspect.

[0100] In one possible implementation, the interrupt control thread is configured to perform interrupt testing based on the interrupt number as follows:

[0101] After receiving interrupt numbers from multiple target test execution units, the interrupt control thread of the virtual embedded platform performs interrupt tests sequentially based on each interrupt number, in descending order of interrupt number priority.

[0102] In one possible implementation, the interrupt control thread is configured to: When calling the interrupt function of the virtual processor core to perform interrupt handling based on a second mapping with the interrupt number.

[0103] The interrupt control thread controls the virtual processor core to suspend the currently executing task and controls the virtual processor to execute interrupt functions;

[0104] Upon detecting that the virtual processor has completed executing the interrupt function, the interrupt control thread controls the virtual processor core to resume the currently suspended task.

[0105] In one possible implementation, the interrupt control thread is set to:

[0106] The interrupt control thread polls the preset interrupt number queue and extracts the newly added interrupt number if it detects that there is at least one new interrupt number in the preset interrupt number queue. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform. The target test execution unit is any one of the test execution units.

[0107] A fifth aspect of this application provides an electronic device, including at least one processor and a memory connected to the processor, wherein:

[0108] Memory is used to store computer programs;

[0109] The processor is used to execute a computer program to enable an electronic device to implement a simulation method for interrupt functionality as described in the first aspect or any implementation thereof, or a test method for interrupt functionality as described in the second aspect or any implementation thereof.

[0110] The sixth aspect of this application provides a computer storage medium carrying one or more computer programs, which, when executed by an electronic device, enable the electronic device to implement a simulation method for interruption functions as described in the first aspect or any implementation thereof, or a test method for interruption functions as described in the second aspect or any implementation thereof.

[0111] A schematic diagram of the structure of an electronic device is provided in the fifth aspect of this application, as shown below. Figure 6 As shown. The electronic devices in the embodiments of this application may include, but are not limited to, fixed terminals such as laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. Figure 6 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0112] like Figure 6 As shown, the electronic device may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. When the electronic device is powered on, the RAM 603 also stores various programs and data required for the operation of the electronic device. The processing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0113] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 including, for example, memory cards, hard drives, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have instead.

[0114] This application also provides a method for simulating an interrupt function as described in the first aspect or any implementation thereof, or a method for testing an interrupt function as described in the second aspect or any implementation thereof, when the computer-readable instructions are executed on an electronic device.

[0115] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0116] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0117] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0118] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method for simulating an interrupt function, characterized in that, include: An interrupt control thread is initialized in a virtual embedded platform used for testing interrupt functionality. A first mapping relationship and a second mapping relationship are stored in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates interrupt functionality based at least on the first mapping relationship and the second mapping relationship. The first mapping relationship is the mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core controlling the execution unit. The second mapping relationship is the mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform. The configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform. The interrupt function in the target embedded platform is stored in the virtual embedded platform.

2. The method for simulating interruption function according to claim 1, characterized in that, The method for simulating the interruption function also includes: A preset interrupt number queue is initialized in the virtual embedded platform. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform, and is used by the interrupt control thread to extract the interrupt numbers.

3. A method for testing interruption functionality, characterized in that, include: After obtaining the interrupt number sent by the target test execution unit running on the virtual embedded platform, the interrupt control thread of the virtual embedded platform performs an interrupt test based on the interrupt number. The interrupt test includes: the interrupt control thread determining at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calling the virtual processor core to perform interrupt processing based on the interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed using the interrupt function simulation method as described in claim 1 or 2.

4. The test method for interruption function according to claim 3, characterized in that, After receiving interrupt numbers sent by multiple target test execution units, the interrupt control thread of the virtual embedded platform performs interrupt testing based on the interrupt numbers, including: After receiving interrupt numbers from multiple target test execution units, the interrupt control thread of the virtual embedded platform performs the interrupt test sequentially based on each interrupt number in descending order of interrupt number priority.

5. The test method for the interruption function according to any one of claims 3 or 4, characterized in that, The invocation of the virtual processor core to perform interrupt handling based on the interrupt function having a second mapping relationship with the interrupt number includes: The interrupt control thread controls the virtual processor core to suspend the currently executing task and controls the virtual processor to execute the interrupt function; Upon detecting that the virtual processor has completed executing the interrupt function, the interrupt control thread controls the virtual processor core to resume the execution of the suspended currently executing task.

6. The test method for interruption function according to any one of claims 3-5, characterized in that, The step of obtaining the interrupt number sent by the target test execution unit running on the virtual embedded platform includes: The interrupt control thread polls the preset interrupt number queue, and if it detects that there is at least one newly added interrupt number in the preset interrupt number queue, it extracts the newly added interrupt number. The preset interrupt number queue is used to store the interrupt numbers sent by each test execution unit in the virtual embedded platform, and the target test execution unit is any one of the test execution units.

7. A simulation system for interrupt functionality, characterized in that, include: A mapping relationship storage unit is used to initialize an interrupt control thread in a virtual embedded platform used for testing interrupt functions, and to store a first mapping relationship and a second mapping relationship in the interrupt control thread of the virtual embedded platform, so that the interrupt control thread simulates interrupt functions based at least on the first mapping relationship and the second mapping relationship. The first mapping relationship is a mapping relationship between the interrupt number of each execution unit in the target embedded platform and the processor core controlling the execution unit; the second mapping relationship is a mapping relationship between each interrupt number in the target embedded platform and the interrupt function. The configuration information of the test execution unit in the virtual embedded platform is consistent with that of the execution unit in the target embedded platform; the configuration information of the virtual processor core in the virtual embedded platform is consistent with that of the processor core in the target embedded platform; and the interrupt functions of the target embedded platform are stored in the virtual embedded platform.

8. A test system for interrupt functionality, characterized in that, include: An interrupt control thread is configured to perform an interrupt test based on an interrupt number sent by a target test execution unit running on a virtual embedded platform after obtaining the interrupt number. The interrupt test includes: the interrupt control thread determining at least one virtual processor core in the virtual embedded platform that has a first mapping relationship with the interrupt number, and calling the virtual processor core to perform interrupt processing based on an interrupt function that has a second mapping relationship with the interrupt number. The virtual embedded platform is a virtual embedded platform processed using the interrupt function simulation method as described in claim 1 or 2.

9. An electronic device, characterized in that, It includes at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program to enable the electronic device to implement the interrupt function simulation method as described in any one of claims 1 to 2, or the interrupt function test method as described in any one of claims 3 to 6.

10. A computer storage medium, characterized in that, The storage medium carries one or more computer programs that, when executed by an electronic device, enable the electronic device to implement the interrupt function simulation method as described in any one of claims 1 to 2, or the interrupt function testing method as described in any one of claims 3 to 6.

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