Memory attribute management method and device, and chip

Abstract

This application relates to the semiconductor field, providing a memory attribute management method, apparatus, and chip, including: acquiring a memory access request initiated by a processor; determining a target chip node identifier based on a first address segment in the physical address, and determining an on-chip offset address within the target chip node based on a second address segment in the physical address; performing mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules to determine the memory attribute corresponding to the memory access request; generating access control information corresponding to the memory access request based on the memory attribute; and routing the memory access request carrying access control information based on the target chip node identifier to access target hardware resources in the target chip node. This improves the configuration efficiency, access consistency, and address space utilization of memory attribute management in multi-die or multi-chip systems.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically to a memory attribute management method, apparatus, and chip. Background Technology

[0002] With the increasing computing power demands and integration scale of processor systems, the Reduced Instruction Set Computer Five (RISC-V) architecture can be applied to scenarios such as chiplet multi-die systems and multi-chip systems. In these system scenarios, different physical address regions may correspond to different hardware resources such as memory resources, peripheral registers, and memory-mapped input / output (MMIO) spaces. The processor typically needs to determine the corresponding access method based on physical memory attributes (PMA).

[0003] In existing technologies, PMA (Physical Address Management) is typically configured according to physical address ranges. If the system contains multiple dies or chips, the relevant resources in different dies or chips need to be configured with corresponding memory attributes, resulting in high difficulty in attribute configuration, high maintenance complexity, and low system configuration efficiency. Furthermore, during cross-die or cross-chip access, different modules may handle access attributes inconsistently, easily increasing the risk of access anomalies. Even worse, some address planning methods may generate unused address ranges, significantly reducing address space utilization. Therefore, improving the configuration efficiency, access consistency, and address space utilization of memory attribute management in multi-die or multi-chip systems has become an urgent technical problem to be solved. Summary of the Invention

[0004] This application provides a memory attribute management method, device, and chip. It can determine memory attributes by dividing the physical address into chip node identifiers and on-chip offset addresses, and by combining the mask matching of chip node identifiers with the interval matching of on-chip offset addresses. This allows resources with the same offset in different chip nodes to share memory attribute rules, thereby solving the technical problems of high memory attribute configuration complexity, inconsistent handling of cross-die or cross-chip access attributes, and low address space utilization in the prior art.

[0005] In a first aspect, embodiments of this application provide a memory attribute management method, which is applied to a system including multiple chip nodes, wherein the chip nodes include dies or chips, and the method includes: Obtain a memory access request initiated by the processor, the memory access request including the physical address to be accessed; The target chip node identifier is determined based on the first address segment in the physical address, and the on-chip offset address within the target chip node is determined based on the second address segment in the physical address. The target chip node identifier is used to identify the target chip node, and at least some hardware resources of multiple chip nodes are set based on the same on-chip offset address. According to the preset memory attribute rules, the target chip node identifier is masked and the on-chip offset address is range matched to determine the memory attribute corresponding to the memory access request. The memory attribute rules are used to make hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attribute. Based on the memory attributes, access control information corresponding to the memory access request is generated. The access control information is used to instruct the processor to execute the memory access request according to the access method corresponding to the memory attributes. Based on the target chip node identifier, memory access requests carrying the access control information are routed to access the target hardware resources in the target chip node.

[0006] Secondly, embodiments of this application provide a memory attribute management device, which has the function of implementing the memory attribute management method corresponding to the first aspect described above. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above function, and the modules can be software and / or hardware.

[0007] In one embodiment, the memory attribute management device is applied to a system including multiple chip nodes, wherein the chip nodes include dies or chips, and the memory attribute management device includes: The acquisition unit is configured to acquire a memory access request initiated by the processor, the memory access request including a physical address to be accessed; The determining unit is configured to determine a target chip node identifier based on a first address segment in the physical address, and to determine an on-chip offset address within the target chip node based on a second address segment in the physical address, wherein the target chip node identifier is used to identify the target chip node, and at least some hardware resources of a plurality of chip nodes are set based on the same on-chip offset address; The matching unit is configured to perform mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules, and determine the memory attribute corresponding to the memory access request. The memory attribute rules are used to make hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attribute. The generation unit is configured to generate access control information corresponding to the memory access request based on the memory attributes, wherein the access control information is used to instruct the processor to execute the memory access request according to the access method corresponding to the memory attributes; The routing unit is configured to route memory access requests carrying the access control information based on the target chip node identifier, so as to access the target hardware resources in the target chip node.

[0008] Thirdly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the memory attribute management method as described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the memory attribute management method described in the first aspect.

[0010] Fifthly, embodiments of this application provide a chip including a processor coupled to a transceiver for executing the technical solution provided in the first aspect of this application. In one possible design, the chip can also be a dedicated hardware structure for implementing the technical solution provided in the first aspect above; for example, processing involving neural network models can be implemented by a dedicated neural network processor or a graphics processor.

[0011] In a sixth aspect, embodiments of this application provide a computer program product containing instructions that, when the computer program product is run on a computer, cause the computer to execute the memory attribute management method provided in the first aspect.

[0012] Compared to existing technologies, in this embodiment, after the processor initiates a memory access request, it can first parse a first address segment to identify the target chip node and a second address segment to represent the on-chip offset address from the physical address to be accessed. Since at least some hardware resources in multiple chip nodes are set based on the same on-chip offset address, hardware resources with the same on-chip offset address range in different chip nodes can share the corresponding memory attribute rules. When determining the memory attribute, on the one hand, the target chip node identifier is masked, and on the other hand, the on-chip offset address is range matched, and the memory attribute corresponding to the memory access request is determined based on the matching result of the two. In this way, it is not necessary to configure memory attribute rules separately for the same type of resources in each die or chip, which can reduce redundant configuration, reduce the complexity of attribute configuration and maintenance, and thus improve the efficiency of memory attribute management in multi-die or multi-chip systems. At the same time, after determining the memory attribute, this embodiment generates access control information corresponding to the memory access request according to the memory attribute, so that the processor can perform access according to the access attribute corresponding to the target hardware resource. Subsequently, the memory access request carrying the access control information is routed based on the target chip node identifier to access the target hardware resource in the target chip node. Therefore, the determination of memory attributes and the generation of access control information can be coordinated with chip node routing, making access attributes more consistent during cross-die or cross-chip access processes, and reducing the risk of access anomalies caused by inconsistent handling of access attributes by different modules. Furthermore, since the physical address locates the target hardware resource through the chip node identifier and the on-chip offset address, different chip nodes can reuse the same on-chip offset address and corresponding memory attribute rules, thereby reducing the need to reserve a large number of independent address ranges for different system configurations. This is beneficial for improving address space utilization and facilitates the reuse of address layout and memory attribute configuration between single-die, multi-die, and multi-chip systems. Overall, the embodiments of this application can improve the configuration efficiency, access consistency, and address space utilization of memory attribute management in multi-die or multi-chip systems. Attached Figure Description

[0013] Figure 1 This is a flowchart illustrating the memory attribute management method in an embodiment of this application; Figure 2 This is a schematic diagram of the address space layout within a chip node according to an embodiment of this application; Figure 3 This is a schematic diagram of the global physical address bit field structure according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the memory attribute generation logic for high-bit mask matching and low-bit interval matching in an embodiment of this application. Figure 5 This is a schematic diagram of the memory attribute management device according to an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," etc., are used only to distinguish the objects described and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, apparatus, product, or device that comprises a list of elements may include not only the elements expressly listed but also other elements not expressly listed, or elements inherent to the process, method, apparatus, product, or device.

[0016] To address the problems of high complexity in configuring physical memory attributes, inconsistent access attribute processing during cross-die or cross-chip access in existing multi-die or multi-chip systems, and low address space utilization due to certain address planning methods, this application provides a memory attribute management scheme in some embodiments. This scheme locates target hardware resources by using the chip node identifier and on-chip offset address in the physical address, and determines memory attributes by combining mask matching of the chip node identifier and address range matching of the on-chip offset address. This allows hardware resources with the same on-chip offset address range in different chip nodes to share the corresponding memory attribute rules. The technical solutions provided in the embodiments of this application are illustrated below with reference to the accompanying drawings.

[0017] The memory attribute management method provided in this application can be applied to a system including multiple chip nodes. This system can be RISC-V. A chip node can include a die or a chip. For example, in a Chiplet multi-die system, one chip node can correspond to one die. In a multi-chip system, one chip node can correspond to one chip. Multiple chip nodes can be connected through die-to-die interconnects, chip-to-chip interconnects, or other interconnect structures. For ease of description, the term "chip node" is used as a unified concept in the following description, applicable to both scenarios where the chip node is a die and scenarios where the chip node is a chip.

[0018] In some embodiments, multiple chip nodes can be multiple homogeneous dies or multiple homogeneous chips. Multiple chip nodes can be located within the same package structure or in a system formed by board-level interconnects, package-level interconnects, or chip-to-chip interconnects. This application does not limit the physical package form of the multiple chip nodes; as long as the multiple chip nodes can be distinguished based on the chip node identifier in the address and the target hardware resources within the chip nodes can be located based on the on-chip offset address, the memory attribute management scheme provided in this application can be applied.

[0019] In some embodiments, the system may include a processor, a memory attribute management module, an on-chip interconnect bus, and an inter-chip node interconnect interface. The processor can be used to initiate memory access requests. The memory attribute management module can be used to determine memory attributes based on the physical address in the memory access request and generate access control information. The on-chip interconnect bus can be used to determine whether the memory access request corresponds to a local chip node or a remote chip node based on the target chip node identifier. The inter-chip node interconnect interface can be used to forward the memory access request to the target chip node in the case of remote chip node access. The aforementioned memory attribute management module can be integrated on the processor side or implemented as part of the physical memory attribute matching logic in the processor; this application embodiment does not limit this.

[0020] In some embodiments, multiple chip nodes may employ the same or substantially the same on-chip address layout and mapping rules. At least some hardware resources in different chip nodes may be configured based on the same on-chip offset address. For example, storage resources, peripheral registers, memory-mapped input / output spaces, etc., in different chip nodes may have the same or corresponding on-chip offset address ranges. In this way, a target chip node can be identified by a portion of the physical address range, and the on-chip offset address within the target chip node can be represented by another portion of the address range, thereby locating the target hardware resource in a system comprising multiple chip nodes.

[0021] In this context, on-chip address layout can be understood as the arrangement of various hardware resources within a chip node in the on-chip address space. Mapping rules can be understood as the correspondence between on-chip offset addresses and hardware resources within a chip node. In the embodiments of this application, different chip nodes adopt the same or substantially the same on-chip address layout and mapping rules, which allows the same on-chip offset address range to correspond to the same source hardware resources in different chip nodes. For example, on-chip dynamic random access memory, on-chip storage resources, peripheral registers, or memory-mapped input / output spaces in different chip nodes can be mapped to the same or corresponding on-chip offset address ranges. Based on this homogeneous address space, memory attribute rules do not need to be repeatedly configured for each chip node, but can be uniformly managed for the same source hardware resources in different chip nodes based on the on-chip offset address range.

[0022] It should be noted that the physical memory attributes in this application embodiment may include, but are not limited to, cacheable attributes, non-cacheable ordinary memory attributes, device attributes, etc. Different physical memory attributes can be used to instruct the processor to adopt different access methods, such as whether cached access is allowed, whether access reordering is allowed, and whether speculative access is allowed. The specific attribute types and access control methods can be configured according to the processor architecture, bus protocol, and system design requirements, and this application embodiment does not limit them.

[0023] For example, the cacheable attribute can indicate that a corresponding address region can be cached and accessed in the same way as normal memory. The non-cacheable normal memory attribute can indicate that a corresponding address region is not cached but is still considered normal memory, allowing speculative fetching or access reordering. The device attribute can indicate that a corresponding address region belongs to a device type access region, typically used for peripheral registers or memory-mapped input / output spaces, and can be used to disable cached access, access reordering, and / or speculative access. By distinguishing these different physical memory attributes, the processor can execute the corresponding access according to the actual access requirements of the target hardware resource when initiating an access, reducing the risk of inconsistencies between access attributes and hardware resource requirements.

[0024] Reference Figure 1 , Figure 1 This is a flowchart illustrating a memory attribute management method provided in an embodiment of this application. The method can be executed by a memory attribute management device. The method is applied to a system comprising multiple chip nodes, wherein the chip nodes include dies or chips. (Reference) Figure 1 As shown, the method includes steps 101-105: First, it should be noted that memory attribute management devices can be implemented through hardware logic or through a combination of hardware and software. For example, a memory attribute management device may include address resolution logic, a memory attribute rule table, mask matching logic, address range matching logic, and access control information generation logic. The address resolution logic can be used to parse the target chip node identifier and on-chip offset address from the physical address. The memory attribute rule table can be used to store preset memory attribute rules. The mask matching logic can be used to perform mask matching on the target chip node identifier. The address range matching logic can be used to perform address range matching on the on-chip offset address. The access control information generation logic can be used to generate access control information based on the determined memory attributes.

[0025] Step 101: Obtain the memory access request initiated by the processor.

[0026] The memory access request includes the physical address to be accessed. Specifically, the memory access request can be an access request initiated by the processor when executing instruction fetching, reading / writing memory, accessing peripheral registers, or accessing memory-mapped input / output space. The physical address can be the target access address generated when the processor initiates the access. This physical address can be used to locate the target hardware resource in a system including multiple chip nodes. The multiple chip nodes can be multiple homogeneous dies or multiple homogeneous chips. Accordingly, the physical address can include a high-order identifier segment for identifying the target chip node and a low-order on-chip offset segment for identifying the internal access location of the target chip node. The target hardware resource can be located in the local chip node initiating the access or in a remote chip node.

[0027] Physical addresses can be formed by concatenating a high-order identifier segment and a low-order on-chip offset segment. For example, when the processor supports 44-bit effective physical addresses, the physical address can be divided into a high-order die identifier or chip identifier (Die / Chip Identifier, Die / Chip-ID) segment and an on-chip offset segment. The high-order Die / Chip-ID segment distinguishes different dies or chips in the system, while the on-chip offset segment indicates the homogeneous address space location within each die or chip. Since multiple dies or chips can use a consistent on-chip address layout, the same on-chip offset can correspond to the same hardware module in different dies or chips, distinguished only by the value of the high-order Die / Chip-ID. For example, when the on-chip offset falls into the on-chip DDR region, DDRs in different dies can be distinguished by different high-order Die-IDs. When the on-chip offset falls into the on-chip peripheral register region, peripheral registers with the same name in different dies can also be distinguished by different high-order Die-IDs.

[0028] In some embodiments, the processor may generate memory access requests during the pipelined access phase, address generation phase, instruction fetch phase, or memory access phase. Memory access requests may carry access type information, such as read requests, write requests, instruction fetch requests, or atomic access requests. Different access types, combined with memory attributes, can jointly determine the subsequent access method adopted by the processor. For example, for access requests related to device attributes, speculative access may be prohibited. For access requests related to cacheable attributes, cached access may be allowed.

[0029] In some embodiments, memory access requests can be cross-chip node access requests. For example, when a local die of the processor initiates an access to the DDR region of a remote die, the high-order Die-ID in the physical address can point to the remote die, and the low-order on-chip offset can point to the DDR region within that remote die. The processor can determine the cacheable attribute corresponding to the access request at the source of the access based on this physical address and generate corresponding bus transaction attribute information. As another example, when a local die of the processor initiates an access to the peripheral register region of a remote die, the high-order Die-ID in the physical address can point to the remote die, and the low-order on-chip offset can point to the peripheral register region within that remote die. The processor can determine the device attribute corresponding to the access request at the source of the access based on this physical address and prohibit speculative access, out-of-order access, and cached access before the request enters the on-chip interconnect bus or inter-chip interconnect path.

[0030] Based on this approach, the physical address to be accessed is obtained when the processor initiates the access. This helps to complete the memory attribute judgment before the access request enters the downstream interconnect path, avoiding the need for a second correction of the access attributes during the interconnect forwarding stage, which could lead to inconsistencies in the access attributes.

[0031] Step 102: Determine the target chip node identifier based on the first address segment in the physical address, and determine the on-chip offset address within the target chip node based on the second address segment in the physical address.

[0032] The target chip node identifier is used to identify the target chip node, and at least some of the hardware resources of the multiple chip nodes are set based on the same on-chip offset address.

[0033] Specifically, physical addresses can employ a segmented concatenation structure. The first address segment identifies the chip node where the target is located, and the second address segment represents the on-chip offset address within the target chip node. The processor or memory attribute management device can determine the target chip node by parsing the first address segment and determine the on-chip address range of the target hardware resource within the target chip node by parsing the second address segment. In this way, physical addresses can both distinguish different chip nodes and locate hardware resources within a chip node using a unified on-chip offset address.

[0034] The target chip node identifier can be the Die / Chip-ID described earlier. In a Chiplet multi-Die system, this target chip node identifier can be used to identify a Die. In a multi-chip system, this target chip node identifier can be used to identify a chip. Since the address allocation, attribute matching, and routing mechanisms can remain consistent in the embodiments of this application, the target chip node identifier is used uniformly for description. That is, the target chip node can be a Die connected within the same package via Die-to-Die interconnect, or a chip connected via Chip-to-Chip interconnect, serial interconnect, or other inter-chip interconnect methods.

[0035] As an optional embodiment, the first address segment is located at the higher end of the second address segment. The first address segment is used for mask matching of the target chip node identifier and cross-chip node routing. The second address segment is used to represent the intra-chip offset address to locate the target hardware resource within the target chip node. The target chip node identifier and the intra-chip offset address are concatenated to form a globally unified homogeneous address space corresponding to the physical address. In the homogeneous address space, different chip nodes reuse the same intra-chip offset address. The same intra-chip offset address corresponds to the same source hardware resource in different chip nodes, and the same source hardware resources in different chip nodes are distinguished by the target chip node identifier.

[0036] In the above implementation, the first address segment is not merely used as the high-order bits of a regular physical address for address comparison, but also participates in mask matching of the target chip node identifier and cross-chip node routing. The second address segment is used for on-chip address location within the target chip node. Thus, the physical address can present a structured address format combining the chip node identifier and the on-chip offset address, making the global address space distinguishable at the chip node level and reusable at the on-chip address level.

[0037] For example, if multiple chip nodes are equipped with on-chip dynamic random access memory (DRAM), and the on-chip offset address range of the DRAM is the same in each chip node, then the same memory attribute rule can cover the on-chip DRAM in different chip nodes based on the on-chip offset address range, without having to configure a corresponding complete physical address range rule for each chip node.

[0038] For example, if multiple chip nodes have on-chip peripheral register areas, and the peripheral registers such as serial port controllers, general-purpose input / output controllers, interrupt controllers, or direct memory access controllers in each chip node use the same on-chip offset address range, then the same device attribute rule can be used to cover the peripheral register areas with the same name in different chip nodes, and the first address segment can be used to distinguish whether the peripheral register is actually located in the local chip node or the remote chip node.

[0039] For example, if different chip nodes are equipped with on-chip dynamic random access memory, and the on-chip offset address range of the on-chip dynamic random access memory is the same in each chip node, then the same memory attribute rule can cover the on-chip dynamic random access memory in different chip nodes based on the on-chip offset address range, without having to configure a corresponding complete physical address range rule for each chip node.

[0040] In some embodiments, the homogeneous address space can refer to at least some functional units in multiple chip nodes adopting consistent on-chip local address mapping rules and module address distribution. That is, memory regions, peripheral regions, and register regions within different chip nodes can have the same base address and the same interval division. The global physical address can adopt a segmented concatenation structure, where the first address segment represents the target chip node identifier, and the second address segment reuses a unified on-chip offset address. The same on-chip offset address can correspond to the same source hardware resource in different chip nodes, distinguished only by the target chip node identifier. Based on this homogeneous address space, address decoding logic, peripheral IP cores, and memory controller IP cores in different chip nodes can reuse the same address layout rules without requiring differentiated adaptation for different chip nodes. This homogeneous address space can serve as the basis for performing target chip node identifier mask matching, reducing the number of memory attribute rules, and achieving globally unified memory attribute management.

[0041] Optionally, the physical address further includes a third address segment. This third address segment is located at the higher end of the first address segment and is a reserved address segment. It is understood that this reserved address segment is used for wider physical addresses or expansion to more chip nodes.

[0042] The third address segment can correspond to a high-order address segment that is not currently implemented or used by the processor. This third address segment can be kept at a preset value in the current system, such as all zeros. By setting the third address segment, address space can be reserved for future expansions to a wider physical address space, more chip nodes, or other system expansions, avoiding the need to redesign existing chip node identifier segments and on-chip offset address segments when expanding the system.

[0043] For example, the effective physical address in the physical address is at least 44 bits, the first address segment is 3 bits, the second address segment is 41 bits, the first address segment is used to identify no more than 8 chip nodes, and the second address segment is used to represent the 2TB on-chip address space within a single chip node.

[0044] For example, in one exemplary implementation, the physical address may include ADDR[63:44], ADDR[43:41], and ADDR[40:0]. ADDR[63:44] can be a reserved address range, ADDR[43:41] can be a chip node identifier range, and ADDR[40:0] can be an on-chip offset address range. The 3-bit chip node identifier range can support up to 8 chip nodes, and the 41-bit on-chip offset address range can support 2TB of on-chip address space within a single chip node. This example is only used to illustrate an optional address partitioning method and does not constitute a limitation on the embodiments of this application.

[0045] In some examples, if the on-chip dynamic random access memory (DRAM) has an on-chip offset address range of 0x080_0000_0000 to 0x0FF_FFFF_FFFF, then the DRAM in the chip node with target chip node identifier 0 and the DRAM in the chip node with target chip node identifier 1 can have the same on-chip offset address range, but they are distinguished in the global physical address space by different target chip node identifiers. Similarly, if the on-chip peripheral register region has an on-chip offset address range of 0x001_0000_0000 to 0x003_FFFF_FFFF, then the on-chip peripheral register regions in different chip nodes can reuse the same on-chip offset address range, and their respective chip nodes can be distinguished by the target chip node identifier.

[0046] Based on the aforementioned on-chip offset address reuse mechanism, the target chip node identifier and on-chip offset address can be further mapped to different address segments of the physical address using a fixed physical address bit segment division method. For example, when the processor uses the 44-bit effective physical address of the CPU IP, ADDR[43:0] can be used as the effective physical address, and ADDR[63:44] as a constant-zero reserved segment. In this case, the bit segment division of the physical address can be as shown in the table below: Through the above bit segmentation, chip nodes with target chip node identifier 0 and target chip node identifier 1 can reuse the same on-chip offset address range and be distinguished in the global physical address by different values ​​of ADDR[43:41]. The on-chip offset address is represented by ADDR[40:0], which is used to locate hardware resources such as on-chip dynamic random access memory, on-chip storage resources, peripheral registers or memory-mapped input / output space inside the corresponding chip node.

[0047] Based on the above bit segmentation, when ADDR[43:41] uses a 3-bit target chip node identifier segment and ADDR[40:0] uses a 41-bit on-chip offset segment, a maximum of 8 chip nodes can be supported, with each chip node corresponding to 2TB of on-chip homogeneous address space. Therefore, the global address space capacity corresponding to 8 chip nodes is 8 × 2TB, or 16TB, corresponding to 2 44 The address space range can match the 44-bit effective physical address space of the CPUIP. Based on this, different chip nodes can adopt a completely consistent on-chip address layout, and divide the on-chip address space into different attribute regions such as cacheable attributes, non-cacheable ordinary memory attributes, and device attributes according to the physical access characteristics of hardware resources. For example, each chip node can adopt the following identical on-chip address layout: In the above on-chip address layout, although on-chip storage resources are not cached, they are still considered ordinary memory, allowing speculative fetching and access reordering. This satisfies the access requirements of direct instruction fetching and execution from XIP Flash, and instruction prefetching during the reset and boot phase. Therefore, this type of region can be configured as non-cacheable ordinary memory instead of as device memory. On-chip peripheral registers and PCIe MMIO regions typically require strong sequential access and can be configured as device memory to prohibit cached access, access reordering, and speculative access. For reserved or unmapped regions, they can be configured as device memory by default, or access control information prohibiting speculative access can be generated to reduce the risk of anomalies caused by the processor speculative access to empty or unimplemented address spaces.

[0048] Therefore, the target chip node identifier is used to distinguish different chip nodes globally, while the on-chip offset address is used to locate the corresponding hardware resources within the target chip node. The global physical address can be formed by concatenating the target chip node identifier and the on-chip offset address. For example, when the on-chip offset address of the on-chip DDR is 0x080_0000_0000, the DDR in the chip node with a target chip node identifier of 0 can correspond to one global physical address range, and the DDR in the chip node with a target chip node identifier of 1 can correspond to another global physical address range. Their on-chip offset addresses are the same, but the global physical addresses are distinguished by different values ​​of the target chip node identifier. Based on this method, each chip node can reuse the same on-chip address decoding logic, peripheral IP, and memory controller IP, without needing to perform address layout adaptation separately for different chip nodes.

[0049] As an optional embodiment, step 102, determining the target chip node identifier based on the first address segment in the physical address and determining the on-chip offset address within the target chip node based on the second address segment in the physical address, includes: parsing the physical address according to a preset address segment division method; extracting the first address segment from the high-order side of the physical address and using the first address segment as the target chip node identifier; extracting the second address segment from the low-order side of the physical address and using the second address segment as the on-chip offset address; wherein, the physical address, through the combination of the target chip node identifier and the on-chip offset address, locates hardware resources with the same on-chip offset address range in different chip nodes.

[0050] The preset address segment division method can be determined during the system design phase or configured through configuration registers, boot configuration information, or firmware initialization information. The memory attribute management device can extract address segments from the physical addresses generated when the processor initiates access, based on this preset address segment division method. In this way, the memory attribute management device does not need to maintain completely independent address resolution logic for different chip nodes, but can reuse a unified address resolution rule. For multiple chip nodes using a homogeneous on-chip address layout, the memory attribute management device can, after resolving the on-chip offset address, determine the type of the target hardware resource based on the same set of on-chip address range rules, and then combine this with the target chip node identifier to determine the specific chip node where the target hardware resource resides.

[0051] Further optionally, during the parsing of the physical address, a third address segment located on the high side of the first address segment is identified, the third address segment being a reserved address segment; if the third address segment meets the preset reserved address conditions, the target chip node identifier and the on-chip offset address are determined based on the first address segment and the second address segment; if the third address segment does not meet the preset reserved address conditions, the memory access request is blocked, or the access control information corresponding to the memory access request is configured as access control information that prohibits speculative access.

[0052] For example, preset reserved address conditions may include the third address segment being all zeros, or the third address segment belonging to a preset set of allowed values. If the third address segment does not meet the preset reserved address conditions, it indicates that the physical address may exceed the range of valid physical addresses supported by the current system, or that it is accessing an unimplemented address space. In this case, the memory access request can be blocked, or the access control information corresponding to the memory access request can be configured to prohibit speculative access, thereby reducing the risk caused by the processor speculative access to unmapped or abnormal addresses. This approach is particularly suitable for scenarios where the processor may prematurely access uninitialized regions during reset startup, instruction prefetching, or out-of-order execution. By identifying and constraining reserved address segments, the probability of system anomalies or startup failures caused by invalid address access can be reduced.

[0053] Further optionally, the step of parsing the physical address according to a preset address segment division method includes: parsing the physical address according to a 44-bit valid physical address; extracting 3 bits from the 44-bit valid physical address as the first address segment to identify up to 8 chip nodes; and extracting 41 bits from the 44-bit valid physical address as the second address segment to represent the 2TB on-chip address space within a single chip node.

[0054] Based on this implementation, unified addressing of multiple chip nodes can be achieved within a 44-bit effective physical address space. For example, when the system includes 8 chip nodes, each chip node can correspond to 2TB of on-chip address space, and multiple chip nodes together constitute the global address space. Compared to reserving large segments of global address regions for different resource types, this address partitioning method can distinguish different chip nodes through chip node identifiers and reuse on-chip resource layouts through on-chip offset addresses, which helps reduce address gaps and improve address space utilization.

[0055] Furthermore, in a single-chip node configuration, only one target chip node identifier can be enabled. Access to other target chip node identifiers can be hardware-masked, return an error response, or be configured with access control information to prohibit speculative access. In a multi-chip node configuration, multiple target chip node identifiers can be enabled, using the same on-chip address layout and memory attribute rules. Therefore, a single-chip node, a chipplet system consisting of multiple dies, and a system consisting of multiple chips can reuse the same set of address resolution rules and on-chip resource layout, reducing the complexity of reconfiguring physical address space and memory attribute rules due to changes in system configuration.

[0056] Reference Figure 2 , Figure 2 This is a schematic diagram of the address space layout within a chip node, provided as an embodiment of this application. Figure 2 As shown, within a single chip node, different types of hardware resources can be uniformly divided according to on-chip offset addresses. For example, on-chip offset addresses 0x000_0000_0000 to 0x000_FFFF_FFFF can correspond to on-chip memory areas, which may include on-chip memory resources such as BootROM, XIP Flash, and on-chip SRAM. This area can be configured as non-cacheable ordinary memory, i.e., no cache allocation is performed, but speculative instruction fetching or access rearrangement is allowed to meet access requirements such as reset-start instruction fetching and direct instruction fetching from XIP Flash.

[0057] Offsets from 0x001_0000_0000 to 0x003_FFFF_FFFF correspond to the on-chip peripheral area, which may include on-chip peripheral registers such as CLINT, APLIC, IMSIC, UART, SPI, I2C, and DMA. Since these registers typically require strong-order access, they can be configured as device attributes to disable cached access, access reordering, and speculative access. Offsets from 0x004_0000_0000 to 0x07F_FFFF_FFFF correspond to a reserved area. This reserved area can be used for future resource expansion and can be configured as a device attribute by default or to generate access control information that prohibits speculative access, reducing the risk of anomalies caused by the processor accessing unmapped or empty addresses.

[0058] Offsets 0x080_0000_0000 to 0x0FF_FFFF_FFFF on-chip correspond to on-chip dynamic random access memory regions, such as on-chip DDR regions. These regions can be used as general main memory regions and configured with cacheable attributes to support cached access and normal memory access reordering. Offsets 0x100_0000_0000 to 0x1FF_FFFF_FFFF on-chip correspond to memory-mapped input / output spaces, such as PCIe MMIO regions. Since these regions are typically used to access external devices or device register spaces, they can be configured with device attributes to disable cached access, access reordering, and speculative access.

[0059] In some embodiments, multiple chip nodes can be adopted with Figure 2 The diagram shows the same on-chip address layout. This means that on-chip memory areas, on-chip peripheral areas, reserved areas, on-chip dynamic random access memory areas, and memory-mapped input / output spaces in different chip nodes can have the same on-chip offset address range. Based on this approach, the same set of memory attribute rules can cover the same hardware resources in multiple chip nodes based on the on-chip offset address range, without needing to configure complete physical address range rules for each chip node, thereby reducing the number of memory attribute rules to configure and the complexity of maintenance.

[0060] Reference Figure 3 , Figure 3 This is a schematic diagram of a global physical address bit field structure provided in an embodiment of this application. For example... Figure 3 As shown, when the processor uses 44-bit effective physical addresses, ADDR[43:0] can be used as the effective physical address, and ADDR[63:44] can be used as a reserved address range. This reserved address range can be kept at a preset value, such as all zeros, to reserve address bits for future expansion of the physical address space or more chip nodes.

[0061] In ADDR[43:0], ADDR[43:41] can be used as a target chip node identifier segment, which can be 3 bits and used to identify the target chip node. For example, when the target chip node identifier segment is 3 bits, it can represent up to 8 chip nodes. ADDR[40:0] can be used as an on-chip offset segment, which can be 41 bits and used to represent the on-chip offset address inside the target chip node. Since a 41-bit on-chip offset address can represent 2TB of on-chip address space, each chip node can correspond to 2TB of homogeneous on-chip address space.

[0062] In some embodiments, the global physical address can be formed by concatenating the target chip node identifier and the on-chip offset address. For example, the global physical address can be represented as the target chip node identifier shifted left by 41 bits and then combined with the on-chip offset address. With this address structure, the target chip node identifier is used to distinguish different chip nodes globally, while the on-chip offset address is used to locate specific hardware resources within the target chip node. The same on-chip offset address can correspond to the same hardware resource in different chip nodes, distinguished only by different values ​​of the target chip node identifier in terms of their global physical addresses.

[0063] Furthermore, with the partitioning method of a 3-bit target chip node identifier segment and a 41-bit on-chip offset segment, 8 chip nodes can collectively form a 16TB global physical address space, i.e., 8 × 2TB, corresponding to 2 44 The effective physical address range. Therefore, unified addressing can be achieved across multiple chip nodes without redesigning the on-chip address layout for different chip nodes, and different chip nodes can reuse the same on-chip address mapping rules, address decoding logic, peripheral IP cores, and memory controller IP cores.

[0064] Step 103: According to the preset memory attribute rules, perform mask matching on the target chip node identifier and address range matching on the on-chip offset address to determine the memory attribute corresponding to the memory access request.

[0065] The memory attribute rules are used to ensure that hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attributes. Further optionally, the hardware resources in the plurality of chip nodes include at least one of on-chip dynamic random access memory, on-chip storage resources, peripheral registers, and memory-mapped input / output spaces.

[0066] Specifically, memory attribute rules can include fields for matching chip node identifiers, fields for matching on-chip offset address ranges, and fields for indicating memory attributes. The field for matching chip node identifiers can be a mask field or a wildcard field to match multiple chip nodes; the field for matching on-chip offset address ranges can be used to distinguish different types of hardware resources within the same chip node; the field for indicating memory attributes can be used to identify whether the address range corresponds to a cacheable attribute, a non-cacheable ordinary memory attribute, or a device attribute. A cacheable attribute indicates that the corresponding address range belongs to an ordinary storage area accessible as main memory. The processor can enable cached access to this address range and can perform prefetching, merging, out-of-order, or reordering access behaviors according to ordinary memory access rules. A non-cacheable ordinary memory attribute indicates that the corresponding address range belongs to an ordinary storage area but is not cached, such as ROM, on-chip execution flash memory, or on-chip static random access memory. This type of area may not enter the cache, but instruction fetching, prefetching, or ordinary memory access reordering is still allowed. Device attributes can be used to indicate that the corresponding address range belongs to a strong order access region, such as peripheral registers or memory-mapped input / output space. Such regions can be configured to disable cached access, disable out-of-order access, disable access merging, and disable speculative access to reduce the risk of peripheral malfunctions or bus timing anomalies.

[0067] By performing mask matching on the target chip node identifier and address range matching on the on-chip offset address, the chip node dimension and the on-chip resource dimension can be combined to determine memory attributes. Compared with configuring attribute rules on a chip node-by-chip node according to the complete physical address range, the embodiments of this application can cover similar hardware resources in multiple chip nodes with a smaller number of memory attribute rules, thereby reducing the complexity of configuring and maintaining memory attribute rules.

[0068] As an optional embodiment, different chip nodes adopt the same on-chip address layout and mapping rules. The same on-chip address layout includes: at least one of the memory regions, peripheral regions and register regions in different chip nodes has the same base address and the same interval division.

[0069] The same mapping rule includes mapping at least one of the following in different chip nodes: on-chip dynamic random access memory, on-chip storage resources, peripheral registers, and memory-mapped input / output spaces, to a corresponding on-chip offset address range. Address decoding logic, peripheral IP cores, and / or memory controller IP cores in different chip nodes are reused based on the same on-chip address layout and mapping rule.

[0070] Specifically, on-chip dynamic random access memory (DRAM) in different chip nodes can be mapped to the same first-type on-chip offset address range, on-chip storage resources can be mapped to the same second-type on-chip offset address range, peripheral registers can be mapped to the same third-type on-chip offset address range, and memory-mapped input / output spaces can be mapped to the same fourth-type on-chip offset address range. In this way, the address decoding logic within different chip nodes can decode according to the same on-chip offset address rules, and peripheral IP cores and memory controller IP cores can be reused based on the same address layout, reducing the need for separate address mapping adaptations for different chip nodes.

[0071] For example, in some embodiments, on-chip dynamic random access memory can correspond to cacheable attributes, on-chip storage resources can correspond to non-cacheable ordinary memory attributes, and peripheral registers and memory-mapped input / output spaces can correspond to device attributes. Since the above-mentioned hardware resources in different chip nodes use the same or corresponding on-chip offset address ranges, the same set of memory attribute rules can cover the corresponding resources in multiple chip nodes.

[0072] As an optional embodiment, hardware resources in different chip nodes are address-mapped according to the same on-chip address layout and mapping rules. Specifically, at least one of the memory regions, peripheral regions, and register regions in different chip nodes has the same base address or the same range division, so that the same on-chip offset address range corresponds to the same source hardware resources in different chip nodes.

[0073] Specifically, a unified on-chip address mapping table can be set for multiple chip nodes. This on-chip address mapping table can specify the on-chip offset address range of resources such as on-chip dynamic random access memory, boot read-only memory, on-chip execution flash memory, on-chip static random access memory, peripheral registers, and memory-mapped input / output space. Different chip nodes can load or embed the same on-chip address mapping table so that the same on-chip offset address corresponds to the same type or source of hardware resources in different chip nodes.

[0074] Optionally, the step of mapping hardware resources in different chip nodes according to the same on-chip address layout and mapping rules includes: mapping on-chip dynamic random access memory, on-chip storage resources, peripheral registers, and memory-mapped input / output spaces in different chip nodes to the same on-chip offset address range. The preset memory attribute rules are configured based on the same on-chip offset address range so that the same memory attribute rule can match the same source hardware resources in multiple chip nodes.

[0075] Specifically, when the chip node identifier field in a memory attribute rule is configured as a mask field or a wildcard field, the memory attribute rule does not need to be limited to a unique chip node; instead, it can match multiple valid chip nodes. In this case, the on-chip address range field in the memory attribute rule can be used to limit the on-chip offset address range of the same hardware resources. Therefore, the same memory attribute rule can apply to the same hardware resources with the same on-chip offset address range across multiple chip nodes, allowing the number of memory attribute rules to primarily depend on the number of on-chip attribute partitions, rather than increasing linearly with the number of chip nodes.

[0076] For example, in an exemplary on-chip address layout, on-chip memory resources can be located at on-chip offset addresses 0x000_0000_0000 to 0x000_FFFF_FFFF, peripheral registers can be located at on-chip offset addresses 0x001_0000_0000 to 0x003_FFFF_FFFF, on-chip dynamic random access memory can be located at on-chip offset addresses 0x080_0000_0000 to 0x0FF_FFFF_FFFF, and memory-mapped input / output space can be located at on-chip offset addresses 0x100_0000_0000 to 0x1FF_FFFF_FFFF. In this example, if the system includes multiple chip nodes, each chip node can use the above-mentioned on-chip offset address range. Memory attribute rules can be configured separately for the above-mentioned on-chip offset address ranges, and the chip node identification field can cover multiple chip nodes through a mask or a valid chip node set. Therefore, a cacheable attribute rule for on-chip dynamic random access memory can cover dynamic random access memory in multiple chip nodes, and a device attribute rule for peripheral registers can cover peripheral register regions in multiple chip nodes.

[0077] As an optional embodiment, in step 103, the step of performing mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules to determine the memory attribute corresponding to the memory access request includes: Based on the node mask field in the preset memory attribute rules, the target chip node identifier is masked to obtain a node matching result; based on the address range field in the preset memory attribute rules, the on-chip offset address is matched to obtain an address matching result; if both the node matching result and the address matching result are successful, the attribute field in the preset memory attribute rules is determined as the memory attribute corresponding to the memory access request; if the on-chip offset address falls into a reserved address range, an unmapped address range, or does not match any of the preset memory attribute rules, the memory attribute corresponding to the memory access request is determined as a device attribute, or access control information for prohibiting speculative access is generated; if multiple preset memory attribute rules are matched, the memory attribute corresponding to the memory access request is determined according to the priority of the multiple memory attribute rules.

[0078] The node mask field is used to match the same memory attribute rule with multiple chip nodes, and the on-chip address range field is used to distinguish different types of hardware resources among the multiple chip nodes. The number of memory attribute rules is related to the number of on-chip attribute partitions, but is independent of the number of multiple chip nodes.

[0079] Specifically, each memory attribute rule can include a node mask field, a node matching field, an on-chip address range field, and an attribute field. The node mask field can be used to indicate the bits in the target chip node identifier that are involved in the matching; the node matching field can be used to indicate the chip node identifiers or chip node sets that are allowed to match; the on-chip address range field can be used to indicate the on-chip offset address range; and the attribute field can be used to indicate the memory attribute corresponding to the rule being matched.

[0080] In one example, the memory attribute management device can first perform a bitwise AND operation on the target chip node identifier and the node mask field to obtain the mask operation result. Then, it compares the mask operation result with the node matching field or the set of valid chip nodes to obtain the node matching result. Simultaneously, the memory attribute management device can determine whether the on-chip offset address falls within the address range corresponding to the on-chip address range field to obtain the address matching result. When both the node matching result and the address matching result are successful, the attribute field in this memory attribute rule can be used as the memory attribute corresponding to the memory access request.

[0081] Based on this implementation, the high-order mask matching of the target chip node identifier and the low-order interval matching of the on-chip offset address can jointly determine the final memory attributes. Compared to configuring attribute rules one by one according to the complete physical address interval, this method can utilize the mask wildcard capability of the chip node identifier to allow a single rule to cover the same type of on-chip resources in multiple chip nodes, which helps to reduce the number of memory attribute rules to be configured.

[0082] It is worth noting that the processor-side or memory attribute management device can set up high-bit mask matching logic based on the standard address range matching logic. This high-bit mask matching logic can be used to perform wildcard matching on the target chip node identifier segment in the physical address, enabling a memory attribute rule to match one or more valid chip nodes without needing to configure a complete physical address range rule for each chip node. Specifically, the target chip node identifier can first undergo masking operations on the node mask field, and then be compared with the node matching field or the set of valid chip nodes to obtain the node matching result. The on-chip offset address can be range matched according to the address range field to obtain the address matching result. The node matching result and the address matching result can be combined into the final matching result, and when a match is successful, the corresponding attribute field is determined as the memory attribute corresponding to the memory access request.

[0083] Further optionally, the step of performing mask matching on the target chip node identifier according to the node mask field in the preset memory attribute rules to obtain the node matching result includes: Based on the node mask field, a mask operation is performed on the target chip node identifier; the mask operation result is matched with the set of valid chip nodes; if the target chip node identifier belongs to the set of valid chip nodes, the node matching result is determined to be a successful match; if the target chip node identifier does not belong to the set of valid chip nodes, the node matching result is determined to be a failed match, and the forwarding of the memory access request to the chip node interconnection interface is prohibited.

[0084] The node matching result includes whether the target chip node identifier belongs to the set of valid chip nodes. The set of valid chip nodes represents the chip nodes that are enabled in the system.

[0085] The effective chip node set represents the chip nodes that are currently enabled in the system configuration. For example, in a single-chip node system, the effective chip node set may only include chip node 0. In a dual-chip node system, the effective chip node set may include chip node 0 and chip node 1. In a multi-chip node system, the effective chip node set may include multiple chip nodes that have been assembled or trained through interconnection. Using the effective chip node set, system configurations with different numbers of chip nodes can be adapted without modifying the on-chip address layout and memory attribute rules.

[0086] Optionally, based on the aforementioned set of valid chip nodes, before routing based on the target chip node identifier, it is determined whether the target chip node identifier belongs to the set of valid chip nodes. If the target chip node identifier does not belong to the set of valid chip nodes, the access route corresponding to the target chip node identifier is blocked and an access error is returned, or the access control information corresponding to the memory access request is configured as access control information that prohibits speculative access.

[0087] Further optionally, the same on-chip address layout and the same preset memory attribute rules are configured for single-chip node systems and multi-chip node systems; different effective chip node sets are generated based on at least one of package configuration information, fuse configuration information, boot configuration information, or inter-chip node interconnection training results; through the different effective chip node sets, the single-chip node system and the multi-chip node system can adapt to different system forms without modifying the on-chip address layout and the preset memory attribute rules.

[0088] Optionally, during the startup phase, the preset memory attribute rules and the set of valid chip nodes can also be loaded. Before the preset memory attribute rules are fully loaded, the memory attribute corresponding to cross-chip node access is determined as a device attribute, or cross-chip node access is prohibited. After the preset memory attribute rules and the set of valid chip nodes are fully loaded, cross-chip node access is allowed according to the preset memory attribute rules.

[0089] Optionally, the preset memory attribute rules are configured according to the on-chip attribute partitions; the chip node identifier field in the preset memory attribute rules is configured as a mask field; and different on-chip attribute partitions are distinguished by the on-chip address range field. The number of preset memory attribute rules is related to the number of on-chip attribute partitions, but is independent of the number of chip nodes.

[0090] On-chip attribute partitions can be created based on the physical access characteristics of hardware resources. For example, on-chip dynamic random access memory (DRAM) can be divided into cacheable attribute partitions, boot ROM, on-chip execution flash memory (EPF), or on-chip static random access memory (SRAM) can be divided into non-cacheable general memory attribute partitions, and peripheral registers or memory-mapped input / output spaces can be divided into device attribute partitions. Since each chip node uses the same or nearly identical on-chip address layout, the on-chip offset address range of each on-chip attribute partition can remain consistent across different chip nodes. Based on this approach, memory attribute rules can be configured according to on-chip attribute partitions without needing to copy memory attribute rules based on the number of chip nodes.

[0091] Further optionally, the memory attributes include at least one of cacheable attributes, non-cacheable ordinary memory attributes, and device attributes. For example, the memory attribute rules include at least one of the following: rules for configuring the on-chip offset address range corresponding to on-chip dynamic random access memory as a cacheable attribute; rules for configuring the on-chip offset address range corresponding to on-chip storage resources as a non-cacheable ordinary memory attribute; rules for configuring the on-chip offset address range corresponding to peripheral registers as a device attribute; and rules for configuring the on-chip offset address range corresponding to memory-mapped input / output spaces as device attributes.

[0092] Furthermore, at least one of the preset memory attribute rules is used to match hardware resources with the same on-chip offset address range across multiple chip nodes, thereby decoupling the number of preset memory attribute rules from the number of chip nodes. Based on the above configuration, the number of memory attribute rules can be decoupled from the number of chip nodes. For example, when the on-chip attribute partitions include on-chip storage resource partitions, on-chip peripheral register partitions, on-chip dynamic random access memory partitions, and memory-mapped input / output space partitions, a small number of memory attribute rules can cover the corresponding on-chip resources across multiple chip nodes. Compared to configuring complete physical address range rules for each chip node separately, this method reduces the need for repeated configuration of memory attribute rules as the number of chip nodes increases. Even if the on-chip attribute partitions in the actual chip nodes are further refined, the number of memory attribute rules can primarily change with the number of on-chip attribute partitions, rather than increasing linearly with the number of chip nodes.

[0093] The on-chip storage resources include at least one of boot read-only memory, on-chip execution flash memory, and on-chip static random access memory. The non-cacheable general memory attribute indicates that no cache allocation is performed and allows speculative instruction fetching or access reordering. The device attribute indicates that at least one of prohibiting cache access, prohibiting access reordering, and prohibiting speculative access is allowed. Among the multiple memory attribute rules, device attribute rules take precedence over non-cacheable general memory attribute rules, and non-cacheable general memory attribute rules take precedence over cacheable attribute rules.

[0094] For example, on-chip dynamic random access memory (DRAM) can typically be used as main memory and is suitable for configuration as cacheable to support both cached and normal memory access. Boot read-only memory (BRROM), on-chip execution flash memory (ESF), or on-chip static random access memory (SRAM) are generally not suitable for cache allocation, but in boot fetch or on-chip execution scenarios, it may still be necessary to allow speculative fetching or access reordering; therefore, they can be configured as non-cacheable normal memory. Peripheral registers and memory-mapped input / output spaces typically require strong sequential access and are suitable for configuration as device attributes to prohibit cached access, access reordering, or speculative access.

[0095] In some embodiments, if multiple memory attribute rules are all matched, their priority can be determined according to the strength of the attribute security constraints. For example, device attribute rules can take precedence over non-cacheable ordinary memory attribute rules, and non-cacheable ordinary memory attribute rules can take precedence over cacheable attribute rules. By setting this priority, the risk of peripheral registers or memory-mapped input / output spaces being incorrectly identified as ordinary memory or cacheable memory due to rule overlap can be reduced.

[0096] As a specific example of rule configuration, the memory attribute management device or processor can set high-order mask matching logic and configure globally wildcard memory attribute rules according to on-chip attribute partitions. The target chip node identifier segment in each memory attribute rule can be matched using a mask wildcard method, and the on-chip offset address segment can be used to distinguish different on-chip attribute partitions. For example, the following rule can be configured: On-chip storage resource rules: When the on-chip offset address is between 0x000_0000_0000 and 0x000_FFFF_FFFF, the corresponding region will be configured as non-cacheable ordinary memory. This region may include BootROM, XIP Flash or on-chip static random access memory. No cache allocation is performed, but speculative instruction fetching or access rearrangement is allowed.

[0097] On-chip peripheral register rules: When the on-chip offset address is between 0x001_0000_0000 and 0x003_FFFF_FFFF, the corresponding area will be configured as a device attribute; this area can include on-chip peripheral registers such as CLINT, APLIC, IMSIC, UART, SPI, I2C, GPIO, or DMA, and cached access, access reordering, and speculative access are prohibited.

[0098] On-chip dynamic random access memory rules: When the on-chip offset address is between 0x080_0000_0000 and 0x0FF_FFFF_FFFF, the corresponding region will be configured as cacheable to support cache access and normal memory access rearrangement.

[0099] Memory-mapped input / output space rules: When the on-chip offset address is between 0x100_0000_0000 and 0x1FF_FFFF_FFFF, the corresponding region will be configured as a device attribute; this region may include memory-mapped input / output spaces such as PCIe MMIO, and cached access, access reordering, and speculative access are prohibited.

[0100] Furthermore, for the reserved address range of 0x004_0000_0000 to 0x07F_FFFF_FFFF within the on-chip offset address, it can be configured as a device attribute by default memory attribute rules, or access control information that prohibits speculative access can be generated to prevent the processor from speculative access to unmapped regions or empty addresses.

[0101] In the example above, the target chip node identifier segment uses a masked wildcard approach, and the on-chip offset address segment is used to distinguish on-chip attribute partitions. Therefore, when the system includes multiple chip nodes, the aforementioned few rules can cover the same on-chip resources across multiple chip nodes. For example, four rules can cover on-chip storage resources, on-chip peripheral registers, on-chip dynamic random access memory, and memory-mapped input / output spaces in up to eight chip nodes. Thus, the number of memory attribute rules can primarily depend on the number of on-chip attribute partitions, rather than increasing linearly with the number of chip nodes. Compared to configuring complete physical address range rules for each chip node, this approach reduces the number of memory attribute rules required and the complexity of maintenance.

[0102] Optionally, after determining the memory attribute corresponding to the memory access request, the memory attribute can be downgraded based on page table attributes or page-based memory type attributes. This downgrade process includes downgrading a cacheable attribute to a non-cacheable ordinary memory attribute, or downgrading an ordinary memory attribute to a device attribute, and prohibiting the upgrade of device attributes to ordinary memory attributes or cacheable attributes.

[0103] Page table attributes can be provided by page table entries used by the memory management unit, and page-based memory type attributes can include page-granularity memory type identifiers supported by the processor architecture. Attribute degradation allows for further tightening of access attributes for specific pages or access scenarios, based on the determined hardware physical memory attributes. For example, a specific page in a cacheable memory region can be downgraded to a non-cacheable ordinary memory attribute, or a specific page in an ordinary memory region can be downgraded to a device attribute. Because attribute degradation is only used to tighten access constraints, not to relax hardware physical attribute constraints, it avoids the mistaken promotion of device attributes to ordinary memory attributes or cacheable attributes.

[0104] Reference Figure 4 , Figure 4 This is a schematic diagram illustrating the memory attribute generation logic for high-bit mask matching and low-bit interval matching provided in an embodiment of this application. For example... Figure 4As shown, when the processor initiates a memory access request, it can generate an access address ADDR[43:0]. The memory attribute management device can parse this access address to obtain the high-order target chip node identifier segment ADDR[43:41] and the low-order on-chip offset address segment ADDR[40:0].

[0105] For the target chip node identifier segment, the memory attribute management device can perform high-order mask matching. For example, the target chip node identifier can be masked by the node mask field, and the result can be compared with the node matching field or the set of valid chip nodes to determine whether the target chip node corresponding to the access request belongs to the valid chip nodes allowed to be accessed in the current system. Through this high-order mask matching method, the same memory attribute rule can match one or more valid chip nodes without configuring complete physical address range rules for each chip node.

[0106] For on-chip offset address segments, the memory attribute management device can perform low-order range matching. For example, when the on-chip offset address falls into the on-chip storage area, it can be determined that the access request corresponds to a non-cacheable ordinary memory attribute; when the on-chip offset address falls into the on-chip peripheral area or PCIe MMIO area, it can be determined that the access request corresponds to a device attribute; when the on-chip offset address falls into the on-chip DDR area, it can be determined that the access request corresponds to a cacheable attribute; when the on-chip offset address falls into the reserved area or unmapped area, it can be determined by default as a device attribute, or access control information prohibiting speculative access can be generated.

[0107] When both the node matching result and the address range matching result satisfy the corresponding memory attribute rules, the memory attribute management device can synthesize the memory attribute corresponding to the memory access request. For example, when the high-order target chip node identifier matches a valid set of chip nodes and the low-order on-chip offset address falls into the DDR region, a cacheable attribute can be generated; when the high-order target chip node identifier matches a valid set of chip nodes and the low-order on-chip offset address falls into the peripheral register region or the PCIeMMIO region, a device attribute can be generated; when the high-order target chip node identifier fails to match, the access request can be blocked, an access error can be returned, or access control information prohibiting speculative access can be generated.

[0108] Furthermore, after determining the memory attributes, the memory attribute management device can generate bus transaction memory attribute information. This bus transaction memory attribute information can be used to control the processor's cache access, access reordering, speculative access, and bus transaction type. Since the memory attributes are generated on the processor side or before the access request enters the downstream interconnect path, the on-chip interconnect bus, inter-die interconnect interface, or inter-chip interconnect interface can forward data based solely on the target chip node identifier during subsequent routing, transparently transmitting the bus transaction memory attribute information without needing to modify the access attributes again. Based on this approach, the risks of bus timing conflicts, peripheral mis-triggering, or system anomalies caused by inconsistencies between processor-side access behavior and downstream interconnect path attribute corrections can be reduced.

[0109] Step 104: Generate access control information corresponding to the memory access request based on the memory attributes.

[0110] The access control information is used to instruct the processor to execute the memory access request according to the access mode corresponding to the memory attribute. The access control information may include internal processor information used to control cache access, access reordering, speculative access, bus transaction type, or bus transaction attributes. For example, the access control information may be used to indicate whether cache allocation is allowed, whether prefetching is allowed, whether out-of-order execution is allowed, whether access according to device type is required, or to generate memory attribute fields in a bus transaction.

[0111] As an optional embodiment, in step 104, generating access control information corresponding to the memory access request based on the memory attributes includes: generating bus transaction memory attribute information based on the memory attributes before the memory access request is forwarded to the interconnect module; and controlling at least one of cached access, access reordering, and speculative access of the processor for the memory access request based on the bus transaction memory attribute information. The bus transaction memory attribute information is transmitted along the inter-chip node interconnect path with the memory access request.

[0112] In the above embodiments, the determination of memory attributes and the generation of bus transaction memory attribute information can be completed on the processor side or before the access request enters the downstream interconnect path. That is, the processor can determine the memory attributes corresponding to the access target based on the target chip node identifier and on-chip offset address when initiating a memory access request, and control caching, reordering, and speculative access behavior accordingly. Compared with the downstream interconnect module modifying access attributes during the forwarding phase, the embodiments of this application can reduce inconsistencies between processor-side access behavior and downstream bus attributes, which is beneficial for improving the consistency of access attributes during cross-chip node access.

[0113] In some examples, the determination of memory attributes and the generation of bus transaction attribute information can both be completed on the processor side, and the access control information of the on-chip interconnect bus, the inter-die interconnect interface, or the inter-chip interconnect interface does not need to be modified in the subsequent forwarding process.

[0114] For example, when a processor initiates an on-chip dynamic random access memory (DRAM) access across chip nodes, it can determine that the target resource is located on a remote chip node by identifying the target chip node, and determine its corresponding cacheable attribute by placing the on-chip offset address into the on-chip DRAM region, thereby generating access control information that allows cached access and normal memory access reordering. As another example, when the processor accesses BootROM, XIP Flash, or on-chip static random access memory (SRAM), it can determine its corresponding non-cacheable normal memory attribute by placing the on-chip offset address into the on-chip storage resource region, thereby generating access control information that does not perform cache allocation but allows instruction fetch prefetching or access reordering. Furthermore, when the processor accesses on-chip peripheral registers or memory-mapped input / output spaces such as PCIe MMIO, it can determine its corresponding device attribute by placing the on-chip offset address into the device region, thereby generating access control information that prohibits cached access, access reordering, and speculative access.

[0115] Step 105: Based on the target chip node identifier, route the memory access request carrying the access control information to access the target hardware resources in the target chip node.

[0116] As an optional embodiment, in step 105, routing the memory access request carrying the access control information based on the target chip node identifier includes: determining whether the memory access request corresponds to a local chip node access or a remote chip node access based on the target chip node identifier; if the memory access request corresponds to a local chip node access, routing the memory access request to the target hardware resource within the local chip node; if the memory access request corresponds to a remote chip node access, forwarding the memory access request to the target chip node through the chip node interconnect interface.

[0117] Specifically, the on-chip interconnect bus can determine whether the target hardware resource is located on the local chip node based on the target chip node identifier. If the target chip node identifier matches the local chip node identifier, the memory access request can be routed to the target hardware resource within the local chip node. If the target chip node identifier does not match the local chip node identifier, but the target chip node identifier belongs to the valid chip node set, the memory access request can be forwarded to the target chip node through the chip node interconnect interface, and the on-chip interconnect bus within the target chip node will then continue to route the memory access request to the target hardware resource.

[0118] Optionally, the inter-chip node interconnect interface includes a die-to-die interconnect interface or an inter-chip interconnect interface. In the above embodiments, the on-chip interconnect bus and the inter-chip node interconnect interface can perform routing forwarding based solely on the target chip node identifier and transparently transmit the access control information already generated on the processor side. That is, during the routing process, the on-chip interconnect bus and the inter-chip node interconnect interface do not need to perform attribute determination or attribute modification on the access control information. This avoids timing inconsistencies caused by the processor initiating access according to one memory attribute, while the downstream interconnect module modifies it to another memory attribute.

[0119] Optionally, the access control information is kept unchanged during the routing of memory access requests carrying the access control information. In the above embodiments, the on-chip interconnect bus and the inter-chip node interconnect interface can perform routing forwarding based solely on the target chip node identifier and transparently transmit the access control information already generated on the processor side. That is, during the routing process, the on-chip interconnect bus and the inter-chip node interconnect interface do not need to determine or modify the attributes of the access control information. This avoids timing inconsistencies caused by the processor initiating access according to one memory attribute, while the downstream interconnect module modifies it to another memory attribute.

[0120] In some embodiments, after receiving a memory access request initiated by the processor, the on-chip interconnect bus can determine whether the memory access request corresponds to a local chip node access or a remote chip node access based on the target chip node identifier. If the target chip node identifier matches the local chip node identifier, the on-chip interconnect bus can directly route the memory access request to the target hardware resource within the local chip node. If the target chip node identifier does not match the local chip node identifier, and the target chip node identifier belongs to the valid chip node set, the on-chip interconnect bus can forward the memory access request to the target chip node through the inter-die interconnect interface or the inter-chip interconnect interface, and the on-chip interconnect bus within the target chip node can continue to route it to the corresponding target hardware resource. During the above routing process, the on-chip interconnect bus, the inter-die interconnect interface, or the inter-chip interconnect interface can perform routing forwarding based solely on the target chip node identifier and transparently transmit the access control information already generated on the processor side without re-evaluating or modifying the access control information. For accesses corresponding to invalid target chip node identifiers, the on-chip interconnect bus, the inter-die interconnect interface, or the inter-chip interconnect interface can return an access error or block the routing path corresponding to the access.

[0121] Further, optionally, memory attribute rule version information or verification information corresponding to the multiple chip nodes can be obtained; if the memory attribute rule version information or verification information does not meet the consistency condition, cross-chip node access can be restricted, or the memory attribute corresponding to cross-chip node access can be determined as a device attribute; if the memory attribute rule version information or verification information meets the consistency condition, cross-chip node access can be allowed.

[0122] For example, during system startup, the version number of memory attribute rules, rule table verification values, or valid chip node set verification values ​​can be obtained for multiple chip nodes. If the version information or verification information of memory attribute rules is inconsistent between different chip nodes, it indicates that different chip nodes may not be using consistent attribute rule configurations. In this case, cross-chip node access can be restricted, or the memory attribute corresponding to cross-chip node access can be identified as a device attribute to reduce the risk of access anomalies caused by inconsistent rule configurations. If the version information or verification information of memory attribute rules meets the consistency condition, cross-chip node access can be allowed. Based on this approach, the rule consistency verification capability during the startup or initialization phase of a multi-chip node system can be enhanced.

[0123] In some alternative embodiments, different system configurations can be adapted using the effective chip node set. In a single-chip node system or a single-die system, only the chip node with target chip node identifier 0 can be enabled, and access to the other target chip node identifiers can be masked by hardware, return access errors, or be configured with access control information to prohibit speculative access. In a multi-die chiplet system or a multi-chip system, the corresponding target chip node identifiers can be enabled based on the actual packaging, assembly, or interconnect training results. For example, a dual-die or dual-chip system can enable target chip node identifiers 0 and 1, while an eight-die or eight-chip system can enable target chip node identifiers 0 to 7. Based on this approach, single-chip node systems, multi-die chiplet systems, and multi-chip systems can share the same on-chip address layout, the same set of memory attribute rules, and the same software configuration, differing only in the effective chip node set, thereby reducing the complexity of reconfiguring address layout and memory attribute rules between different system configurations.

[0124] In some optional embodiments, a valid set of chip nodes can be generated based on at least one of package configuration information, fuse configuration information, boot configuration information, or interconnect training results between chip nodes. For example, in a single-chip node system, only one chip node identifier may be enabled. In a multi-chip node system, a valid set of chip nodes can be generated based on the chip nodes that have been successfully assembled or interconnected. In this way, single-chip node systems and multi-chip node systems can share the same on-chip address layout and the same memory attribute rules, and can distinguish system configurations through different sets of valid chip nodes.

[0125] In this embodiment, the physical address is divided into a first address segment for identifying chip nodes and a second address segment for representing on-chip offset addresses. The memory attributes corresponding to memory access requests are determined based on the mask matching result of the target chip node identifier and the address range matching result of the on-chip offset address. This allows hardware resources with the same on-chip offset address range in different chip nodes to share the corresponding memory attribute rules, thereby solving the technical problems of high memory attribute configuration complexity, inconsistent handling of cross-die or cross-chip access attributes, and low address space utilization in existing technologies. Based on the above implementation, the same memory attribute rule can cover hardware resources with the same on-chip offset address range in multiple chip nodes, reducing the need for repeated configuration of memory attribute rules as the number of chip nodes increases, which helps reduce memory attribute configuration complexity and maintenance costs. Simultaneously, the processor can determine the memory attributes and generate access control information before the memory access request enters the interconnect path. The interconnect path can be routed based on the target chip node identifier while maintaining the access control information, which helps improve the consistency of access attributes during cross-chip node access. Furthermore, reusing the same on-chip offset address and corresponding memory attribute rules across different chip nodes can reduce the need to reserve a large number of independent address ranges for different chip nodes or product forms, which is beneficial to improving address space utilization and facilitates the reuse of address layout and memory attribute configuration between single dies, multiple dies, and multi-chip systems.

[0126] The above describes a memory attribute management method in the embodiments of this application. The memory attribute management device that performs the above method will be described below.

[0127] See Figure 5 ,like Figure 5 The diagram shows a structural schematic of a memory attribute management device. The memory attribute management device in this embodiment can achieve the above-mentioned... Figure 1The steps of the memory attribute management method executed in the corresponding embodiments are described above. The functions implemented by the memory attribute management device can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions, and these modules can be software and / or hardware. The memory attribute management device may include an acquisition unit, a determination unit, a matching unit, a generation unit, and a routing unit; the functional implementation of these units can be found in [reference needed]. Figure 1 The operations performed in the corresponding embodiments will not be described in detail here. Specifically, the memory attribute management device includes the following units: The acquisition unit is configured to acquire a memory access request initiated by the processor, the memory access request including a physical address to be accessed; The determining unit is configured to determine a target chip node identifier based on a first address segment in the physical address, and to determine an on-chip offset address within the target chip node based on a second address segment in the physical address, wherein the target chip node identifier is used to identify the target chip node, and at least some hardware resources of a plurality of chip nodes are set based on the same on-chip offset address; The matching unit is configured to perform mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules, and determine the memory attribute corresponding to the memory access request. The memory attribute rules are used to make hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attribute. The generation unit is configured to generate access control information corresponding to the memory access request based on the memory attributes, wherein the access control information is used to instruct the processor to execute the memory access request according to the access method corresponding to the memory attributes; The routing unit is configured to route memory access requests carrying the access control information based on the target chip node identifier, so as to access the target hardware resources in the target chip node.

[0128] In some implementations, the first address segment is located at the higher end of the second address segment, and the first address segment is used for mask matching of the target chip node identifier and cross-chip node routing; the second address segment is used to represent the on-chip offset address to locate the target hardware resource within the target chip node; The target chip node identifier and the on-chip offset address are concatenated to form a globally unified homogeneous address space corresponding to the physical address; In the homogeneous address space, different chip nodes reuse the same on-chip offset address. The same on-chip offset address corresponds to the same hardware resource in different chip nodes, and the same hardware resources in different chip nodes are distinguished by the target chip node identifier. The physical address also includes a third address segment, which is located on the higher side of the first address segment and is a reserved address segment.

[0129] In some implementations, when the matching unit performs mask matching on the target chip node identifier and address range matching on the on-chip offset address to determine the memory attribute corresponding to the memory access request, according to preset memory attribute rules, it is specifically configured as follows: According to the node mask field in the preset memory attribute rules, the target chip node identifier is masked and matched to obtain a node matching result; according to the address range field in the preset memory attribute rules, the on-chip offset address is matched to obtain an address matching result; if both the node matching result and the address matching result are successful, the attribute field in the preset memory attribute rules is determined as the memory attribute corresponding to the memory access request; if the on-chip offset address falls into a reserved address range, an unmapped address range, or does not match any of the preset memory attribute rules, the memory attribute corresponding to the memory access request is determined as a device attribute, or access control information for prohibiting speculative access is generated; if multiple preset memory attribute rules are matched, the memory attribute corresponding to the memory access request is determined according to the priority of the multiple memory attribute rules; wherein, the node mask field is used to enable the same memory attribute rule to match multiple chip nodes, and the on-chip address range field is used to distinguish different types of hardware resources in the multiple chip nodes; the number of memory attribute rules is related to the number of on-chip attribute partitions, but is not related to the number of multiple chip nodes.

[0130] In some implementations, when the matching unit performs mask matching on the target chip node identifier according to the node mask field in the preset memory attribute rules to obtain a node matching result, it is specifically configured to: perform a mask operation on the target chip node identifier according to the node mask field; match the mask operation result with the set of valid chip nodes; if the target chip node identifier belongs to the set of valid chip nodes, determine that the node matching result is a successful match; if the target chip node identifier does not belong to the set of valid chip nodes, determine that the node matching result is a failed match, and prohibit forwarding the memory access request to the chip node interconnect interface.

[0131] In some implementations, the matching unit is further configured to configure the preset memory attribute rules according to the on-chip attribute partitions; configure the chip node identifier field in the preset memory attribute rules as a mask field; and distinguish different on-chip attribute partitions through the on-chip address range field; wherein the number of preset memory attribute rules is related to the number of on-chip attribute partitions and is independent of the number of the plurality of chip nodes.

[0132] In some implementations, the memory attribute rules include at least one of the following: rules for configuring the on-chip offset address range corresponding to the on-chip dynamic random access memory as a cacheable attribute; rules for configuring the on-chip offset address range corresponding to the on-chip storage resources as non-cacheable ordinary memory attributes; rules for configuring the on-chip offset address range corresponding to the peripheral registers as device attributes; and rules for configuring the on-chip offset address range corresponding to the memory-mapped input / output space as device attributes.

[0133] In some implementations, the matching unit is further configured to, after determining the memory attribute corresponding to the memory access request, perform attribute downgrading processing on the memory attribute based on page table attributes or page-based memory type attributes; wherein the attribute downgrading processing includes downgrading a cacheable attribute to a non-cacheable ordinary memory attribute, or downgrading an ordinary memory attribute to a device attribute, and prohibiting the upgrading of device attributes to ordinary memory attributes or cacheable attributes.

[0134] In some implementations, the generation unit, when generating access control information corresponding to the memory access request based on the memory attributes, is configured to: generate bus transaction memory attribute information based on the memory attributes before the memory access request is forwarded to the interconnect module; and control the processor to perform at least one of cached access, access reordering, and speculative access to the memory access request based on the bus transaction memory attribute information; wherein the bus transaction memory attribute information is transmitted along the chip node interconnect path with the memory access request.

[0135] When the routing unit routes a memory access request carrying the access control information based on the target chip node identifier, it is specifically configured to: determine whether the memory access request corresponds to a local chip node access or a remote chip node access based on the target chip node identifier; if the memory access request corresponds to a local chip node access, route the memory access request to the target hardware resource within the local chip node; if the memory access request corresponds to a remote chip node access, forward the memory access request to the target chip node through the chip node interconnection interface.

[0136] In this embodiment, the same memory attribute rule in the aforementioned device can cover hardware resources with the same on-chip offset address range across multiple chip nodes. This reduces the need for redundant configuration of memory attribute rules as the number of chip nodes increases, thus lowering the complexity and maintenance cost of memory attribute configuration. Simultaneously, the processor can determine the memory attribute and generate access control information before a memory access request enters the interconnect path. The interconnect path can be routed based on the target chip node identifier while maintaining the access control information, improving the consistency of access attributes during cross-chip node access. Furthermore, reusing the same on-chip offset address and corresponding memory attribute rules across different chip nodes reduces the need to reserve a large number of independent address ranges for different chip nodes or product forms, improving address space utilization and facilitating the reuse of address layouts and memory attribute configurations between single-die, multi-die, and multi-chip systems.

[0137] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0138] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0139] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0140] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0142] In the above embodiments, the implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0143] The computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0144] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A method for managing memory attributes, characterized in that, The method is applied to a system comprising multiple chip nodes, wherein the chip nodes include dies or chips, and the method includes: Obtain a memory access request initiated by the processor, the memory access request including the physical address to be accessed; The target chip node identifier is determined based on the first address segment in the physical address, and the on-chip offset address within the target chip node is determined based on the second address segment in the physical address. The target chip node identifier is used to identify the target chip node, and at least some hardware resources of multiple chip nodes are set based on the same on-chip offset address. According to the preset memory attribute rules, the target chip node identifier is masked and the on-chip offset address is range matched to determine the memory attribute corresponding to the memory access request. The memory attribute rules are used to make hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attribute. Based on the memory attributes, access control information corresponding to the memory access request is generated. The access control information is used to instruct the processor to execute the memory access request according to the access method corresponding to the memory attributes. Based on the target chip node identifier, memory access requests carrying the access control information are routed to access the target hardware resources in the target chip node.

2. The memory attribute management method according to claim 1, characterized in that, The first address segment is located on the higher side of the second address segment, and the first address segment is used for mask matching of the target chip node identifier and cross-chip node routing; The second address segment is used to represent the on-chip offset address in order to locate the target hardware resource within the target chip node; The target chip node identifier and the on-chip offset address are concatenated to form a globally unified homogeneous address space corresponding to the physical address; In the homogeneous address space, different chip nodes reuse the same on-chip offset address. The same on-chip offset address corresponds to the same hardware resource in different chip nodes, and the same hardware resources in different chip nodes are distinguished by the target chip node identifier. The physical address also includes a third address segment, which is located on the higher side of the first address segment and is a reserved address segment.

3. The memory attribute management method according to claim 1, characterized in that, The step of performing mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules to determine the memory attribute corresponding to the memory access request includes: Based on the node mask field in the preset memory attribute rules, the target chip node identifier is matched by a mask to obtain the node matching result; According to the address range field in the preset memory attribute rules, the on-chip offset address is matched with the address range to obtain the address matching result; If both the node matching result and the address matching result are successful, the attribute field in the preset memory attribute rule is determined as the memory attribute corresponding to the memory access request. If the on-chip offset address falls into a reserved address range, an unmapped address range, or fails to hit any of the preset memory attribute rules, the memory attribute corresponding to the memory access request will be determined as a device attribute, or access control information will be generated to prohibit speculative access. If multiple preset memory attribute rules are matched, the memory attribute corresponding to the memory access request is determined according to the priority of the multiple memory attribute rules. The node mask field is used to match the same memory attribute rule with multiple chip nodes, and the on-chip address range field is used to distinguish different types of hardware resources in the multiple chip nodes. The number of memory attribute rules is related to the number of on-chip attribute partitions, but is not related to the number of multiple chip nodes.

4. The memory attribute management method according to claim 3, characterized in that, The step of performing mask matching on the target chip node identifier according to the node mask field in the preset memory attribute rules to obtain the node matching result includes: Perform a mask operation on the target chip node identifier based on the node mask field; Match the mask operation result with the set of valid chip nodes; If the target chip node identifier belongs to the set of valid chip nodes, the node matching result is determined to be a successful match; If the target chip node identifier does not belong to the set of valid chip nodes, the node matching result is determined to be a matching failure, and the memory access request is prohibited from being forwarded to the chip node interconnection interface.

5. The memory attribute management method according to claim 4, characterized in that, The method further includes: Configure the preset memory attribute rules according to the on-chip attribute partitioning; Configure the chip node identifier field in the preset memory attribute rules as a mask field; Different on-chip attribute partitions are distinguished by the on-chip address range field; The number of preset memory attribute rules is related to the number of on-chip attribute partitions, but is not related to the number of multiple chip nodes.

6. The memory attribute management method according to claim 5, characterized in that, The memory attribute rules include at least one of the following: Rules used to configure the on-chip offset address range corresponding to the on-chip dynamic random access memory as cacheable; Rules used to configure the on-chip offset address range corresponding to on-chip storage resources as non-cacheable ordinary memory attributes; Rules used to configure the on-chip offset address range corresponding to peripheral registers as device attributes; Rules used to configure the on-chip offset address range corresponding to the memory-mapped input / output space as a device attribute.

7. The memory attribute management method according to claim 6, characterized in that, The method further includes: After determining the memory attribute corresponding to the memory access request, the memory attribute is downgraded according to the page table attribute or the page-based memory type attribute. The attribute downgrade process includes downgrading a cacheable attribute to a non-cacheable ordinary memory attribute, or downgrading an ordinary memory attribute to a device attribute, and prohibiting the upgrading of device attributes to ordinary memory attributes or cacheable attributes.

8. The memory attribute management method according to claim 1, characterized in that, The step of generating access control information corresponding to the memory access request based on the memory attributes includes: Before the memory access request is forwarded to the interconnect module, bus transaction memory attribute information is generated based on the memory attributes. Based on the bus transaction memory attribute information, the processor is controlled to perform at least one of cached access, access reordering, and speculative access to the memory access request; wherein the bus transaction memory attribute information is transmitted along the inter-chip node interconnect path with the memory access request; The step of routing memory access requests carrying the access control information based on the target chip node identifier includes: Based on the target chip node identifier, determine whether the memory access request corresponds to a local chip node access or a remote chip node access. When the memory access request corresponds to a local chip node access, the memory access request is routed to the target hardware resource within the local chip node. In the case where the memory access request corresponds to a remote chip node access, the memory access request is forwarded to the target chip node through the chip node interconnect interface.

9. A memory attribute management device, characterized in that, The apparatus is used in a system comprising multiple chip nodes, wherein the chip nodes include dies or chips, and the apparatus includes: The acquisition unit is configured to acquire a memory access request initiated by the processor, the memory access request including a physical address to be accessed; The determining unit is configured to determine a target chip node identifier based on a first address segment in the physical address, and to determine an on-chip offset address within the target chip node based on a second address segment in the physical address, wherein the target chip node identifier is used to identify the target chip node, and at least some hardware resources of a plurality of chip nodes are set based on the same on-chip offset address; The matching unit is configured to perform mask matching on the target chip node identifier and address range matching on the on-chip offset address according to preset memory attribute rules, and determine the memory attribute corresponding to the memory access request. The memory attribute rules are used to make hardware resources with the same on-chip offset address range in different chip nodes correspond to the same memory attribute. The generation unit is configured to generate access control information corresponding to the memory access request based on the memory attributes, wherein the access control information is used to instruct the processor to execute the memory access request according to the access method corresponding to the memory attributes; The routing unit is configured to route memory access requests carrying the access control information based on the target chip node identifier, so as to access the target hardware resources in the target chip node.

10. A chip, characterized in that, The chip includes a processor coupled to a transceiver for executing the memory attribute management method as described in any one of claims 1-8.

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