Incremental dirty data flush for persistent memory

Abstract

A persistent memory device is disclosed. The non-volatile memory device can store data, and the volatile memory device can cache the data. A cache controller can manage access to the non-volatile memory device and the data in the volatile memory device. The persistent memory device may include a storage device for a table that associates a first number of dirty pages of data to be copied from the volatile memory device to the non-volatile memory device with an energy level. A second controller can be configured to copy dirty pages of data from the volatile memory device to the non-volatile memory device, at least in part, based on a second number of dirty pages of data in the volatile memory device exceeding the first number of dirty pages.

Description

[0001] Relevant application data

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 787,697, filed April 11, 2025, which is incorporated herein by reference in its entirety for various purposes. Technical Field

[0003] This disclosure generally relates to persistent memory, and more specifically, to managing dirty data in persistent memory. Background Technology

[0004] Persistent storage devices can include both non-volatile and volatile storage devices. If data written to a persistent storage device is stored in a volatile storage device, the data may be lost in the event of a power outage.

[0005] Data in persistent storage devices still needs to be managed to prevent data loss. Summary of the Invention

[0006] Persistent storage devices can track the number of dirty pages in their volatile storage. When the number of dirty pages exceeds a threshold, the controller of the persistent storage device can copy the page from the volatile storage to non-volatile storage to persist it. Attached Figure Description

[0007] The accompanying drawings described below are examples of how embodiments of this disclosure may be implemented and are not intended to limit the scope of embodiments of this disclosure. Various embodiments of this disclosure may include elements not shown in specific drawings and / or elements shown in specific drawings may be omitted. The drawings are intended to provide illustration and may not be drawn to scale.

[0008] Figure 1 A machine equipped to use a persistent memory device according to an embodiment of the present disclosure is shown.

[0009] Figure 2 An embodiment according to this disclosure is shown. Figure 1 Details of the machine.

[0010] Figure 3A An embodiment according to this disclosure is shown. Figure 1 A version of a persistent storage device.

[0011] Figure 3B An embodiment according to this disclosure is shown. Figure 1 Another version of the persistent storage device.

[0012] Figure 4An embodiment according to this disclosure is shown. Figures 3A to 3B Details of non-volatile storage devices.

[0013] Figure 5A An embodiment according to this disclosure is shown. Figures 3A to 3B A flowchart illustrating an example process of how a cache controller handles requests.

[0014] Figure 5B Continuing with embodiments of this disclosure Figures 3A to 3B A flowchart illustrating an example of how a cache controller processes requests. Figure 5A The flowchart.

[0015] Figure 6 The storage according to embodiments of the present disclosure is shown. Figures 3A to 3B A graph showing the change in the number of dirty pages in a volatile storage device over time.

[0016] Figure 7 An embodiment according to this disclosure is shown. Figures 3A to 3B firmware to Figures 3A to 3B The cache controller issues commands to retrieve data from the cache. Figures 3A to 3B A flowchart illustrating an example process for flushing dirty pages from a volatile storage device.

[0017] Figure 8 The embodiments of the present disclosure are shown with Figure 1 persistent memory device communication Figure 1 The processor.

[0018] Figure 9 The illustration shows the transfer of various quantities of data from... according to embodiments of the present disclosure. Figures 3A to 3B Copying volatile storage devices to Figures 3A to 3B A graph showing how much energy a non-volatile storage device requires, and a table showing how to store this relationship.

[0019] Figure 10 An embodiment according to this disclosure is shown. Figures 3A to 3B The firmware update indicates how many pages can be stored. Figures 3A to 3B A flowchart illustrating an example process for setting a threshold in a volatile storage device.

[0020] Figure 11 An embodiment according to this disclosure is shown. Figure 1 The persistent storage device determines when to remove the page from the memory. Figures 3A to 3B Copying volatile storage devices to Figures 3A to 3B A flowchart illustrating an example process for a non-volatile storage device.

[0021] Figure 12 An embodiment according to this disclosure is shown. Figures 3A to 3BThe firmware is determined to be stored Figures 3A to 3B A flowchart illustrating an example process for determining the number of dirty pages in a volatile storage device.

[0022] Figure 13 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware instructions Figures 3A to 3B The cache controller will retrieve the page from Figures 3A to 3B Copying volatile storage devices to Figures 3A to 3B A flowchart illustrating an example process for a non-volatile storage device.

[0023] Figure 14 An embodiment according to this disclosure is shown. Figures 3A to 3B The cache controller processes data from... Figure 1 processor Figure 8 A flowchart of an example process for a write request.

[0024] Figure 15 An embodiment according to this disclosure is shown. Figure 1 Switching persistent storage devices Figures 3A to 3B A flowchart illustrating an example process for an energy storage device.

[0025] Figure 16 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware updates need to be stored in Figures 3A to 3B A flowchart illustrating an example process for determining the number of dirty pages in a volatile storage device.

[0026] Figure 17 An embodiment according to this disclosure is shown. Figures 3A to 3B The cache controller has been removed from the page. Figures 3A to 3B Copying volatile storage devices to Figures 3A to 3B After updating the non-volatile storage device Figure 6 The flowchart shows an example process for a dirty page counter.

[0027] Figure 18 An embodiment according to this disclosure is shown. Figures 3A to 3B firmware based on Figure 6 The threshold is used to determine when to indicate Figures 3A to 3B The cache controller will retrieve the page from Figures 3A to 3B Copying volatile storage devices to Figures 3A to 3B A flowchart illustrating an example process for a non-volatile storage device.

[0028] Figure 19 An embodiment according to this disclosure is shown. Figures 3A to 3B The firmware determines when to start and stop from Figures 3A to 3B A flowchart illustrating an example process for flushing operations on a volatile storage device.

[0029] Figure 20 An embodiment according to this disclosure is shown. Figure 1 Persistent storage devices refuse to accept data from Figure 1 processor Figure 8 A flowchart of an example process for a write request.

[0030] Figure 21 An embodiment according to this disclosure is shown. Figure 1 persistent storage devices to Figure 1 A flowchart illustrating an example process for the processor or baseboard management controller to report information.

[0031] Figure 22 An embodiment according to this disclosure is shown. Figures 3A to 3B The cache controller from Figures 3A to 3B A flowchart illustrating an example process of evicting pages from a volatile storage device. Detailed Implementation

[0032] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Numerous specific details are set forth in the following detailed description to enable a thorough understanding of the present disclosure. However, it should be understood that those skilled in the art can practice the present disclosure without these specific details. In other instances, well-known methods, processes, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0033] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module.

[0034] The terminology used in the description of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used in the description of this disclosure and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or,” as used herein, refers to and covers any and all possible combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Components and features in the accompanying drawings are not necessarily drawn to scale.

[0035] Computer systems typically employ two methods for managing data: memory and storage devices. Memory is generally fast to access, but it is expensive and usually does not offer persistence. Therefore, data stored in memory may be lost in the event of a power outage. Storage devices, such as hard disk drives and solid-state drives (SSDs), offer large storage capacity and persistence, but they may be relatively slower to access than memory.

[0036] Typically, computer systems attempt to strike a balance between the amount of memory and storage devices available. However, persistent storage devices can offer a balance between the two, supporting storage capacity while providing access speeds closer to those of memory.

[0037] Persistent storage devices can include both volatile and non-volatile storage devices. Non-volatile storage devices are typically where data is stored and provide persistence. When data needs to be read from a non-volatile storage device, the data can be copied to the volatile storage device. In this way, data can be accessed using the speed of the volatile storage device. When the host writes data back to the persistent storage device, the data can be written to the volatile storage device, allowing the persistent storage device to quickly return acknowledgments, and the data can be copied to the non-volatile storage device at a later time.

[0038] However, because persistent storage devices include volatile memory that can be used to store data that has not yet been written to non-volatile memory, persistent storage devices may require some form of backup power. This ensures that, in the event of a power outage to the persistent storage device's mains, the persistent storage device can still copy or persistently save data from volatile memory to non-volatile memory before all power is lost, thus guaranteeing no data loss.

[0039] The size of the backup power required for persistent storage devices can be determined by the amount of volatile storage within the persistent storage device. The larger the volatile storage, the larger the backup power required to support data replication from volatile to non-volatile storage. However, increasing the size of the backup power increases the cost, weight, and complexity of the persistent storage device. On the other hand, while a smaller backup power is considered advantageous, a smaller backup power may force smaller volatile storage devices, potentially causing the persistent storage device to thrash when data is moved between volatile and non-volatile storage.

[0040] Backup power supplies themselves can also degrade over time. While a backup power supply may be sufficient to copy all data from volatile storage to non-volatile storage when it is manufactured, after a few years of use, the power provided by the backup power supply may not be enough to copy all data from volatile storage to non-volatile storage.

[0041] Embodiments of this disclosure attempt to address these problems by tracking the number of dirty pages in the volatile storage device. A dirty page can be understood as a page that has been updated in the volatile storage device but whose update has not yet been persistently saved to the non-volatile storage device. Dirty pages can be contrasted with clean pages, which are pages that have not been updated since they were loaded from the non-volatile storage device into the volatile storage device. This comparison of dirty and clean pages can be considered analogous to how pages in a cache are considered dirty or clean. The persistent storage device can know how much power a backup power source (which may also be referred to as an energy storage unit) can provide at any given time. The persistent storage device can then determine how much data can be copied from the volatile storage device to the non-volatile storage device using that power, and can manage the number of dirty pages in the volatile storage device to avoid exceeding this amount of dirty data in the volatile storage device.

[0042] Embodiments of this disclosure enable persistent memory devices to flush dirty pages from volatile memory to non-volatile memory conveniently or when necessary, ensuring that the backup power supply has sufficient power to perform such flushing operations.

[0043] Embodiments of this disclosure enable persistent storage devices to initiate and halt the flushing operation of dirty data from volatile storage to non-volatile storage in an attempt to optimize overall latency. Therefore, when the amount of dirty data in the volatile storage is relatively low, the flushing operation can be paused, allowing read and write requests from the host processor to take priority. On the other hand, if the number of dirty pages in the volatile storage is too large for the power available from the backup power supply, the persistent storage device can reject requests from the host processor (or at least reject new write requests) until the number of dirty pages decreases to a level where the available power from the backup power supply can be used for flushing.

[0044] Embodiments of this disclosure enable the use of different backup power supplies, volatile storage elements, and non-volatile storage elements. A persistent storage device may include a table that can correlate the amount of electricity required to copy various amounts of data from a volatile storage device to a non-volatile storage device based on the included elements. Therefore, embodiments of this disclosure allow for more general-purpose persistent storage devices that can operate regardless of the type of backup power supply or the amount of power provided by the backup power supply, the type or size of the volatile storage device, or the type or size of the non-volatile storage device.

[0045] Figure 1 A machine equipped to use a persistent memory device according to an embodiment of the present disclosure is shown. Figure 1 In this context, machine 105 (also referred to as a host or system) may include processor 110, memory 115, and storage device 120. Although Figure 1 A storage device 120 is shown, but embodiments of this disclosure may include any number of storage devices 120.

[0046] Processor 110 (which may also be referred to as a host processor) can be any type of processor. (For ease of illustration, processor 110 and other components discussed below are shown external to the machine: embodiments of this disclosure may include these components internally.) Although Figure 1 A single processor 110 is shown, but the machine 105 may include any number (one or more, but not limited to) of processors, each of which may be a single-core or multi-core processor, each of which may implement a Reduced Instruction Set Computer (RISC) architecture or a Complex Instruction Set Computer (CISC) architecture (and other possibilities), and may be mixed in any desired combination.

[0047] Processor 110 may be coupled to memory 115. Memory 115 (which may also be referred to as main memory) may be any type of memory, such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM), such as magnetoresistive random access memory (MRAM), etc. Memory 115 may also be any desired combination of different memory types and may be managed by memory controller 125. Memory 115 may be used to store data that can be referred to as "short-term": that is, data that is not expected to be stored for extended periods. Examples of short-term data may include temporary files, data used locally by the application (which may have been copied from other storage locations), etc.

[0048] Processor 110 and memory 115 can also support various applications running on top of them. These applications can issue requests (which may also be referred to as commands) to read data from or write data to memory 115 or storage device 120. While memory 115 can be used to store data considered "short-term," storage device 120 can be used to store data considered "long-term": that is, data expected to be retained for a longer period of time and should be persistently retained even if power supply to machine 105 is interrupted. Storage device 120 can be accessed using device driver 130. Although Figure 1 A device driver 130 is shown for managing access to storage device 120, but embodiments of this disclosure may include more than one device driver 130, each device driver for managing access to different storage devices 120, or a single device driver 130 may be used to manage access to all storage devices 120.

[0049] Storage device 120 may be associated with an accelerator. Such an accelerator can be used for, for example, near-data processing. That is, the accelerator can be used to process data closer to storage device 120 to reduce or eliminate data transfer from storage device 120 to memory 115. The use of an accelerator for near-data processing can also offload processing from processor 110, as the accelerator can perform such processing in place of processor 110. Like processor 110, such an accelerator can implement a Reduced Instruction Set Computer (RISC) architecture or a Complex Instruction Set Computer (CISC) architecture (among other possibilities), and can be implemented, for example, using a Central Processing Unit (CPU), Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), System-on-Chip (SoC), Graphics Processing Unit (GPU), General Purpose GPU (GPGPU), Neural Processing Unit (NPU), or Tensor Processing Unit (TPU).

[0050] The combination of storage device 120 and the accelerator may also be referred to as a computing storage device, a computing storage unit, or a computing device. Storage device 120 and the accelerator may be designed and manufactured as a single integrated unit, or the accelerator may be separate from storage device 120. The phrase "associated with" is intended to cover both a single integrated unit including the storage device and the accelerator, and both storage devices paired with an accelerator but not manufactured as a single integrated unit. In other words, they may be said to be "paired" when the storage device and the accelerator are physically separate devices but connected in a way that allows them to communicate with each other. Furthermore, throughout the remainder of this document, any reference to storage device 120 may be understood as a reference to both storage device 120 and the accelerator, which are either physically separate but paired (and therefore may include another device), or integrated into a single component as a computing storage unit.

[0051] Although Figure 1 The term "storage device" is used, but embodiments of this disclosure may include any type of storage device, examples of which may include hard disk drives (HDDs) and solid-state drives (SSDs). In some embodiments of this disclosure, storage device 120 may also be a type of storage device that can operate in combination with or in conjunction with an accelerator or certain other types of near-memory processors (computing storage devices). Additionally, in a system including multiple storage devices 120, the storage devices 120 may be of the same or different types. For example, one storage device 120 may be an SSD, while another storage device 120 may be a hard disk drive (HDD). Any references below to a specific type of storage device, such as "SSD," should be understood to include such other embodiments of this disclosure.

[0052] Processor 110 and storage device 120 can cross the fabric ( Figure 1 (Not shown in the diagram) communicates. This structure can be any structure along which information can be passed. Such a structure can include structures that are internal to machine 105 and can use interfaces such as Peripheral Component Rapid Interconnect (PCIe), Serial AT Accessory (SATA), or Small Computer System Interface (SCSI). Such structures can also include structures that are external to machine 105 and can use interfaces such as Ethernet, Unlimited Bandwidth, or Fibre Channel. Additionally, such a structure can support one or more protocols, such as Fast Non-Volatile Memory (NVMe), Architectural NVMe (NVMe-oF), Simple Service Discovery Protocol (SSDP), or Cache Coherent Interconnect protocols such as Compute Fast Link® (CXL®) protocol. (Compute Fast Link and CXL are registered trademarks of the Compute Fast Link Consortium.) Therefore, such a structure can be considered to include both internal and external network connections through which commands can be sent directly or indirectly to storage device 120. In embodiments of this disclosure where such a structure supports external networking connections, storage device 120 can be located external to machine 105, and storage device 120 can receive requests from a processor remote from machine 105.

[0053] In addition to (or in place of) memory 115 and storage device 120, machine 105 may include persistent memory device 135. The persistent memory device may be a combination of volatile storage devices (such as memory 115) and non-volatile storage devices (such as storage device 120). That is, persistent memory device 135 can combine the capabilities of both memory 115 and storage device 120. The persistent memory device can provide access times similar to those of memory 115, but can provide storage capacity similar to that of storage device 120. Therefore, persistent memory device 135 can achieve the best of both worlds. (See below for reference.) Figures 3A to 3B Further details of persistent memory device 135 will be discussed.

[0054] In some embodiments of this disclosure, persistent memory device 135 may support a cache coherent interconnect protocol. In some embodiments of this disclosure, the cache coherent interconnect protocol may be the Compute Fast Link® (CXL®) protocol. (Compute Fast Link and CXL are registered trademarks of the Compute Fast Link Consortium.) Therefore, persistent memory device 135 may use protocols such as CXL.io, CXL.mem, and / or CXL.cache to access data. For example, persistent memory device 135 may use only the CXL.mem protocol for access, where persistent memory device 135 presents its entire address space as an extension (or replacement) of memory 115.

[0055] Figure 2 An embodiment according to this disclosure is shown. Figure 1 Details of machine 105. Figure 2 Typically, machine 105 includes one or more processors 110, which may include a memory controller 125 and a clock 205, which can be used to coordinate the operation of the machine's components. Processor 110 may also be coupled to memory 115, which, for example, may include random access memory (RAM), read-only memory (ROM), or other state-saving media. Processor 110 may also be coupled to storage device 120 and to network connector 210, which may be, for example, an Ethernet connector or a wireless connector. Processor 110 may also be connected to bus 215, and user interface 220 and input / output (I / O) interface ports, I / O interface ports that can be managed by I / O engine 225, and other components may be attached to bus 215.

[0056] Figure 3A An embodiment according to this disclosure is shown. Figure 1 A version of the persistent storage device 135. Figure 3AIn the diagram, persistent memory device 135 is shown as including various elements. Persistent memory device 135 may include connector 305, which enables persistent memory device 135 to connect to… Figure 1 The processor 110 communicates. Connector 305 can also provide main power to persistent memory device 135, although in some embodiments of this disclosure, this can be achieved across a second connector separate from connector 305 (in... Figure 3A (Not shown) provides main power to persistent storage device 135.

[0057] Power can be received and delivered to voltage regulator 310, as shown by line 315. Voltage regulator 310 can regulate the voltage to the voltage defined for other components of persistent memory device 135 in the specification of persistent memory device 135. For example, the voltage received across connector 305 can be 12 volts (V), 5 V, 3.3 V, or any other voltage, but the components of persistent memory device 135 can expect voltages of 1.1 V, 3.3 V, 0.8 V, or any other voltage. Voltage regulator 310 can ensure that the power delivered to the rest of persistent memory device 135 is at the expected voltage level, regardless of the actual voltage supplied to persistent memory device 135.

[0058] In addition to supplying power to voltage regulator 310, line 315 can also supply power to power interruption detector 320. Power interruption detector 320 can determine whether the main power to persistent storage device 135 has been interrupted, allowing persistent storage device 135 to switch to backup power provided by energy storage unit 325. Power interruption detector 320 may include circuit(s) and controller(s) using electrical signals such as pulses or level changes. Such pulses or level changes can be monitored by digital logic (such as controller(s)) to take appropriate action based on the power changes detected using pulses or level changes.

[0059] Energy storage unit 325 can be powered from any desired backup power source: for example, batteries such as lithium-ion (Li-ion) batteries, capacitors, or solid-state batteries. Furthermore, energy storage unit 325 can include multiple backup power sources. For example, energy storage unit 325 can include multiple batteries or capacitors, each of which can be of the same or different type. Thus, for example, energy storage unit 325 can include a solid-state battery, a lithium-ion battery, and a capacitor.

[0060] When a mains power outage is detected (this could be due to the administrator shutting down...), Figure 1As a result of the interruption of power supply to the persistent storage device 135 (either a temporary halt to power delivery to the persistent storage device 135 or a long-term termination of main power to the persistent storage device 135), the power interruption detector 320 can send a signal to the remainder of the persistent storage device 135 to begin using the backup power provided by the energy storage unit 325. This signal, which can travel along line 330, can instruct the voltage regulator 310 to begin receiving power from the energy storage unit 325 instead of from the main power supplied across connectors (such as connector 305). The voltage regulator 310 can still regulate the voltage received from the energy storage unit 325 to ensure that the remainder of the persistent storage device 135 receives the appropriate amount of power as desired by the remainder of the persistent storage device 135.

[0061] Regardless of the power source (main power or energy storage 325), the internal voltage rail 335 can deliver power from the voltage regulator 310 to the rest of the persistent storage device 135.

[0062] The persistent memory device 135 may also include a volatile storage device 340 and a non-volatile storage device 345. The volatile storage device 340, such as DRAM, can be a relatively faster form of storage device compared to the non-volatile storage device 345, which may be, for example, an SSD or a hard disk drive. However, the non-volatile storage device 345 can have a relatively larger capacity than the volatile storage device 340. Therefore, the persistent memory device 135 can use the volatile storage device 340 as a cache for data stored on the non-volatile storage device 345, thereby providing faster access to the data stored on the non-volatile storage device 345. Thus, the persistent memory device 135 can effectively provide a capacity equivalent to that of the non-volatile storage device 345, but with access speeds closer to those of the volatile storage device 340, thus providing a potentially superior combination of solutions. (Obviously, using DRAM (which serves as a volatile storage device 340 with a capacity equal to that of an SSD) as a non-volatile storage device 345 would be the ideal solution, but considering the cost of DRAM, using only DRAM would be significantly more expensive than using a combination of DRAM and SSD. Furthermore, since DRAM does not persistently store data, the form of a non-volatile storage device 345 is still needed to persistently retain the data. Therefore, when considering the combination of cost, capacity, access speed, and data persistence, the solution provided by the persistent memory device 135 is likely superior to alternative solutions.)

[0063] The persistent memory device 135 may also include circuitry 350. Circuitry 350 can be any type of circuitry: for example, an FPGA or an ASIC. Circuitry 350 can be responsible for managing the operation of the persistent memory device 135, including accessing data across connector 305. Figure 1 The processor 110 requests data and controls when to flush data from volatile storage device 340 to non-volatile storage device 345. In this context, "flushing data" can be understood as copying data from volatile storage device 340 to non-volatile storage device 345. If power is interrupted, there is no need to actually remove data from volatile storage device 340, because the data will be erased once persistent storage device 135 loses all power. Circuitry 350 may include endpoint 355, which can cross connector 305 from... Figure 1 The processor 110 receives the request. Circuitry 350 may also include a cache controller 360, which can manage whether data is copied to volatile storage device 340. For example, when... Figure 1 When the processor 110 issues a request to read data, the cache controller 360 can determine whether the data is currently stored in the volatile memory device 340. If the data in question is currently stored in the volatile memory device 340, the cache controller 360 can return the data from the volatile memory device 340; otherwise, the cache controller 360 can read the data from the non-volatile memory device 345 and return the data. Figure 1 The processor 110 stores the data in volatile storage device 340 for later use. Similarly, when Figure 1 When the processor 110 issues a request to write data, the cache controller can store the data in volatile storage device 340, and the persistent storage device 135 can later copy the data to non-volatile storage device 345 to ensure the data is persisted. Note that, in addition to the data already written by the processor 110, the cache controller can store the data in volatile storage device 340, and the persistent storage device 135 can later copy the data to non-volatile storage device 345 to ensure the data is persisted. Figure 1 In addition to the data written by the processor 110 to the persistent memory device 135, any data currently stored in the volatile memory device 345 can be assumed to also be stored in the non-volatile memory device 345 and thus persisted in case of power interruption.

[0064] As implied above, ensure that by Figure 1 It may be important that the data written by the processor 110 is persistently stored in the non-volatile storage device 345. Therefore, the cache controller 360 can track information such as which data pages stored in the volatile storage device 340 are currently dirty (already contaminated by...). Figure 1The data written by the processor 110 but not yet persistently stored in the non-volatile storage device 345 (i.e., data that is also persistently stored in the non-volatile storage device 345) or clean data. For example, the cache controller 360 may include a storage device that can store a bitmap, where one bit corresponds to each page in the volatile storage device 340. (In some embodiments of this disclosure, the bitmap may be stored in the non-volatile storage device 345; in other embodiments of this disclosure, the cache controller 360 may access the bitmap from another storage device.) If the value of any individual bit in the bitmap is one, the corresponding page in the volatile storage device 340 is dirty; otherwise, the value of the bit is zero, and the corresponding page in the volatile storage device 340 is clean. Therefore, in order to mark a page as dirty, the cache controller 360 may set the bit corresponding to that page in the volatile storage device 340 to one. Note that even though the volatile storage device 340 is relatively large, the size of the bitmap is still a small proportion relative to the overall size of the volatile storage device 340. For example, if the volatile storage device 340 is 32GB and each page is 4 kilobytes (KB), then the bitmap requires 1 megabyte (MB) (2 32 Byte capacity ÷ 4096 bytes per page = 8,388,608 pages: one bit per page, 8,388,608 bits = 1,048,576 bytes, or 1 MB, or 0.003% of the total capacity of volatile storage device 340.

[0065] The cache controller 360 can also track a dirty page counter: the number of dirty pages in the volatile storage device 340, because the number of dirty pages in the volatile storage device 340 may affect whether and / or when dirty data is flushed from the volatile storage device 340 to the non-volatile storage device 345.

[0066] The above discussion implies that the cache controller 360 can be responsible for flushing data from the volatile storage device 340 (i.e., copying dirty pages from the volatile storage device 340 to the non-volatile storage device 345). In some embodiments of this disclosure, the cache controller 360 may perform this function. However, in other embodiments of this disclosure, this function may be handled by a separate controller independent of the cache controller 360. In some embodiments of this disclosure, this second controller may even be external to the persistent memory device 135.

[0067] Note that since volatile storage device 340 can act as a cache for non-volatile storage device 345, pages stored in volatile storage device 340 can be referred to as cached pages. The terms "page" and "cache page" can be understood as synonymous, at least when referring to volatile storage device 340.

[0068] Firmware 365 can be used to manage when dirty data is flushed from volatile storage device 340 to non-volatile storage device 345. Firmware 365 may include logic for determining when to instruct cache controller 360 to flush dirty data from volatile storage device 340 to non-volatile storage device 345. This logic may take into account the current energy level provided by energy storage unit 325 and the number of dirty pages stored in volatile storage device 340 (which, as described above, can be tracked by cache controller 360). Firmware 365 may be stored in storage device 370, which may also store a table that correlates the amount of data that can be copied from volatile storage device 340 to non-volatile storage device 345 with the power required to complete such a copy operation. (See below for reference.) Figure 9 Let's discuss this table further.

[0069] Ideally, energy storage unit 325 will always provide the same amount of power. However, in the real world, batteries and other power storage components may degrade over time, providing less and less power. Therefore, circuitry 350 may include monitor circuitry 375, which can periodically check the health status of energy storage unit 325 via line 380. Monitor circuitry 375 can query energy storage unit 325 for its currently stored power, and this information can then be returned from energy storage unit 325 to monitor circuitry 375. Firmware 365 can then use this information, in conjunction with a table stored in storage device 370, to determine how many dirty pages can be stored in volatile storage device 340 (because persistent storage device 135 can attempt to limit the number of dirty pages in volatile storage device 340 to no more than the number of dirty pages that persistent storage device 135 can guarantee to copy to non-volatile storage device 345 based on the available power in energy storage unit 325).

[0070] exist Figure 3A In this diagram, volatile storage device 340 and non-volatile storage device 345 are shown as being external to circuit 350. Therefore, for communication with non-volatile storage device 345, circuit 350 may include ports, such as root port 385, which can initiate communication with non-volatile storage device 345. Root port 385 can be considered as the root of a tree for communicating with other devices, each of which may include an endpoint, such as endpoint 355. However, in some embodiments of this disclosure, volatile storage device 340 and non-volatile storage device 345 may be part of circuit 350, such as... Figure 3B As shown.

[0071] Figure 3B An embodiment according to this disclosure is shown. Figure 1 Another version of the persistent memory device 135. Figure 3BIn, with Figure 3A In contrast, circuit 350 may include volatile storage device 340 and non-volatile storage device 345. Although Figure 3B It did not indicate relative to Figure 3A Aside from the location of the volatile storage device 340 and the non-volatile storage device 345, no changes have been made to the volatile storage device 340 and the non-volatile storage device 345, although some changes may actually exist. For example, instead of including the non-volatile storage device 345 "entirely," various components of the non-volatile storage device 345 can be directly included in the circuit 350, which avoids changes to... Figure 3A The root port 385 is required (because the cache controller 360 can communicate directly with other components of the non-volatile memory device 345). See below for reference. Figure 4 Let’s discuss these other components further.

[0072] Although Figures 3A to 3B Two variations of the persistent memory device 135 are shown—one including a volatile memory device 340 and a non-volatile memory device 345 as part of circuitry 350, both of which are separate from circuitry 350—but embodiments of this disclosure can support any desired combination (where one of the volatile memory device 340 and the non-volatile memory device 345 is included in circuitry 350, but the other is not). Additionally, depending on the desired implementation, some components of the volatile memory device 340 and / or the non-volatile memory device 345 may be part of circuitry 350, but other components may not be part of circuitry 350. Embodiments of this disclosure are intended to include all such variations. Furthermore, although... Figures 3A to 3B All components that are part of the persistent memory device 135 are shown, but embodiments of this disclosure may have some elements external to the persistent memory device 135. For example, an energy storage unit 325 may be external to the persistent memory device 135, with appropriate connections between the persistent memory device 135 and the energy storage unit 325 such that the persistent memory device 135 is powered even if the main power is interrupted.

[0073] The above description indicates that the instruction from firmware 365 to flush dirty cache pages from volatile storage device 340 to non-volatile storage device 345 can be similar to that from... Figure 1 The processor 110 receives the request and processes it. While some embodiments of this disclosure can operate in this manner, other embodiments of this disclosure can execute instructions from firmware 365 to copy dirty cache pages from volatile storage device 340 to non-volatile storage device 345 as a background operation. Therefore, these embodiments of this disclosure may be preferred from Figure 1The processor 110 requests a request, thereby attempting to reduce the persistent memory device 135 on behalf of. Figure 1 The time required for processor 110 to process a request. However, it is worth noting that prioritizing host requests may increase the number of dirty cache pages in volatile storage device 340, which could have negative effects, such as potentially causing persistent storage device 135 to reject requests from... Figure 1 The write requests of processor 110 are as follows (see reference below). Figure 8 The subject of discussion.

[0074] Figure 4 An embodiment according to this disclosure is shown. Figures 3A to 3B Non-volatile storage device 345 (or Figure 1 Details of the storage device 120. Figure 4 The embodiments described herein use an implementation including an SSD and illustrate a non-volatile storage device 345, but the embodiments of this disclosure are applicable to any type of storage device that can support data caching, as described below.

[0075] The non-volatile storage device 345 may include an interface 405 and a host interface layer 410. The interface 405 may be used to connect the non-volatile storage device 345 to... Figure 1 The interface of machine 105. Examples of such interfaces may include Serial AT Accessory (SATA), mSATA, Serial Connect Small Computer System Interface (SCSI) (SAS), Non-Volatile Fast Memory (NVMe), Peripheral Component Rapid Interconnect (PCIe), U.2, M.2, and Enterprise and Data Center Standard Form Factor (EDSFF); other interfaces are also possible. Non-volatile storage device 345 may include more than one interface 405: for example, one interface may be used for block-based read and write requests, and another interface may be used for key-value read and write requests. Although Figure 4 This indicates that interface 405 is Figure 1The interface 405 represents the physical connection between the non-volatile storage device 345 and the machine 105, but it can also represent protocol differences that can be used across a common physical interface. For example, the non-volatile storage device 345 can be connected to the machine 105 using a U.2, EDSFF, or M.2 connector, and the non-volatile storage device 345 can support block-based requests, byte-based requests, and / or key-value requests, such as those provided using CXL.io, CXL.mem, or key-value protocols: handling different types of requests can be performed by different interfaces 405. The non-volatile storage device 345 may also include a single interface 405, which may include multiple ports, each of which may be considered a separate interface 405, or simply a single interface 405 with a single port, and the interpretation of information received through interface 405 is left to another element, such as the SSD controller 415.

[0076] The host interface layer 410 manages the interface 405, thereby providing an interface between the SSD controller 415 and external connections to the non-volatile storage device 345. If the non-volatile storage device 345 includes more than one interface 405, a single host interface layer 410 can manage all interfaces. The non-volatile storage device 345 may include a host interface layer 410 for each interface, or some combination thereof.

[0077] The non-volatile storage 345 may also include an SSD controller 415 and various flash memory chips 420-1 to 420-8, which may be organized along channels 425-1 to 425-4. The flash memory chips 420-1 to 420-8 may be collectively referred to as flash memory chip 420, and may also be referred to as flash chip, memory chip, NAND chip, chip, or die. Channels 425-1 to 425-4, which may also be referred to as flash channels, may be collectively referred to as channel 425.

[0078] SSD controller 415 can manage the sending of read and write requests to flash memory chip 420 along channel 425. SSD controller 415 may also include flash memory controller 430, which can be responsible for issuing commands to flash memory chip 420 along channel 425. In embodiments of this disclosure where storage device 120 uses technologies other than flash memory chip 420 to store data, flash memory controller 430 may also be more generally referred to as memory controller 430. Although Figure 4Eight flash memory chips 420, four channels 425, and a flash memory controller 430 are shown, but embodiments of this disclosure may include any number (one or more, without limitation) of channels 425, which include any number (one or more, without limitation) of flash memory chips 420 and any number (one or more, without limitation) of flash memory controllers 430.

[0079] Within each flash memory chip or die, space can be organized as planes. These planes can include multiple erase blocks (also referred to as blocks), which can be further subdivided into word lines. A word line can include one or more pages. For example, a word line for a three-level cell (TLC) flash memory medium can include three pages, while a word line for a multi-level cell (MLC) flash memory medium can include two pages. In some embodiments of this disclosure, a page can be the smallest unit of data that can be written to or read from the non-volatile memory device 345; in other embodiments of this disclosure, the smallest unit of data that can be written to or read from the non-volatile memory device 345 may be different from the size of a page.

[0080] Erasable blocks can also be logically grouped together by the SSD controller 415, which may be referred to as a superblock. This logical grouping allows the SSD controller 415 to manage the group as a whole, rather than managing each block individually. For example, a superblock may include one or more erase blocks from each plane of each die in the storage device 120. Thus, for example, if the storage device 120 includes eight channels, two dies per channel, and four planes per die, then the superblock may include 8 × 2 × 4 = 64 erase blocks.

[0081] The SSD controller 415 may also include a flash translation layer (FTL) 435 (which may be more generally referred to as a translation layer for storage devices that do not use flash memory). The FTL 435 can handle logical block addresses (LBAs) or other logical IDs (such as...). Figure 1 The FTL 435 is responsible for translating data from the processor 110 to physical block addresses (PBAs) or other physical addresses where data is stored in the flash memory chip 420. The FTL 435 can also be responsible for tracking data as it is relocated from one PBA to another, as may occur during garbage collection and / or wear leveling.

[0082] Although Figure 4 The SSD controller 415 is shown as including a flash memory controller 430 and a flash translation layer 435, but embodiments of this disclosure may have any, some, or all of these elements located outside the SSD controller 415 without loss of generality.

[0083] In the like above Figure 3B In the embodiments of this disclosure shown (where the components of the non-volatile storage device 345 may be...) Figure 3B (part of circuit 350) Figure 3B The cache controller 360 can communicate directly with the SSD controller 415 and its components, which allows for the omission of... Figure 3A The root port is 385.

[0084] Figures 5A to 5B An embodiment according to this disclosure is shown. Figures 3A to 3B A flowchart illustrating an example of how the 360 ​​cache controller processes requests. Figure 5A In the middle, at position 505, Figures 3A to 3B The cache controller 360 can determine whether the request is a host write operation, and at box 510, Figures 3A to 3B The cache controller 360 can determine whether the request is a firmware flush command. If the request is neither a host write operation nor a firmware flush command, then at box 515, Figures 3A to 3B The Cache Controller 360 can handle requests as would normally be expected.

[0085] If the request is a host write operation, then in box 520 ( Figure 5B ) place, Figures 3A to 3B The 360 ​​cache controller can be used to... Figure 1 The processor 110 receives and writes the data. Figures 3A to 3B In the cache pages of the volatile storage device 340. At box 525, Figures 3A to 3B The Cache Controller 360 can mark cached pages on the device as dirty. For example, as referenced above. Figures 3A to 3B The subject of discussion Figures 3A to 3B The cache controller 360 may include a bitmap, wherein one bit corresponds to Figures 3A to 3B Each page in the volatile storage device 340, and can be written to Figures 3A to 3B The cache page bit of the non-volatile storage device 345 is set to 1 to indicate that the corresponding cache page is dirty. Finally, at box 530, Figures 3A to 3B The cache controller 360 can increment the dirty page counter, which can... Figures 3A to 3B The total number of dirty pages in the volatile storage device 340 is counted. Note that this dirty page counter may simply be a count of the number of bits in the bitmap described above that have a value set to 1. Then, the processing of the request is completed.

[0086] It is worth noting that there may be cases where box 530 can be omitted. For example, consider... Figure 1 The processor 110 sends to the processor in a shorter sequence. Figure 1 The persistent storage device 135 sends two write requests for the same logical address. If Figure 1 The persistent storage device 135 has not yet flushed the data written in the first write request to... Figures 3A to 3B If the non-volatile storage device 345 is used, then the second write request remains unchanged. Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340: The second write request simply replaces the old dirty page with the new dirty page. Therefore, the total number of dirty pages remains unchanged, and Figures 3A to 3B The cache controller 360 should not increment the dirty page counter. Figures 3A to 3B The cache controller 360 can check the current write operation. Figures 3A to 3B The bitmap associated with the pages of the volatile storage device 340 determines whether this has occurred: if the bitmap reflects that the page currently being written to has been marked as dirty, then the number of dirty cache pages in the volatile storage device 340 has not actually changed, and Figures 3A to 3B The cache controller 360 should not increment the dirty page counter.

[0087] On the other hand, if the request is a firmware flash command, then at box 535, Figures 3A to 3B The 360 ​​cache controller is optional. Figures 3A to 3B Dirty cache pages in volatile storage device 340, and can be flushed to Figures 3A to 3B 345. Note that... Figures 3A to 3B The cache controller 360 can use any desired method to select dirty cache pages to flush. For example, Figures 3A to 3B The cache controller 360 may include an eviction policy that can be used to select... Figures 3A to 3B The cache pages (dirty or clean) in the volatile storage device 340 are evicted to make room for new cache pages. Such an eviction policy can use, for example, Least Recently Used (LRU) or Least Frequently Used (LFU) eviction policies or other eviction algorithms. Figures 3A to 3B The cache controller 360 can use an eviction policy to identify dirty cache pages closest to the top of the eviction list (note that the eviction list can also include clean cache pages that do not need to be flushed), and then flush those dirty cache pages. The principle behind this policy is that when the most likely dirty cache page to be evicted is removed from the cache list... Figures 3A to 3B When a dirty cache page is evicted from volatile storage device 340, it is necessary to flush the dirty cache page regardless of the circumstances. Therefore, selecting the dirty cache page to flush may have implications for... Figure 1The operation of persistent memory device 135 has minimal impact. However, any strategy can be used to select dirty cache pages to flush: for example, Figures 3A to 3B The Cache Controller 360 can randomly select dirty cache pages (based on reflection). Figures 3A to 3B Which cache pages in the volatile storage device 340 are clean or dirty bitmaps).

[0088] At box 540, Figures 3A to 3B The 360 ​​cache controller has flushed dirty cache pages to... Figures 3A to 3B After the non-volatile storage device 345, Figures 3A to 3B The 360 ​​cache controller can mark cached pages as clean (because the data has been flushed to the cache). Figures 3A to 3B The non-volatile storage device 345, so the data is no longer considered dirty. Finally, at box 545, Figures 3A to 3B The cache controller 360 can decrement the dirty page counter because... Figures 3A to 3B A dirty page is missing from the volatile storage device 340. Then the processing of the request is completed.

[0089] Figure 6 The storage according to embodiments of the present disclosure is shown. Figures 3A to 3B A graph showing the change in the number of dirty pages in the volatile storage device 340 over time. Figure 6 Figure 605 is shown, which is a graph of the dirty page counter over time: that is, graph 605 can represent the cache's performance relative to time. Figures 3A to 3B The number of dirty pages in the volatile storage device 340. It can be seen that the dirty page counter 610 can change over time, as... Figure 1 The processor 110 issues a request and as Figures 3A to 3B Firmware 365 issues commands to remove dirty data from Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345 rises and falls.

[0090] As in Figure 6 As can be seen, three thresholds can be established. Given... Figures 3A to 3B The energy storage unit 325 has currently available power, and the maximum threshold of 615 can represent the energy that can be cached. Figures 3A to 3B The maximum number of dirty pages in the volatile storage device 340. For Figures 3A to 3B A given level of available power in energy storage 325 can exist that can be used from... Figures 3A to 3B The volatile storage device 340 persistently saves to Figures 3A to 3BThe maximum number of pages corresponding to the non-volatile storage device 345: The maximum threshold 615 can be set to the maximum number of pages that can be persistently stored using the available power at that level. See below for reference. Figure 9 Further discussion Figures 3A to 3B The relationship between the available power level in the energy storage unit 325 and the maximum number of dirty pages that the available power level can sustainably retain. However, other embodiments of this disclosure may use other methods to determine the maximum threshold 615.

[0091] If the dirty page counter 610 exceeds the maximum threshold 615, then take into account Figures 3A to 3B The energy storage unit has 325 units of usable electricity. Figure 1 The persistent memory device 135 may not be able to guarantee that all dirty pages can be retrieved from it. Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345. Therefore, when the dirty page counter 610 reaches the maximum threshold 615, Figure 1 The persistent memory device 135 can stop accepting data from... Figure 1 The processor 110's write requests (to ensure) Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340 will not increase further. For example... Figure 1 The persistent storage device 135 may report itself as busy, or may discard write requests, which could force... Figure 1 The processor 110 reissues the write request after the timeout, or makes... Figure 1 The persistent storage device 135 delays the execution of received write requests until the dirty page counter 610 falls below the maximum threshold 615 again. Then, when the dirty page counter 610 falls below the maximum threshold 615, Figure 1 The persistent memory device 135 can begin accepting data from [other sources]. Figure 1 Write requests to processor 110.

[0092] Figures 3A to 3B Firmware 365 can also select two other thresholds to attempt to prevent the dirty page counter 610 from reaching the maximum threshold 615. The high threshold 620 can indicate the level at which the persistent memory device 135 of FIG3 begins to approach its maximum storage for dirty cache pages. Therefore, when the dirty page counter 610 rises above the high threshold 620 (i.e., when the dirty page counter 610 increases beyond the high threshold 620),... Figures 3A to 3B Firmware 365 can begin to... Figures 3A to 3B The cache controller 360 issues a flush command in an attempt to prevent... Figures 3A to 3BThe number of dirty cache pages in the volatile storage device 340 grows too rapidly (and, if possible, the dirty page counter 610 is kept below the maximum threshold 615). The high threshold 620 can be set in any desired manner: for example, as a percentage of the maximum threshold 615 (e.g., 70%).

[0093] Finally, the low threshold of 625 can indicate... Figure 1 The number of dirty cache pages in persistent storage device 135 is at a relatively low level. The low threshold 625 can be set in any desired manner: for example, as a percentage of the maximum threshold 615 (e.g., 30%). While having a low dirty page counter 610 is not inherently bad, continuing to move dirty pages from... Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345 may be worthless. For example, if Figure 1 If the processor 110 frequently issues write requests to update previously written data, then the data will be repeatedly transferred from... Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345 may cause unnecessary data to be written. Figures 3A to 3B 345. Non-volatile storage device. If Figures 3A to 3B If the non-volatile storage device 345 takes the form of having a limited programmable / erase count, such as an SSD, then these unnecessary flushes may cause... Figures 3A to 3B The non-volatile storage device 345 wears out earlier than necessary, thus attempting to minimize wear and tear. Figures 3A to 3B The number of programming / erase cycles used in the non-volatile storage device 345 (and hopefully increasing) Figures 3A to 3B (The lifespan of the non-volatile storage device 345). Additionally, when the dirty page counter 610 is low, data is transferred from... Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345 may delay from Figure 1 The processing operations of processor 110 may affect Figure 1 The processor 110 has a negative impact. Therefore, when the dirty page counter 610 drops below the low threshold 625 (i.e., when the dirty page counter drops below the low threshold 625). Figures 3A to 3B Firmware 365 can stop issuing flush commands to reduce... Figures 3A to 3BThe load on the cache controller 360. Note the symmetry between the use of the high threshold 620 and the low threshold 625: the flush command can start or stop when the dirty page counter 610 first crosses the high threshold 620 or the low threshold 625 in the appropriate direction. Another use of the low threshold 625 is to avoid thrashing behavior of data flush operations near the high threshold 620 when the maximum threshold 615 and the low threshold 625 are not used.

[0094] To repeat earlier points, the dirty page counter 610 only tracks... Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340. Therefore, although Figures 3A to 3B The total number of cached pages in the volatile storage device 340 may be higher than the dirty page counter 610, but the pages stored in... Figures 3A to 3B Clean cache pages in the volatile storage device 340 are not counted in the dirty page counter 610, and therefore do not trigger (or stop) the removal of dirty data from the cache. Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B 345. Non-volatile storage device.

[0095] In some embodiments of this disclosure, the high threshold 620 and the low threshold 625 can be calculated as a function of the maximum threshold 615. For example, the high threshold 620 and the low threshold 625 can be calculated as percentages of the maximum threshold 615. As a specific example, the high threshold 620 can be calculated as 70% or 80% of the maximum threshold 615, and the low threshold 625 can be calculated as 30% or 40% of the maximum threshold 615. Other percentages can also be used for calculation. However, in other embodiments of this disclosure, other methods can be used to calculate the high threshold 620 and the low threshold 625. For example, the high threshold 620 and the low threshold 625 can represent... Figure 1 Persistent storage device 135 with different workload levels: with Figure 1 The persistent memory device 135 becomes busier, and the high threshold 620 and / or low threshold 625 can be adjusted upwards to support [the operation]. Figure 1 The persistent storage device 135 stores a larger amount of dirty data (in order to reduce the amount of dirty data transferred from the storage device 135). Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345 is applied to Figure 1 The load on the persistent memory device 135), while when Figure 1 When the workload on the persistent storage device 135 decreases, thresholds 620 and 625 can be similarly reduced, resulting in less dirty data being cached. Figures 3A to 3BIn the volatile storage device 340. For example, recall that the high threshold 620 and the low threshold 625 can be set as percentages of the maximum threshold 615. Depending on the workload characteristics and / or from Figure 1 The instructions of processor 110 can adjust the threshold to different values ​​by changing the percentage calculation used for the high threshold 620 and / or the low threshold 625. Therefore, if Figure 1 The workload on persistent storage device 135 involves more read requests than write requests, or Figure 1 The processor 110 is updating only a few pages, then Figure 1 The processor 110 can instruct Figure 1 The persistent memory device 135 uses higher values ​​for the high threshold 620 and / or the low threshold 625.

[0096] In some embodiments of this disclosure, Figure 1 The persistent storage device 135 can also check when determining whether to update the high threshold 620 and / or the low threshold 625 (and the maximum threshold 615). Figures 3A to 3B The state of energy storage unit 325. For example, if Figures 3A to 3B If the energy storage unit 325 experiences frequent changes in its available power level (increasing or decreasing the reported available power level), then this fact may indicate... Figures 3A to 3B The 325 energy storage unit has become unreliable and may need to be replaced (or if) Figures 3A to 3B The energy storage unit 325 is not independently replaceable, therefore Figure 1 The persistent storage device 135 may need to be replaced. To resolve... Figures 3A to 3B The potential unreliability of the energy storage unit 325 Figure 1 The persistent memory device 135 can adjust the levels of the high threshold 620 and / or the low threshold 625 (e.g., by increasing the high threshold 620 and decreasing the low threshold 625, dirty pages can be retrieved more frequently from the hard drive). Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B (Non-volatile storage device 345). Figure 7 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 Figures 3A to 3B The cache controller 360 issues commands to retrieve data from the cache. Figures 3A to 3B A flowchart illustrating an example process for flushing dirty pages from a volatile storage device 340. Figure 7 In the middle, at position 705, Figures 3A to 3B Firmware 365 can periodically (e.g., every 100 microseconds (μs), every millisecond (ms), etc.) check to see Figure 6 Is the dirty page counter 610 greater than... Figure 6The high threshold is 620. If not, firmware 365 can return to box 705 to repeat the check to see. Figure 6 Is the dirty page counter 610 greater than... Figure 6 The high threshold is 620; otherwise, at box 710, Figures 3A to 3B Firmware 365 can begin to... Figures 3A to 3B The cache controller 360 issues a flush command to remove dirty cache pages from the cache. Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The non-volatile storage device 345. Then, at frame 715, Figures 3A to 3B Firmware 365 can be checked to view Figure 6 Is the dirty page counter 610 less than... Figure 6 The low threshold is 625. If not, then Figures 3A to 3B Firmware 365 can return to box 710 to... Figures 3A to 3B The cache controller 360 issues another flush command; otherwise, the firmware 365 can return to box 705, thus effectively stopping the flushing process. Figures 3A to 3B The cache controller 360 sends a flush request.

[0097] Although Figure 7 No response Figure 6 The maximum threshold is 615 for the role, but it is at or near box 710. Figures 3A to 3B Firmware 365 can also be checked. Figure 6 Is the dirty page counter 610 greater than the maximum threshold 615? If so, then Figures 3A to 3B Firmware 365 can indicate Figures 3A to 3B 360's cache controller rejects requests from... Figure 1 Write requests to processor 110; otherwise, Figures 3A to 3B The 360 ​​cache controller can continue to accept data from... Figure 1 The processor 110 made a write request. However, Figure 6 The dirty page counter exceeds 610. Figure 6 The effect of the maximum threshold of 615 has no effect Figures 3A to 3B Does firmware 365... Figures 3A to 3B The cache controller 360 issues a flush command, thus... Figures 3A to 3B The operation of firmware 365 is not entirely relevant, such as Figure 7 As shown.

[0098] Although Figure 7 It appears to reflect a one-time process, but in the implementation, Figures 3A to 3B Firmware 365 can be executed periodically. Figure 7 The flowchart shown. For example, Figures 3A to 3BFirmware 365 can execute every 1 ms, every 5 ms, or at any desired interval. Figure 7 The flowchart shown.

[0099] Figure 8 The embodiments of the present disclosure are shown with Figure 1 Persistent storage devices 135 communication Figure 1 The processor is 110. Figure 8 In this context, processor 110 is shown issuing a write request 805 to persistent storage device 135. At this point, it can be assumed that... Figure 6 The dirty page counter is 610 or lower. Figure 6 The maximum threshold 615, and the persistent storage device 135 can normally receive and process write requests 805, thereby causing the persistent storage device 135 to return a response 810.

[0100] On the other hand, when processor 110 issues write request 815, it may happen that... Figure 6 The dirty page counter 610 is equal to or greater than Figure 6 The maximum threshold is 615. Therefore, Figures 3A to 3B Firmware 365 may have already indicated Figures 3A to 3B The cache controller 360 rejects the write request from the processor 110 during this period. The persistent memory device 135 can then return a busy response 820 to the processor 110. As mentioned above, the busy response 820 can be a message indicating that the write request 815 has not been processed, or the busy response 820 can be that the persistent memory device 135 simply discards or otherwise ignores the write request 815, which may cause the processor 110 to resend the write request 815 after a timeout. Another possibility is that the persistent memory device 135 caches the write request 815 until... Figure 6 The dirty page counter 610 has dropped to below Figure 6 The maximum threshold is 615 for the specified time. However, this option may cause... Figure 1 The processor 110 waits for a response from the persistent storage device 135 for an unreasonable amount of time (unless the persistent storage device 135 issues an early acknowledgment to the write request 815 that the data has already been stored in the persistent storage device 135). Figure 6 The dirty page counter 610 is already higher than Figure 6 (This would be undesirable if the maximum threshold is 615).

[0101] In some embodiments of this disclosure, as described above, if Figure 6 The dirty page counter 610 is equal to or greater than Figure 6If the maximum threshold 615 is reached, the persistent storage device 135 may reject the write request 815. However, if the application issuing the write request 815 can accept data loss, the persistent storage device 135 may accept the write request 815, even if it will result in data loss. Figure 6 The dirty page counter 610 increased to above Figure 6 The maximum threshold is 615. That is, if the processor 110 can accept the possibility of data loss in the event of an unexpected power outage, the persistent storage device 135 can process the write request 815 even if there is a possibility of data loss in the event of a power outage.

[0102] Figure 9 The illustration shows the transfer of various quantities of data from... according to embodiments of the present disclosure. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B A graph showing how much energy the non-volatile storage device 345 requires, and a table showing how to store this relationship. Figure 9 In the diagram, graph 905 is shown. Although it is intuitively expected that from... Figures 3A to 3B The amount of energy required to copy data in the volatile storage device 340 is linear—that is, the amount of energy required to copy, for example, 8 GB of data is twice the amount of energy required to copy 4 GB of data—but in reality, the required energy may be more like a curve, such as curve 910. Therefore, copying the first amount of data from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The amount of energy required by the non-volatile storage device 345 may be greater than the amount of data to be transferred from the second additional storage device. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The amount of energy required by the non-volatile storage device 345. Therefore, for example, copying 1 GB of data might require 24 joules (J) of energy (which can be assumed to be generated by…). Figures 3A to 3B The energy storage unit is 325, but copying 2 GB of data may require 32 J: only 8 extra joules are needed.

[0103] The information represented by curve 910 in graph 905 can be used to create table 915, which can be data for a given quantity, and the data for that quantity can be extracted from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The energy required by the non-volatile storage device 345. Table 915 can store, for example... Figures 3A to 3B The storage device 370. Table 915 may include two columns: data volume 920, which may represent the data stored in the storage device 370. Figures 3A to 3B In the volatile storage device 340 for replication Figures 3A to 3BThe amount of data (measured in KB, MB, or GB, or other possible units) or cache pages in the non-volatile storage device 345; and the energy required 925, which can represent the amount of associated data transferred from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The amount of energy required by the non-volatile storage device 345. Note that it can be obtained from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The amount of data in the non-volatile storage device 345 is comparable to the amount of data that can be stored in. Figures 3A to 3B There is a direct relationship between the number of dirty cache pages in the non-volatile storage device 345 and the number of cache pages, because the size of the cache page is a known quantity that does not change, so the number of cache pages can be calculated directly from the amount of data. Table 915 may also include entries, such as entries 930-1, 930-2, 930-3, and 930-4 (which may be collectively referred to as entry 930), which associate each data quantity with the amount of data retrieved from the storage device 345. Figures 3A to 3B The volatile storage device 340 transmits to Figures 3A to 3B The corresponding energy required for the non-volatile storage device 345 is associated with this.

[0104] Note that, similar to graph 905, table 915 can be independent of... Figures 3A to 3B The energy storage unit 325. That is, graph 905 and table 915 can reflect the transfer of data from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The amount of energy required by the non-volatile storage device 345, without considering Figures 3A to 3B How much energy is available in energy storage unit 325? Table 915 shows the amount of energy that can be used in manufacturing. Figure 1 The persistent memory device 135 is determined at that time, and it can be expected for... Figure 1 All equivalent persistent memory devices 135 are consistent. Then, when Figures 3A to 3B Energy storage unit 325 was added Figure 1 When the persistent memory device 135 is given from Figures 3A to 3B The energy storage unit has 325 units of usable energy. Figure 1 The persistent storage device 135 can be determined using Table 915. Figures 3A to 3B How many dirty cache pages can be stored in the volatile storage device 340?

[0105] Given the information in Table 915, it is possible to calculate Figure 6 The maximum threshold is 615. For example, if... Figures 3A to 3B The available energy in energy storage unit 325 is 44 J, then Figures 3A to 3BFirmware 365 can perform a reverse lookup in Table 915 and determine that up to 4 GB of data can be stored. Figures 3A to 3B In the volatile storage device 340, and Figure 1 The persistent storage device 135 can still guarantee that all dirty data can be copied in the event of a power outage. Figures 3A to 3B The non-volatile storage device 345 can be used to set Figure 6 The maximum threshold is 615. (See above for reference) Figure 6 What is being discussed can be relative to Figure 6 The maximum threshold of 615 is used to determine Figure 6 High threshold 620 and Figure 6 The low threshold is 625.

[0106] Although Figure 9 The storage of various energy levels along curve 910 and the energy levels that can be obtained from it were discussed. Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B The relationship between the corresponding number of data pages in the non-volatile storage device 345 can be specified, but other data structures can also be used to store this information. For example, if curve 910 is a linear curve (i.e., the energy level along curve 910 is related to the number of data pages available from...), then... Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B If there is a linear relationship between the number of corresponding data pages in the non-volatile storage device 345, then Table 915 can be replaced by a simple equation that maps the energy level along curve 910 to the energy level that can be obtained from... Figures 3A to 3B The number of corresponding data pages flushed by the volatile storage device 340. However, for more complex or non-linear relationships, Table 915 may be the simplest representation.

[0107] Figure 10 An embodiment according to this disclosure is shown. Figures 3A to 3B The firmware 365 update indicates how many pages can be stored. Figures 3A to 3B A flowchart illustrating an example process for setting a threshold in volatile storage device 340. Figure 10 In the middle, at position 1005, Figures 3A to 3B The monitoring circuit 375 can monitor Figures 3A to 3B The energy storage device has an energy level of 325. At box 1010, Figures 3A to 3B Firmware 365 can be used Figure 9 Perform a reverse lookup on table 915 to find the given... Figures 3A to 3B The energy storage device at an energy level of 325 is determined to be able to store [energy]. Figures 3A to 3B The amount of dirty data (or the number of dirty cache pages) in the volatile storage device 340. Finally, at box 1015, Figures 3A to 3BFirmware 365 can be based on a given Figures 3A to 3B The energy storage unit 325 can be used from the current energy level. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B The non-volatile storage device 345 updates the amount of data to be updated. Figure 6 Maximum threshold 615 Figure 6 High threshold 620 and Figure 6 The low threshold is 625.

[0108] Although Figure 10 It appears to reflect a one-time process, but in the implementation, Figures 3A to 3B Firmware 365 can be executed periodically. Figure 10 The flowchart shown. For example, Figures 3A to 3B Firmware 365 can execute every 5 seconds, or every minute, or every day, or at any desired interval. Figure 10 The flowchart shown. Figures 3A to 3B The periodic interval used by firmware 365 can be Figures 3A to 3B A function of the expected health status of energy storage body 325: can be expected Figures 3A to 3B The newer energy storage units 325 maintain their energy levels fairly consistently, and this can be expected. Figures 3A to 3B The older energy storage units 325 have greater fluctuations in their power levels.

[0109] Figure 11 An embodiment according to this disclosure is shown. Figure 1 The persistent storage device 135 determines when to remove the page from the memory. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B A flowchart of an example process for a non-volatile storage device 345. Figure 11 In the middle, at frame 1105, Figures 3A to 3B Firmware 365 can be based on Figures 3A to 3B The current energy level of energy storage unit 325 determines what can be stored. Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340 (i.e., Figure 6 The maximum threshold is 615. Figures 3A to 3B The current energy level of the energy storage unit 325 can be used to set... Figure 6 The maximum threshold of 615 is the only factor. However, there may be... Figures 3A to 3B In cases where a portion of the energy level in energy storage 325 can be used for other purposes, for example, Figure 1 The persistent storage device 135 can use from Figures 3A to 3B The energy storage unit 325 uses some energy to perform Figure 1 A clean shutdown of persistent storage device 135. In this case, not Figures 3A to 3B All the energy in energy storage unit 325 must be available to transfer data from Figures 3A to 3B The volatile storage device 340 persistently saves to Figures 3A to 3B The non-volatile storage device 345, and Figure 6 The maximum threshold of 615 can be set to a lower level accordingly. At box 1110, Figures 3A to 3B Firmware 365 can be confirmed Figure 6 The dirty page counter 610 indicates the current page stored in the dirty page counter. Figures 3A to 3B The number of dirty cache pages in volatile storage device 340. Finally, at box 1115, Figures 3A to 3B The 360 ​​cache controller can be based on Figure 6 The dirty page counter 610 exceeds the maximum threshold 615, thus removing dirty cache pages from the cache. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B 345. Non-volatile storage device.

[0110] Figure 12 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 determines which firmware to store Figures 3A to 3B A flowchart illustrating an example process for determining the number of dirty pages in a volatile storage device 340. Figure 12 In the middle, at box 1205, given Figures 3A to 3B The available energy level of the energy storage device is 325. Figures 3A to 3B Firmware 365 can be used Figure 9 Perform a reverse lookup on table 915 to determine which table can be stored. Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340.

[0111] Figure 13 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 instructions Figures 3A to 3B The 360 ​​cache controller will move the page from Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B A flowchart of an example process for a non-volatile storage device 345. Figure 13 In the middle, at position 1305, Figures 3A to 3B Firmware 365 can be used to... Figures 3A to 3B The cache controller 360 issues a command to remove dirty cache pages from the cache. Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B 345. Non-volatile storage device. Figures 3A to 3BFirmware 365 can issue this command, as shown in the reference above. Figure 7 As described.

[0112] Figure 14 An embodiment according to this disclosure is shown. Figures 3A to 3B The 360 ​​cache controller processes data from... Figure 1 processor 110 Figure 8 A flowchart illustrating an example process for a write request 805. Figure 14 In the middle, at position 1405, Figure 1 The persistent storage device 135 can be obtained from Figure 1 The processor 110 receives Figure 8 Write request 805. At box 1410, Figures 3A to 3B The 360 ​​cache controller can store user data in Figures 3A to 3B In the cache pages of the volatile storage device 340. (See above reference.) Figures 3A to 3B The discussion focuses on storing user data in... Figures 3A to 3B A portion of the cache pages in the volatile storage device 340, Figures 3A to 3B The cache controller 360 can also mark cache pages as dirty in the bitmap. Finally, at box 1415, Figures 3A to 3B The 360-speed cache controller can be incremented. Figure 6 The dirty page counter is 610. Again, as referenced above... Figures 3A to 3B The discussion, if Figures 3A to 3B 360 only updates the cache controller. Figures 3A to 3B The cache pages in the volatile storage device 340 that are already dirty, then Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340 is not actually changed, and box 1415 can be omitted.

[0113] Figure 15 An embodiment according to this disclosure is shown. Figure 1 Persistent storage device 135 switched to Figures 3A to 3B A flowchart illustrating an example process for the energy storage unit 325. Figure 15 In the middle, at position 1505, Figures 3A to 3B The power interruption detector 320 can check to see if the main power has been interrupted. If not, no action is needed; otherwise, at box 1510, Figure 1 The persistent storage device 135 can be switched from mains power. Figures 3A to 3B Energy storage unit 325 to Figure 1 The persistent storage device 135 is powered while dirty data is transferred from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B345. Non-volatile storage device.

[0114] Figure 16 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 updates need to be stored in Figures 3A to 3B A flowchart illustrating an example process for determining the number of dirty pages in a volatile storage device 340. Figure 16 In the middle, at position 1605, Figures 3A to 3B The 375 monitoring circuit can monitor Figures 3A to 3B The health status of energy storage unit 325. At box 1610, Figure 1 The persistent storage device 135 can be updated Figures 3A to 3B The available energy level of the energy storage unit is 325. Finally, at box 1615, Figures 3A to 3B Firmware 365 can be based on Figures 3A to 3B The updated energy level of the energy storage unit 325 is used to redetermine what can be cached in. Figures 3A to 3B The number of dirty pages in the volatile storage device 340. (Refer to the above.) Figures 9-10 and Figure 12 The discussion can be based on Figures 3A to 3B The available energy level of the energy storage unit is 325. Figure 9 A reverse lookup is performed in Table 915 to complete this determination.

[0115] Figure 17 An embodiment according to this disclosure is shown. Figures 3A to 3B The 360 ​​cache controller has been removed from the page. Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B Non-volatile storage device 345 and later update Figure 6 A flowchart of an example process for the dirty page counter 610. Figure 17 In the middle, at frame 1705, in Figures 3A to 3B The 360 ​​cache controller has removed dirty cache pages from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B After the non-volatile storage device 345 (and possibly after the bitmap has been changed to reflect that the cache pages in question are no longer dirty), Figures 3A to 3B The 360 ​​cache controller can be decremented. Figure 6 Dirty page counter 610.

[0116] Figure 18 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 based Figure 6 The threshold is used to determine when to indicate Figures 3A to 3B The 360 ​​cache controller will move the page from Figures 3A to 3BThe volatile storage device 340 is copied to Figures 3A to 3B A flowchart of an example process for a non-volatile storage device 345. Figure 18 In the middle, at position 1805, Figures 3A to 3B Firmware 365 can be based on high-speed caching in Figures 3A to 3B The number of dirty pages in the volatile storage device 340 is used to determine Figure 6 Maximum threshold 615 Figure 6 High threshold 620 and Figure 6 The low threshold is 625. Then, at box 1810, Figures 3A to 3B Firmware 365 can be based on Figure 6 The dirty page counter exceeds 610. Figure 6 The high threshold of 620 is used to indicate Figures 3A to 3B The 360 ​​cache controller will remove dirty cache pages from... Figures 3A to 3B The volatile storage device 340 is copied to Figures 3A to 3B 345. Non-volatile storage device.

[0117] Figure 19 An embodiment according to this disclosure is shown. Figures 3A to 3B Firmware 365 determines when to start and stop from Figures 3A to 3B A flowchart illustrating an example process of flushing operation for the volatile storage device 340. Figure 19 In the middle, at position 1905, Figures 3A to 3B Firmware 365 can be confirmed Figure 6 Is the dirty page counter 610 lower than... Figure 6 The low threshold is 625. If so, then at box 1910, Figures 3A to 3B Firmware 365 can stop the flashing operation (by not sending to...). Figures 3A to 3B The 360 ​​cache controller sends data from Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B (Commands for non-volatile storage device 345). Otherwise, at box 1915, Figures 3A to 3B Firmware 365 can be checked to view Figure 6 Is the dirty page counter 610 greater than... Figure 6 The high threshold is 620. If so, then at box 1920, Figures 3A to 3B Firmware 365 can begin the flashing process (by sending...). Figures 3A to 3B The 360 ​​cache controller sends data from Figures 3A to 3B The volatile storage device 340 was washed to Figures 3A to 3B (Commands for the non-volatile storage device 345).

[0118] Figure 20 An embodiment according to this disclosure is shown. Figure 1Persistent storage device 135 rejects from Figure 1 processor 110 Figure 8 A flowchart of an example process for write request 815. Figure 20 In the middle, at box 2005, firmware 365 can be checked to view... Figure 6 Has the dirty page counter 610 exceeded the limit? Figure 6 The maximum threshold is 615. If so, then at box 2010, Figures 3A to 3B Firmware 365 can indicate Figures 3A to 3B 360's cache controller rejects requests from... Figure 1 processor 110 Figure 8 Write request 815. (See reference...) Figure 8 The rejection discussed could be a refusal to Figure 1 The processor 110's explicit response: Figure 8 The write request 815 was not processed, or the rejection may involve... Figures 3A to 3B The 360 ​​cache controller is "ignored". Figure 8 Write request 815, which may make Figure 1 Processor 110 timed out (at this time, Figure 6 The dirty page counter 610 may have dropped to Figure 6 The maximum threshold is below 615, and Figures 3A to 3B The 360 ​​cache controller may be able to handle Figure 8 Reissued after write request 815) Figure 8 Write request 815. Note that once... Figure 6 The dirty page counter 610 dropped below Figure 6 If the maximum threshold is 615, then Figures 3A to 3B The 360 ​​cache controller can recover processing from... Figure 1 processor 110 Figure 8 Write requests 805 and 815.

[0119] Figure 21 An embodiment according to this disclosure is shown. Figure 1 Persistent storage device 135 Figure 1 A flowchart illustrating an example process for the processor 110 or the baseboard management controller to report information. Figure 21 In the middle, at frame 2105, Figure 1 The persistent memory device 135 can report various data to the processor 110 and / or the baseboard management controller (BMC). The reported data may include, for example, data that can be stored... Figures 3A to 3B The number of dirty cache pages in the volatile storage device 340 Figure 6 Dirty page counter 610, Figure 9 Table 915, and / or Figure 1 Persistent storage device 135 Figures 3A to 3B The current health status of energy storage unit 325.

[0120] Figure 22 An embodiment according to this disclosure is shown. Figures 3A to 3B The 360 ​​cache controller from Figures 3A to 3B A flowchart illustrating an example process for evicting pages from a volatile storage device 340. Figure 22 In the middle, at frame 2205, Figures 3A to 3B The 360 ​​cache controller is optional. Figures 3A to 3B The cached pages in the volatile storage device 340 are used for eviction. As discussed above with reference to Figure 5, Figures 3A to 3B The cache controller 360 can use LFU or LRU eviction policies.

[0121] exist Figures 11 to 22 Some embodiments of the present disclosure are shown in the figures. However, those skilled in the art will recognize that other embodiments of the present disclosure are possible by changing the order of the boxes, by omitting boxes, or by including links not shown in the figures. All such variations of the flowcharts, whether explicitly described or not, are considered embodiments of the present disclosure.

[0122] Embodiments of this disclosure may include a persistent storage device, comprising both non-volatile and volatile storage devices. The persistent storage device may also include an energy storage unit that can power the persistent storage device in the event of a mains power outage. The persistent storage device can track the available power supplied by the energy storage unit. Using a table that associates the amount of electricity required to copy data from the volatile storage device to the non-volatile storage device with the required amount of electricity, the persistent storage device can manage dirty data in the volatile storage device. The persistent storage device can limit the amount of dirty data in the volatile storage device to the amount that can be copied to the non-volatile storage device based on the available power supplied by the energy storage unit. If the amount of dirty data in the volatile storage device is greater than the amount of dirty data that can be copied to the non-volatile storage device based on the available power of the energy storage unit, the persistent storage device can initiate the copying of dirty data from the volatile storage device to the non-volatile storage device. Therefore, the persistent storage device can ensure that, in the event of a mains power outage, the available power of the energy storage unit is sufficient to power the persistent storage device to copy dirty data from the volatile storage device to the non-volatile storage device. By ensuring no data loss in the event of a mains power outage, persistent storage devices offer a technological advantage over persistent storage devices without this technology. Such persistent storage devices allow for trade-offs in functionality and performance throughout the device's lifespan. In other words, embodiments of this disclosure enable high-capacity persistent storage devices to maintain their functionality even when the power source is at a lower write throughput energy level as its lifespan degrades over time.

[0123] Embodiments of this disclosure may also use different tables that correlate the amount of electricity required to copy data from volatile storage to non-volatile storage, depending on the hardware used for the volatile and non-volatile storage devices. By enabling a single persistent memory device to manage dirty data regardless of the available power supplied by the energy storage medium or the hardware implementation of the volatile and non-volatile storage devices, persistent memory devices offer a technical advantage over solutions that may require hard-coded limits on the amount of dirty data that can be stored.

[0124] Embodiments of this disclosure also take into account the possibility that the energy storage unit may degrade over time, thereby providing power levels that may fluctuate over time. By taking into account the available power provided by the energy storage unit, persistent storage devices offer technical advantages over solutions that assume the energy storage unit provides a constant amount of power.

[0125] Fast Compute Link (CXL) memory devices can determine how much data can be safely and persistently stored for a given amount of holding energy. CXL memory devices can dynamically limit the amount of "dirty" data in their cache that needs to be flushed during a sudden power outage, based on the energy available during a power failure. Even as the energy storage of a CXL memory device (e.g., one or more supercapacitors) degrades over time, the device remains functional, and the throughput impact of reduced dirty data levels is minimized. CXL memory devices achieve a trade-off between persistence / functionality guarantees and performance.

[0126] According to the subject matter disclosed herein, CXL memory devices monitor and track the amount of dirty data pages in the device cache. CXL memory devices can use a first threshold including a low dirty data threshold and a second threshold including a high dirty data threshold to determine whether to flush dirty data or persist dirty data. For example, the low dirty data threshold and the high dirty data threshold can be programmed by the host or by the CXL memory device. In another example, in addition to the low dirty data threshold and the high dirty data threshold, a third threshold including a maximum dirty data threshold can be employed. The maximum dirty data threshold, the low dirty data threshold, and the high dirty data threshold can be calculated using the retention energy level available to the CXL memory device. One or more of the low dirty data threshold, the high dirty data threshold, and the maximum dirty data threshold can be dynamically calculated and programmed throughout the lifetime of the CXL memory device. For example, the CXL memory device can dynamically monitor and track the retention energy level.

[0127] According to the subject matter disclosed herein, CXL memory devices can dynamically report retention energy levels to a host or board management controller (BMC). CXL memory devices can dynamically report the amount or quantity of dirty data pages to the host or BMC. A determination of the amount or level of energy required for flushing various amounts of dirty data by the CXL memory device can be made, and this determination can be stored in a data retention energy table. This determination of flushing energy requirements for various data amounts can be determined during device manufacturing and stored in the device at that time. The data retention energy table can be programmed within the CXL memory device. The data retention energy table can be reported to the host or BMC. The maximum dirty data threshold, high dirty data threshold, and low dirty data threshold can be derived by performing a reverse lookup on the data retention energy table. The CXL memory device can dynamically adjust the dirty data level thresholds based on the health status of one or more supercapacitors in the energy storage cell.

[0128] The subject matter disclosed herein can provide a more precise and efficient way to prioritize data flushing in persistent memory systems. This can reduce data flushing latency, reduce power budgets, and thus save costs. It can improve data reliability and system performance. It enables lifecycle management of CXL memory devices. In some embodiments of this disclosure, these memory devices can use the CXL interface to provide high-capacity persistent memory solutions, thereby providing a hybrid approach combining dynamic random access memory (DRAM) and NAND flash memory for tiered memory systems.

[0129] This paper discloses a high-capacity CXL-based persistent memory device that addresses several challenges associated with data persistence in such devices. The CXL protocol provides a traditional load / store interface to memory devices accessed via the Peripheral Component Rapid Interconnect (PCIe) / CXL bus. The CXL protocol enables memory devices to provide very large capacities of memory, such as 1 terabyte (TB), 4 TB, etc., at a relatively low cost. CXL memory devices can combine DRAM and NAND memory in a hybrid manner to achieve low-cost, large-capacity memory expansion. A small amount of volatile DRAM in the device can be used as a device cache, while the NAND memory allows the full capacity of the CXL memory device to be utilized. When a host reads data from the memory device, if the data is available in the cache, it can be provided from the device cache. If the data requested by the host is not present in the device cache, the device cache controller can retrieve the requested data from the NAND memory and store it in the DRAM device cache, and then return the data to the host.

[0130] According to the subject matter disclosed herein, in response to a host writing data to a device, the device cache controller can insert the written data into the corresponding data page in the device cache. If the page written / modified by the host does not exist in the device cache, the device cache controller can first fetch the page from NAND memory into the device cache DRAM and then insert the new data into that page. When the host writes some data to the device, the modified data page can be kept in the DRAM device cache. Such a data page can be referred to as a "dirty" page because the modified data page has not yet been written back to NAND memory.

[0131] As disclosed in this article, because device cache DRAM is volatile, new data will be lost if power is lost and dirty pages are not written back to NAND memory. To avoid such data corruption when the device is powered off or suddenly powered off for any reason, one or more dirty data pages residing in the device cache can be written to NAND memory before the device is completely powered off. Because NAND memory is a non-volatile storage device, it can be used to provide persistent data storage. CXL memory devices can provide the host with a guarantee that all host data written and acknowledged by the device is persistently stored. That is, after the device loses power, is powered off, or is restarted, and in the event of a sudden power outage, it is guaranteed that all host data written to the device before these events is available with 100% fidelity. To achieve this persistence guarantee, CXL memory devices maintain an energy storage bank, sometimes referred to as a hold-up power supply or backup power supply in the device. In the event of power off, restart, or a sudden power outage, energy from the energy storage bank is used to flush any dirty data that may exist in the volatile memory (DRAM) device cache to the non-volatile memory (NAND).

[0132] The host central processing unit (CPU) communicates with the CXL memory device via a connector. The connector may include data interface pins and power pins. The CXL memory device can use CXL host interface protocols (such as CXL.IO, CXL.mem, and CXL.cache) for data read / write operations. CXL endpoint modules can implement CXL protocol logic. The device cache controller module can perform data caching operations using a small amount of DRAM and the full capacity of NAND memory. The device cache controller uses a non-volatile fast memory (NVMe) host module to access the NAND memory using the NVMe protocol. In some embodiments of this disclosure, the CXL memory device may use two controller chips: one chip for CXL logic and a second chip, which may be referred to as a solid-state drive (SSD) controller chip, for NAND memory operations.

[0133] According to the subject matter disclosed herein, the CXL memory device receives power from a host using one or more connector pins, which provide one or more voltage levels, such as 12 volts (V), 5 V, 3.3 V, etc. The connector voltage pins can be connected to a voltage regulator to generate any internal voltage level required for the operation of the device circuitry, such as 1.1 V, 3.3 V, 0.8 V, etc. The connector pins can also be connected to a rechargeable energy storage unit to store energy for future use. The energy storage unit can be implemented using supercapacitors or other components. The energy storage unit can also be referred to as a hold-up energy source or a backup energy source. The amount or level of energy present in the energy storage unit can be monitored by a field-programmable gate array (FPGA) / application-specific integrated circuit (ASIC) controller. The amount or level of energy can be obtained by the FPGA / ASIC chip using I2C or SMBUS buses, etc. The FPGA / ASIC can periodically check the amount of energy available, as it may change over time. Over time, supercapacitors or other components used for energy storage may degrade and lose power, so the FPGA / ASIC can dynamically monitor the hold-up energy level. FPGAs / ASICs can also monitor the health of energy storage devices, which may sometimes fail completely and may not be able to reliably supply energy in such cases.

[0134] According to the subject matter disclosed herein, connector pins can be connected to a power loss detection circuit designed to detect power loss from the connector pins. When a power loss is detected, the power loss detection circuit can instruct a voltage regulator to switch the input power supply from the connector pins to the energy storage unit. The voltage regulator can then smoothly switch the input power supply without generating any glitches or interruptions on the internal voltage rails, so as not to disrupt the operation of the device logic and circuitry. The power loss detection event or trigger can also be provided to the FPGA / ASIC controller.

[0135] Upon receiving a power-down detection trigger, the FPGA / ASIC controller chip can immediately begin "writing" (flushing dirty data pages) from DRAM to NAND memory. The controller chip can also attempt to conserve power by minimizing or stopping any non-critical logic operations to reduce power consumption. Once all dirty data pages, any relevant metadata, and critical data structures have been written to the NAND memory, the FPGA / ASIC controller can enter an idle or safe state to prepare for an impending power outage.

[0136] The ARM core residing in the FPGA / ASIC controller can monitor the amount of dirty pages in the device cache. The ARM core firmware can terminate flush commands to the device cache controller, which are used to write or flush one or more data pages from the device cache to NAND memory. The device cache controller can provide the ARM core firmware with multiple dirty data page presentation information at any given time.

[0137] In a single-chip integrated CXL memory device, the CXL host interface logic and device cache controller logic can communicate directly with the Flash Translation Layer (FTL). The NVMe protocol is not required in this integrated device. The FTL layer can perform logic-to-physical address translation and one or more NAND media management operations, such as wear leveling and garbage collection. The flash channel logic enables data read and write operations on the NAND media using protocols such as Open NAND Flash Interface (ONFI) and Toggle.

[0138] Incremental dirty data flushing

[0139] The device cache controller tracks dirty pages in the device cache. When the host performs a write or storage operation, the corresponding page is marked as dirty. At any given time, the device cache may contain a certain number of dirty pages. When a dirty page is written back to NAND memory, it can be marked as clean (i.e., no longer dirty). The device cache controller may sometimes flush some or all of the dirty pages to NAND to make room for new data. Therefore, the number of dirty pages in the device cache can change dynamically.

[0140] According to the subject matter disclosed herein, a device cache controller tracks the number of dirty pages in the device cache and makes this information dynamically available to the ARM firmware. In some embodiments of this disclosure, the ARM firmware dynamically queries the device cache controller about the status of each device cache page. By querying the status of pages in the device cache, the ARM firmware can generate statistics on the number of dirty pages at that time. In other embodiments of this disclosure, the ARM firmware maintains a bitmap of dirty pages as a result of the page status query process. In other embodiments of this disclosure, the device cache controller and / or the ARM firmware can make dirty page numbers and a dirty page bitmap available to the host. Host software can use various methods such as Compressed Sparse Lines (CSR), Vision Development Module (VDM), DoE, logging, or telemetry to read or retrieve the number of dirty pages in the device cache and / or dirty page bitmap.

[0141] According to the subject matter disclosed herein, ARM firmware repeatedly or periodically checks the dirty page level, for example, at time intervals of 1 millisecond (ms), 100 ms, or 1 second. At one or more time intervals, the ARM firmware can determine whether the current dirty page level is higher than a high threshold. If the current dirty page level is higher than the high threshold, the ARM firmware can issue a dirty page flush command to the device cache controller. The device cache controller can then flush one or more corresponding dirty page data to NAND memory. This action reduces the dirty page level in the device cache. The ARM firmware can continue to issue dirty page flush commands to the device cache controller until the dirty page level drops below the low threshold. This method ensures that at any given time, independent of the host application workload, the amount of dirty data present in the device cache is always below a maximum threshold and can be safely maintained if necessary.

[0142] Even with an aggressive dirty flushing approach after a high threshold is exceeded, the flushing process may not reduce the level of dirty data in the device cache below the high threshold. This can happen if the active host application workload is very write-intensive. If the dirty data page level reaches the maximum threshold, the device cache controller can stop accepting any further host application writes. This backpressure or throttling can cap or limit further increases in the level of dirty data in the device cache. The maximum threshold can correspond to the available hold power at the time required to safely flush all dirty data in the device cache in the event of a sudden power outage or shutdown. In other words, based on the amount of hold power available to the device, the device can provide a guarantee of safe and persistent storage of up to the maximum threshold amount of data.

[0143] Based on the subject matter disclosed herein, methods for calculating a maximum threshold, a high threshold, and a low threshold are described. In some embodiments of the invention, the maximum threshold, the high threshold, and the low threshold are flush thresholds that can be set by a memory device. In other embodiments of the invention, the maximum flush threshold, the high flush threshold, and the low flush threshold can be programmed by the host and / or BMC using various methods such as CSR, VDM, DoE, Mailbox, etc.

[0144] The maximum threshold shown can change over time during the lifespan of the storage device. This can occur as supercapacitors and other such components used in energy storage systems age and deteriorate over time. Both the high and low thresholds can also change over time for any of a variety of reasons.

[0145] The maximum threshold for dirty data levels can be calculated based on the holding energy available in a memory device (e.g., a CXL memory device) at any given time. The amount of data that can be safely written to NAND memory for a given amount of energy may not be a linear equation. For this reason, the CXL memory device can perform a characterization cycle for itself, whereby the CXL memory device determines the amount of energy required to flush a given amount of data, and performs this determination for each of several different amounts of data. These determinations can be stored as a data holding energy table, which can be pre-programmed into the CXL memory device by the device manufacturer, device user, or another entity. The data holding energy table is shown below.

[0146]

[0147] The data retention energy table above can be constructed for various data size granularities, such as 1 megabyte (MB), 100MB, 1 gigabyte (GB), 10 GB, etc. The 1 GB unit used above is merely an example. In some embodiments of this disclosure, the data retention energy table is reported to the host and / or BMC. The host and / or BMC can use this information to program maximum thresholds, high thresholds, low thresholds, and to make other operational and administrative decisions.

[0148] According to the subject matter disclosed herein, the ARM firmware determines the health status of the energy storage of the memory device and the amount of available hold energy in the energy storage at intervals of 1 second, 5 minutes, or 1 day, either periodically or repetitively. The ARM firmware can then perform a reverse lookup in the data flush energy table to obtain the corresponding maximum amount of dirty data that can be flushed using that amount of energy. For example, in the data hold energy table above, if the available energy is 14 joules, the ARM firmware sets the maximum threshold to 3 GB. That is, in this example, the memory device can only guarantee the safe and persistent storage of up to 3 GB of dirty data in the device cache. Furthermore, the CXL memory device can ensure that it does not have more than 3 GB of dirty data in its device cache at any given time by performing a background flush operation. Since the energy state of the energy storage can change over time during the lifetime of the CXL memory device, the ARM firmware can appropriately adjust the maximum threshold based on the hold energy state.

[0149] Periodically, at intervals of 1 second, 5 minutes, or 1 day, the ARM firmware can check the health status of the device's energy storage and the amount of available holding power in the energy storage. The ARM firmware can then perform a reverse lookup in the aforementioned data holding power table to determine the maximum amount of dirty data that can be persistently stored using that amount of power. Since the energy state of the energy storage can change over time during the CXL memory device's lifespan, the ARM firmware can appropriately adjust the maximum flushing threshold based on the holding power state.

[0150] Alternatively or additionally, the memory device may maintain a minimum energy threshold as a parameter in any of the operations described above. If the energy level remains below this threshold, the ARM firmware may send an alert to the host. The device can be replaced to ensure uninterrupted functionality in the system.

[0151] The following discussion is intended to provide a brief general description of one or more suitable machines in which certain aspects of this disclosure may be implemented. One or more machines may be controlled at least in part by input from conventional input devices such as a keyboard, mouse, etc., and by instructions received from another machine, interaction with a virtual reality (VR) environment, biometric feedback, or other input signals. As used herein, the term "machine" is intended to broadly encompass a single machine, a virtual machine, or a system of communication-coupled machines, virtual machines, or devices operating together. Exemplary machines include computing devices such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc., and transportation devices such as private or public transportation, such as cars, trains, taxis, etc.

[0152] One or more machines may include embedded controllers, such as programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), embedded computers, smart cards, etc. One or more machines may utilize one or more connections to one or more remote machines, such as via network interfaces, modems, or other communication coupling. Machines may be interconnected via physical and / or logical networks, such as intranets, the Internet, local area networks (LANs), wide area networks (WANs), etc. Those skilled in the art will understand that network communications can utilize a variety of wired and / or wireless short-range or long-range carriers and protocols, including radio frequency (RF), satellite, microwave, IEEE 802.11, Bluetooth®, optical, infrared, cable, laser, etc.

[0153] Embodiments of this disclosure can be described by reference to or in conjunction with relevant data, including functions, procedures, data structures, applications, etc., which, when accessed by a machine, cause the machine to perform tasks or define abstract data types or low-level hardware contexts. The associated data can be stored, for example, in volatile and / or non-volatile memory (e.g., RAM, ROM, etc.), or in other storage devices and their associated storage media, including hard disk drives, floppy disks, optical storage, magnetic tape, flash memory, memory sticks, digital video disks, bio-storage devices, etc. The associated data can be transmitted via a transmission environment (including physical and / or logical networks) in the form of packets, serial data, parallel data, propagated signals, etc., and can be used in compressed or encrypted formats. The associated data can be used in a distributed environment and stored locally and / or remotely for machine access.

[0154] Embodiments of this disclosure may include a tangible, non-transitory machine-readable or storage medium comprising instructions executable by one or more processors, including instructions for performing elements of this disclosure as described herein.

[0155] The various operations of the methods described above can be performed by any suitable means capable of performing these operations, such as various hardware and / or software components, circuits, and / or modules. The software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium for use by or in conjunction with an instruction execution system, apparatus, or device, such as a single-core or multi-core processor or a system containing a processor.

[0156] The methods, algorithms, and functionalities described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, as software modules executed by a processor, or a combination of both. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted through a tangible, non-transitory computer-readable medium. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0157] Having described and illustrated the principles of this disclosure with reference to the illustrated embodiments, it will be appreciated that the illustrated embodiments may be modified in arrangement and detail without departing from these principles, and may be combined in any desired manner. Furthermore, although the foregoing discussion focuses on particular embodiments, other configurations are contemplated. In particular, even when expressions such as "according to an embodiment of this disclosure" are used herein, these phrases imply the general possibility of reference to the embodiments and are not intended to limit this disclosure to particular embodiment configurations. As used herein, these terms may refer to the same or different embodiments that can be combined into other embodiments.

[0158] The foregoing illustrative embodiments should not be construed as limiting the scope of the disclosure. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to these embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

[0159] Therefore, given the various arrangements of the embodiments described herein, the detailed description and the appended materials are intended to be illustrative only and should not be considered as limiting the scope of this disclosure. Thus, this disclosure claims protection for all such modifications that may fall within the scope and spirit of the appended claims and their equivalents.

Claims

1. A persistent storage device, comprising: A non-volatile storage device for storing data; A volatile storage device, which serves as a cache for the data; A cache controller for managing access to non-volatile storage devices and data in volatile storage devices; and A storage device, the storage device being used to store a table relating a first number of dirty pages to be copied from a volatile storage device to a non-volatile storage device to an energy level. The second controller is configured to copy dirty pages of data from the volatile storage device to the non-volatile storage device, based at least in part on the fact that a second number of dirty pages of data in the volatile storage device exceeds a first number of dirty pages.

2. The persistent memory device of claim 1, further comprising an energy storage medium for providing the energy level.

3. The persistent memory device according to claim 2, wherein: The persistent storage device further includes a power interruption detector for switching the persistent storage device to the energy storage body, at least in part, based on a power interruption to the main power supply of the persistent storage device. and A cache controller configured to copy dirty pages of data from a volatile storage device to a non-volatile storage device, at least in part, based on a power outage of the mains power of the persistent storage device.

4. The persistent storage device according to claim 2, further comprising a monitoring circuit for monitoring the health status of the energy storage body.

5. The persistent memory device according to claim 4, wherein: The monitoring circuit is configured to determine a second energy level based on the health status of the energy storage unit; The persistent memory device is configured to determine a first number of dirty page updates based on a second energy level; and The cache controller is configured to copy dirty pages of data from the volatile storage device to the non-volatile storage device, based at least in part on a second number of dirty pages of data in the volatile storage device exceeding a first number of dirty page updates.

6. The persistent memory device according to claim 1, wherein: Persistent storage devices are based on low threshold, high threshold, and maximum threshold; The maximum threshold is based, at least in part, on a table that associates a first number of dirty pages of data to be copied from volatile storage to non-volatile storage with an energy level; The high threshold is based at least in part on a first percentage of the maximum threshold; and The low threshold is based at least in part on a second percentage of the maximum threshold.

7. The persistent memory device according to claim 6, wherein, The cache controller is configured to reject write requests from the processor based on a second number of dirty pages exceeding a maximum threshold.

8. The persistent memory device according to claim 1, wherein, The cache controller is the second controller.

9. The persistent memory device of claim 1, wherein the second controller is external to the device.

10. A method comprising: Determine a first number of dirty pages to be stored in the volatile storage device of the persistent storage device, the first number of dirty pages being based on the energy level of the energy storage medium; Determine the second number of dirty pages in the volatile storage device of the persistent storage device; and The dirty pages are copied from the volatile storage device of the persistent storage device to the non-volatile storage device of the persistent storage device, at least in part based on the fact that the second number of dirty pages exceeds the first number of dirty pages.

11. The method according to claim 10, wherein, Determining the first number of dirty pages to be stored in the volatile storage device of the persistent storage device includes: looking up the first number of dirty pages in a table based on the energy level of the energy storage medium.

12. The method of claim 10, further comprising: Receive a write request for the dirty page from the processor, the write request including user data; The user data is stored in a volatile storage device; and The second number of dirty pages is incremented.

13. The method of claim 10, wherein: The method further includes: It was determined that the main power to the persistent storage device was interrupted; and At least in part, the persistent storage device is switched to an energy storage device due to a power outage affecting its main power supply; and Copying dirty pages from the volatile storage device of a persistent storage device to the non-volatile storage device of a persistent storage device, at least in part based on a second number of dirty pages exceeding a first number of dirty pages, includes: copying dirty pages from the volatile storage device of a persistent storage device to the non-volatile storage device of a persistent storage device, at least in part based on a main power interruption of the persistent storage device.

14. The method of claim 10 further includes monitoring the health status of the energy storage unit.

15. The method according to claim 14, wherein, Monitoring the health status of energy storage systems includes: Based on the health status of the energy storage system, the energy level is updated to the second energy level; and Based on the second energy level of the energy storage, a first number of dirty pages to be stored in the volatile storage device of the persistent storage device is determined.

16. The method of claim 10, wherein, Copying dirty pages from the volatile storage device of a persistent storage device to the non-volatile storage device of a persistent storage device, at least in part based on the second number of dirty pages exceeding the first number of dirty pages, includes: decreasing the second number of dirty pages.

17. The method of claim 10, further comprising determining a high threshold based at least in part on a first number of dirty pages. in, Copying dirty pages from the volatile storage device of a persistent storage device to the non-volatile storage device of a persistent storage device, at least in part based on a second number of dirty pages exceeding a first number of dirty pages, includes: copying dirty pages from the volatile storage device of a persistent storage device to the non-volatile storage device of a persistent storage device, at least in part based on a second number of dirty pages exceeding a high threshold.

18. The method of claim 17, further comprising: The maximum threshold is determined at least in part based on the second number of dirty pages; and Determining the high threshold based at least in part on the second number of dirty pages includes: determining the high threshold as a percentage of the maximum threshold.

19. A system comprising a non-transitory storage medium having instructions stored thereon, the instructions causing, when executed by a machine: Determine a first number of dirty pages to be stored in the volatile storage device of the persistent storage device, the first number of dirty pages being based on the energy level of the energy storage medium; Determine the second number of dirty pages in the volatile storage device of the persistent storage device; and The dirty pages are copied from the volatile storage device of the persistent storage device to the non-volatile storage device of the persistent storage device, at least in part based on the fact that the second number of dirty pages exceeds the first number of dirty pages.

20. The system according to claim 19, wherein, Determining the first number of dirty pages to be stored in the volatile storage device of the persistent storage device includes: looking up the first number of dirty pages in a table based on the energy level of the energy storage medium.

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