Hbm data migration control system based on access frequency analysis

Abstract

This application provides an HBM data migration control system based on access frequency analysis. It acquires memory access requests from the host and extracts access information of the target data block and the address distribution information of its data block group. It then performs adaptive access frequency analysis on the target data block using micro and macro time windows to obtain a heat value reflecting the real-time access characteristics of the data. By combining the spatial locality hopping of the data block group with the real-time operating status of the high-bandwidth memory HBM, it predicts the comprehensive migration index of the target data block. This allows data migration decisions to not only reflect the access activity of the target data block but also comprehensively consider data access correlation and HBM resource status, improving the accuracy of data migration decisions. Furthermore, by combining real-time load status and the comprehensive migration index to control the migration of the target data block, the data migration process can be coordinated with the system data transmission status, improving HBM cache resource utilization and overall system performance.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to an HBM data migration control system based on access frequency analysis. Background Technology

[0002] With the development of applications such as artificial intelligence inference and large-scale model computing, the scale of model parameters and computational data is constantly increasing. A single storage medium can hardly balance storage capacity and access performance. Therefore, a tiered storage architecture is usually adopted, consisting of high-bandwidth memory (HBM) and storage media such as SSDs and DDR. In this architecture, HBM is used to cache frequently accessed data, while storage media such as SSDs and DDR are used to store larger volumes of low-frequency data. A data migration mechanism is used to migrate hot data to HBM to improve data access efficiency and computational performance.

[0003] In the aforementioned tiered storage architecture, to fully leverage the performance advantages of HBM, it is typically necessary to migrate data across different storage media based on data access patterns. However, existing data migration control methods mostly rely on relatively simple migration strategies to determine migration targets and timing, making it difficult to accurately adapt to the constantly changing characteristics of data access behavior. When data access patterns change, issues such as untimely data migration and inappropriate selection of migration targets can easily arise, resulting in underutilization of HBM cache space. Furthermore, the data migration process may consume system transmission resources, impacting normal data access and ultimately reducing the overall performance of the storage system. Summary of the Invention

[0004] This invention provides an HBM data migration control system based on access frequency analysis to solve the problem that the single data migration strategy in the existing storage architecture leads to low utilization of HBM cache resources and reduced system performance.

[0005] In a first aspect, embodiments of this application provide an HBM data migration control method based on access frequency analysis, including: Obtain the memory access request issued by the host, and extract the access information for the target data block in the preset storage medium, as well as the address distribution information of the data block group to which the target data block belongs, based on the memory access request; Based on the current access information of the target data block, adaptive access frequency analysis is performed on the target data block through time windows at different levels of micro and macro to calculate the real-time heat value of the target data block being accessed. Based on address distribution information, the spatial locality kilometry of the data block group to which the target data block belongs is calculated. Spatial locality kilometry is used to characterize the dispersion of access addresses of all active data blocks within the data block group. Based on the real-time running status of high-bandwidth memory (HBM), spatial locality hopping, and the real-time heat value of the target data block, the comprehensive migration index of the target data block is predicted. The status of the storage bus connecting the preset storage medium and the high-bandwidth memory HBM is monitored to obtain the real-time load status of the storage bus. Migration control of the target data block is performed based on real-time load status and comprehensive migration index, so that when the comprehensive migration index meets the migration conditions, the target data block is migrated from the preset storage medium to the high bandwidth memory HBM for storage.

[0006] Secondly, embodiments of this application provide an HBM data migration control system based on access frequency analysis, including a storage controller. The storage controller includes an acquisition module, an analysis module, a calculation module, a correction module, a monitoring module, and a migration module, and the modules work in coordination to implement the above-mentioned method.

[0007] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described above.

[0008] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0009] Fifthly, embodiments of this application provide a computer program product, which includes a computer program that implements the above-described method when executed by a processor.

[0010] In one solution provided by the HBM data migration control system based on access frequency analysis, the system acquires memory access requests issued by the host, extracts access information of the target data block and address distribution information of its data block group, and performs adaptive access frequency analysis on the target data block using micro and macro time windows to obtain a heat value that reflects the real-time access characteristics of the data. Then, by combining the spatial locality hopping of the data block group and the real-time operating status of the high-bandwidth memory HBM, the system predicts the comprehensive migration index of the target data block. This ensures that data migration decisions not only reflect the access activity of the target data block but also comprehensively consider data access correlation and HBM resource status, improving the accuracy of data migration decisions. Furthermore, by real-time load monitoring of the storage bus connecting the preset storage medium and the HBM, and combining the real-time load status with the comprehensive migration index to control the migration of the target data block, the data migration process is coordinated with the system data transmission status. When migration conditions are met, the target data block is migrated to HBM storage, thereby improving HBM cache resource utilization and data access efficiency, reducing the impact of data migration on normal system memory access operations, and improving the overall system performance. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of an HBM data migration control system based on access frequency analysis in one embodiment of the present invention; Figure 2 This is a flowchart illustrating an HBM data migration control method based on access frequency analysis in one embodiment of the present invention. Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S20; Figure 4 yes Figure 2 A schematic diagram of the implementation process of step S40; Figure 5 yes Figure 2 A schematic diagram of the implementation process of step S60; Figure 6 yes Figure 1 A schematic diagram of the structure of the memory controller; Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0015] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0016] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0017] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0018] The HBM data migration control method based on access frequency analysis provided in this invention can be applied to applications such as... Figure 1 The HBM data migration control system based on access frequency analysis shown (hereinafter referred to as the system) includes a host, a storage controller, high-bandwidth memory HBM and other storage media (such as preset storage media), wherein the host communicates with the storage controller through a network or bus.

[0019] In practical applications, the storage controller receives memory access requests from the host and extracts access information for a target data block in the preset storage medium, as well as the address distribution information of the data block group to which the target data block belongs. Then, based on the current access information of the target data block, the storage controller performs adaptive access frequency analysis on the target data block through micro and macro time windows to calculate the real-time access heat value of the target data block. Based on the address distribution information, it calculates the spatial locality kilometry of the data block group to which the target data block belongs; spatial locality kilometry characterizes the dispersion of access addresses for all active data blocks within the data block group. Subsequently, based on the real-time operating status of the high-bandwidth memory (HBM), the spatial locality kilometry, and the real-time heat value of the target data block, the storage controller predicts the comprehensive migration index of the target data block. Finally, it monitors the status of the storage bus connecting the preset storage medium and the high-bandwidth memory (HBM) to obtain the real-time load status of the storage bus. Finally, the storage controller performs migration control on the target data block based on the real-time load status and the comprehensive migration index, so that when the comprehensive migration index meets the migration conditions, the target data block is migrated from the preset storage medium to the high bandwidth memory HBM for storage.

[0020] This solution has the following technical effects: First, by acquiring host memory access requests and extracting access information such as access count and access time for target data blocks, a multi-scale access frequency analysis mechanism combining micro and macro time windows is used to dynamically analyze data block access behavior. This allows for the simultaneous perception of short-term access surges and long-term stable access trends, avoiding misjudgments of popularity caused by a single time window, and improving the accuracy of target data block popularity calculation. This solves the problem of inaccurate data popularity identification in existing technologies.

[0021] Secondly, by obtaining the address distribution information of the data block group to which the target data block belongs and calculating the spatial locality judder of the data block group, the spatial correlation between data blocks can be quantitatively analyzed. This can determine whether data access is concentrated in a continuous area, identify a set of data blocks with common access potential, avoid invalid caching caused by migration based solely on the access frequency of a single data block, thereby improving the rationality of data migration object selection and solving the problems of unreasonable migration granularity and low caching benefits.

[0022] Furthermore, by combining the real-time operating status of HBM, spatial locality hopping, and the real-time heat value of the target data block, a comprehensive migration index is predicted. This allows migration decisions to no longer rely on a single access indicator, but to comprehensively consider the data access value, the spatial correlation value of the data, and the current carrying capacity of HBM. As a result, high-value data can be migrated first, and invalid data can be reduced to occupy HBM space, thereby improving HBM cache utilization.

[0023] In addition, by monitoring the storage bus load status between the preset storage medium and HBM in real time, and dynamically adjusting the migration behavior according to the bus load status, data migration is performed when the bus is idle to improve migration efficiency, and migration pressure is reduced when the bus is busy to avoid affecting business access. Resource coordination between migration tasks and normal memory access tasks is also achieved, thereby improving the overall stability of the system and data access performance.

[0024] In summary, this application achieves intelligent control of the HBM cache data migration process by integrating multi-timescale access heat analysis, spatial locality evaluation, HBM state awareness, and bus load adjustment. This improves the utilization efficiency of HBM cache space and data access efficiency, and solves the problems of inaccurate data heat judgment, unreasonable migration decisions, and the impact of the migration process on business performance in the existing HBM hierarchical storage architecture.

[0025] In one embodiment, such as Figure 2 As shown, an HBM data migration control method based on access frequency analysis is provided, which is then applied to... Figure 1 Taking the storage controller in the example, the following steps are included: S10: Obtain the memory access request issued by the host, and extract the access information for the target data block in the preset storage medium, as well as the address distribution information of the data block group to which the target data block belongs, based on the memory access request.

[0026] The storage controller first receives a memory access request from the host (i.e., a computing unit such as a CPU or GPU) through its front-end interface. This memory access request is a standard read / write instruction, which contains the target logical address to be accessed. The storage controller maintains an address mapping table internally. By querying this address mapping table, the logical address issued by the host is translated into the corresponding physical address in a preset storage medium (such as a solid-state drive (SSD) or non-volatile memory (NVM), thereby determining the target data block.

[0027] Next, the storage controller extracts the access information of the target data block from the memory access request. The access information includes the access timestamp (i.e., the time when the host initiated this access) and the number of accesses. At the same time, the storage controller determines the data block group to which the target data block belongs based on the preset data block grouping rules (e.g., grouping multiple data blocks into a group according to a continuous physical address range), and obtains the address distribution information of all data blocks in the data block group, that is, the physical address range and distribution of each data block in the group in the preset storage medium.

[0028] The pre-defined storage medium refers to the back-end storage device used for long-term data storage, typically a non-volatile storage medium such as NAND flash solid-state drives (SSDs) or non-volatile high-speed memory (NVM). Its access speed is lower than high-bandwidth memory (HBM) but its capacity is larger. The target data block refers to the smallest unit of data currently targeted by a host memory access request, which is then used for access frequency analysis and migration decisions. A data block cluster refers to a collection of multiple data blocks divided according to pre-defined rules (such as physical address contiguousness, logical address association, or similar application characteristics), used to evaluate spatial locality characteristics.

[0029] S20: Based on the current access information of the target data block, adaptive access frequency analysis of the target data block is performed through time windows at different levels of micro and macro to calculate the real-time heat value of the target data block being accessed.

[0030] The micro-time window refers to a short window (e.g., seconds) used to capture short-term bursty access patterns of data blocks. At the macro-level, the historical heat value of the target data block within a preset macro-time window is obtained. This macro-time window is used to assess the long-term stable access trend of the data block and has a longer window length (e.g., minutes). Simultaneously, an adaptive cooling coefficient is calculated based on the real-time operating status of High Bandwidth Memory (HBM). High Bandwidth Memory (HBM) is a high-performance memory that interconnects multiple stacked DRAM chips using through-silicon via (TSV) technology. The real-time heat value is a dimensionless numerical value used to quantify the current access frequency of a data block.

[0031] After extracting the current access information of the target data block, the storage controller maintains two time windows at different scales. At the micro level, it statistically analyzes the real-time access frequency of the target data block within a preset micro-time window and calculates the standard deviation of the time interval between each access within that window to quantify the suddenness and regularity of access. Finally, by combining the real-time access frequency and standard deviation of access intervals at the micro level, the historical popularity value at the macro level, and the adaptive cooling coefficient, a preset adaptive frequency analysis algorithm is used to calculate the real-time popularity value of the target data block being accessed.

[0032] For example, the storage controller uses a dual sliding window frequency ratio method to calculate the real-time heat value. It counts real-time access frequency within a micro-time window and total access frequency within a macro-time window. It maintains a preset baseline frequency threshold and calculates both micro-activity and macro-activity indicators. It obtains the current remaining bandwidth percentage and current temperature of the HBM, calculates the system load factor, and finally calculates the real-time heat value. S30: Based on address distribution information, calculate the spatial locality jitter of the data block group to which the target data block belongs. Spatial locality jitter is used to characterize the dispersion of access addresses of all active data blocks within the data block group.

[0033] Based on the acquired address distribution information, the storage controller first divides the data storage space of the data block group to which the target data block belongs within a preset storage medium. Then, it acquires the physical addresses of all active data blocks within this space and calculates the variance of all physical addresses to obtain the address variance value. Finally, it uses a preset positive correlation increasing function to calculate the dispersion of the address variance value, obtaining the spatial locality jerk. The spatial locality jerk is a quantitative index used to characterize the dispersion of access addresses of all active data blocks within a data block group, typically ranging from 0 to 1. Random access corresponds to a large address variance value, and therefore a large spatial locality jerk; sequential access corresponds to a small address variance value, and therefore a small spatial locality jerk. In this way, random access and sequential access are clearly distinguished.

[0034] S40: Based on the real-time operating status of high-bandwidth memory (HBM), spatial locality hopping, and the real-time heat value of the target data block, predict the comprehensive migration index of the target data block.

[0035] The storage controller uses three types of input parameters to predict the comprehensive migration index. The first type is the real-time operating status of HBM, including the active page ratio and real-time temperature, used to calculate the operating status correction factor, which characterizes the current hardware security boundary of HBM. The second type is the spatial locality jitter calculated in step S30, used to calculate the spatial correction coefficient to amplify the migration priority of random access data blocks. The third type is the real-time heat value calculated in step S20. Finally, the real-time heat value is corrected using the correction coefficient and the operating status correction factor to obtain the comprehensive migration index. The comprehensive migration index is a comprehensive score calculated by considering the data block's own access heat, the address distribution characteristics of its data block group, and the real-time operating status of HBM, used to ultimately determine whether to migrate the target data block to HBM.

[0036] For example, a storage controller can use a neural network prediction model to calculate the comprehensive migration index. A three-layer fully connected neural network (6 nodes in the input layer, 8 nodes in the hidden layer, and 1 node in the output layer) is pre-trained using historical data. During real-time inference, six parameters—the proportion of active pages in the HBM, the real-time HBM temperature, the spatial locality hopping, the real-time heat value of the target data block, the standard deviation of the access interval within the micro-time window, and the historical heat value within the macro-time window—are used as input feature vectors. These parameters are then fed into the neural network for forward propagation calculation, directly outputting the comprehensive migration index.

[0037] S50: Monitors the status of the storage bus that connects the preset storage medium to the high-bandwidth memory HBM, and obtains the real-time load status of the storage bus.

[0038] The storage controller continuously monitors the status of the storage bus connecting the preset storage medium and the HBM. The storage bus refers to the data communication channel connecting the back-end slow storage and the front-end high-speed cache, such as a PCIe bus or a CXL interconnect bus. By reading the performance monitoring counters on the bus or the status register of the bus controller, the controller obtains indicators such as the current bandwidth utilization, transaction queue depth, and average latency of the bus, and comprehensively obtains the real-time load status of the storage bus. This real-time load status reflects the current workload of the bus.

[0039] S60: Based on real-time load status and comprehensive migration index, the target data block is migrated from the preset storage medium to the high bandwidth memory HBM when the comprehensive migration index meets the migration conditions.

[0040] The storage controller dynamically calculates the current migration admission threshold based on the real-time load status of the storage bus, and then compares the comprehensive migration index calculated in step S40 with this threshold. When the comprehensive migration index is greater than or equal to the migration admission threshold, the migration condition is met, and the storage controller initiates the migration process, writing the target data block from the preset storage medium to the free address space of the HBM through the storage bus, and updating the address mapping table so that subsequent accesses point to the new location in the HBM. When the comprehensive migration index is less than the migration admission threshold, migration is not performed.

[0041] For example, the storage controller uses a proportional-integral-derivative (PID) controller to dynamically adjust the migration rate. The input to the PID controller is the deviation between the current real-time load state of the storage bus and the preset target load state. The PID outputs a migration rate factor, sorts all data blocks to be migrated from high to low according to the overall migration index, and performs migration sequentially according to the rate determined by the migration rate factor. When the bus load is lower than the target, the migration rate increases; when the bus load is higher than the target, the migration rate decreases or even stops.

[0042] This embodiment provides foundational data support for subsequent multi-level analysis by acquiring access information of the target data block and the address distribution information of its group of data blocks. Adaptive access frequency analysis using micro and macro time windows at different levels can sensitively capture short-term burst access characteristics while also considering long-term stable access trends. Simultaneously, dynamic adjustment based on HBM real-time operating status is introduced, ensuring that the heat value accurately reflects the actual heat of the data block under the current system state. By calculating spatial locality judder, random access and sequential access are effectively distinguished, giving random access data a higher migration priority. A comprehensive migration index is predicted by combining HBM real-time operating status, spatial locality judder, and real-time heat value, comprehensively evaluating the migration value of the data block from multiple dimensions. Through storage bus status monitoring and load-based dynamic migration control, it is ensured that migration operations do not interfere with normal host memory access performance, significantly reducing access latency for hot data and improving the overall storage performance of the system.

[0043] In one embodiment, such as Figure 3 As shown, in step S20, based on the current access information of the target data block, adaptive access frequency analysis is performed on the target data block through time windows at different micro and macro levels to calculate the real-time access popularity value of the target data block. This specifically includes the following steps: S21: Based on access information, count the real-time access frequency of the target data block within a preset micro time window, and calculate the standard deviation of the access interval between each access of the target data block within the preset micro time window.

[0044] The storage controller retrieves all access records of the target data block within a preset micro-time window from the access information. The access information includes access time and access frequency. The preset micro-time window refers to a relatively short time length preset by the system to limit the statistical range at the micro-level, typically on the order of seconds. The storage controller maintains a circular buffer to store the timestamps of each access to the target data block within the micro-time window. When a new access arrives, the timestamp is written, and old timestamps outside the micro-time window are removed. The real-time access frequency is obtained by counting the number of valid timestamps in the buffer. Simultaneously, the difference between the timestamps of two adjacent accesses in the buffer is calculated to obtain an access interval sequence, and then the standard deviation of these access intervals is calculated using the standard deviation formula. The standard deviation of the access interval is used to measure the regularity or burstiness of access: a smaller standard deviation indicates more regular access (e.g., periodic scanning), while a larger standard deviation indicates more bursty access (e.g., a periodic high-volume access followed by a long period of idle time).

[0045] S22: Obtain the historical heat value of the target data block within a preset macro time window, and calculate the adaptive cooling coefficient of the high bandwidth memory HBM based on the real-time running status of the high bandwidth memory HBM.

[0046] The storage controller reads the historical heat values ​​of the target data block within a preset macro-time window from the metadata of persistent storage. The preset macro-time window refers to a relatively long time period preset by the system to measure the long-term access heat trend of the data block, typically on the order of minutes. The historical heat values ​​refer to the heat values ​​calculated and stored for the target data block in previous heat calculation cycles. Simultaneously, the storage controller queries the HBM controller for the current real-time operating status of the HBM, which includes the number of active pages occupied in the HBM and the real-time temperature of the HBM. Based on these parameters, an adaptive cooling coefficient is calculated using a preset calculation function. The adaptive cooling coefficient is a decay coefficient that dynamically adjusts according to the real-time operating status of the HBM, used to control the decay rate of the heat value over time. When the HBM load is high or the temperature is high, the cooling coefficient increases, the heat decay accelerates, and new data migration is inhibited; when the HBM is idle and the temperature is low, the cooling coefficient decreases, the heat decay slows down, and it is conducive to the migration of hot data.

[0047] S23: Based on the adaptive cooling coefficient, access interval standard deviation, real-time access frequency, and historical heat value, analyze the current access frequency of the target data block to obtain the real-time heat value.

[0048] The storage controller uses the real-time access frequency and access interval standard deviation obtained in step S21, and the historical heat value and adaptive cooling coefficient obtained in step S22 as input parameters, and performs a comprehensive analysis through a preset heat calculation model. First, it uses the real-time access frequency and historical heat value to calculate an initial heat value. Then, it uses the access interval standard deviation to identify the regularity of access patterns and corrects the initial heat value—moderately suppressing access when the standard deviation is small to exclude periodic scans, and moderately enhancing access when the standard deviation is large to highlight the high value of random access. Simultaneously, it uses the adaptive cooling coefficient to dynamically adjust the attenuation of the historical heat value. Finally, after comprehensive calculation, it outputs the current real-time heat value of the target data block.

[0049] This embodiment achieves a multi-dimensional evaluation of data block access frequency by combining micro and macro time windows at different levels. The real-time access frequency and standard deviation of the access interval of the micro time window capture the characteristics and regularity of short-term burst access, while the historical heat value of the macro time window maintains the continuity of long-term access trends. The introduction of an adaptive cooling coefficient enables heat calculation to perceive the real-time carrying capacity of the HBM, accelerating heat decay to reduce migration frequency under high load and slowing down heat decay to allow more migration under low load. The real-time heat value obtained by the comprehensive calculation of these three factors can accurately and comprehensively reflect the actual heat of the data block under the current system state, providing a reliable quantitative basis for subsequent migration decisions and effectively avoiding misjudgments caused by burst access and performance degradation caused by system overload.

[0050] In one embodiment, step S23, which involves analyzing the current access frequency of the target data block based on the adaptive cooling coefficient, access interval standard deviation, real-time access frequency, and historical heat value to obtain the real-time heat value, specifically includes the following steps: S231: Using a preset time decay factor, perform an exponentially weighted moving average calculation on the real-time access frequency and historical popularity value to obtain the current initial popularity of the target data block.

[0051] The storage controller reads a preset time decay factor (typically between 0.3 and 0.7) from the system configuration. This preset time decay factor is a constant between 0 and 1, used to control the rate at which the weights of historical data decay in the exponentially weighted moving average. The exponentially weighted moving average is a weighted averaging method where the weight of each data point decreases exponentially over time, with more recent data having a larger weight. The storage controller normalizes the real-time access frequency and then calculates an exponentially weighted moving average with the historical popularity values ​​to obtain the current initial popularity. Through this calculation, historical popularity values ​​influence the current popularity in an exponentially decaying manner; earlier historical popularity contributes less, while more recent access frequencies contribute more.

[0052] S232: Determine the thermal correction value based on the standard deviation of the time interval and the adaptive cooling coefficient.

[0053] The storage controller takes the calculated access interval standard deviation and adaptive cooling coefficient as inputs, and calculates a thermal correction value using a preset correction function. The thermal correction value is a correction amount calculated based on the access interval standard deviation and adaptive cooling coefficient, used to adjust the initial temperature positively or negatively.

[0054] The design principle of the correction function is as follows: when the standard deviation of the access interval is large (bursting or random access patterns), positive correction is applied because randomly accessed data blocks usually have higher caching value; when the standard deviation of the access interval is small (regular access patterns), negative correction or a small positive correction is applied to suppress misjudgment of regular access patterns. Meanwhile, the adaptive cooling coefficient acts as a scaling factor; a larger value compresses the correction magnitude, while a smaller value amplifies it.

[0055] S233: Perform nonlinear correction on the initial heat value based on the heat correction value to obtain the real-time heat value.

[0056] The storage controller uses the initial heat value and heat correction value to calculate the final real-time heat value through a nonlinear correction function. This nonlinear correction refers to the process of transforming the initial data using a nonlinear function, aiming to improve the data distribution characteristics or control the mapping relationship within a specific range. The nonlinear correction function can be a sigmoid function or a piecewise power function. Through nonlinear correction, the heat value can have better discrimination in the middle range and better saturation control in the extreme ranges, avoiding frequent out-of-bounds heat values.

[0057] This embodiment achieves a smooth transition of popularity values ​​through an exponentially weighted moving average, preserving the long-term trend of historical popularity values ​​while incorporating short-term changes in current access frequency, effectively avoiding the problem of drastic fluctuations in popularity values ​​caused by a single sudden access. Popularity correction based on the standard deviation of access intervals positively corrects random accesses to improve migration priority, suppresses regular accesses to reduce the probability of false migrations, and the introduction of an adaptive cooling coefficient allows the correction magnitude to dynamically change with system load. Through nonlinear correction, the final real-time popularity value has better numerical distribution characteristics, higher discrimination in the medium popularity region, and saturation control in the high and low popularity regions.

[0058] In one embodiment, the real-time operating status of the high-bandwidth memory (HBM) includes the number of active pages occupied in the HBM and the real-time temperature of the HBM. Step S22, which calculates the adaptive cooling coefficient of the HBM based on its real-time operating status, specifically includes the following steps: S221: The ratio of the number of active pages in the high-bandwidth memory HBM to the total physical capacity of the high-bandwidth memory HBM is used as the active page ratio.

[0059] The storage controller sends a status query command to the HBM controller to obtain the number of currently occupied active pages in the HBM and reads the total physical capacity from the HBM's configuration register. The number of active pages refers to the number of memory pages currently allocated and in active use within the HBM. The total physical capacity refers to the maximum storage capacity that the HBM can provide at the physical level, expressed in pages. Then, the active page ratio is calculated; this ratio is a real number between 0 and 1, reflecting the current space occupancy rate of the HBM.

[0060] S222: The temperature deviation value is calculated based on the real-time temperature of the high-bandwidth memory HBM and the preset safe temperature threshold.

[0061] The storage controller reads the real-time temperature value of the HBM through its temperature sensor interface and retrieves a preset safe temperature threshold from the system configuration. The real-time temperature refers to the current operating temperature of the HBM chip, collected in real-time by the HBM's built-in temperature sensor. The preset safe temperature threshold is the system-preset maximum safe operating temperature value for the HBM, typically recommended by the HBM manufacturer. Then, a temperature deviation value is calculated. A calculated temperature deviation value less than or equal to 0 indicates that the HBM temperature is within the safe range; a calculated temperature deviation value greater than 0 indicates that the temperature has exceeded the safe threshold.

[0062] S223: By multiplying the logarithmic function of the active page ratio and the exponential function of the temperature deviation value, the preset base cooling coefficient is proportionally adjusted to generate an adaptive cooling coefficient.

[0063] The storage controller takes the active page ratio and temperature deviation as inputs and adjusts the preset base cooling coefficient proportionally. The base cooling coefficient refers to a preset benchmark value for cooling coefficients, which serves as the starting point for adaptive adjustment.

[0064] For example, the product of the logarithmic function of the active page ratio and the exponential function of the temperature deviation value can be used as the ratio adjustment coefficient, which is then multiplied by the preset base cooling coefficient to obtain the adaptive cooling coefficient.

[0065] In this embodiment, a fine-grained dynamic adjustment of the cooling coefficient is achieved by combining the logarithmic and exponential functions of the active page ratio and temperature deviation value. The logarithmic function of the active page ratio reflects the decreasing characteristics of the impact of capacity utilization, making the adjustment smoother and more reasonable; the exponential function of the temperature deviation value amplifies the impact of temperature exceeding limits exponentially, enabling a sharp increase in the cooling coefficient when the HBM temperature is about to exceed the safety threshold, effectively preventing thermal runaway caused by frequent migration at high temperatures. The product of the two functions couples the comprehensive influence of capacity load and thermal state on the cooling coefficient, allowing the adaptive cooling coefficient to fully reflect the load-bearing capacity and safety margin of the HBM, providing accurate attenuation control parameters for subsequent thermal calculations.

[0066] In one embodiment, step S30, which involves calculating the spatial locality jitter of the data block group to which the target data block belongs based on address distribution information, specifically includes the following steps: S31: Divide the data storage space range of the data block group to which the target data block belongs in the preset storage medium.

[0067] The storage controller determines the contiguous address range occupied by the data block group to which the target data block belongs within the physical address space of the preset storage medium, according to preset data block group partitioning rules. The data storage space range of the data block group refers to the contiguous physical address interval allocated to a specific data block group in the preset storage medium.

[0068] The partitioning rules for data block groups can be either physical address-aligned partitioning (dividing the entire storage space into several fixed-size contiguous regions, each region being a data block group) or logical address-based hash grouping. The storage controller queries the group metadata table to find the data block group ID to which the target data block belongs based on its physical address, and obtains the start and end physical addresses of that data block group.

[0069] S32: Obtain the physical addresses of all active data blocks within the data storage space, and calculate the variance of all physical addresses to obtain the address variance value.

[0070] Within the data storage space determined in step S31, the storage controller traverses the address mapping table or active bitmap of all data blocks within this range, marking all data blocks in an active state. The active data blocks refer to data blocks stored in a preset storage medium that have been accessed by the host within the most recent monitoring period. For each active data block, its physical address is obtained. Assuming the total number of active data blocks is N, the arithmetic mean of the physical addresses is calculated for the set of physical addresses, and then the address variance is calculated. The address variance reflects the spatial dispersion of the physical addresses of active data blocks within the data block group; a larger variance indicates a more dispersed address distribution, while a smaller variance indicates a more concentrated address distribution.

[0071] S33: The address variance value is discretely calculated using a preset positive correlation increasing function to obtain the spatial locality judder, wherein the spatial locality judder corresponding to random access is greater than that corresponding to sequential access.

[0072] The storage controller takes the address variance as input and converts it into spatial locality jerk using a preset positive correlation increasing function. The preset positive correlation increasing function is a predefined function whose output value monotonically increases with the input value. The spatial locality jerk is a quantitative indicator used to characterize the dispersion of access addresses of all active data blocks within a data block group, typically ranging from 0 to 1.

[0073] For example, a nonlinear normalization function can be used to perform discreteness mapping calculation on the address variance value. Through this mapping, the address variance generated by random access is large, and the corresponding spatial locality judder is close to 1; the address variance generated by sequential access is small, and the corresponding spatial locality judder is close to 0.

[0074] This embodiment accurately quantifies the address dispersion of active data blocks within a data block cluster by calculating address variance and mapping using a positively correlated increasing function. Address variance effectively reflects the distribution characteristics of data blocks in the storage space; a larger variance indicates a higher degree of random access. The positively correlated increasing function transforms address variance into spatial locality judder, clearly distinguishing between random and sequential access. The spatial locality judder corresponding to random access is much greater than that of sequential access, which aligns with the basic principle of cache replacement strategies—randomly accessed data blocks, lacking spatial locality, may cause random reads of slow storage media with each access, making migration to HBM more beneficial. Spatial locality judder provides crucial spatial feature input for subsequent migration index calculation, enabling migration decisions to fully consider the impact of address distribution characteristics.

[0075] In one embodiment, such as Figure 4 As shown, step S40, which involves predicting the comprehensive migration index of the target data block based on the real-time operating status of the high-bandwidth memory (HBM), spatial locality hopping, and the real-time heat value of the target data block, specifically includes the following steps: S41: Obtain the percentage of active pages occupied in the high-bandwidth memory HBM, as well as the real-time temperature of the high-bandwidth memory HBM.

[0076] The storage controller obtains real-time operational status data packets of the HBM by sending status query commands to the HBM controller. From these packets, the number of active pages and total physical capacity are extracted, the active page ratio is calculated, and the real-time temperature value reported by the HBM's built-in temperature sensor is also extracted. The active page ratio reflects the HBM's capacity load status, and the real-time temperature reflects the HBM's thermal safety status.

[0077] S42: Based on the active page ratio and real-time temperature, calculate the operating state correction factor used to characterize the hardware security boundary.

[0078] Specifically, the natural logarithm of the active page ratio plus 1 is used as the capacity load characteristic value; the temperature deviation between the real-time temperature and the preset safe temperature threshold is used as the exponent of the natural logarithm base to calculate the temperature safety characteristic value; the product of the capacity load characteristic value and the temperature safety characteristic value is added to 1 and the reciprocal is taken to obtain the operating status correction factor.

[0079] The capacity load characteristic value is obtained by adding 1 to the active page ratio and taking the natural logarithm, used to quantify the HBM's capacity occupancy. The temperature safety characteristic value is obtained by exponentiation of the temperature deviation value as the base of the natural logarithm, used to quantify the HBM's temperature safety risk level. The operating status correction factor is a correction coefficient calculated based on the HBM's current capacity load and thermal state, used to characterize the HBM's ability to safely receive new migrated data, with a value range of (0,1). When the HBM load is light and the temperature is safe, M is close to 1; when the HBM load is heavy or the temperature is high, M approaches 0.

[0080] S43: Based on spatial locality judder, the correction coefficient of spatial locality judder is calculated, and the correction coefficient is used to amplify the random access migration priority.

[0081] The correction coefficient for spatial locality judder is a multiplicative coefficient calculated based on spatial locality judder, used to adjust migration priorities according to the address distribution characteristics of data block groups. Specifically, the correction coefficient can be the product of a preset coefficient and the spatial locality judder, plus 1.

[0082] S44: Based on the correction coefficient and the operation status correction factor, the real-time heat value of the target data block is corrected and calculated to obtain the comprehensive migration index.

[0083] The storage controller takes the real-time heat value, correction coefficient, and operating status correction factor as inputs and calculates the comprehensive migration index using a comprehensive correction formula. The comprehensive migration index is a comprehensive score calculated by considering the access heat of the data block itself, the address distribution characteristics of its data block group, and the real-time operating status of HBM. The real-time heat value reflects the access heat of the data block itself, the correction coefficient reflects the amplification effect of random access characteristics, and the operating status correction factor reflects the constraint effect of the HBM hardware security boundary.

[0084] For example, the comprehensive migration index can be obtained by multiplying the real-time heat value, the correction coefficient, and the running status correction factor. The three can be combined through multiplication: the hotter the data block, the stronger the random access characteristics, and the more secure the HBM state, the higher the comprehensive migration index, indicating that the data block should be migrated to HBM.

[0085] This embodiment provides a complete multi-dimensional comprehensive migration index prediction scheme through the comprehensive calculation of the operating status correction factor, spatial correction coefficient, and real-time thermal value. The operating status correction factor uses the product of the capacity load characteristic value and the temperature safety characteristic value, added to 1 and taking the reciprocal, to couple the HBM's capacity load and thermal state to the migration decision. The exponential function of the temperature safety characteristic value causes the correction factor to decrease sharply when the temperature exceeds the limit, enabling rapid response to thermal risks. The spatial correction coefficient adopts a simple and efficient linear function form, and the amplification intensity can be flexibly adjusted through preset coefficients, realizing the automatic amplification of the migration priority of random access data blocks. The multiplicative calculation formula of the comprehensive migration index comprehensively and objectively reflects the actual migration value of the target data block under the current system state, ensuring that frequently accessed data is migrated first, randomly accessed data receives additional priority, and migration behavior is automatically suppressed when HBM resources are scarce or the temperature is too high, achieving a balance between high performance and high reliability.

[0086] In one embodiment, such as Figure 5 As shown, in step S60, migration control of the target data block is performed based on the real-time load status and the comprehensive migration index, so that when the comprehensive migration index meets the migration conditions, the target data block is migrated from the preset storage medium to the high-bandwidth memory HBM for storage. Specifically, this includes the following steps: S61: Based on the real-time load status of the storage bus, dynamically calculate the migration admission criteria for high-bandwidth memory HBM to obtain the current migration admission threshold for high-bandwidth memory HBM.

[0087] The storage controller acquires the real-time load status of the storage bus and calculates the current migration admission threshold according to a preset dynamic admission threshold calculation formula. The migration admission criterion refers to the threshold condition for determining whether a data block is allowed to migrate from a preset storage medium to HBM. The current migration admission threshold is a numerical threshold dynamically calculated based on the current real-time load status of the storage bus; only data blocks whose comprehensive migration index reaches or exceeds this threshold can be migrated.

[0088] For example, multiply the preset load sensitivity coefficient by the real-time load status and add it to 1 to obtain the load coefficient. Multiply the load coefficient by the preset basic admission threshold to obtain the current migration admission threshold for high bandwidth memory (HBM). When the bus is idle, the admission threshold is lower; when the bus is busy, the admission threshold is higher.

[0089] S62: When the overall migration index is greater than or equal to the current migration admission threshold, the target data block will be migrated from the preset storage medium to the high bandwidth memory HBM for storage.

[0090] The storage controller compares the overall migration index with the current migration admission threshold. If the overall migration index is greater than or equal to the current migration admission threshold, the target data block is deemed to meet the migration conditions, and the storage controller initiates the data migration process. The migration process includes: allocating free physical address space in HBM; initiating data transfer from the preset storage medium source physical address to the target physical address in HBM via the DMA controller; updating the address mapping table after the transfer is complete; modifying the logical address mapping of the target data block to the new address in HBM; and finally, releasing the source page in the preset storage medium. After completing the above operations, all subsequent accesses to the target data block will be directly served by HBM, resulting in lower access latency and higher bandwidth.

[0091] This embodiment achieves adaptive adjustment of migration behavior to bus load conditions by calculating a dynamic admission threshold based on the real-time load status of the storage bus. When the bus is idle, the admission threshold is lowered to fully utilize idle bandwidth for data migration; when the bus is busy, the admission threshold is raised to reduce interference with normal host access during migration operations. Strict threshold comparisons ensure that only data blocks whose overall migration index meets the admission criteria are migrated, achieving high-quality screening for migration operations. The migrated data blocks are served by HBM, significantly reducing access latency and increasing access bandwidth, thereby significantly accelerating the execution efficiency of host applications.

[0092] In one embodiment, step S61, which involves dynamically calculating the migration admission criteria for high-bandwidth memory (HBM) based on the real-time load status of the storage bus to obtain the current migration admission threshold for HBM, specifically includes the following steps: S611: Real-time monitoring of the instruction queue depth of the controller for high-bandwidth memory (HBM) and the current bandwidth utilization of the storage bus.

[0093] The storage controller reads the current depth of its instruction queue, or instruction queue depth, through the register interface of the HBM controller. The instruction queue depth refers to the number of instructions currently queued and waiting to be processed in the HBM controller's instruction queue, and is used to measure the HBM controller's workload level. Simultaneously, the storage controller reads the current bandwidth utilization through the link layer performance counter of the storage bus. The current bandwidth utilization of the storage bus refers to the ratio of the current actual data transfer rate to the maximum theoretical bandwidth, and is used to measure the bus link's workload level. These two metrics reflect the current congestion level of the storage data path from two dimensions: the internal workings of the HBM controller and the bus links, respectively.

[0094] S612: By utilizing the positive correlation function between instruction queue depth and bandwidth utilization, a weighted amplification of the preset basic admission threshold is obtained to obtain the migration admission threshold, thereby raising the admission threshold for data migration to high-bandwidth memory (HBM) when the storage bus is busy.

[0095] The storage controller takes the instruction queue depth and bandwidth utilization as inputs, and weights and amplifies the basic admission threshold using a preset positive correlation function to obtain the migration admission threshold. The positive correlation function is a function whose output value monotonically increases as the input value increases.

[0096] As instruction queue depth increases or bandwidth utilization rises, the migration admission threshold increases accordingly, thereby raising the entry barrier for data migration to HBM. When both metrics are low (system idle), the admission threshold is close to the baseline value, allowing more data migration; when both metrics are high (system busy), the admission threshold is significantly amplified, allowing only extremely high-volume data blocks to migrate.

[0097] This embodiment comprehensively perceives the real-time congestion status of the storage data path from two levels by simultaneously monitoring the instruction queue depth of the HBM controller and the bandwidth utilization of the storage bus. The instruction queue depth reflects the pressure on the HBM controller side, while the bandwidth utilization reflects the pressure on the bus links. The combination of these two provides a more accurate load perception input for dynamic admission threshold calculation. By weighting and amplifying the basic admission threshold through a positive correlation function, the migration admission threshold can reflect the congestion status of the storage data path in real time. When the system is busy, the admission threshold is automatically raised to ensure that migration operations do not exacerbate congestion, and when the system is idle, the admission threshold is lowered to make full use of idle resources for data warm-up, significantly improving the precision of migration control and system stability.

[0098] In one embodiment, step S60 or S62, which involves migrating the target data block from the preset storage medium to the high-bandwidth memory (HBM) for storage, specifically includes the following steps: S621: Maintain cold track queue, observation track queue and jump track queue inside the storage control system. The cold track queue, observation track queue and jump track queue are used to store the index information of data blocks in preset storage media with different migration priorities.

[0099] The storage control system maintains three independent data structures. The cold track queue stores index information for data blocks with low access frequency and has the lowest migration priority. The observation track queue stores indexes of data blocks that have shown some activity but have not yet met migration criteria; it is used for continuous monitoring and evaluation. The leap track queue stores indexes of data blocks that have met all migration criteria and are awaiting physical data migration; it has the highest migration priority. Each queue stores index information for data blocks (such as data block ID, physical address, logical address, etc.), not the data content itself. These three queues form a three-stage pipeline structure: data block indexes first enter the cold track queue; when the access frequency reaches a threshold, they are upgraded to the observation track queue; and when the overall migration index reaches the admission standard, they are upgraded to the leap track queue to await actual migration.

[0100] S622: When the real-time access frequency of the target data block within the preset micro time window reaches the preset frequency, the index information of the target data block is moved from the cold track queue to the observation track queue, and a shadow routing pointer pointing to the reserved space in the high bandwidth memory HBM is allocated for the target data block in the memory page table. At this time, no physical data migration occurs.

[0101] The storage controller continuously monitors the real-time access frequency of each data block in the cold track queue within a preset micro-time window. When the real-time access frequency of a target data block reaches or exceeds a preset frequency threshold, it determines that the data block has exhibited sufficient access activity. The preset frequency refers to a system-preset access frequency threshold used to trigger an upgrade operation from the cold track queue to the observation track queue. The storage controller removes the index information of the target data block from the cold track queue and inserts it into the observation track queue. Simultaneously, a shadow routing pointer pointing to pre-reserved free space in the HBM is allocated for the target data block in the page table of the memory management unit. This shadow routing pointer is a pointer pre-allocated in the memory page table pointing to reserved space in the HBM, used directly during subsequent physical migration to reduce address allocation latency. At this time, no actual physical data migration occurs, and the target data block remains intact in the preset storage medium.

[0102] S623: When the comprehensive migration index corresponding to the target data block in the observation track queue is greater than or equal to the migration admission threshold, obtain the number of migrations of the target data block within the preset historical period and calculate the historical migration penalty factor.

[0103] The storage controller continuously calculates the comprehensive migration index T for each data block in the observation track queue and compares T with the current migration admission threshold. When the comprehensive migration index of a target data block is greater than or equal to the migration admission threshold, the next step of judgment is triggered. The storage controller queries the metadata of the data block to record the number of historical migrations within a preset historical period. The preset historical period refers to a backtracking time range preset by the system to count the number of historical migrations of data blocks within that time period. The historical migration penalty factor is a penalty coefficient calculated based on the number of migrations of a data block within the preset historical period, used to suppress frequent oscillating migration behavior of data blocks.

[0104] For example, the historical migration penalty factor is calculated as: P = 1 + δ × N_mig, where δ is the preset penalty coefficient and N_mig is the number of historical migrations. The more historical migrations, the larger the historical migration penalty factor P, indicating that the data block has oscillating characteristics: it frequently migrates back and forth between the storage medium and HBM, wasting migration bandwidth and system resources.

[0105] S624: The migration admission threshold is weighted and amplified using the historical migration penalty factor to obtain the judgment threshold. When the comprehensive migration index is greater than or equal to the judgment threshold, the index information of the target data block is moved into the jump track queue, and the direct memory access DMA controller inside the storage control system is triggered to perform physical data migration.

[0106] The storage controller uses the historical migration penalty factor P obtained in step S623 to weight and amplify the current migration admission threshold Th, resulting in the final decision threshold Th_final = Th × P. This decision threshold refers to the final migration decision threshold after weighting and amplifying by the historical migration penalty factor; only data blocks whose comprehensive migration index reaches or exceeds this threshold can be migrated.

[0107] Since P ≥ 1, Th_final ≥ Th, meaning that data blocks with historical migration records require a higher overall migration index to pass the final judgment. The overall migration index T of the target data block is compared with the judgment threshold Th_final. If T ≥ Th_final, the data block is finally confirmed to be migrated. The storage controller removes the index information of the target data block from the observation track queue and inserts it into the skip track queue, then triggers the internal DMA controller to perform physical data migration.

[0108] The Direct Memory Access (DMA) controller is a hardware engine that enables direct data transfer between a pre-defined storage medium and the HBM without CPU intervention. The DMA controller initiates a physical data copy operation from the source address to the destination address based on the source physical address in the index information and the shadow routing pointer pre-allocated in step S622. After the DMA transfer is complete, the storage controller updates the address mapping table, ensuring that subsequent access to the data block is serviced by the HBM.

[0109] This embodiment achieves refined and progressive management of data block migration status through hierarchical management of cold track → observation track → jump track; by weighting and amplifying the migration admission threshold with a historical migration penalty factor, the system can effectively suppress frequent oscillating migration behavior of data blocks—the threshold for the first migration is the lowest, and the threshold for each subsequent migration gradually increases, so that only truly hot and consistently stable data blocks can be repeatedly migrated, while those data blocks that fluctuate in temperature will be gradually excluded from the migration candidates; combined with the hardware acceleration of the DMA controller, the physical data migration process is efficient and does not consume CPU resources, achieving migration control that combines high performance and high stability.

[0110] In one embodiment, the method further includes performing data consistency control on the migrated data, the data consistency control specifically including the following steps: S71: When performing physical data migration on the target data block, the page table status bit of the target data block in the memory management unit is marked as being in the migration state.

[0111] When the storage control system triggers the DMA controller to start the physical data migration of the target data block from the preset storage medium to the HBM, the storage controller first finds the page table entry corresponding to the target data block in the page table of the memory management unit (MMU) and modifies the status bit in the page table entry from the valid state to the migration in progress state.

[0112] The Memory Management Unit (MMU) is a hardware unit in the processor responsible for translating logical addresses into physical addresses. The page table status bit refers to a flag in the page table entry used to identify the current state of the page. The "migration in progress" state refers to the transitional state where a data block is undergoing physical migration from the preset storage medium to the HBM; at this time, the data has not yet fully arrived in the HBM. Setting this status bit is a crucial first step in ensuring data consistency during the migration process, providing a clear basis for differentiated handling of subsequent read and write requests.

[0113] S72: When a read request for a target data block in a migration state is received, the read request is bypassed to the corresponding source physical address in the preset storage medium for data reading.

[0114] While the target data block is in the migration process, if the host issues a read request for that target data block, the storage controller will find the page table status bit to be in the migration state when querying the MMU page table. At this time, the storage controller performs a read bypass operation, directly forwarding the read request to the source physical address corresponding to the data block in the preset storage medium. Complete data is read from the source address and returned to the host via the storage bus. The bypass refers to bypassing the normal HBM read path and sending the request directly to the source physical address in the preset storage medium for processing. The principle behind this design is that during the migration process, the source data in the preset storage medium remains valid and complete until the migration is complete. Therefore, reading from the source address guarantees that correct and complete data is read, and the read request latency is not affected by the migration operation.

[0115] S73: When a write request for a target data block in the migration state is received, asynchronous write-through control is initiated to synchronously write the write data carried by the write request to the source physical address in the preset storage medium and the corresponding reserved free physical address in the high bandwidth memory HBM. After writing to both places is completed, a write success response is returned to the host.

[0116] While the target data block is in the migration process, if the host issues a write request for that target data block, the storage controller queries the MMU page table and finds the status bit to be in the migration state. At this time, the asynchronous write-through control mechanism is activated. The asynchronous write-through control is a data consistency control strategy that simultaneously writes data to both the source and target storage media during the migration process. Specifically, the storage controller writes the write data carried in the write request to two target locations simultaneously—the source physical address corresponding to the data block in the preset storage medium and the free physical address pre-allocated for the data block in the HBM (i.e., the address pointed to by the shadow routing pointer in step S622). The two write operations can be executed in parallel to reduce latency. The storage controller waits for both writes to be completed before returning a write success response to the host. This dual-write strategy ensures that the data in the source storage medium and the HBM remains consistent regardless of the migration stage.

[0117] S74: After the physical data migration is completed, the page table pointer in the memory management unit is updated through atomic operations to point the page table pointer from the source physical address to the physical address in the high bandwidth memory (HBM), and the page table status bits are modified to the valid state.

[0118] Once the DMA controller completes the physical data migration of the target data block, it sends a completion interrupt signal to the memory controller. The memory controller then performs the final switching operation: updating the page table entry corresponding to the target data block in the MMU page table through atomic operations. An atomic operation is a single, uninterruptible operation unit that either succeeds entirely or fails completely, without any intermediate states.

[0119] The page table pointer refers to the field in the MMU page table entry that stores the physical address. Specifically, the physical address field in the page table entry is modified from the source physical address in the preset storage medium to the target physical address in the HBM, and the page table status bit is changed from "migration in progress" to "valid". The "valid" status means that the page table entry is in a normal and usable state, indicating that the corresponding physical address is valid and the data is available. After this atomic update operation is completed, the entire migration process is officially finished. Thereafter, all access requests for the target data block will be translated through the HBM address, and the HBM will provide the data service.

[0120] This embodiment ensures data security and consistency during data migration through a complete data consistency control mechanism. Asynchronous write-through control synchronously writes the data to the source storage medium and HBM, and returns a response only after both places have completed writing. This avoids the risk of write loss or partial write completion, and ensures that no data inconsistency problem will occur even if a system failure occurs during the migration process.

[0121] In one embodiment, the method further includes a bus interleaving and bandwidth compensation process, which specifically includes the following steps: S81: Monitors the ratio of read requests to write requests in memory access requests issued by the host in real time to determine the degree of read-write imbalance.

[0122] The storage controller performs real-time classification and counting of all memory access requests issued by the host at its front-end interface. It maintains a read request counter R_count and a write request counter W_count, respectively counting the number of read requests and write requests received within a preset monitoring time window. At the end of each monitoring time window, the read / write imbalance is calculated as: D = (R_count - W_count) / (R_count + W_count + ε), where ε is a small constant to prevent division by zero.

[0123] The read / write imbalance refers to the relative difference between the number of read requests and the number of write requests within a preset monitoring time window, reflecting the load balancing status of the storage bus read / write channels. The value range of D is [-1, 1]: D = 1 indicates that all requests are read requests (write channel is completely idle), D = -1 indicates that all requests are write requests (read channel is completely idle), and D = 0 indicates that the number of read and write requests is equal.

[0124] S82: When the read-write imbalance indicates that there are only read requests and the write channel of the storage bus is idle, the control scheduler occupies the idle bandwidth of the write channel and performs physical data migration of the target data block from the preset storage medium to the high bandwidth memory HBM.

[0125] The storage controller continuously monitors the read / write imbalance calculated in step S81. When the read / write imbalance is detected to be equal to or very close to 1 (e.g., greater than 0.95), it indicates that the host is only issuing read requests or read requests dominate during the current time period, and the write channel of the storage bus is completely idle. The storage controller sends a control signal to the bus scheduler, requesting the scheduler to allocate the idle bandwidth of the write channel to the data migration operation. The scheduler refers to the bus arbitration or scheduling unit on the storage bus, which is responsible for allocating bus bandwidth to different requesters. After the scheduler approves, the storage controller sends the migration tasks of the data blocks to be migrated in the jump track queue through the write channel: the DMA controller reads the data from the preset storage medium and then transmits the data to the target address of the HBM through the write channel of the storage bus.

[0126] S83: When writing a target data block to a high-bandwidth memory HBM, the target data block is split into multiple sub-data blocks, and these sub-data blocks are interleaved and written to different physical pseudo-channels and different storage array blocks of the high-bandwidth memory HBM.

[0127] When the storage controller performs a physical write operation on the target data block from the preset storage medium to the HBM via the DMA controller, the data writing process is optimized.

[0128] Specifically, the storage controller splits the target data block into multiple smaller sub-data blocks, each sub-data block being the smallest access granularity of an HBM pseudo-channel. A sub-data block refers to a smaller data unit obtained by splitting the original data block according to HBM's smallest access granularity. A pseudo-channel is an independent access channel in HBM, each with independent timing control and data path; multiple pseudo-channels can be accessed in parallel. A storage array block (i.e., a Bank) is a logical partition of the internal storage array of HBM; each Bank can perform independent read and write operations. Then, the storage controller, through the multi-channel interleaved write function of the HBM controller, sequentially and cyclically distributes these sub-data blocks to different physical pseudo-channels and different storage array blocks within HBM.

[0129] This embodiment achieves zero-impact optimization of system performance through bus interleaving and bandwidth compensation processes. By monitoring read / write imbalance in real time, the system can accurately perceive the load differences between read and write channels on the storage bus. When an idle write channel is detected, data migration is performed using the idle write channel bandwidth, ensuring that the bandwidth occupied by the migration operation was originally idle and does not affect the host's normal memory access performance, achieving zero-overhead migration. This bandwidth reuse strategy significantly improves the utilization of the system bus and is particularly suitable for application scenarios with read-centric operations. Simultaneously, by splitting the target data block into sub-blocks and interleaving them across different physical pseudo-channels and storage array blocks in HBM, the advantages of HBM's multi-channel, multi-bank internal parallel architecture are maximized.

[0130] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0131] In one embodiment, a storage controller is provided, which corresponds one-to-one with the HBM data migration control method based on access frequency analysis described in the above embodiments. For example... Figure 6 As shown, the functional modules included in this storage controller are described in detail below: The acquisition module 601 is used to acquire the memory access request issued by the host, and extract the access information of the target data block in the preset storage medium and the address distribution information of the data block group to which the target data block belongs based on the memory access request. Analysis module 602 is used to perform adaptive access frequency analysis on the target data block based on the current access information of the target data block, through time windows at different levels of micro and macro, so as to calculate the real-time heat value of the target data block being accessed. The calculation module 603 is used to calculate the spatial locality judder of the data block group to which the target data block belongs based on address distribution information. The spatial locality judder is used to characterize the dispersion of the access addresses of all active data blocks within the data block group. The correction module 604 is used to predict the comprehensive migration index of the target data block based on the real-time running status of the high-bandwidth memory HBM, the spatial locality judder, and the real-time heat value of the target data block. The monitoring module 605 is used to monitor the status of the storage bus that connects the preset storage medium and the high bandwidth memory HBM, and obtain the real-time load status of the storage bus. The migration module 606 is used to control the migration of the target data block based on the real-time load status and the comprehensive migration index, so as to migrate the target data block from the preset storage medium to the high bandwidth memory HBM when the comprehensive migration index meets the migration conditions.

[0132] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0133] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0134] This application also provides an electronic device, such as... Figure 7 As shown, the electronic device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above-described method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiments. For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0135] Those skilled in the art will understand that Figure 7 The examples described are merely illustrative of the electronic device and do not constitute a limitation on the device. The device may include more or fewer components than illustrated, or combine certain components, or use different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc. The processor described may be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0136] The memory can be an internal storage unit of the electronic device, such as a hard drive or RAM. The memory can also be an external storage device of the electronic device, such as a plug-in hard drive, smart memory card, secure digital card, flash memory card, etc. The memory may include both internal and external storage units of the electronic device.

[0137] This application also provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0138] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographic device / terminal device, a recording medium, a computer memory, a read-only memory, a random access memory, an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0140] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0141] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for HBM data migration control based on access frequency analysis, characterized in that, include: Obtain the memory access request issued by the host, and extract the access information for the target data block in the preset storage medium and the address distribution information of the data block group to which the target data block belongs based on the memory access request; Based on the current access information of the target data block, adaptive access frequency analysis is performed on the target data block through time windows at different levels of micro and macro to calculate the real-time popularity value of the target data block being accessed. Based on the address distribution information, the spatial locality judder of the data block group to which the target data block belongs is calculated. The spatial locality judder is used to characterize the dispersion of the access addresses of all active data blocks within the data block group. Based on the real-time operating status of high-bandwidth memory (HBM), the spatial locality hopping, and the real-time heat value of the target data block, the comprehensive migration index of the target data block is predicted. The status of the storage bus connecting the preset storage medium and the high bandwidth memory HBM is monitored to obtain the real-time load status of the storage bus. Based on the real-time load status and the comprehensive migration index, the target data block is migrated to the high-bandwidth memory (HBM) for storage when the comprehensive migration index meets the migration conditions.

2. The method as described in claim 1, characterized in that, The migration control of the target data block based on the real-time load status and the comprehensive migration index, so as to migrate the target data block from the preset storage medium to the high-bandwidth memory (HBM) when the comprehensive migration index meets the migration conditions, includes: Based on the real-time load status of the storage bus, the migration admission criteria for the high-bandwidth memory (HBM) are dynamically calculated to obtain the current migration admission threshold for the high-bandwidth memory (HBM). When the overall migration index is greater than or equal to the current migration admission threshold, the target data block is migrated from the preset storage medium to the high bandwidth memory (HBM) for storage.

3. The method as described in claim 1, characterized in that, The step of performing adaptive access frequency analysis on the target data block based on its current access information, using time windows at different micro and macro levels, to calculate the real-time access popularity value of the target data block includes: Based on the access information, the real-time access frequency of the target data block within a preset micro-time window is counted, and the standard deviation of the access interval between each access of the target data block within the preset micro-time window is calculated. The access information includes access time and access count information. The historical heat value of the target data block within a preset macro time window is obtained, and the adaptive cooling coefficient of the high bandwidth memory HBM is calculated based on the real-time operating status of the high bandwidth memory HBM. Based on the adaptive cooling coefficient, the standard deviation of the access interval, the real-time access frequency, and the historical heat value, the current access frequency of the target data block is analyzed to obtain the real-time heat value.

4. The method as described in claim 3, characterized in that, The process of analyzing the current access frequency of the target data block based on the adaptive cooling coefficient, the standard deviation of the access interval, the real-time access frequency, and the historical heat value to obtain the real-time heat value includes: Using a preset time decay factor, an exponentially weighted moving average is calculated on the real-time access frequency and the historical popularity value to obtain the current initial popularity of the target data block; The heat correction value is determined based on the standard deviation of the time interval and the adaptive cooling coefficient; The initial heat value is nonlinearly corrected based on the heat correction value to obtain the real-time heat value.

5. The method as described in claim 1, characterized in that, The step of calculating the spatial locality sag of the data block group to which the target data block belongs based on the address distribution information includes: The data storage space range of the data block group to which the target data block belongs is divided in the preset storage medium; Obtain the physical addresses of all active data blocks within the data storage space, and calculate the variance of all physical addresses to obtain the address variance value; The spatial locality jerk is obtained by calculating the dispersion of the address variance using a preset positive correlation increasing function, wherein the spatial locality jerk corresponding to random access is greater than the spatial locality jerk corresponding to sequential access.

6. The method according to any one of claims 1-5, characterized in that, Also includes: When performing physical data migration on the target data block, the page table status bit of the target data block in the memory management unit is marked as being in the migration state; When a read request is received for the target data block in the migration state, the read request is bypassed to the corresponding source physical address in the preset storage medium for data reading; When a write request is received for the target data block in the migration state, asynchronous write-through control is initiated to synchronously write the write data carried by the write request to the source physical address in the preset storage medium and the corresponding reserved free physical address in the high bandwidth memory HBM. After writing to both places is completed, a write success response is returned to the host. Once the physical data migration is complete, the page table pointer in the memory management unit is updated via atomic operations to point the page table pointer from the source physical address to the physical address in the high-bandwidth memory (HBM), and the page table status bit is modified to a valid state.

7. An HBM data migration control system based on access frequency analysis, characterized in that, Includes a storage controller, the storage controller comprising: The acquisition module is used to acquire memory access requests issued by the host, and extract access information for a target data block in a preset storage medium and address distribution information of the data block group to which the target data block belongs based on the memory access requests. The analysis module is used to perform adaptive access frequency analysis on the target data block based on the current access information of the target data block, through time windows at different levels of micro and macro, so as to calculate the real-time heat value of the target data block being accessed. The calculation module is used to calculate the spatial locality judder of the data block group to which the target data block belongs based on the address distribution information. The spatial locality judder is used to characterize the dispersion of the access addresses of all active data blocks within the data block group. The correction module is used to predict the comprehensive migration index of the target data block based on the real-time running status of the high-bandwidth memory HBM, the spatial locality judder, and the real-time heat value of the target data block. The monitoring module is used to monitor the status of the storage bus connecting the preset storage medium and the high bandwidth memory HBM, and obtain the real-time load status of the storage bus. The migration module is used to perform migration control on the target data block based on the real-time load status and the comprehensive migration index, so as to migrate the target data block from the preset storage medium to the high bandwidth memory (HBM) for storage when the comprehensive migration index meets the migration conditions.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 6.

9. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 6.

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