Memory access method, processor, system on chip, and computing device

Abstract

This application discloses a memory access method, a processor, a system-on-a-chip, and a computing device. The method includes: in response to receiving a memory access request, simultaneously issuing an instruction to access the memory access request and acquiring a first memory coloring value corresponding to the memory access request, wherein the first memory coloring value is used to verify the memory access request; during the execution of the memory access request, verifying the memory access request based on the first memory coloring value to obtain a verification result, wherein the verification result indicates whether the memory access request was successfully verified; if the verification result indicates that the memory access request was successfully verified, accessing memory based on the memory access request. This application solves the technical problem of low security in memory access in related technologies.

Description

Technical Field

[0001] This application relates to the field of processors, and more specifically, to a memory access method, a processor, a system-on-a-chip, and a computing device. Background Technology

[0002] Currently, memory safety is an important topic in computer science, aiming to prevent vulnerabilities and failures caused by erroneous memory accesses. Traditional software-level memory error detection methods are often inefficient and difficult to fully cover in complex systems, resulting in low security for memory accesses.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This application provides a memory access method, processor, system-on-a-chip, and computing device to at least address the technical problem of low security in memory access in related technologies.

[0005] According to one aspect of the embodiments of this application, a memory access method is provided, applied to a processor, the method comprising: in response to receiving a memory access request, simultaneously issuing an instruction for the memory access request and obtaining a first memory coloring value corresponding to the memory access request, wherein the first memory coloring value is used to verify the memory access request; during the execution of the memory access request, verifying the memory access request based on the first memory coloring value and obtaining a verification result, wherein the verification result is used to characterize whether the memory access request has been successfully verified; and if the verification result characterizes that the memory access request has been successfully verified, accessing memory based on the memory access request.

[0006] According to one aspect of the embodiments of this application, a processor is provided, comprising: a launch queue for launching memory access requests; a data buffer connected to the launch queue for launching instructions for the memory access requests; a preset buffer connected to the launch queue and operating in parallel with the data buffer for acquiring a first memory coloring value corresponding to the memory access request, wherein the first memory coloring value is used to verify the memory access request; a verification device for verifying the memory access request based on the first memory coloring value during the execution of the memory access request, and obtaining a verification result, wherein the verification result is used to indicate whether the memory access request has been successfully verified; and an access device for accessing memory based on the memory access request if the verification result indicates that the memory access request has been successfully verified.

[0007] According to one aspect of the embodiments of this application, a system-on-a-chip is provided, including: a processor of any one of the above embodiments.

[0008] According to another aspect of the embodiments of this application, a computing device is also provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in various embodiments of this application when it runs.

[0009] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein the methods of various embodiments of this application are implemented when the executable program is executed by a processor.

[0010] According to another aspect of the embodiments of this application, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the methods in various embodiments of this application.

[0011] According to another aspect of the embodiments of this application, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the methods in various embodiments of this application.

[0012] According to another aspect of the embodiments of this application, a computer program is also provided, which, when executed by a processor, implements the methods of the various embodiments of this application.

[0013] In this embodiment, in response to receiving a memory access request, while issuing the instruction for the memory access request, a first memory coloring value corresponding to the memory access request is obtained. This first memory coloring value is used to verify the memory access request. During the execution of the memory access request, the memory access request is verified based on the first memory coloring value to obtain a verification result. This verification result indicates whether the memory access request has been successfully verified. If the verification result indicates that the memory access request has been successfully verified, memory is accessed based on the memory access request, thereby improving the security of memory access. The processor only performs the actual memory access when the first memory coloring value matches the memory coloring information in the memory access request, i.e., when the verification is successful. This verification mechanism effectively prevents illegal or erroneous memory access and improves the system's memory security level. Since the memory coloring value is allocated at the virtual address level, compared to memory tagging schemes based on physical addresses, this method reduces memory overhead. Furthermore, by directly integrating the verification step into the execution flow of the memory access instruction, additional memory read operations are avoided, thus maintaining the processor's memory access performance unaffected, thereby solving the technical problem of low memory access security in related technologies.

[0014] It is worth noting that the general description above and the detailed description that follow are for illustrative purposes only and do not constitute a limitation on this application. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing a memory access method according to an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of a RISC-V architecture on-chip system according to an embodiment of this application;

[0018] Figure 3 This is a flowchart of a memory access method according to Embodiment 1 of this application;

[0019] Figure 4 This is a flowchart of a load / store instruction according to an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the structure of an instruction execution unit within a processor according to an embodiment of this application;

[0021] Figure 6 This is a schematic diagram of a data path for setting a tag and setting an invalid tag according to an embodiment of this application;

[0022] Figure 7 This is a schematic diagram illustrating multi-core memory tag consistency maintenance according to an embodiment of this application;

[0023] Figure 8 The following figure is a schematic diagram of a data path for loading / storing instruction memory tag query and inspection according to an embodiment of this application;

[0024] Figure 9 This is a schematic diagram of a processor according to an embodiment of this application;

[0025] Figure 10 This is a schematic diagram of a memory access device according to an embodiment of this application;

[0026] Figure 11 This is a structural block diagram of a computing device according to an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows:

[0030] Memory safety refers to ensuring that programs correctly access and manage memory resources during runtime, avoiding errors such as buffer overflows, accessing illegal addresses, and using freed memory. Memory safety is crucial for preventing data leaks, program crashes, and improving overall system stability.

[0031] Memory Tag: A memory tag is a technical feature that allows hardware to verify the validity of tags during memory access operations by attaching specific identifiers (tags) to memory data blocks, thereby helping to ensure memory security. In open instruction set architectures, memory tags are typically allocated based on virtual addresses, with each 16 bytes of data corresponding to a 4-bit or 7-bit tag value, but this is not a limitation and can be adjusted according to actual needs.

[0032] Tag Check: Tag check refers to the process by which the hardware compares the expected memory tag value with the actual memory data tag value when executing Load / Store instructions. If they match, the memory access is considered legitimate; otherwise, an exception may be triggered, indicating a potential memory error.

[0033] Memory access: Memory access refers to the operation of the processor reading or writing data in memory. In computer architecture, memory access is the foundation for executing programs and maintaining data, and its performance directly affects the system's operating efficiency.

[0034] Currently, Memory Tag Extension (ARM MTE) allocates memory tags based on physical memory, which results in approximately one-sixth (actually 1 / 16th) of the memory overhead, considering that each 16-byte data block has a 4-bit tag. In contrast, the MTE of the open-source Reduced Instruction Set Computing Fifth Generation (RISC-V) architecture allocates memory tags based on virtual memory. This method significantly reduces memory overhead and provides a more cost-effective and efficient memory safety management approach compared to ARM MTE.

[0035] According to an embodiment of this application, a memory access method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0036] The method embodiment provided in Embodiment 1 of this application can be executed in a RISC-V system, RISC-V chip or similar device, without limitation. It should be noted that, in addition to RISC-V, other architectures can also be used to implement this application. For example, similar functions can be implemented on architectures such as Advanced Reduced Instruction Set Machine (ARM) and x86 architecture. Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing a memory access method according to an embodiment of this application. Figure 1As shown, the RISC-V system can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including the basic instruction set 101-1 and extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2 and middleware services 105-3) and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system also includes a toolchain 107 that runs from the underlying hardware to the application layer. This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.

[0037] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set. The basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.

[0038] Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0039] The operating system layer 104 sits above the hardware, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.

[0040] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

[0041] The application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.

[0042] Toolchain 107 is a key component connecting the underlying hardware to the upper-level software. The various tools in toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0043] It should be noted that the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and improved independently. In one alternative embodiment, Figure 2 The above demonstrates the use of Figure 1 The diagram shown illustrates a System-on-Chip (SOC) based on the RISC-V architecture. Figure 2 This is a schematic diagram of a RISC-V architecture on-chip according to an embodiment of this application. Figure 2 As shown, the SOC contains at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices via bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0044] Under the aforementioned operating environment, this application provides the following: Figure 3 The memory access method shown. Figure 3 This is a flowchart of a memory access method according to Embodiment 1 of this application.

[0045] Step S302: In response to receiving a memory access request, while issuing an instruction for the memory access request, the first memory coloring value corresponding to the memory access request is obtained.

[0046] The first memory coloring value is used to verify memory access requests.

[0047] The aforementioned memory access request refers to the request issued by the processor to the memory system when executing load or store instructions, requesting to read or write data to a specific memory location.

[0048] The first memory coloring value mentioned above, within the Memory Tag attribute, refers to the memory tag value associated with the requested memory location. This tag value is used during memory access request processing to verify the legitimacy of the access and the integrity of the data.

[0049] The aforementioned verification refers to confirming whether the request meets the expected access permissions and data security requirements by comparing the address information in the memory access request with the memory tag value before the memory access is executed.

[0050] The instruction issuance described above occurs within the processor's issue pipeline stage. The issue pipeline is primarily responsible for instruction decoding and preparation, including obtaining the operands required for the instruction and allocating execution resources. During this stage, the processor simultaneously decodes memory access requests and obtains the memory tag value associated with the request, preparing for subsequent access verification.

[0051] When the processor receives a memory access request, it immediately decodes the request during its Issue Pipeline phase. Simultaneously, the processor also acquires the first memory coloring value associated with the request, known as the memory tag value. This value will be used for subsequent access verification. Acquiring the memory tag value during the decoding phase ensures timely tag verification before memory access, preventing illegal or unauthorized access and thus enhancing system memory security.

[0052] When the processor executes Load / Store instructions, it not only needs to decode the instructions and obtain the required address information and operands, but also needs to simultaneously obtain the first memory coloring value associated with the accessed address during the Issue Pipeline stage. This step ensures that the memory tag value can be effectively verified before memory access is executed, thereby enhancing memory security without affecting hardware performance and avoiding potential software errors and system vulnerabilities. Without reducing processor performance, the security of memory operations is significantly improved through hardware assistance. By obtaining the first memory coloring value simultaneously during the memory access instruction decoding stage, the processor can quickly perform memory access verification, effectively preventing unauthorized access and data corruption, shortening system development cycles and deployment time, and providing a solid security guarantee for large-scale software and hardware deployments.

[0053] For example, the processor is preparing to execute a Store instruction targeting a 16-byte physical memory block. During the Issue Pipeline phase, the processor not only decodes the Store instruction but also retrieves a first memory tag value associated with that address according to preset rules. If the memory tag value matches the expected tag value for the memory address in the current access request, the processor will allow the data write operation to continue; if the tag values ​​do not match, the access will be blocked, and exception handling may be triggered to further verify the access's legitimacy.

[0054] The above example demonstrates how to enhance memory security while maintaining performance within the processor's memory access unit. By acquiring and verifying the first memory coloring value during the decoding phase, the processor can prevent potential unauthorized accesses before executing memory access instructions, thereby ensuring data integrity and system reliability.

[0055] Step S304: During the execution of the memory access request, the memory access request is verified based on the first memory coloring value to obtain the verification result;

[0056] The verification result is used to indicate whether the memory access request was successfully verified.

[0057] The aforementioned execution of memory access requests falls within the processor's execution pipeline stage, which is responsible for the actual execution of instructions. In this stage, the processor performs the corresponding computation, data operation, or memory access tasks based on the decoded instruction requirements.

[0058] The above verification result, obtained during memory access request processing, compares the memory tag value with the expected value to determine whether the request is legitimate and the data is complete. Verification results typically include two states: "verification successful" and "verification failed."

[0059] The processor enters the processor pipeline stage and begins processing memory access requests. In this stage, the processor performs memory access operations and memory tag verification, comparing the first memory coloring value with the expected value of the memory tag contained in the requested access address. The result of this verification process is used to determine whether the memory access request is legally executed.

[0060] During the execution of a memory access request, the processor compares the first memory coloring value with the expected tag value of the access request to determine whether the request can proceed safely. If the memory tag values ​​match, the access is considered legitimate, the verification result is "successful," and the processor will continue to execute the memory access operation. Conversely, if the tag values ​​do not match, the verification result is "failure," the processor will block the access, potentially triggering an exception handling process to maintain system memory safety and data integrity.

[0061] When the processor is in the Execution Pipeline phase, it verifies memory access requests based on the first memory coloring value. This process is done by checking whether the memory tag value matches the expected value in the access request. The verification result directly determines whether the memory operation can continue. If the verification result indicates that the access is legal, the processor continues to execute the data read or write. Conversely, if the access is marked as illegal, the processor will take measures to prevent the access, such as correcting the error through exception handling mechanisms.

[0062] The above steps enable memory security verification during the execution phase of memory resource access, effectively preventing unauthorized access and data corruption without requiring additional hardware resources or steps. By embedding tag verification within the execution phase of memory access operations, the processor can ensure the legitimacy and security of data operations while maintaining system efficiency and performance. This instant verification mechanism significantly shortens the overall system development cycle, accelerates software and hardware deployment, and improves the accuracy and security of memory operations.

[0063] For example, the processor is executing a Load instruction aimed at reading 16 bytes of data at a virtual address. Upon entering the Execution Pipeline phase, the processor begins reading the data while simultaneously performing memory tag verification, checking if the first memory coloring value matches the tag information implicit in the virtual address. If the verification result is "successful," meaning the tag value matches, the processor continues reading the data and loading it into a register. Conversely, if the verification result is "failed," the processor immediately stops memory access and may trigger exception or error handling to prevent potential memory safety issues, such as illegal data reads. This example demonstrates how to leverage Memory Tag features to enhance memory safety without sacrificing processor performance, ensuring that only verified memory access operations can be executed, thereby improving the overall stability and security of the system.

[0064] Step S306: If the verification result indicates that the memory access request has been successfully verified, the memory is accessed based on the memory access request.

[0065] The aforementioned memory access refers to the processor reading or writing data into memory based on the address information in the memory access request. This operation is one of the core functions of the processor in executing programs, involving the interaction between physical memory and cache.

[0066] The memory access based on the memory access request described above occurs within the processor. Once the memory access request is verified and the verification result indicates that the access is legitimate, the processor will execute the specific memory read or write operation according to the address information and operation type (Load or Store) in the request.

[0067] During the execution phase of a memory access request (i.e., the execution pipeline phase), the processor determines whether to allow memory access based on the memory tag verification result. If the verification result shows that the memory access request is valid (verification successful), the processor will perform data read or write operations based on the actual address information of the request. Conversely, if the verification fails, the processor will not perform memory access and may trigger an exception handling process to avoid potential system errors or security threats.

[0068] After verifying the legitimacy and security of a memory access request (verification successful), the processor translates the access operation into an access to physical memory based on the specific details of the memory access request (e.g., virtual address, data size, etc.). This involves the process of translating virtual addresses into physical addresses and coordination with the cache to ensure efficient and consistent data access.

[0069] During the processor's Execution Pipeline phase, once a memory access request passes the preceding verification and the verification result confirms the request's legitimacy (i.e., the access request matches the memory tag stored at the corresponding memory location), the processor will execute the actual memory access operation, reading or writing data to the specified memory location. This process ensures that only verified access operations can affect memory contents, thereby enhancing the system's memory security and data integrity.

[0070] When the processor finds that the memory access request has been successfully verified during the execution pipeline (meaning the memory tag matches the expected tag in the instruction), the processor will continue with the memory access operation. This means the processor will calculate the physical address based on the virtual address of the requested instruction and then access the data in memory. If the request is of type Load, the processor will read the data; if it is of type Store, the processor will write the data. This process maintains high processor performance and efficient data access while ensuring memory safety.

[0071] By strictly relying on the verification results of memory tags during the memory access execution phase to determine whether to perform memory access, this solution effectively improves the security and controllability of the system's memory operations, avoiding data corruption or security vulnerabilities that may result from unauthorized access. Furthermore, since the verification process is parallel to the memory access operation, it ensures stable processor performance without increasing the additional hardware burden, shortens the system development cycle, and facilitates large-scale deployment of software and hardware.

[0072] For example, in the memory access function of a processor (Central Processing Unit, or CPU) design and delivery, suppose the processor is processing a Store instruction, intending to write data to a memory location corresponding to a tagged virtual address. After the memory tag is verified and the access request is confirmed to be legitimate (verification result successful), the processor enters the Execution Pipeline stage and begins to execute the data write operation. It uses the virtual address to physical address mapping mechanism to find the correct memory location and then writes the data. This process ensures that only instructions that have passed memory tag verification can perform actual operations on memory, thereby avoiding potential security risks, such as illegal data writing. This example illustrates that this application improves the security of memory operations through hardware-assisted means while maintaining high performance, which has positive significance for maintaining system stability and accelerating software and hardware deployment.

[0073] When the processor receives a memory access request, it decodes the request and simultaneously obtains a first memory coloring value associated with it. This memory coloring value is calculated based on the virtual address of the request and is used for later access verification. Subsequently, during the execution pipeline phase of the memory access process, the processor uses the first memory coloring value to verify the memory access request. The verification process involves comparing the memory coloring value with the expected tag value carried in the access request to determine whether the access is legitimate. Finally, if the verification result shows that the request is legitimate (verification successful), the processor will perform the actual data read or write operation on the specified memory location based on the memory access request.

[0074] For example, the processor receives a Load instruction requesting to read data located in the virtual address space. Upon receiving this memory access request, the processor immediately enters the Issue Pipeline stage, begins decoding the Load instruction, and simultaneously obtains the first memory coloring value corresponding to the virtual address. This is achieved through a calculation formula, and the calculated memory coloring value will be used for subsequent verification. Next, the processor enters the Execution Pipeline stage, where the memory access operation begins. During the execution of the Load instruction, the processor uses the previously obtained first memory coloring value to verify the legality of the access. The verification process involves comparing the first memory coloring value with the expected memory coloring value implied by the virtual address in the Load instruction. If the two values ​​match (i.e., verification is successful), the processor continues and completes the Load instruction, that is, reads data from memory into the processor's internal registers. Conversely, if verification fails, meaning that the memory access request does not match the expected memory label, the processor will interrupt the operation and may trigger exception handling to prevent potential memory safety issues, such as illegal data reads.

[0075] Finally, if the verification result confirms that the access is legitimate, the processor will perform the actual memory access, that is, map the physical address to the corresponding memory unit according to the virtual address information of the Load instruction, and read the data for subsequent processing. The entire process, from receiving the memory access request to finally accessing the data, tightly integrates the acquisition and verification of memory coloring values ​​to ensure that all memory operations are within the correct authorized scope, thereby improving the system's memory security and data integrity.

[0076] By seamlessly integrating memory tag verification across multiple stages (decoding, execution) within the processor, automated memory safety monitoring is achieved without negatively impacting processor performance. This ensures that only legitimate memory access requests are executed, enhancing overall system stability and security, and is crucial for accelerating software and hardware development and deployment. It efficiently detects and prevents illegal memory accesses caused by software errors without requiring frequent manual checks at the software level, simplifying developer workload while improving system efficiency and reliability. For example, in multi-threaded or multi-core environments, memory shading helps ensure the correctness of shared data between different threads or cores, preventing data conflicts or corruption caused by concurrent access, which is particularly critical in high-concurrency applications.

[0077] Through the above steps, in response to a received memory access request, while issuing the instruction for the memory access request, a first memory coloring value corresponding to the memory access request is obtained. This first memory coloring value is used to verify the memory access request. During the execution of the memory access request, the memory access request is verified based on the first memory coloring value, and a verification result is obtained. This verification result indicates whether the memory access request was successfully verified. If the verification result indicates that the memory access request was successfully verified, memory is accessed based on the memory access request, thus improving the security of memory access. Only when the first memory coloring value matches the memory coloring information in the memory access request, i.e., verification is successful, will the processor execute the actual memory access. This verification mechanism effectively prevents illegal or erroneous memory access, improving the system's memory security level. Since the memory coloring value is allocated at the virtual address level, compared to memory tagging schemes based on physical addresses, this method reduces memory overhead. Furthermore, by directly integrating the verification step into the execution flow of the memory access instruction, additional memory read operations are avoided, thus maintaining the processor's memory access performance unaffected, thereby solving the technical problem of low memory access security in related technologies.

[0078] In the above embodiments of this application, obtaining the first memory coloring value corresponding to the memory access request includes: determining the first virtual address based on the memory access request; and if the memory coloring value corresponding to the first virtual address exists in the preset buffer, reading the memory coloring value corresponding to the first virtual address from the preset buffer to obtain the first memory coloring value.

[0079] The first virtual address mentioned above refers to the virtual address involved in the memory access request. More specifically, it is the virtual address used to access the Memory Tag, that is, the virtual address corresponding to the Memory Tag of the Load / Store instruction.

[0080] The aforementioned preset buffer (Memory Tag Translation Lookaside Buffer, or MTLB for short) is used to store and quickly look up the Memory Tag Value corresponding to the virtual address, i.e., the memory coloring value.

[0081] The address calculation mentioned above is handled by the AGU (Address Generation Unit) module, which generates the relevant physical address based on the memory access request, and also includes calculating the virtual address of the Memory Tag.

[0082] When processing a memory access request, the processor first uses the AGU to calculate the first virtual address corresponding to the request, which is the virtual address of the Memory Tag. Next, the processor accesses the MTLB, a cache that stores the corresponding Memory Tag Value based on the virtual address. If the MTLB contains the Memory Tag Value corresponding to the first virtual address, the processor directly reads this value from the MTLB, which is the first memory coloring value, for subsequent memory access verification.

[0083] When the processor receives a Load or Store instruction, it immediately calculates the virtual address of the corresponding Memory Tag, i.e., the first virtual address. Then, the processor queries the MTLB (Memory Layer Load Balancer) to quickly locate and retrieve the Memory Tag Value associated with the first virtual address. If the query is successful, meaning the MTLB contains the Memory Tag Value corresponding to the first virtual address, the processor uses this value (the first memory coloring value) to verify the memory access request. This step improves verification efficiency, avoiding slow memory read operations on every access, thus maintaining system performance.

[0084] The first virtual address is calculated using a formula and represents the virtual address of the memory tag corresponding to the Load / Store instruction. If a memory coloring value matching the first virtual address exists in the Medium Memory Loading Buffer (MTLB), the processor will directly read this value from the MTLB without accessing main memory. This significantly reduces access latency and improves access efficiency. The existence of the MTLB allows the processor to quickly obtain memory coloring values ​​during execution, thereby enabling effective memory tag verification for Load / Store instructions without performance degradation.

[0085] By utilizing the MTLB cache to quickly retrieve the Memory Tag Value associated with the request while executing Load / Store instructions, the dual goals of memory access security checks and performance preservation are achieved. This allows the processor to not only quickly verify the legitimacy of memory accesses, preventing unauthorized access and data corruption, but also ensure efficient data operations without increasing the burden on additional hardware resources. Furthermore, since the verification process is executed automatically at the hardware level, software intervention is reduced, simplifying software development complexity, shortening the overall system development cycle, and facilitating rapid deployment and upgrades of hardware and software solutions.

[0086] In the memory access functionality of CPU design and delivery, suppose the processor is executing a Load instruction to read data from a memory location pointed to by a virtual address. In the processing flow of this instruction, the AGU first calculates the virtual address of the Memory Tag, i.e., the first virtual address, based on the virtual address of the Load instruction. Then, the processor queries the MTLB to find the Memory Tag Value corresponding to the first virtual address, i.e., the first memory coloring value. If this value exists in the MTLB, the processor will immediately read the first memory coloring value from the MTLB without accessing main memory, which significantly reduces access latency and improves access speed. Next, the processor uses the first memory coloring value to verify the Load instruction, ensuring that the access is legitimate. Once verification is successful, the processor will perform the actual memory read operation based on the virtual address, thus ensuring memory safety while maintaining high processor performance and efficient data access.

[0087] By automatically performing Memory Tag verification at the hardware level, the processor can enhance the security of memory operations and the integrity of data without sacrificing performance. This has a significant effect on accelerating the large-scale deployment of software and hardware and improving the overall stability of the system.

[0088] In the above embodiments of this application, the method further includes: canceling the execution of the memory access request and converting the first virtual address to a target physical address when there is no memory coloring value corresponding to the first virtual address in the preset buffer; reading the memory coloring value corresponding to the first virtual address from memory based on the target physical address; and storing the memory coloring value corresponding to the first virtual address in the preset buffer.

[0089] The aforementioned cancellation of a memory access request means that during the processor's execution phase, if it finds that the required conditions are not met (for example, the Memory Tag value is not found in the preset buffer), the processor will temporarily stop executing the memory access request until the missing information is obtained and ready.

[0090] The target physical address mentioned above refers to the physical address obtained through Virtual-to-Physical Address Mapping (VA2PA), which can be directly used to access actual memory. In this context, the target physical address is obtained by translating the first virtual address through the Memory Management Unit (MMU).

[0091] The above-mentioned method of reading the memory tag value corresponding to the first virtual address from memory based on the target physical address is necessary when the processor fails to find the memory tag value associated with the first virtual address in the preset buffer (MTLB). In this case, the first virtual address needs to be converted into a physical address through the MMU, and then the corresponding Memory TagValue is read from the main memory based on this physical address.

[0092] If the processor finds that the memory tag value corresponding to the first virtual address does not exist in the Mean Time Limit (MTLB), it cancels the current memory access request to avoid invalid operations and potential errors. Then, the processor translates the first virtual address into the target physical address; this process is implemented by the MTag Translation Engine within the MMU. After obtaining the target physical address, the processor reads the corresponding Memory Tag Value from main memory, i.e., the memory tag value corresponding to the first virtual address. Finally, the processor updates and stores the read Memory Tag Value in the MTLB for quick verification in subsequent access requests.

[0093] When the processor executes a memory access request, if it cannot find a first memory tag value corresponding to the requested virtual address in the MTLB, it can take a series of actions to ensure the request is processed correctly. First, the processor suspends the execution of the current request to avoid invalid operations. Next, the processor uses the MMU to perform VA2PA mapping, translating the virtual address into a physical address, and then reads the memory tag value from main memory based on this physical address. Once the memory tag value is obtained, the processor stores it back in the MTLB so that subsequent memory access requests can directly retrieve this value from the cache without accessing main memory again, thereby improving processing efficiency and response speed.

[0094] When the MTLB lookup result is Miss (i.e., the memory coloring value corresponding to the first virtual address does not exist in the default cache), the processor will translate the first virtual address into its physical address (target physical address) through the MTag Translation Engine within the MMU. Next, the processor reads the Memory Tag Value from main memory based on this physical address. Once the Memory Tag Value is retrieved, it will be updated in the MTLB to ensure the high speed and efficiency of subsequent accesses. This process ensures that even in the event of a cache miss, the processor can still perform necessary address translation and data read operations through the MMU, thereby continuing to execute memory access requests and maintaining system stability and performance.

[0095] This application, through the efficient cooperation of the MMU and MTLB, can automatically and quickly respond to missing Memory Tag Values ​​when processing memory access requests, avoiding invalid execution or system latency caused by cache misses. By taking immediate action after an MTLB miss—translating the virtual address into a physical address and reading the Memory Tag Value from main memory—the processor ensures the integrity and security of memory access operations. Simultaneously, by caching the Memory Tag Value in the MTLB, the number of physical address reads for subsequent memory accesses is reduced, significantly improving processing speed and system performance. This mechanism not only strengthens memory security but also improves processor resource utilization efficiency, significantly promoting faster hardware and software deployment and shorter system development cycles.

[0096] For example, in a multi-core processor design and delivery scenario, processor A is executing a Store instruction, attempting to write data to a memory location pointed to by a virtual address. However, during execution, processor A discovers that the MTLB does not contain a Memory Tag Value corresponding to the virtual address. Therefore, processor A temporarily suspends the execution of the Store instruction and instead uses the MMU to translate the virtual address into the target physical address. This translation process is performed by the MTag Translation Engine within the MMU, which can perform VA2PA mapping based on pre-defined rules. After obtaining the target physical address, processor A reads the corresponding Memory Tag Value from main memory. Once the Memory Tag Value is obtained, the processor not only verifies the memory access operation based on this information but also updates the Memory Tag Value to the MTLB so that subsequent memory accesses can directly retrieve the Memory Tag Value from the cache without accessing main memory again. In this way, processor A not only ensures the safety of memory operations but also improves the efficiency of data access. In multi-threaded or multi-core environments, it helps reduce latency caused by cache misses, maintains high-performance system operation, and is of significant value for large-scale hardware and software deployment and system stability improvement.

[0097] This application, through the coordinated work of the MMU and MTLB, enables the rapid acquisition and verification of Memory Tag Values ​​even in the event of a cache miss when the processor executes a memory access request, thereby performing memory operations efficiently and securely. This mechanism not only enhances the security of memory access but also significantly improves processor performance and response speed by reducing the number of physical memory accesses, thus playing a practical role in accelerating software and hardware deployment and shortening product development cycles.

[0098] The above embodiments of this application store the memory coloring value corresponding to the first virtual address into a preset buffer, including: performing a hash operation on the target physical address to obtain a hash physical address; and updating the memory coloring value corresponding to the first virtual address into the preset buffer based on the hash physical address.

[0099] The hash operation described above is an algorithm that transforms an input of arbitrary length (such as a physical address) into a fixed-length output. This transformation typically has a one-to-one mapping relationship, meaning that the same input always produces the same output, but different inputs may produce the same output (hash collision).

[0100] The hash physical address (PA) mentioned above is a compressed representation of the physical address obtained through hash operations, used for fast location and storage in a pre-defined buffer (such as MTLB). It is designed to be of fixed length to facilitate efficient lookups in the cache.

[0101] After the processor reads the Memory Tag value corresponding to the first virtual address from memory, in order to quickly update and store it in a preset buffer (such as MTLB), the processor performs a hash operation on the target physical address to generate a compressed hash physical address. This compressed address can be used to locate the storage location in the preset buffer, thereby updating the memory coloring value corresponding to the first virtual address for quick verification of subsequent access requests.

[0102] After executing a memory access request and reading a Memory Tag Value from memory, the processor performs a hash operation to transform the target physical address, generating a compressed hash physical address (hash PA). This hash PA is used to quickly locate and update the storage location in the Medium Memory Load Balancer (MTLB), updating the MTLB with the memory coloring value corresponding to the first read virtual address, providing a basis for fast verification of subsequent memory access requests. This process ensures the security and efficiency of data access; even in the event of a cache miss, the hash operation can quickly locate and update the cache, reducing latency in physical memory access.

[0103] When the MMU refills the MTLB, it performs a hash operation based on the target physical address to generate a compressed hash physical address (i.e., hash PA). This hash PA is used to locate the memory position in the MTLB to update the Memory Tag Value corresponding to the first virtual address in the MTLB. This process aims to improve the lookup efficiency of the MTLB by converting the physical address into a shorter hash PA, making the operations of updating and looking up the Memory Tag Value in the MTLB faster. In this way, even after an MTLB miss, the processor can quickly obtain the Memory Tag Value through the MMU and update it in the MTLB, providing the ability to quickly verify subsequent memory access requests, ensuring data access security and system performance stability.

[0104] This application implements efficient management and verification of memory tags within the processor. By converting physical addresses to hashed physical addresses through hash operations, it accelerates the updating and lookup process of memory tag values ​​in the Medium Memory Load Balancer (MTLB). This mechanism is particularly beneficial in multi-core processors or multi-threaded environments, ensuring the correctness and security of data access while avoiding the performance impact of cache misses. By reducing the number of physical memory accesses and latency, it maintains the high efficiency of system operation. It not only enhances memory security but also improves processor resource utilization through the combination of cache management and hashing techniques, shortening the system development cycle and facilitating large-scale hardware and software deployment.

[0105] For example, in the memory access function of CPU design and delivery, suppose the processor is processing a Load instruction that requests to read data from a memory location pointed to by a virtual address. During execution, the processor finds that the Memory Tag Value corresponding to the requested virtual address does not exist in the MTLB, so it uses the MMU to translate the virtual address into a target physical address. After reading the Memory Tag Value from main memory, the processor converts the target physical address into a hash physical address using a hash operation. This hash physical address is then used to locate the storage location in the MTLB, and the read Memory Tag Value is updated in the MTLB. This process ensures that subsequent memory access requests can directly and quickly obtain the Memory Tag Value from the MTLB for verification without accessing main memory again, thereby reducing the number of physical memory accesses and improving system performance while maintaining memory operation security.

[0106] This application achieves efficient management of Memory Tag Values ​​in the Medium Memory Load Balancer (MTLB) by generating and updating hashed physical addresses when the processor executes memory access requests. This improves data access speed and efficiency while ensuring memory operation security. By reducing physical memory access latency, this solution helps maintain system performance and has a practical effect on shortening software and hardware development cycles and accelerating product deployment. Especially in high-performance computing scenarios where the processor needs to frequently access memory, this mechanism can significantly improve system stability and response speed, and is of great value in improving memory security and resource utilization efficiency.

[0107] By integrating this mechanism into the processor, the processor can quickly locate and update the Memory Tag Value even when a cache miss occurs, ensuring the legality and efficiency of memory access. This is especially important for high-concurrency, multi-threaded computing environments, and helps maintain the overall stability and data integrity of the system.

[0108] According to the above embodiments of this application, the method further includes: updating the memory coloring value corresponding to the first virtual address to the second-level cache.

[0109] The L2 cache mentioned above is a high-speed cache that is much faster than main memory, but has a smaller capacity. Here, it refers to storing the memory coloring value corresponding to the first virtual address in the L2 cache so that subsequent memory access operations can more quickly verify the memory coloring value, improving access efficiency.

[0110] After the processor retrieves the memory coloring value corresponding to the first virtual address from main memory via the MMU, in addition to updating the Master Memory Load Balancer (MTLB), it also updates this information in the Level 2 Cache. This operation ensures that in subsequent memory accesses, the processor can quickly access the memory coloring value from a location closer to the execution unit, avoiding additional latency caused by a lower cache level.

[0111] After the processor processes a memory access request and reads the corresponding Memory Tag Value from memory, to avoid performance penalties caused by cache misses when accessing the same data again in the future, it updates the Memory Tag Value to both the MTLB and L2 Cache. The L2 Cache, as a high-speed cache layer, is located closer to the processor than main memory. This allows the processor to directly read the Memory Tag Value from the L2 Cache for verification when executing subsequent memory access instructions, without needing to access lower-level caches or main memory again, greatly improving verification speed and data access efficiency.

[0112] When the MMU reads back Memory Tag Values, it needs to update these values ​​not only to the MTLB but also to the L2 Cache, which is closer to the processor's execution unit. As a secondary cache, the L2 Cache has a faster access speed than main memory and other lower-level caches. Therefore, storing Memory Tag Values ​​in the L2 Cache reduces the latency caused by rereading data from main memory after an MTLB miss, thus ensuring memory safety while maintaining the processor's high-performance operation.

[0113] By updating the Memory Tag Value to the L2 Cache, this application reduces the latency of memory access operations and improves the overall efficiency of data access and verification. The high-speed performance of the L2 Cache allows the processor to obtain the necessary Memory Tag Value more quickly during subsequent memory access instruction execution, enabling memory safety verification. This strategy not only ensures the legality and security of data access but also maintains system performance stability by reducing the frequency of accessing slow physical memory. Especially in high-concurrency, multi-threaded environments, it can significantly improve data access speed and system responsiveness, which is beneficial for shortening the overall development cycle and accelerating software and hardware deployment.

[0114] For example, in a memory access scenario during processor design and delivery, suppose the processor is executing a Load instruction that needs to access the memory location pointed to by a specific virtual address. During the Load instruction processing, the processor finds that the MTLB does not contain a Memory Tag Value corresponding to that virtual address. Therefore, it uses the MMU to translate the virtual address to a physical address and reads the Memory Tag Value from main memory. Subsequently, the processor not only updates the Memory Tag Value to the MTLB but also stores this information in the L2 Cache. In this way, when subsequent access instructions attempt to access the same memory location pointed to by the same virtual address again, the processor can directly and quickly read the Memory Tag Value from the L2 Cache for verification, avoiding the additional latency caused by accessing main memory or lower-level caches again. This improvement significantly enhances the security and efficiency of memory access, and has clear benefits for improving system stability and accelerating hardware and software deployment.

[0115] This application achieves both high efficiency and security in data access verification by updating the Memory Tag Value to the L2 Cache when the processor executes a memory access request. Through this mechanism, the processor ensures memory safety while reducing unnecessary memory access latency, thereby improving overall system efficiency and responsiveness. For large-scale hardware and software deployments, this strategy can effectively shorten development cycles, accelerate product launches, and have a substantial impact on improving system performance and user experience. In multi-core processors or multi-threaded environments, the introduction of this mechanism can significantly reduce potential memory access latency, which is crucial for maintaining system stability and data integrity.

[0116] The above embodiments of this application verify memory access requests based on a first memory coloring value to obtain a verification result, including: obtaining a second memory coloring value carried in the memory access request; if the second memory coloring value and the first memory coloring value match successfully, determining that the verification result is that the memory access request verification is successful; if the second memory coloring value and the first memory coloring value do not match, determining that the verification result is that the memory access request verification fails.

[0117] The verification result mentioned above refers to the conclusion drawn after checking the legality of the memory access request based on the first memory coloring value, which determines whether the request can continue to be executed.

[0118] The second memory coloring value mentioned above refers to the memory coloring value carried in the memory access request and associated with the requested virtual address. During the execution of the memory access instruction, the processor compares this value with the first memory coloring value obtained from the MTLB or L2 cache.

[0119] The above definition of a successful match and a failed match is as follows: a successful match occurs when the second memory coloring value matches the first memory coloring value, indicating that the memory access request is legitimate and can continue execution. Conversely, a failed match occurs when the two memory coloring values ​​do not match, meaning that the request may be illegitimate and should be blocked or an exception should be reported.

[0120] Upon receiving a memory access request, the processor retrieves a first memory tag value, the target memory tag value, based on the request. Next, the processor reads the second memory tag value carried in the memory access request and compares the two values ​​on the execution pipeline of the execution unit. If the second memory tag value matches the first memory tag value, the processor determines that the memory access request has been successfully verified and allows the access to proceed. Conversely, if the match fails, the processor determines that the memory access request has failed, blocks the access, and may trigger an exception mechanism.

[0121] When the processor executes a memory access request (such as a Load / Store instruction), to ensure the legitimacy and security of data access, it retrieves a first memory tag value from the Mediatory Load Balancer (MTLB) or the L2 cache. Simultaneously, it reads a second memory tag value carried in the memory access request; this value is typically stored in the high-order bits of the requested virtual address. The processor compares these two memory tag values ​​on the execution pipeline to determine if the access is legitimate. If a match is found, the verification passes, and the processor continues with the memory access operation; if a match fails, the verification is deemed a failure, the processor blocks the access, and may report an exception depending on the specific instruction type, thereby protecting memory from unauthorized access.

[0122] During execution, the Load / Store instructions acquire and compare Memory Tag Values. These Memory Tag Values ​​correspond to the first memory coloring value, while the higher bits of the virtual address carry the second memory coloring value. If they match, the instruction can continue the access operation; otherwise, an exception mechanism is triggered. This application further clarifies this process by comparing values ​​on the Execution Pipeline, ensuring that the validity verification of memory access occurs before the access operation, thereby effectively preventing any unauthorized memory operations and enhancing system memory security.

[0123] This application ensures the legitimacy of data operations by verifying the Memory Tag Value before memory access, and reduces latency in memory access operations by performing fast comparisons on the Execution Pipeline, thus maintaining system performance. Simultaneously, by adding additional memory coloring value information to the memory access request, the processor can effectively perform memory safety checks without increasing the burden on additional hardware resources, improving both security and efficiency. Furthermore, this mechanism simplifies software-level memory access control, shortens the overall system development cycle, and facilitates large-scale hardware and software deployment.

[0124] For example, in the memory access function of a CPU design and delivery, suppose the processor is executing a Load instruction whose goal is to read data at virtual address X. During the lifecycle of the Load instruction, the high-order bits of virtual address X carry a second memory tag value. When the processor begins processing the Load instruction, it first retrieves the first memory tag value (i.e., memory tag value) corresponding to virtual address X from the MTLB or L2 cache. Next, the processor compares the second memory tag value with the first memory tag value on the Execution Pipeline. If they match, the processor determines that the memory access request has been successfully verified, allowing the Load instruction to read the data at address X; if the match fails, the processor determines that the memory access request has failed, prevents the Load instruction from executing, and may trigger an exception mechanism, such as generating a synchronization exception, to notify the software layer to handle the illegal access situation.

[0125] This application verifies the legitimacy of a memory access request by comparing a first memory coloring value with a second memory coloring value when the processor executes a memory access instruction, and takes measures to protect memory security when verification fails. By performing a fast comparison on the execution pipeline, the processor can prevent unauthorized memory operations without degrading performance, playing a crucial role in maintaining system stability and data integrity. Furthermore, since this mechanism operates at the hardware level, requiring minimal software intervention, it simplifies the complexity of memory access control, shortens the overall development cycle, and facilitates rapid deployment and upgrades of hardware and software solutions.

[0126] According to the above embodiments of this application, the method further includes: storing a first memory coloring value in a target queue corresponding to the memory access request based on the type of the memory access request; and reading the first memory coloring value from the target queue during the execution of the memory access request.

[0127] The write buffer mentioned above is a high-speed cache area in the processor used to temporarily store write operation data. When a write operation is performed, the data is first written to the write buffer, and then the data is written to the main memory or low-level cache in batches at appropriate times (such as when the buffer is full or when a specific event occurs) to reduce the frequency of direct access to the main memory and improve data writing efficiency and performance.

[0128] The aforementioned storage of memory access requests in the write buffer refers to the process whereby, after the processor has completed a write operation (i.e., the memory access request is a write request and has been completed), the write request and its operation data are temporarily stored in the write buffer so that they can be subsequently written to main memory or low-level cache in batches.

[0129] The aforementioned storage of the memory coloring value corresponding to the memory access request in the write buffer means that when the memory access request is a write request and has been completed, the processor will also temporarily store the memory coloring value (i.e., the first memory coloring value) related to the write request in the write buffer so that it can be updated to the main memory or low-level cache together during batch write operations, ensuring the consistency and integrity of the memory coloring value.

[0130] After the processor processes a write request, it temporarily stores the write request and its data in a write buffer before writing the write operation data to main memory or the low-level cache. Simultaneously, if an associated memory coloring value exists, the processor also temporarily stores this memory coloring value in the write buffer. This ensures that the data and memory coloring value can be updated together in main memory or the low-level cache at the appropriate time, thereby improving the efficiency and performance of write operations while maintaining memory safety.

[0131] After executing a write request, the processor temporarily stores the write request and its data in a write buffer to improve the efficiency and performance of the write operation. Furthermore, to verify the validity of memory access requests, the processor also temporarily stores the memory coloring value associated with the write request in the write buffer. This strategy ensures that the data and its corresponding memory coloring value are updated together to lower-level storage devices, such as main memory or low-level cache, thereby maintaining memory access security and data consistency. The use of a write buffer reduces frequent direct access to main memory, improving system write performance and response speed.

[0132] When a memory access request is a write request, the processor writes the write request and its corresponding data to the write buffer after completing the write operation. Simultaneously, the memory coloring value (first memory coloring value) associated with the write request is also stored in the write buffer, ready to be updated to the L2 cache or other lower-level storage devices in subsequent batch write operations. This process ensures the security and consistency of data access, while the use of the write buffer improves the efficiency of write operations and system performance, avoiding unnecessary latency and resource waste.

[0133] By storing write requests, their corresponding data, and memory coloring values ​​in a write buffer, this application effectively improves the efficiency and performance of write operations without sacrificing memory safety. The write buffer mechanism reduces the frequency of direct access to main memory, avoiding unnecessary latency. Especially in multi-core processor or multi-threaded environments, this mechanism significantly improves data write speed and system responsiveness, helping to shorten the overall development cycle and accelerate software and hardware deployment. Furthermore, storing memory coloring values ​​along with write requests in the write buffer ensures the security and consistency of data access, providing strong protection for maintaining system stability and data integrity.

[0134] For example, in a memory access scenario during CPU design and delivery, suppose the processor is processing a Store instruction, the goal of which is to write data to a memory location pointed to by a specific virtual address. After the Store instruction is executed, the processor temporarily stores the write request and its data in a write buffer so that when the write buffer is full or a specific event is triggered, these write operations can be batch-written to the L2 cache or main memory. Simultaneously, the processor also stores the memory coloring value (first memory coloring value) associated with the write request in the write buffer, ensuring that during batch writing, the data and its corresponding memory coloring value are updated together in the L2 cache or main memory, thereby improving the efficiency of write operations while maintaining memory safety. This strategy not only enhances the legitimacy verification of data access but also maintains system performance stability by reducing frequent accesses to physical memory, which is beneficial for accelerating hardware and software deployment and shortening product development cycles.

[0135] This application improves write operation efficiency through a write buffer mechanism when the processor executes write requests, while ensuring the legitimacy of memory access requests and data consistency, thus practically promoting processor performance and memory security. Especially in high-concurrency, multi-threaded environments, this strategy can significantly reduce memory access latency and improve overall system efficiency, which is of great significance for maintaining system stability and accelerating product time-to-market. Through this mechanism, the processor can strengthen the verification of memory access legitimacy without compromising performance, effectively preventing unauthorized memory write operations and providing a solid security guarantee for large-scale hardware and software deployment and system operation.

[0136] According to the above embodiments of this application, the method further includes: when the memory access request is a write request and the memory access request has been completed, storing the memory access request in a write buffer and storing the memory coloring value corresponding to the memory access request in the write buffer.

[0137] The write buffer mentioned above is a caching mechanism of the processor, mainly used to temporarily store completed write operation data (such as the result of the Store instruction) so that it can be written to main memory or L2 cache in batches later, thereby reducing the number of direct accesses to main memory and improving the efficiency of data writing.

[0138] The memory access instructions mentioned above are used to write data into memory, such as the Store instruction.

[0139] Once the aforementioned memory access request is completed, in the processor architecture, the entire process from the issuance of an instruction to its completion of execution is called its lifecycle. When an instruction is in the "retired" state, it means that all execution stages have been completed, including data computation, storage, and possible exception handling, and can be considered as truly completed.

[0140] The aforementioned storage of memory access requests in the write buffer means that after the processor executes the Store instruction (write request) and completes all execution stages, it will temporarily store the Store instruction and its result data in the write buffer, waiting for subsequent write operations.

[0141] The aforementioned storage of the memory coloring value corresponding to the memory access request to the write buffer means that after the processor executes the write request (i.e., the Store instruction), in addition to storing the instruction itself and the result data into the write buffer, it will also store the first memory coloring value (i.e., the Memory Tag Value) associated with the instruction into the write buffer, so that when finally writing data, the memory coloring information can be updated at the same time to maintain the consistency of data and tags.

[0142] When the processor finishes executing a Store instruction (write request) and considers it "retired," it temporarily stores the instruction's result data and its associated memory coloring value in a write buffer. Subsequently, at an appropriate time, the data in the write buffer and the memory coloring value are written together to main memory or L2 cache to complete persistent data storage and tag updates, thereby ensuring the legitimacy of data access and data consistency.

[0143] After executing a Store instruction (write request) and confirming its retired state, the processor stores the instruction's result data and the corresponding memory coloring value in the write buffer. This process occurs in the late stage of instruction execution; the processor only stores its data and memory coloring value into the write buffer when the Store instruction has completed all execution stages and is considered "retired." Subsequently, the data and memory coloring value in the write buffer are updated together during batch writes to main memory or L2 cache, ensuring data and tag consistency, improving write operation efficiency, and reducing the frequency of direct access to main memory.

[0144] When a Store instruction completes execution and is considered retired, the processor stores the instruction and its data in a write buffer, along with the associated memory coloring value (i.e., the first memory coloring value) in the same buffer. This mechanism ensures that during data write operations, the memory coloring value is updated to the L2 cache or main memory along with the data, maintaining the legitimacy and consistency of data access. Simultaneously, by utilizing the write buffer, the processor reduces the number of direct accesses to main memory, improving the efficiency of write operations and helping to shorten system development cycles and accelerate hardware and software deployment.

[0145] By storing completed Store instructions (write requests) and their corresponding memory coloring values ​​in a write buffer, this application effectively improves the efficiency of data write operations while ensuring the legality and consistency of data access. The write buffer mechanism reduces the number of direct accesses to main memory, avoiding unnecessary latency. Especially in multi-core processor or multi-threaded environments, this strategy significantly improves data write speed and system responsiveness, shortens the overall development cycle, and accelerates the deployment of hardware and software solutions. Furthermore, storing the memory coloring value along with the write request in the write buffer ensures the synchronous updating of data and its corresponding tag, enhances memory safety, and provides strong protection for maintaining system stability and data integrity.

[0146] For example, in the memory access function of CPU design and delivery, suppose the processor is processing a Store instruction, which requires writing specific data to the memory location corresponding to virtual address C. After the Store instruction is executed and considered retired, the processor temporarily stores the written data and its corresponding memory coloring value (first memory coloring value) in a write buffer. Subsequently, when the write buffer is full or a specific event is triggered, the data in the write buffer and the memory coloring value are written together to L2 cache or main memory, completing the persistent storage of data and the update of the tag. This process not only improves the efficiency of data writing and reduces the number of direct accesses to main memory, but also ensures the security and consistency of data access, which is beneficial to accelerating the processor performance and hardware / software deployment process, and has significant benefits for maintaining system stability and shortening product development cycles.

[0147] This application improves the efficiency of write operations by using a write buffer mechanism when the processor executes write requests (i.e., Store instructions), while ensuring the legitimacy and consistency of data access. This has a practical positive impact on processor performance and memory security. Especially in high-concurrency, multi-threaded environments, this strategy can significantly improve data write speed and reduce potential memory access latency, which is of great significance for maintaining system stability and accelerating product time-to-market. Through this mechanism, the processor can improve data write efficiency while ensuring memory security, effectively preventing unauthorized memory write operations and providing a robust security guarantee for large-scale hardware and software deployments and system operation.

[0148] According to the above embodiments of this application, the method further includes: in response to receiving a memory coloring value processing instruction, determining a second virtual address based on the memory coloring value processing instruction; if a first data item corresponding to the second virtual address exists in a preset buffer, setting the first data item to an invalid state, wherein the first data item is used to store the memory coloring value corresponding to the second virtual address; and storing a third memory coloring value carried in the memory coloring value processing instruction into memory and a secondary cache.

[0149] The aforementioned preset buffer is a hardware cache used to store and manage memory coloring values, such as MTLB, which is responsible for storing memory coloring values ​​associated with virtual addresses for quick checking in subsequent memory accesses.

[0150] The second virtual address mentioned above is a virtual address in a program, associated with a specific location in memory, used to identify the memory region where the memory coloring value to be processed is located.

[0151] In memory management, the first data item mentioned above refers to a data unit stored in the cache or memory. Here, the first data item refers to the cache entry in the MTLB associated with the second virtual address, used to store the corresponding memory coloring value.

[0152] In cache management, the aforementioned invalid state means that when a data item or entry is marked as invalid, it no longer contains currently valid or up-to-date data, thus preventing it from being referenced by subsequent memory operations. Here, invalidity refers to the MTLBEntry being set invalid, making it unusable for subsequent memory access checks.

[0153] The aforementioned third memory coloring value is a new memory coloring value carried in memory coloring value processing instructions (such as Settag / Setinvtag instructions). It will be written into memory and the second-level cache to update or set the memory coloring information of the memory region pointed to by the second virtual address.

[0154] When the processor receives a memory coloring instruction (such as Settag / Setinvtag), it determines the second virtual address based on the instruction's parameters. This second virtual address identifies the memory region the instruction intends to modify. Next, the processor searches the MTLB (Memory Management Load Balancer) for a first data entry corresponding to the second virtual address. If found, this data entry is immediately set to invalid, preventing it from being referenced by subsequent memory access instructions for tag checking. Finally, the processor writes the third memory coloring value carried in the memory coloring instruction to main memory and the L2 cache, completing the update or setting of the memory coloring value for the specified memory region.

[0155] When the processor receives a Settag or Setinvtag instruction, it parses the second virtual address from the information in the instruction, indicating the memory location where the memory coloring operation will be performed. If a first data entry (i.e., an MTLB Entry) corresponding to the second virtual address is found in the Medium Memory Load Balancer (MTLB), the processor immediately invalidates it, ensuring that subsequent memory access instructions do not reference the updated data entry for tag checking, thus avoiding potential inconsistencies and errors. Next, the processor writes the third memory coloring value carried in the Settag or Setinvtag instruction into main memory and the L2 cache, updating or setting the memory coloring information of the memory region pointed to by the second virtual address, maintaining the safety of memory access and data consistency.

[0156] When the processor executes the Settag or Setinvtag instruction, it determines the second virtual address based on the information in the instruction. If a first data entry (i.e., an MTLB Entry) corresponding to the second virtual address is found in the MTLB, the processor sets it to an invalid state, i.e., "invalidated". Next, the processor writes the third memory coloring value carried in the instruction to main memory and the L2 cache, completing the update or setting of the memory coloring value for the specified memory region. This process ensures the correctness and integrity of the memory tags, and maintains the security and efficiency of data access by updating the cache and main memory.

[0157] This application improves data access security by invalidating the first data item in the preset buffer MTLB during the execution of Settag or Setinvtag instructions, effectively preventing older memory coloring values ​​from being misused by subsequent memory access instructions. Simultaneously, by writing the third memory coloring value to both main memory and the L2 cache, it ensures the availability and consistency of the latest memory coloring value, reduces access latency caused by cache hierarchy differences, and improves system performance. This mechanism simplifies memory coloring value management, enhances memory security, and plays a crucial role in maintaining system stability and data integrity. It also improves processor execution efficiency and shortens product development cycles.

[0158] For example, in the memory access function of CPU design and delivery, suppose the processor is processing a Setinvtag instruction that requests a zeroing operation on the memory coloring value at a specific virtual address D. The processor first parses the instruction and determines that the second virtual address is D. Then, it checks the MTLB to see if a first data item corresponding to the second virtual address D exists. If it does, it immediately sets it to an invalidated state, preventing it from being used by subsequent Load / Store instructions for memory coloring value checks. Next, the processor writes the third memory coloring value (usually zero in this case) carried by the Setinvtag instruction into main memory and the L2 cache, completing the zeroing operation on the memory coloring value at virtual address D. This process ensures memory safety, prevents unauthorized memory access, and improves the execution efficiency of subsequent memory access instructions by updating the memory coloring value in the L2 cache, thus having a positive impact on maintaining system stability and accelerating hardware and software deployment.

[0159] This application ensures the security and efficiency of memory access by setting the corresponding data item in the preset buffer to an invalid state and writing the new memory coloring value to memory and the L2 cache when the processor executes memory coloring value processing instructions (Settag or Setinvtag instructions). This has practical application value for processor performance and memory management. Especially in complex data access control and high-concurrency memory operation scenarios, this strategy can significantly enhance memory security and reduce access latency caused by cache coherency issues, which is of great significance for maintaining system stability and accelerating software and hardware deployment. Through this mechanism, the processor can improve the flexibility and efficiency of data access control while ensuring memory security, effectively preventing unauthorized memory access and providing a solid security guarantee for the deployment and operation of large-scale software and hardware projects.

[0160] According to the above embodiments of this application, the method further includes: when a replacement operation is detected on the target cache line in the secondary cache, reading the target hash physical address in the target cache line; determining whether a second data item corresponding to the target hash physical address is stored in a preset buffer; and if the second data item is stored in the preset buffer, setting the second data item to an invalid state, wherein the second data item is used to store the memory coloring value corresponding to the target hash physical address.

[0161] The target cache line described above is the basic storage unit of the L2 cache (or higher-level cache). It contains a fixed-size data block and some metadata, such as valid memory coloring values. When a line in the cache needs to be replaced, that line is called the target cache line.

[0162] When a cache line (such as the target cache line) is replaced, the compressed form of its physical address (PA) generated by hashing is called the target hash physical address. It is crucial information used to find matching entries in the default memory buffer (MTLB), helping to maintain the consistency of memory coloring values ​​in the cache.

[0163] The second data item mentioned above refers to the entry in the MTLB that stores the memory coloring value corresponding to the physical address of the target hash, i.e., the second data item associated with the physical address of the target cache line. When the target cache line is replaced, it is necessary to determine whether there is a matching second data item in the preset buffer MTLB. If it exists, it should be set to an invalid state.

[0164] The invalid state in the aforementioned preset buffer is when the second data item associated with the target cache line in the MTLB is marked as invalid (i.e., invalidated). This means that the entry is no longer considered valid or up-to-date cache information and will not be used by subsequent memory access instructions for checking memory coloring values, in order to ensure the legality of memory access and the consistency of data.

[0165] In the processor's cache replacement mechanism, when a target cache line in the L2 cache needs to be replaced, the processor first reads the target hash physical address from the target cache line. Next, the processor checks if the Medium Memory Load Balancer (MTLB) stores information corresponding to that target hash physical address (i.e., a second data item). If this information is found in the MTLB, the processor marks the second data item as invalid, disallowing it from being referenced by subsequent memory access instructions for memory coloring value checks. This ensures the legality of memory accesses and data consistency, avoiding data inconsistency issues between caches.

[0166] When the processor performs a cache replacement operation, if a target cache line in the L2 cache needs to be replaced, it first reads the hash physical address (Hash PA) of the target cache line. Then, the processor checks the Medium Memory Load Balancer (MTLB) for a second data item corresponding to the target hash PA. If such an entry exists in the MTLB, the processor invalidates it to ensure that when the memory coloring value of the target cache line changes, the old memory coloring value will not be referenced by subsequent Load / Store instructions for validity verification, thus preventing potential data inconsistencies and memory access errors. This mechanism maintains the standard of memory access security and data consistency, playing a crucial role in improving system stability and performance.

[0167] When a target cache line (Memory Tag Cacheline) in the L2 cache is replaced, its target hash physical address (Hash PA) is first calculated. The processor then broadcasts this hash address to the MTLB (Memory Tag Buffer) to check if a matching second data item exists. If an entry corresponding to the target hash PA is found in the MTLB, the processor sets it to an invalidated state. This ensures that the updated memory coloring value in the L2 cache is consistent with the information in the MTLB, avoiding cache inconsistency and memory access errors, and maintaining the safety of memory operations and data consistency.

[0168] This application introduces a mechanism for checking the physical address of the target hash and invalidating entries in the preset buffer during cache replacement operations. This effectively prevents data inconsistencies between cache levels and unauthorized memory access, enhancing the security of memory operations. By promptly reflecting changes in the memory coloring value of the target cache line in the L2 cache to the preset buffer MTLB, it ensures that data access instructions can obtain the latest memory coloring value information during execution. This reduces access latency and performance loss caused by outdated cached data, positively impacting overall system performance and stability. This strategy simplifies the cache consistency maintenance process, strengthens memory security management, and helps shorten product development cycles, accelerating hardware and software deployment and upgrades.

[0169] For example, in a memory access scenario during CPU design and delivery, consider a processor performing a cache replacement operation to free up L2 cache space for new data blocks. When a target cache line needs to be replaced, the processor first reads the target hash physical address of that line. Assume the target hash physical address is E. Subsequently, the processor checks the MTLB for a second data entry (i.e., an MTLB Entry) corresponding to E. If an entry associated with E is found in the MTLB, the processor immediately sets it to an invalidated state, disallowing it from being used by subsequent memory access instructions for checking memory color values. This ensures that after the target cache line's memory color value in the L2 cache is updated, the old memory color value is not referenced by subsequent Load / Store instructions, thus preventing potential memory access errors, maintaining the safety of memory operations and data consistency, and practically promoting faster hardware and software deployment and system stability maintenance.

[0170] This application's solution ensures memory coloring consistency across cache levels by reading the target hash physical address from the target cache line and searching for a matching entry in the MTLB (Mean Time Limit Balance) during cache replacement operations. This provides practical benefits to processor performance and memory safety. Particularly in high-concurrency, multi-threaded environments, this strategy significantly reduces memory access latency caused by cache consistency issues, improves data access efficiency and system responsiveness, and is crucial for maintaining system stability and accelerating time-to-market. Through this mechanism, the processor can improve memory access efficiency while ensuring memory safety, effectively preventing memory access errors caused by outdated cached data, and providing robust security for large-scale hardware and software deployment and system operation.

[0171] Memory tagging is an effective hardware-assisted technology for solving memory safety issues. It can efficiently locate relevant errors online and offline, shorten the overall system development cycle, and thus accelerate the large-scale deployment of software and hardware.

[0172] The open-source instruction set architecture (Reduced Instruction Set Computing Fifth Generation, or RISC-V for short) uses memory coloring to allocate memory tags to data based on virtual addresses. The architecture specifies that every 16 bytes of data can correspond to a 4-bit or 7-bit memory tag.

[0173] This application primarily addresses the scenario where each 16-byte of data corresponds to a 4-bit memory tag. When executing load / store instructions, the hardware simultaneously needs to query the memory tag and perform a tag check. That is, each load / store instruction adds an extra memory tag loading operation, which may halve the performance of memory access.

[0174] This application proposes a hardware implementation scheme to ensure that the processor's memory access performance does not degrade after adding memory coloring features. It mainly involves the allocation and updating of memory tags, the consistency maintenance of memory tags in multi-core processors, and the querying and verification of memory tags.

[0175] During memory tag allocation and updating, the RISC-V architecture defines instructions for setting memory tags (settag instructions) and instructions for setting memory tags to an invalid state (setinvtag instructions) for memory tag allocation and updating. It should be noted that this application only uses the RISC-V architecture as an example for illustration and is not limited to it. The instruction has the following format:

[0176] `settag rs1,imm4`: This instruction sets a tag for a specified memory region. `rs1` is the source register, which contains a portion of the virtual address, and `imm4` is an immediate value representing the number of memory chunks to be tagged. For example, if `imm4` is set to 1, the `settag` instruction will tag the 16-byte (one chunk) memory region pointed to by `rs1`; if `imm4` is set to 16, it will tag the 256-byte memory region pointed to by `rs1`.

[0177] `setinvtag rs1,imm4`: This instruction is similar to `settag`, but it is used to cancel or invalidate memory tags for a specified memory region. Similarly, the `rs1` register contains partial information about the virtual address, and `imm4` indicates the number of memory blocks whose tags are to be invalidated.

[0178] Both of these instructions are designed to enhance memory safety, enabling hardware-level detection of memory access legitimacy and preventing out-of-bounds or improper memory access caused by software errors. By using the `settag` and `setinvtag` instructions, developers can dynamically set or untag memory regions at runtime, thus enabling effective memory access verification during Load / Store instruction execution.

[0179] The virtual address corresponding to a memory tag is represented by the following formula:

[0180] mc_tag_va=VITT_BASE+BIT_TO_BYTE((va>>4)*mc_tag_width(4));

[0181] The mc_tag_va mentioned above is the virtual address used to locate and store memory tag values.

[0182] The aforementioned VITT_BASE can be the base address of the memory tag virtual address defined in the architecture, specifying the starting position of the memory tag page table in the virtual address space. This architecture can be RISC-V, ARM, x86, Microprocessor without Interlocked Pipened Stages (MIPS), Scalable Reduced Instruction Set Computing Architecture for RISC (SPARC), or Performance Optimized With Enhanced RISC (POWER).

[0183] The va mentioned above represents a virtual address, which is the address used by a program when accessing memory.

[0184] The ">>" symbol above indicates a logical right shift operation. `va>>4` means shifting the virtual address `va` right by 4 bits. This is because memory tags are typically associated with 16-byte aligned memory blocks. Shifting right by 4 bits is equivalent to skipping the lowest 4 bits of the address (i.e., skipping a 16-byte address range) and locating the starting address of that 16-byte block.

[0185] The `mc_tag_width` mentioned above represents the width of the memory tag, measured in bits, and can be defined as 4 bits. This means that each 16-byte memory block can have a 4-bit tag.

[0186] The BIT_TO_BYTE function mentioned above is used to convert bit width to byte width. For example, if mc_tag_width is 4 bits, after conversion by BIT_TO_BYTE, you get the number of bytes required for a 4-bit tag, which is 0.5 bytes, or usually implemented as 1 byte, because memory is typically accessed in bytes.

[0187] The above (va>>4)*mc_tag_width(4) calculates the tag's offset in memory relative to VITT_BASE, i.e., the actual storage location of the tag. First, the starting address of the 16-byte block is obtained from va>>4, and then multiplied by mc_tag_width (4 bits in this example) to get the tag's offset position within that block. However, considering the conversion of BIT_TO_BYTE, in actual operation, the bit width will be converted to the offset in bytes.

[0188] Ultimately, `mc_tag_va` is obtained by adding `VITT_BASE` to the offset calculated above. It indicates the actual virtual memory location where the memory tag corresponding to a specific virtual address is stored. The purpose of this is to allow the hardware to quickly locate the correct memory tag value based on the virtual address when executing Load / Store instructions, thereby enabling memory safety and memory access verification.

[0189] The above formula calculates the virtual address used to store memory tags by combining the virtual address, the base address of the memory tag page table, and the width of the memory tags, so that the corresponding tag check can be performed when accessing memory.

[0190] According to the architecture specification, the ordering between Settag / SetInvTag and Load / Store follows these rules: when SetTag / SetInvTag completes, the same ASID / VMID is guaranteed, and the Load / Store VA = Settag / SetInvTagRS1 instruction order ensures that the Younger Load / Store instruction can see the updated Memory Tag. It should be noted that the Settag / setinvtag instructions have similar functions, and this application will not distinguish between the two instructions when describing Memory Tag allocation and updates.

[0191] Figure 4 This is a flowchart of a load / store instruction according to an embodiment of this application, such as... Figure 4 As shown, the process includes the following:

[0192] Step S401, Load / Store Instruction.

[0193] The above steps are the starting point of all processes, indicating that the processor is ready to execute load or store instructions.

[0194] The virtual address of the memory tag corresponding to the Load / Store instruction is represented by the following formula:

[0195] (VITT_BASE+BIT_TO_BYTE(VA>>4)*mc_tag_width(4-bit)).

[0196] Step S402, Virtual Address to Physical Address Translation (VA2PA).

[0197] The virtual address (VA) of the Load / Store instruction needs to be looked up in the page table and translated into a physical address so that physical memory can be actually accessed. The above steps refer to the conditions for the first VA2PA, and they need to be performed every time the Load / Store instruction is executed.

[0198] Step S403, Virtual Address to Physical Address Translation (VA2PA).

[0199] The above steps refer to the conditions for the second VA2PA, which is only required when the page table indicates that the physical page needs a Memory Tag check. In other words, if the corresponding entry in the page table indicates that a Memory Tag check is required, the processor needs to perform a second VA2PA to query and check the Memory Tag before the Load / Store operation. The virtual address associated with the Memory Tag (usually calculated based on a specific virtual address, such as using the mc_tag_va calculation formula mentioned above) is translated into a physical address, thereby reading the Memory Tag value stored in physical memory.

[0200] Step S404: Is a tag check required? If yes, proceed to step S405; otherwise, proceed to step S407.

[0201] The above steps ask whether a Memory Tag check needs to be performed on the physical memory involved in the Load / Store instruction, which depends on the identifier in the page table.

[0202] Load / Store instructions require access to the page table first. The MTAG bit of the Leaf Page Table entry (Leaf PTE) indicates whether the physical page needs a Memory Tag check. If it is 1'b1, a Memory Tag check is required. Otherwise, it is not.

[0203] If no Memory Tag check is required, the Load / Store instructions will access the memory normally.

[0204] If a memory tag check is required, the memory tag must first be looked up and checked. If the memory tag matches the memory tag in the address pointer, the load / store instruction can access the memory normally. Otherwise, the load / store instruction will not access the memory and will report an exception. When a memory access instruction (load / store) is executed, the hardware checks the memory tag to ensure that the data access is as expected, thereby preventing illegal or erroneous memory access operations.

[0205] If an exception is reported, the load command reports a synchronous exception, while the store command reports an asynchronous exception.

[0206] Step S405: Load Memory Tag.

[0207] If the previous step confirms that tag checking is required, the corresponding Memory Tag value will be loaded from physical memory for subsequent comparison and verification.

[0208] Step S406: Has the tag check passed? If yes, proceed to step S407; otherwise, proceed to step S408.

[0209] The above steps can be used to compare the Memory Tag value loaded from memory with the expected tag value stored in the pointer to confirm whether they are consistent.

[0210] Step S407, Read Memory.

[0211] The Load instruction can only continue to execute and read data from physical memory when the tag check is successful, meaning the Memory Tag matches the expected value.

[0212] Step S408: Generate Exception.

[0213] If the tag check fails, the expresser's exception handling mechanism will be triggered, which may be a synchronous exception (for Load instructions) or an asynchronous exception (for Store instructions).

[0214] For the Store command, data can only be written to physical memory when the tag check is successful.

[0215] The above process outlines how the Memory Tag feature is integrated into the execution of memory access instructions within the architecture, ensuring the legality and security of memory operations. It also reveals how the exception handling mechanism works to deal with unsafe memory access behaviors.

[0216] When an application allocates memory, it calls the memory allocation function within the library:

[0217] ptr = malloc(size);

[0218] The `malloc` function mentioned above is short for "memory allocation." It's a function in the C standard library used to dynamically allocate a block of memory from the heap at runtime. It accepts a `size` parameter, representing the size of the memory to be allocated (in bytes). `malloc` attempts to find a sufficiently large contiguous memory region in the heap to satisfy the allocation request and returns the starting address of that memory region.

[0219] The execution process of the statement `ptr = malloc(size)` is as follows:

[0220] Calling malloc(size) requests the operating system to allocate a memory region of size size bytes.

[0221] If the allocation is successful, the malloc function will return the starting address of the memory block.

[0222] The returned address is stored in the pointer variable ptr, making ptr point to the newly allocated memory area.

[0223] After completing the above process, the high-order bits of the returned pointer ptr will be written to the allocated memory tag value.

[0224] In multi-core scenarios, the producer employs a software "barrier" strategy when reclaiming allocated memory tags. Specifically, this means that before reclaiming or updating memory tags, the producer ensures that all consumer threads no longer access those memory tags awaiting reclamation. The barrier strategy acts as a synchronization mechanism, ensuring that modifications to memory tags in a multi-threaded environment do not interfere with the normal operation of other threads, thereby maintaining memory tag consistency and data integrity.

[0225] Barriers are an important concept in multithreaded programming, used to synchronize the execution of multiple threads. When a thread reaches a barrier, it is prevented from proceeding until all related threads have reached the barrier, at which point the threads are simultaneously released and continue execution. In the context of memory tags, barrier strategies ensure that access to memory tags between producers and consumers is ordered and synchronized, avoiding inconsistent states that can result from concurrent access.

[0226] Figure 5 This is a schematic diagram of the structure of an instruction execution unit within a processor according to an embodiment of this application, such as... Figure 5 As shown, it includes the Issue Pipeline, Execution Pipeline, Issue Queue (ISQ), Address Generation Unit (AGU), Data Side Translation Lookaside Buffer (DTLB), Data Side Translation Miss Queue (DTMQ), Memory Management Unit (MMU), Memory Tag Translation Lookaside Buffer (MTLB), Memory Tag Translation Miss Queue (MTMQ), Memory Tag Translation Miss Order (MTMO), Physical Address HASH (HASH_PA), Write Buffer, Store Queue (STQ), Load Queue (LDQ), and Multiplexer Output (MUX out 4-bit). Figure 5 The modules marked with shaded lines are functional modules related to the Memory Tag feature.

[0227] The aforementioned release pipeline is responsible for issuing instructions, that is, sending instructions from the queue to the execution unit for further processing. The aforementioned execution pipeline is responsible for executing instructions, including accessing the data cache and exception handling. The aforementioned release queue is used to temporarily store instructions waiting to be released, i.e., instructions waiting to enter the execution pipeline. The aforementioned address generation unit is responsible for calculating the physical address of the instruction, translating the virtual address into a physical address. The aforementioned data-side translation bypass cache is used for quickly finding and translating virtual addresses to physical addresses on the data side, improving memory access speed. The aforementioned data-side translation miss queue is used when a virtual address to physical address translation is not found in the DTLB; the request is temporarily stored in this queue until the translation is completed. The aforementioned memory management unit is responsible for memory address translation and memory protection, including handling memory tag lookups and updates.

[0228] The aforementioned memory tag translation bypass cache stores memory tag values ​​associated with virtual addresses for fast lookup and verification of memory tags. The aforementioned memory tag translation miss queue is used when a memory tag associated with a virtual address is not found in the MTLB; requests are temporarily stored in this queue, awaiting the MMU to complete the tag lookup or update. The aforementioned data-side translation miss order queue temporarily stores translation requests that have missed in the DTLB, ensuring the execution order of translation requests. The aforementioned memory tag translation miss order ensures that the execution order of memory tag translation requests is consistent with that of data-side translation requests. The aforementioned memory tag indicator indicates whether a row in the L2 cache contains memory tag information, for data consistency maintenance.

[0229] The physical address hashing described above uses a hash algorithm to process physical addresses and generate hash values ​​to accelerate physical address lookups and updates. The tag checking described above compares the memory tag value obtained from the MTLB with the memory tag value carried in the instruction to verify the legitimacy of memory access. The load queue described above manages the queue of load instructions, tracking their status until completion. The store queue described above manages the queue of store instructions, tracking their status until commit. Physical address hashing is implemented to the memory tag translation bypass cache through L2 cache eviction invalidation, whereby when an item in the L2 cache is evicted, it is ensured that the memory tag of that item is also marked invalid in other caches or memory.

[0230] Figure 5In this architecture, the Load / Store execution unit pipeline can be divided into the Issue Pipeline and the Execution Pipeline. The Issue Pipeline's main functions include instruction issuance, operand fetching, TLB lookup, and Load / Store instruction allocation. The Execution Pipeline's main functions include accessing the Data Cache and exception handling. The ISQ (Instruction Query Queue) is responsible for issuing Load / Store instructions. The AGU (Automatic Lookup Unit) is responsible for address calculation. The DTLB (Data Transfer Layer Buffer) is responsible for fast VA2PA (Variable Access Layer Buffer) translation. The DTMQ (Data Transfer Query Queue) is responsible for caching DTLB lookup miss requests. If a DTLB miss occurs, the Load / Store instruction is rejected back to the ISQ, and reissued after the entry is filled. The MTLB (Memory Tag Translation Lookaside Buffer) stores the corresponding Memory Tag Value based on the Virtual Address. In this structure, the Memory Tag Value is tentatively set to 256 bits. Depending on the actual situation, the width of the Memory Tag Value can be 64 bits, 128 bits, 256 bits, 512 bits, or other values; no limitation is made here. MTMQ is responsible for caching MTLB query miss requests. If an MTLB miss occurs, the Load / Store command will be rejected back to ISQ, and will be reissued after the table entries are filled. MTMQ will send the MTLB miss request to the MMU. The MTag Translation Engine within the MMU will first perform VA2PA mapping based on the address calculation formula, and then read the Memory Tag based on the obtained PA. Finally, the Memory Tag Value will be updated in the MTLB.

[0231] Load / Store instructions obtain the memory tag value (MTAGValue) from the MTLB and store it in the LDQ / STQ. The LDQ tracks the lifecycle state of load instructions. The STQ, or Store Queue, tracks the lifecycle state of store instructions before retiring. The MTAGValue in the LDQ is used for memory tag checks. After retiring, the store instruction enters the Write Buffer, where the MTAGValue is merged. The MTAGValue in the Write Buffer is then used for memory tag checks.

[0232] Figure 6 This is a schematic diagram of a data path for setting a tag and setting an invalid tag according to an embodiment of this application, such as... Figure 6 As shown, the shaded modules are the functional modules related to the Settag and Setinvtag instructions. After the Settag / Setinvtag instruction is issued from the ISQ, it first checks the MTLB. If the virtual address (VA) is the same as the tag virtual address (TAG_VA) in the MTLB, the corresponding MTLB Entry needs to be invalidated. The Settag / Setinvtag instruction carries the SetTagindicator into the STQ. When the Settag / Setinvtag instruction retires, it can enter the Write Buffer from the STQ. The Settag / Setinvtag instruction can be merged into the Write Buffer like normal Store instructions. Settag / Setinvtag can only be merged with instructions of this type. When Settag / Setinvtag can write to memory, the Write Buffer will write the data directly to the L2 cache. If there is an L1 cache copy at this time, the L2 cache will maintain data consistency. L2 cache lines updated by Settag / Setinvtag are marked as MTag Indicators, meaning that this cache line is a memory tag cache line.

[0233] Figure 7 This is a schematic diagram of multi-core memory tag consistency maintenance according to an embodiment of this application, such as... Figure 7As shown, the shaded modules are functional modules related to multi-core memory tag consistency maintenance. Cachelines updated by Settag / Setinvtag are marked as Memory Tag Cachelines. Memory Tags read back by the MMU must be populated not only in the MTLB but also in the L2 Cache. The corresponding cacheline is marked as a Memory TagCacheline. When the MMU populates the MTLB, it hashes the PA corresponding to that data to generate a compressed HashPA, and then updates it in the MTLB. When a Memory Tag Cacheline in the L2 Cache is replaced, it first calculates its HashPA and then broadcasts it to the MTLB to query for a matching HashPA. If a match is found, the corresponding MTLB Entry is invalidated.

[0234] Figure 8 The following figure illustrates a data path for querying and checking memory tags in a load / store instruction, according to an embodiment of this application. Figure 8 As shown, the Load / Store instruction queries the MTLB on the Issue Pipeline to determine if a match is found, and whether the calculated address is equal to the virtual address (TAG_VA) in the MTLB. If a match is found, the obtained Memory Tag Value is updated in the LDQ / STQ. The Load / Store instruction compares the obtained Memory Tag Value with the virtual address on the Execution Pipeline. If a match is found, memory access is possible. If a match is not found, an exception is reported. For Load instructions, a synchronous exception can be reported if a match is found. For Store instructions, since memory access is performed in the Write Buffer, an asynchronous exception can be reported if a match is found. If a match is found, the MTMQ is allocated, and the Load / Store instruction is rejected and returned to the ISQ. The MTMQ sends a request to the MMU, which refills the MTLB. Then, the relevant Load / Store instructions in the ISQ are woken up.

[0235] This application proposes a microarchitectural implementation strategy for the Memory Tag feature in the architecture, aiming to enhance the security and reliability of memory operations without sacrificing processor performance.

[0236] By utilizing virtual addresses to allocate and update Memory Tags, this solution effectively monitors and controls access to memory data, identifying inappropriate operations such as unauthorized access or data tampering. This feature is significant for improving the accuracy of online and offline software testing, shortening system development cycles, and accelerating large-scale deployment of software and hardware.

[0237] Traditional methods for implementing Memory Tag features may introduce additional memory access and checking steps, leading to a decrease in memory access performance. However, this application ensures that processor memory access performance is not affected even when MemoryTag features are enabled by improving data paths and reducing unnecessary operations. This is achieved through a series of micro-architectural designs, such as efficient querying and updating of the MTLB, and a fast exception handling mechanism in case of mismatch.

[0238] This application adds a necessary Memory Tag processing module to the existing processor architecture without introducing excessive hardware burden. Leveraging the flexibility of the pipeline structure, and through reasonable resource allocation and task scheduling, the integration of Memory Tag features becomes feasible and cost-effective. Furthermore, through software-level assistance (such as barrier strategies), this application can maintain Memory Tag consistency in a multi-core environment, reducing the complexity and potential overhead of pure hardware implementation. This application ensures zero performance impact through microarchitecture-level improvements while reducing the difficulty of hardware implementation.

[0239] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0240] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0241] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a processor to execute the methods of the various embodiments of this application.

[0242] According to an embodiment of this application, a processor is also provided. Figure 9 This is a schematic diagram of a processor according to an embodiment of this application, such as... Figure 9 As shown, the processor 900 includes: a transmit queue 902, a data buffer 904, a preset buffer 906, a verification device 908, and an access device 910.

[0243] The system includes: a launch queue for launching memory access requests; a data buffer connected to the launch queue for launching instructions for memory access requests; a preset buffer connected to the launch queue and running in parallel with the data buffer for obtaining a first memory coloring value corresponding to the memory access request, wherein the first memory coloring value is used to verify the memory access request; a verification device for verifying the memory access request based on the first memory coloring value during the execution of the memory access request, and obtaining a verification result, wherein the verification result is used to indicate whether the memory access request has been successfully verified; and an access device for accessing memory based on the memory access request if the verification result indicates that the memory access request has been successfully verified.

[0244] In processor architecture, the issue queue is a special data structure used to temporarily store instructions that are about to be issued to the execution unit. It typically contains a series of instruction entries, each with corresponding status information indicating whether the instruction is ready to be issued and whether the resources required for issuance are available.

[0245] The aforementioned data buffer actually refers to the Data Translation Lookaside Buffer (DTLB), which is a caching mechanism used to quickly look up and translate virtual addresses to physical addresses, accelerating memory access operations.

[0246] The aforementioned preset buffer refers to the Memory Tag Translation Lookaside Buffer (MTLB), which stores memory coloring values ​​associated with virtual addresses so that these values ​​can be quickly retrieved and verified before memory access instructions are executed, thereby improving the efficiency of memory safety checks.

[0247] The aforementioned verification device can be a Tag Check mechanism, which verifies the legitimacy of memory access requests based on the first memory coloring value obtained from the preset buffer MTLB during the execution of memory access instructions, and generates a verification result to determine whether memory operations are restricted by permissions or pose a security risk.

[0248] The aforementioned access device refers to a specific memory access unit. After receiving the verification result from the verification device, it will only actually perform access operations on the physical memory based on the memory access request if the verification result shows that the memory access request is successful (i.e., the request is legal and has no security risks).

[0249] Memory access instructions in the processor (such as Load and Store instructions) are first temporarily stored in the Issue Queue, awaiting allocation of execution resources. When an instruction is ready and selected by the Issue Queue, the Data Buffer Block (DTLB) issues the instruction, translating the virtual address into a physical address, ready to access memory. Simultaneously, the Medium Memory Buffer Block (MTLB) runs in parallel, retrieving a first memory coloring value from the MTLB based on the memory access request. This value is used for subsequent permission and security verification. Next, the Tag Check verifies the memory access request based on the first memory coloring value, obtaining a verification result. If the verification result shows that the memory access request successfully passes the security check (i.e., the verification result indicates that the request is legitimate), the access device (i.e., the memory access unit) will then perform the actual read / write operation on the physical memory based on the memory access request. Conversely, if the verification fails, the access device will not perform the memory access operation but will instead take appropriate exception handling measures to prevent illegal memory access.

[0250] When the processor's memory access unit processes memory access instructions, it temporarily stores these instructions in the issue queue (ISQ), awaiting allocation of execution resources. When an instruction arrives at the ISQ and is ready for execution, the data buffer (DTLB) issues the instruction, translating the virtual address into a physical address. Simultaneously, the memory storage buffer (MTLB) queries the first memory coloring value associated with the virtual address in parallel to perform a memory safety check. The tag check verifies the memory access request based on the first memory coloring value obtained from the MTLB, determining whether it complies with access permissions and security regulations. The access unit (i.e., the memory access unit) only executes the memory access operation, accessing the target physical memory location and completing the data read / write operation, upon receiving a successful verification signal from the tag check. Conversely, if the access fails verification, the access unit will not execute the memory operation but may trigger an exception handling mechanism to prevent illegal memory access events, maintaining memory safety and data integrity.

[0251] This application achieves efficient processing and security verification of memory access requests by introducing a parallel operation mechanism of issue queue, data buffer, and media buffer limit (MTLB) in the processor memory access unit. By querying the first memory coloring value associated with the request in the MTLB in parallel before instruction execution and verifying the access request using a tag check, the legality of memory operations can be quickly determined, avoiding security risks caused by illegal access and strengthening memory security. Simultaneously, this mechanism reduces memory access latency, improves instruction execution efficiency, helps shorten system development cycles, accelerates hardware and software deployment, and has a positive impact on maintaining system stability and data integrity.

[0252] In the above embodiments of this application, the processor further includes: an address generation unit, configured to determine a first virtual address based on a memory access request; and a preset buffer, configured to read the memory coloring value corresponding to the first virtual address to obtain a first memory coloring value if a memory coloring value corresponding to the first virtual address exists.

[0253] The aforementioned first virtual address is calculated by the address generation unit (AGU) based on the memory access request when the processor executes a memory access instruction. It is used to identify the memory region that the instruction wants to access. In the disclosure document, for Load / Store instructions, the first virtual address is obtained by multiplying VITT_BASE with the displacement obtained after a right shift operation based on VA>>4 and mc_tag_width to locate the correct memory coloring value.

[0254] The aforementioned first memory coloring value is the memory coloring value associated with the first virtual address stored in the default memory buffer (MTLB), used for validity verification before the execution of memory access instructions. If a first memory coloring value corresponding to the first virtual address exists in the MTLB, the AGU will read this value from the MTLB as part of the verification process.

[0255] When the processor receives a memory access instruction (such as a Load / Store instruction), the Address Generation Unit (AGU) calculates a first virtual address based on the address parameters in the instruction. This virtual address is calculated by adding an offset to VITT_BASE after bit shifting and bit width scaling, and is used to precisely identify the memory location the processor wants to access. Subsequently, if a valid memory coloring value corresponding to the first virtual address exists in the MTLB (Memory Management Load Balancer), the AGU reads this memory coloring value from the MTLB, i.e., the first memory coloring value, to further verify the legality of the memory access. This process is performed before instruction execution, ensuring that memory operations are performed within the scope of legal permissions, which helps maintain memory security and data integrity.

[0256] Upon receiving a Load / Store instruction, the processor's memory access function first uses the Address Generation Unit (AGU) to calculate a first virtual address based on the instruction parameters, thus locating the memory access target. Then, if the MTLB (Memory Management Load Balancer) stores a first memory coloring value corresponding to the first virtual address, the AGU reads this value to serve as the basis for verifying the legality of the memory access during instruction execution. The purpose of this mechanism is to pre-obtain the memory coloring value associated with the access location before the memory access instruction is executed, and through rapid verification, ensure the legality and security of the memory access operation, thereby avoiding the risks of illegal memory access and data leakage, and maintaining system stability and data security.

[0257] When the processor processes a Load / Store instruction, the AGU calculates the first virtual address based on the memory access location requested by the instruction and the VITT_BASE information. If a first memory coloring value corresponding to this virtual address exists in the MTLB (Memory Management Load Balancer), the AGU reads this value from the MTLB and passes it to the subsequent verification mechanism, namely the Tag Check step in the execution pipeline. In this process, the combination of the AGU's computational power and the MTLB's high-speed retrieval capability ensures that the memory access instruction can quickly obtain the memory coloring information related to the access location before execution, enabling timely and effective access legitimacy verification. This plays a positive role in improving memory access security and data integrity.

[0258] This application achieves rapid verification of memory access legitimacy by using an address generation unit (AGU) to calculate a first virtual address before the execution of a memory access instruction, and having a corresponding first memory coloring value provided by a memory mode buffer (MTLB). This mechanism not only improves memory access security and prevents potential threats from unauthorized access, but also reduces pre-access waiting time due to the high-speed retrieval characteristics of the MTLB, thereby improving the overall performance of the processor and accelerating hardware and software deployment and shortening product development cycles. Furthermore, by pre-verifying the memory coloring value, abnormal interruptions during execution can be avoided, enhancing system stability and user experience.

[0259] In the above embodiments of this application, the processor further includes: a memory management unit, configured to convert the first virtual address into a target physical address, read the memory coloring value corresponding to the first virtual address from memory based on the target physical address, and store the memory coloring value corresponding to the first virtual address into the preset buffer when there is no memory coloring value corresponding to the first virtual address in the preset buffer.

[0260] The Memory Management Unit (MMU) described above is an important component of the processor, responsible for managing and executing address translation tasks for memory accesses, including mapping from virtual addresses (VA) to physical addresses (PA). The MMU not only handles regular memory access requests but also coordinates and maintains high-level functions related to memory safety and efficiency, such as memory tag value processing and consistency checks.

[0261] The aforementioned physical address translation refers to the MMU converting the first virtual address into the corresponding target physical address. This process is called address translation. In a memory hierarchy, the physical address is the address space that memory devices can directly recognize and manipulate. Therefore, converting the virtual address into the target physical address is a prerequisite for memory access.

[0262] The above-mentioned reading of memory coloring values ​​from memory is a key process when the MMU finds that there is no first memory coloring value corresponding to the first virtual address in the preset buffer MTLB. It will convert the first virtual address into the target physical address and then read the corresponding memory coloring value from memory based on the physical address. This is crucial information for verifying the legality and security of memory access.

[0263] The aforementioned update of the preset buffer involves the MMU reading the memory coloring value corresponding to the first virtual address from memory and storing this value in the preset buffer MTLB. This value is used for quick verification of subsequent access requests to the same virtual address, avoiding repeated slow memory access operations and improving access speed and system performance.

[0264] When the processor encounters a memory access request, if the Memory Management Unit (MMU) lacks a first memory coloring value corresponding to the first virtual address in the Memory Management Block (MTLB), the MMU will intervene. First, the MMU translates the first virtual address into a target physical address—a necessary address translation step to ensure correct retrieval of the target information from memory. Next, the MMU reads the memory coloring value corresponding to the first virtual address from memory based on the target physical address; this is crucial data for verifying the legality of the memory access. Finally, the MMU updates the MTLB with the read first memory coloring value for rapid verification of subsequent access requests. This process simplifies memory access and improves system performance.

[0265] In a processor, the Memory Management Unit (MMU) plays a crucial role, especially when processing memory access instructions. When the Mediatory Load Balancer (MTLB) fails to provide the required first memory coloring value, the MMU performs a series of operations to ensure that the instruction can continue execution without violating memory safety regulations. The MMU first translates the first virtual address into the target physical address, which is the location of the specific data in memory to be accessed. Then, based on this physical address, the MMU reads the memory coloring value corresponding to the first virtual address from memory to verify the legality and safety of the instruction. Once the reading is complete, the MMU also stores the first memory coloring value back into the MTLB, providing a fast reference for future access requests to the same virtual address, avoiding unnecessary slow memory accesses, and improving access efficiency and system responsiveness.

[0266] When the processor's microarchitecture unit (such as the MTLB) fails to find the first memory coloring value corresponding to the first virtual address in the preset buffer, the Memory Management Unit (MMU) intervenes to perform a series of compensation operations. The MMU first translates the first virtual address into the actual target physical address, which is used to locate the target data block and memory coloring information in main memory. Next, the MMU reads the memory coloring value corresponding to the first virtual address from main memory based on the target physical address to verify the permission and legitimacy of the memory access. After reading, the MMU updates this memory coloring value in the preset buffer MTLB, so that future access requests for the same virtual address can directly and quickly obtain the memory coloring value from the MTLB, avoiding repeated slow memory read operations and improving the overall efficiency of memory access.

[0267] This application, through the integrated MMU's dynamic processing mechanism, effectively compensates for the failure of the default memory buffer (MTLB) to provide the first memory coloring value, ensuring the legality and security of memory access instructions while maintaining high access efficiency. The MMU's intervention not only solves the MTLB cache miss problem but also avoids slow processing of future identical requests by updating the MTLB with the read memory coloring value, thus improving system response speed, reducing memory access latency, and having a positive impact on maintaining data integrity and enhancing user experience.

[0268] According to an embodiment of this application, a memory access apparatus for implementing the above-described memory access method is also provided. Figure 10 This is a schematic diagram of a memory access device according to an embodiment of this application, such as... Figure 10 As shown, the device 1000 includes: an acquisition module 1002, a verification module 1004, and an access module 1006.

[0269] The acquisition module is used to acquire a first memory coloring value corresponding to the memory access request while issuing an instruction for the memory access request, and the first memory coloring value is used to verify the memory access request; the verification module is used to verify the memory access request based on the first memory coloring value during the execution of the memory access request and obtain a verification result, and the verification result is used to indicate whether the memory access request is successfully verified; the access module is used to access the memory based on the memory access request if the verification result indicates that the memory access request is successfully verified.

[0270] It should be noted that the acquisition module 1002, verification module 1004, and access module 1006 mentioned above correspond to steps S302 to S306 in the above embodiments. The three modules and their corresponding steps implement the same instances and application scenarios, but are not limited to the content disclosed in the above embodiments. It should be noted that the above modules or units can be hardware or software components stored in memory and processed by one or more processors. The above modules can also be part of the device and run in the server 10 provided in the above embodiments.

[0271] In the above embodiments of this application, the acquisition module is further configured to determine the first virtual address based on the memory access request; and if there is a memory coloring value corresponding to the first virtual address in the preset buffer, read the memory coloring value corresponding to the first virtual address from the preset buffer to obtain the first memory coloring value.

[0272] In the above embodiments of this application, the device is further configured to cancel the execution of the memory access request and convert the first virtual address into a target physical address when there is no memory coloring value corresponding to the first virtual address in the preset buffer; read the memory coloring value corresponding to the first virtual address from memory based on the target physical address; and store the memory coloring value corresponding to the first virtual address into the preset buffer.

[0273] In the above embodiments of this application, the device is further configured to perform a hash operation on the target physical address to obtain a hash physical address; and based on the hash physical address, update the memory coloring value corresponding to the first virtual address to a preset buffer.

[0274] In the above embodiments of this application, the device is further configured to update the memory coloring value corresponding to the first virtual address to the second-level cache.

[0275] In the above embodiments of this application, the verification module is further configured to obtain the second memory coloring value carried in the memory access request; if the second memory coloring value matches the first memory coloring value successfully, the verification result is determined to be that the memory access request verification is successful; if the second memory coloring value does not match the first memory coloring value, the verification result is determined to be that the memory access request verification fails.

[0276] In the above embodiments of this application, the device is further configured to store a first memory coloring value in a target queue corresponding to the memory access request based on the type of the memory access request; and to read the first memory coloring value from the target queue during the execution of the memory access request.

[0277] In the above embodiments of this application, the device is further configured to store the memory access request in a write buffer and store the memory coloring value corresponding to the memory access request in the write buffer when the memory access request is a write request and the memory access request has been completed.

[0278] In the above embodiments of this application, the device is further configured to, in response to receiving a memory coloring value processing instruction, determine a second virtual address based on the memory coloring value processing instruction; if a first data item corresponding to the second virtual address exists in a preset buffer, set the first data item to an invalid state, wherein the first data item is used to store the memory coloring value corresponding to the second virtual address; and store the third memory coloring value carried in the memory coloring value processing instruction into memory and the second-level cache.

[0279] In the above embodiments of this application, the device is further configured to, when a replacement operation is detected on the target cache line in the secondary cache, read the target hash physical address in the target cache line; determine whether a second data item corresponding to the target hash physical address is stored in a preset buffer; and, if the second data item is stored in the preset buffer, set the second data item to an invalid state, wherein the second data item is used to store the memory coloring value corresponding to the target hash physical address.

[0280] In the above embodiments of this application, a system-on-a-chip is also provided, including: a processor of any one of the above embodiments.

[0281] Embodiments of this application may provide a computing device. Figure 11 This is a structural block diagram of a computing device according to an embodiment of this application. Figure 11 As shown, the computing device A may include one or more (only one is shown in the figure) processors 102, memory 104 and peripheral interfaces 106, wherein the processors 102, memory 104 and peripheral interfaces 106 are interconnected via a bus 108.

[0282] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the methods and apparatus in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to terminal A via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0283] The processor can invoke information and application programs stored in the memory through a transmission device to execute the methods in the various embodiments of this application.

[0284] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0285] Embodiments of this application also provide a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.

[0286] Optionally, in this embodiment, the storage medium may be located in any one of the computing devices in the computing device group.

[0287] Optionally, in this embodiment, the computer-readable storage medium includes a stored executable program, wherein the methods of various embodiments of the present application are implemented when the executable program is executed by a processor.

[0288] Embodiments of this application also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

[0289] Embodiments of this application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the method provided in the above embodiments.

[0290] Embodiments of this application also provide a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it implements the method provided in the above embodiments.

[0291] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0292] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0293] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0294] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0295] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0296] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A memory access method, characterized in that, Applied to a processor, the method includes: In response to receiving a memory access request, while issuing an instruction for the memory access request, a first memory coloring value corresponding to the memory access request is obtained, wherein the first memory coloring value is used to verify the memory access request; During the execution of the memory access request, the memory access request is verified based on the first memory coloring value to obtain a verification result, wherein the verification result is used to characterize whether the memory access request is successfully verified. If the verification result indicates that the memory access request has been successfully verified, the memory is accessed based on the memory access request.

2. The method according to claim 1, characterized in that, The step of obtaining the first memory coloring value corresponding to the memory access request includes: The first virtual address is determined based on the memory access request; If the memory coloring value corresponding to the first virtual address exists in the preset buffer, the memory coloring value corresponding to the first virtual address is read from the preset buffer to obtain the first memory coloring value.

3. The method according to claim 2, characterized in that, The method further includes: If the memory coloring value corresponding to the first virtual address does not exist in the preset buffer, the memory access request is canceled and the first virtual address is converted to the target physical address. Based on the target physical address, read the memory coloring value corresponding to the first virtual address from memory; The memory coloring value corresponding to the first virtual address is stored in the preset buffer.

4. The method according to claim 3, characterized in that, The step of storing the memory coloring value corresponding to the first virtual address into the preset buffer includes: Perform a hash operation on the target physical address to obtain the hash physical address; Based on the hash physical address, the memory coloring value corresponding to the first virtual address is updated in the preset buffer.

5. The method according to claim 3, characterized in that, The method further includes: Update the memory coloring value corresponding to the first virtual address to the second-level cache.

6. The method according to claim 1, characterized in that, The step of verifying the memory access request based on the first memory coloring value to obtain a verification result includes: Obtain the second memory coloring value carried in the memory access request; If the second memory coloring value matches the first memory coloring value, the verification result is determined to be that the memory access request has been successfully verified. If the second memory coloring value fails to match the first memory coloring value, the verification result is determined to be that the memory access request verification failed.

7. The method according to claim 1, characterized in that, The method further includes: Based on the type of the memory access request, the first memory coloring value is stored in the target queue corresponding to the memory access request; During the execution of the memory access request, the first memory coloring value is read from the target queue.

8. The method according to claim 1, characterized in that, The method further includes: If the memory access request is a write request and the memory access request has been completed, the memory access request is stored in the write buffer, and the memory coloring value corresponding to the memory access request is also stored in the write buffer.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: In response to receiving a memory coloring value processing instruction, a second virtual address is determined based on the memory coloring value processing instruction; If a first data item corresponding to the second virtual address exists in the preset buffer, the first data item is set to an invalid state, wherein the first data item is used to store the memory coloring value corresponding to the second virtual address; The third memory coloring value carried in the memory coloring value processing instruction is stored in memory and the second-level cache.

10. The method according to any one of claims 1 to 8, characterized in that, The method further includes: If a replacement operation is detected on the target cache line in the second-level cache, the target hash physical address in the target cache line is read. Determine whether the preset buffer stores the second data item corresponding to the target hash physical address; If the second data item is stored in the preset buffer, the second data item is set to an invalid state, wherein the second data item is used to store the memory coloring value corresponding to the target hash physical address.

11. A processor, characterized in that, include: The launch queue is used to launch memory access requests; A data buffer, connected to the issue queue, is used to issue instructions for the memory access request; A preset buffer, connected to the transmit queue and running in parallel with the data buffer, is used to obtain a first memory coloring value corresponding to the memory access request, wherein the first memory coloring value is used to verify the memory access request; A verification device is used to verify the memory access request based on the first memory coloring value during the execution of the memory access request, and obtain a verification result, wherein the verification result is used to characterize whether the memory access request is successfully verified. An access device is configured to access memory based on the memory access request if the verification result indicates that the memory access request has been successfully verified.

12. The processor according to claim 11, characterized in that, The processor also includes: An address generation unit is used to determine a first virtual address based on the memory access request; The preset buffer is also used to read the memory coloring value corresponding to the first virtual address to obtain the first memory coloring value when the memory coloring value corresponding to the first virtual address exists.

13. The processor according to claim 12, characterized in that, The processor also includes: The memory management unit is configured to, when the memory coloring value corresponding to the first virtual address does not exist in the preset buffer, convert the first virtual address into a target physical address, read the memory coloring value corresponding to the first virtual address from memory based on the target physical address, and store the memory coloring value corresponding to the first virtual address into the preset buffer.

14. A system-on-a-chip, characterized in that, include: The processor according to any one of claims 11 to 13.

15. A computing device, characterized in that, include: Memory, which stores executable programs; A processor for running the program, wherein the program, when running, performs the method according to any one of claims 1 to 10.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein the executable program, when executed by a processor, implements the method according to any one of claims 1 to 10.

17. A computer program product, characterized in that, Includes computer instructions that, when executed by a processor, implement the method according to any one of claims 1 to 10.

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