Solid state storage device and bandwidth adaptation method

Abstract

This application relates to a solid-state storage device and a bandwidth adaptation method. The solid-state storage device includes: a micro-LED array containing at least two pixels; at least one NAND flash memory chip with a parallel data bus, each NAND flash memory chip corresponding to at least two pixels; and a main control chip configured to divide the parallel data bus of each NAND flash memory chip into at least two sub-buses according to the bit width based on the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel. Each sub-bus independently drives one pixel, and each sub-bus contains at least two data bits. The main control chip is also configured to simultaneously drive at least two pixels to emit light through at least two sub-buses. By using the above method, the total bandwidth is made equal to the sum of the modulation rates of each pixel, thereby enabling the use of lower-speed micro-LEDs to match a high-speed flash memory interface.

Description

Technical Field

[0001] This application relates to the field of optical interconnect technology, and in particular to a solid-state storage device and a bandwidth adaptation method. Background Technology

[0002] With the rapid development of solid-state storage technology, the interface speed of NAND flash memory chips is constantly improving (e.g., reaching 2.4Gbps or higher). However, micro light-emitting diodes (MicroLEDs) are limited by materials and processes, resulting in a relatively low modulation rate for a single pixel (e.g., only around 1.2Gbps). Within solid-state storage systems, if traditional electrical interconnect methods are used, problems such as signal attenuation and crosstalk become increasingly prominent. If a single high-speed MicroLED is used for optical interconnect, the speed of a single MicroLED is difficult to match the high speed of the flash memory interface.

[0003] In existing technologies, increasing the modulation rate of a single MicroLED often requires increasing the drive current or optimizing the device structure. However, this leads to a significant decrease in device yield, a substantial increase in cost, and serious heat generation and power consumption issues, which are detrimental to system stability and commercial applications. Therefore, how to achieve bandwidth matching between the high-speed flash memory interface and optoelectronic devices without increasing the modulation rate of a single MicroLED has become a pressing technical challenge in this field. Summary of the Invention

[0004] Therefore, it is necessary to provide a solid-state storage device and a bandwidth adaptation method.

[0005] A solid-state storage device, comprising:

[0006] A miniature light-emitting diode array containing at least two pixels;

[0007] At least one NAND flash memory chip with a parallel data bus;

[0008] The main control chip is connected to the micro light-emitting diode array and the NAND flash memory chip, and is used to split the parallel data bus of each NAND flash memory chip into at least two sets of sub-buses according to the bit width. Each set of sub-buses independently drives one pixel, and each set of sub-buses contains at least two data bits. The main control chip is also used to drive at least two pixels to emit light simultaneously through the at least two sets of sub-buses.

[0009] The main control chip is also used to determine the number of sub-bus groups based on the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel.

[0010] In another embodiment, the main control chip includes a configurable crossbar switch or lookup table. The main control chip dynamically calculates the number of sub-bus groups based on the detected interface rate of the NAND flash memory chip and the modulation rate of a single pixel, and updates the splitting relationship between the parallel data bus and the sub-bus by configuring the crossbar switch or lookup table.

[0011] In another embodiment, at least two data bits in each group of sub-buses are jointly encoded into a single optical signal output by the modulation depth, pulse width, or pulse sequence of the pixels. In another embodiment, the main control chip is also used to enable the at least two pixels to emit light simultaneously or in a set timing sequence.

[0012] In another embodiment, the parallel data bus is divided into at least two groups of sub-buses in bit-width order.

[0013] In another embodiment, the micro-LED array further includes at least one redundant pixel;

[0014] The main control chip is also used to monitor the working status of the at least two pixels. When any of the pixels fails, the sub-bus corresponding to the pixel is remapped to the redundant pixel.

[0015] A bandwidth adaptation method, applied to the solid-state storage device described in any of the above embodiments, includes the following steps:

[0016] The interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro LED array are detected.

[0017] The number of sub-bus groups is determined based on the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro-LED array;

[0018] Configure the data mapping logic of the main control chip so that the data of the NAND flash memory chip is transmitted in parallel through a number of pixels corresponding to the number of sub-bus groups.

[0019] In another embodiment, the data mapping logic for configuring the main control chip includes:

[0020] Maintaining the bit width structure of the parallel data bus, the parallel data bus is divided into multiple groups, each group containing at least two consecutive data bits, and the multiple data bits of each group are mapped as a whole to a corresponding pixel.

[0021] In another embodiment, determining the number of subbus groups based on the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro-LED array includes:

[0022] Calculate the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel, and round it up to get the number of sub-bus groups.

[0023] In another embodiment, the data mapping logic for configuring the main control chip includes:

[0024] The number of sub-bus groups is dynamically calculated based on the detected interface rate of the NAND flash memory chip and the modulation rate of a single pixel.

[0025] The splitting relationship between the parallel data bus and the sub-bus is updated by configuring the crossbar switch or lookup table.

[0026] In another embodiment, the configuration of the main control chip's data mapping logic, which enables the NAND flash memory chip to transmit data in parallel through a number of pixels corresponding to the number of sub-bus groups, includes:

[0027] At least two data bits contained in each group of sub-buses are encoded into an optical signal output by means of the modulation depth, pulse width or pulse sequence of the pixel.

[0028] The aforementioned solid-state storage device and bandwidth adaptation method, by splitting the parallel data of the NAND flash memory chip into multiple sub-buses, each sub-bus containing at least two data bits and independently driving a pixel of a micro LED, ensures that even if the flash memory interface speed is higher than the modulation capability of a single pixel, the total bandwidth requirement can be met by calculating the minimum number of parallel channels required. This avoids data transmission bottlenecks caused by insufficient channels, and thus allows the use of lower-speed micro LEDs to match high-speed flash memory interfaces, avoiding the use of more expensive high-speed optoelectronic devices. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a module connection diagram of a solid-state storage device according to one embodiment;

[0031] Figure 2 A flowchart illustrating the steps of a bandwidth adaptation method according to one embodiment;

[0032] Figure 3 A flowchart illustrating the steps of a bandwidth adaptation method according to another embodiment.

[0033] Explanation of reference numerals in the attached figures:

[0034] 101. Miniature LED array; 1011. Pixel; 102. NAND flash memory chip; 103. Main control chip. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] It is understood that the terms "first," "second," etc., used in this application may be used to describe various concepts herein, but these elements are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of this application, a first subbus may be referred to as a second subbus, and similarly, a second subbus may be referred to as a first subbus. Both the first subbus and the second subbus are subbuses, but they are not the same subbus.

[0038] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0039] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0041] Existing optical interconnect solutions based on inverse multiplexing demultiplexed high-speed serial electrical data streams bit-by-bit into multiple parallel low-speed signals, each driving a micro-LED. These signals are then transmitted in parallel through multi-core optical fibers and remultiplexed into serial data at the receiving end. This solution addresses the rate matching problem between high-speed serial electrical interfaces and low-speed optical devices, with each splitting unit being a single data bit, and each micro-LED carrying only 1 bit of information. However, in the solid-state storage field, NAND flash memory chips use parallel data bus interfaces (e.g., 8-bit or 16-bit), where data is transmitted simultaneously in parallel. If the aforementioned bit-wise inverse multiplexing solution is directly applied to the NAND flash memory interface, the parallel bus data must first be serialized before bit-wise splitting. This not only introduces additional serial / deserialization delays and power consumption but also disrupts the original bit-width structure of the NAND flash memory parallel interface, requiring the receiving end to re-frame and align, increasing system complexity. Therefore, there is an urgent need in the field for an optical interconnect solution that can directly adapt to the characteristics of the NAND flash memory parallel bus interface.

[0042] This application proposes a solid-state storage device, including: a micro light-emitting diode array 101, a NAND flash memory chip 102, and a main control chip 103.

[0043] The miniature light-emitting diode array 101 contains at least two pixels 1011.

[0044] In this embodiment, each pixel 1011 has an independent anode and cathode, and its emission state is individually controlled by a driving circuit. Pixels 1011 can be arranged in a one-dimensional linear array or a two-dimensional planar array, and the center-to-center spacing between adjacent pixels 1011 can be controlled within the micrometer range to achieve high-density parallel light emission. The emission wavelength of each pixel 1011 can be adjusted according to the material composition, for example, selected in the visible light band or the near-infrared band, to adapt to the response characteristics of different photodetectors.

[0045] At least one NAND flash memory chip 102 has a parallel data bus.

[0046] This embodiment uses at least one NAND flash memory chip 102 as the storage medium. Each NAND flash memory chip 102 has a parallel data bus, such as an 8-bit bus (DQ0-DQ7) or a 16-bit bus (DQ0-DQ15). The parallel data bus is used to transmit multiple bits of data simultaneously between the main control chip 103 and the NAND flash memory chip 102. During the transmission, the data transmission of one flash memory chip needs to be completed by at least two pixels 1011. This correspondence can be set according to the interface rate of the NAND flash memory chip 102 and the modulation rate of the pixels 1011. For example, when the flash interface rate is high, more pixels 1011 can be allocated to it, and vice versa.

[0047] The main control chip 103 is connected to the micro light-emitting diode array 101 and the NAND flash memory chip 102, and is used to split the parallel data bus of each NAND flash memory chip 102 into at least two sets of sub-buses according to the bit width. Each set of sub-buses independently drives one pixel 1011, and each set of sub-buses contains at least two data bits. The main control chip 103 is also used to drive at least two pixels 1011 to emit light simultaneously through the at least two sets of sub-buses.

[0048] The main control chip 103 is the control component of the solid-state storage device, used to perform functions such as data read / write management and error correction, and also to implement the parallel data splitting and optical drive control in this application. The main control chip 103 logically divides the parallel data bus of each NAND flash memory chip 102 into at least two sub-buses, such as a first sub-bus and a second sub-bus. The first sub-bus is electrically connected to the driving circuit of one pixel 1011, and the second sub-bus is electrically connected to the driving circuit of another pixel 1011. The main control chip 103 simultaneously sends enable signals to both driving circuits, causing the two pixels 1011 to emit light. At least two data bits on each sub-bus jointly determine the light emission mode of the corresponding pixel 1011, such as intensity, duration, or pulse sequence, thereby converting data into an optical signal output.

[0049] In some embodiments, when the main control chip 103 is simultaneously connected to two or more NAND flash memory chips 102, each NAND flash memory chip 102 has its own independent parallel data bus and corresponds to at least two pixels 1011. The main control chip 103 independently performs data splitting and bandwidth adaptation for each NAND flash memory chip 102.

[0050] The main control chip is also used to determine the number of sub-bus groups based on the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel.

[0051] The main control chip 103 acquires the interface rate of the NAND flash memory chip 102 and the actual modulation rate of a single pixel 1011 in the micro LED array 101. Since the ratio of the two is not necessarily an integer, in this embodiment, the main control chip 103 determines the number of sub-bus groups based on the result of rounding up the ratio. Then, according to the result, the main control chip 103 divides the parallel data bus of the NAND flash memory chip 102 into a corresponding number of sub-buses. Each sub-bus group contains at least two data bits and drives the same number of pixels 1011 as the number of sub-bus groups to emit light simultaneously.

[0052] This embodiment divides the parallel data of the NAND flash memory chip 102 into multiple sub-buses. Each sub-bus contains at least two data bits and independently drives a pixel 1011 of a micro-LED. This ensures that even if the flash memory interface speed is higher than the modulation capability of a single pixel 1011, the total bandwidth requirement can be met by calculating the minimum number of parallel channels required. This avoids data transmission bottlenecks caused by insufficient channels, allowing lower-speed micro-LEDs to be matched with high-speed flash memory interfaces. This reduces the need for more expensive high-speed optoelectronic devices and avoids negative effects such as reduced yield and excessive heat generation caused by forcibly increasing the speed of micro-LEDs. Furthermore, this embodiment differs from the aforementioned optical interconnect scheme based on inverse multiplexing: in terms of data source, this application processes the parallel data bus data of the NAND flash memory chip, where the data itself is already in parallel form, while the bit-wise scheme processes a serial electrical data stream. Regarding the partitioning method, this application partitions the parallel data bus into multiple sub-buses based on bit width, with each sub-bus containing at least two data bits, preserving the bit width structure of the parallel bus. The bit-wise scheme demultiplexes the serial data bit by bit. In terms of partitioning granularity, this application partitions at the bit group level, while the bit-wise scheme partitions at the bit level. Regarding application scenarios, this application is specifically designed for bandwidth matching between NAND flash memory and MicroLED in solid-state storage devices, while the bit-wise scheme is geared towards general-purpose chip interconnects.

[0053] In another embodiment, at least two data bits in each group of sub-buses are jointly encoded into an optical signal output by the modulation depth, pulse width or pulse sequence of the pixel.

[0054] Each sub-bus is connected to the driving circuit of the corresponding pixel 1011. Taking a sub-bus carrying 4 data bits as an example, it can represent 16 different values, namely 0000 to 1111. The main control chip 103 controls the driving circuit to generate the corresponding driving current magnitude according to the value through the modulation depth method to control the brightness of the pixel, or controls the driving pulse width of the pixel according to the value, or controls the pixel to emit a corresponding number of light pulses within a fixed time window according to the value. The receiving end decodes to obtain the corresponding information according to at least one of the corresponding light intensity, pulse width, or pulse sequence. It is understood that the above encoding method is only an example, and this application is not limited to it. Any modulation means that can encode multiple data bits on the sub-bus into the light emission parameters of a single pixel's light signal is within the protection scope of this application.

[0055] This embodiment encodes multiple data bits into the emission parameters of a single pixel's optical signal, enabling a single emission event of a single pixel to carry multiple data bits. This significantly improves the information transmission efficiency of a single channel, reduces the receiver's need for multi-channel merging, and simplifies system design.

[0056] In another embodiment, the main control chip 103 includes a configurable crossbar switch or lookup table. The main control chip 103 dynamically calculates the number of sub-bus groups based on the detected interface rate of the NAND flash memory chip 102 and the modulation rate of a single pixel 1011, and updates the splitting relationship between the parallel data bus and the sub-bus by configuring the crossbar switch or lookup table.

[0057] The crossbar switch is a configurable hardware switch matrix that allows arbitrary temporary connections between multiple input and output channels through programming, thereby enabling data signal rerouting without altering the physical wiring. In this embodiment, the main control chip 103 detects the current interface rate of the NAND flash memory chip 102 and the actual modulation rate of a single pixel 1011 using on-chip sensors or external instructions. When a change in the interface rate or modulation rate is detected, the main control chip 103 calculates the required number of sub-bus groups based on their ratio. Then, the main control chip 103 automatically updates the original parallel data bus to sub-bus splitting relationship to a splitting method matching the new number of groups by configuring the connection path of the crossbar switch or updating the mapping entries in the lookup table. For example, a device that originally split an 8-bit bus into two groups of 4-bit sub-buses may need to split into four groups of 2-bit sub-buses to match four pixels 1011 when the flash memory interface rate increases. The main control chip 103 can achieve dynamic switching of the splitting method without changing the hardware wiring, simply by reconfiguring the crossbar switch or lookup table. In this way, solid-state storage devices can adapt to changes in operating conditions in real time without needing to be redesigned.

[0058] This embodiment sets up a configurable crossbar switch or lookup table in the main control chip 103, and uses it to dynamically calculate the number of sub-bus groups and update the splitting relationship between the parallel data bus and the sub-bus in real time based on the detected flash memory interface rate and the modulation rate of the pixel 1011. This allows the same hardware platform to flexibly adapt to flash memory chips with different rates and micro LEDs with different modulation capabilities, improving the compatibility and scalability of the device and reducing hardware development costs.

[0059] In another embodiment, the main control chip 103 is also used to make the at least two pixels 1011 emit light simultaneously or emit light in a set timing sequence.

[0060] In this embodiment, the main control chip 103 also includes a timing alignment module, which controls the emission timing of multiple pixels 1011. In one operating mode, the timing alignment module causes all driven pixels 1011 to start emitting light at the same time and maintain the same emission duration, thereby achieving completely simultaneous emission to ensure that multiple optical signals can be received simultaneously at the receiving end. In another operating mode, the timing alignment module can cause each pixel 1011 to emit light sequentially according to a preset delay value, for example, the first pixel 1011 emits light first, and the second pixel 1011 emits light after a certain delay. Different modes can be used to adapt to different processing requirements of the receiving end or to avoid optical signal crosstalk. Through this timing control, high-bandwidth parallel transmission can be achieved, and it can also be adapted to different optical receivers.

[0061] This embodiment enables the simultaneous emission of at least two pixels or their emission according to a set timing sequence, thereby adapting to the synchronization requirements of different receivers, avoiding signal crosstalk, and improving the bandwidth utilization, system compatibility, and anti-interference capability of optical interconnects.

[0062] In another embodiment, the parallel data bus is divided into at least two sets of sub-buses in bit-width order.

[0063] In this embodiment, the main control chip 103 divides the data bits on the parallel data bus according to their physical order, i.e., from low to high or from high to low consecutively. For example, for an 8-bit parallel data bus with data bits DQ0-DQ7, when it is divided into two sub-buses in bit-width order, the lower 4 bits (DQ0, DQ1, DQ2, DQ3) form the first sub-bus, and the higher 4 bits (DQ4, DQ5, DQ6, DQ7) form the second sub-bus. Similarly, if it is divided into four sub-buses, DQ0 and DQ1 form the first group, DQ2 and DQ3 form the second group, DQ4 and DQ5 form the third group, and DQ6 and DQ7 form the fourth group. For a 16-bit bus, when divided into two groups, the lower 8 bits (DQ0-DQ7) form the first sub-bus, and the higher 8 bits (DQ8-DQ15) form the second sub-bus. This method of dividing data sequentially by bit width ensures that the data bits in each sub-bus are physically consecutive.

[0064] This embodiment divides the parallel data bus into at least two sub-buses according to the bit width order, which can keep the data bits in each sub-bus in physical order, thereby simplifying the data mapping logic inside the main control chip 103, eliminating the need for complex address rearrangement or interleaving buffers, and reducing hardware implementation cost and power consumption.

[0065] Those skilled in the art will understand that the “splitting by bit width” is not limited to continuous division in bit width order. Other methods such as odd-even interleaved grouping, custom mapping grouping, or unequal width grouping (e.g., splitting an 8-bit bus into three groups, including two groups of 3-bit sub-buses and one group of 2-bit sub-buses) can also be used. As long as each group of sub-buses contains at least two data bits and all sub-buses cover all parallel data bits, the purpose of this invention can be achieved.

[0066] In another embodiment, the micro-LED array 101 further includes at least one redundant pixel.

[0067] In this case, redundant pixels are in an idle mode in the initial state and do not participate in data transmission.

[0068] The main control chip 103 is also used to monitor the working status of the at least two pixels 1011. When any pixel 1011 fails, the sub-bus corresponding to the pixel 1011 is remapped to the redundant pixel.

[0069] The main control chip 103 also has built-in status monitoring logic. For example, it detects the light emission response of each pixel 1011 before each data transmission. If the main control chip 103 detects that a certain pixel 1011 cannot emit light normally, it determines that the pixel 1011 has failed. At this time, the main control chip 103 disconnects the sub-bus data stream originally allocated to the faulty pixel 1011 from the faulty channel, and then reroutes the sub-bus data stream to the drive channel of the redundant pixel by configuring the internal cross switch or lookup table. Finally, the redundant pixel is enabled so that it emits light according to the original timing of the faulty pixel 1011. Optionally, the detection method can be: loop closure detection, for example, driving pixel 1011 to send an optical signal according to preset data, and the receiving end decodes it after receiving it. If the decoded data is consistent with the preset data, it indicates that pixel 1011 is working normally; drive current monitoring, for example, applying a small test voltage to the pixel and measuring the actual current flowing through the pixel. If the current is close to 0, it indicates that an open circuit fault has occurred. If the current is much higher than the normal value, it indicates that a short circuit fault has occurred; bit error rate monitoring, for example, the receiving end counts the number of received erroneous data bits over a period of time. If it exceeds a preset threshold, it indicates that the bit error rate is too high and pixel 1011 has failed.

[0070] This embodiment, by setting redundant pixels and the remapping function of the main control chip 103, can continue to operate the device without disassembling and replacing the pixel in the event of a failure of a certain pixel 1011, thereby improving reliability and fault tolerance.

[0071] This application also proposes a bandwidth adaptation method, applied to the solid-state storage device described in any of the above embodiments, such as... Figure 2 As shown, the bandwidth adaptation method includes steps 201, 202, and 203.

[0072] Step 201: Detect the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro LED array.

[0073] The interface rate of the NAND flash memory chip 102 can be read from the chip's parameter page or detected by on-chip sensors or external commands. The modulation rate of the pixel 1011 can be determined by on-chip calibration circuitry, referring to the nominal value in the device datasheet, or by self-testing using a photodetector that receives its own emitted light signal. The device can perform the detection of the above parameters once during power-on initialization, or periodically or repeatedly during operation based on preset trigger conditions.

[0074] Step 202: Determine the number of sub-bus groups based on the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro LED array.

[0075] Based on the interface rate and modulation rate detected in the previous step, determine the required number of sub-bus groups. This number of groups should ensure that the product of the modulation rate of a single pixel and the number of groups, i.e., the total bandwidth, is not less than the interface rate.

[0076] Step 203: Configure the data mapping logic of the main control chip so that the data of the NAND flash memory chip is transmitted in parallel through the number of pixels corresponding to the number of sub-bus groups.

[0077] Based on the confirmed number of sub-bus groups, the main control chip 103 divides the parallel data output from the NAND flash memory chip 102 into a number of sub-buses equal to the number of groups, with each sub-bus containing at least two data bits and each sub-bus independently connected to the driving circuit of a pixel 1011. Then, the main control chip 103 simultaneously activates a number of driving channels equal to the number of sub-bus groups, causing the corresponding number of pixels 1011 to emit light. The light signal emitted by each pixel 1011 carries all the data bit information on the corresponding sub-bus. In this way, parallel electrical data is converted into multiple parallel optical signal outputs, with the total transmission bandwidth equal to the product of the number of sub-bus groups and the modulation rate of a single pixel 1011, thus matching or exceeding the interface rate of the NAND flash memory chip 102. If a change in the interface rate or modulation rate is subsequently detected, step 201 can be returned to be re-executed to dynamically adjust the number of sub-bus groups and update the data mapping logic, achieving adaptive bandwidth allocation.

[0078] This embodiment detects the interface rate of the NAND flash memory chip 102 and the modulation rate of a single pixel 1011, determines the number of sub-bus groups based on their ratio, and then configures data mapping logic to enable the number of pixels 1011 corresponding to the number of sub-bus groups to emit light in parallel. This method can be implemented according to products with fixed specifications or adjusted according to changes in conditions, enhancing the compatibility and adaptability of the device.

[0079] In another embodiment, the data mapping logic for configuring the main control chip includes:

[0080] Maintaining the bit width structure of the parallel data bus, the parallel data bus is divided into multiple groups, each group containing at least two consecutive data bits, and the multiple data bits of each group are mapped as a whole to a corresponding pixel.

[0081] In this embodiment, the main control chip 103 processes multiple data bits on each sub-bus as a single set of data. It controls the pixel's luminous intensity by modulating the driving circuit to generate a corresponding driving current, or controls the pixel's driving pulse width based on this value, or controls the pixel to emit a corresponding number of light pulses within a fixed time window based on this value. The receiving end decodes the corresponding information based on at least one of the luminous intensity, pulse width, or pulse sequence. It is understood that the above encoding method is merely an example, and this application is not limited thereto. Any modulation method capable of encoding multiple data bits on a sub-bus into the luminous parameters of a single pixel's light signal is within the scope of protection of this application.

[0082] In this embodiment, the main control chip encodes data of multiple data bits and drives the pixels to emit light in different modes, which enables a single pixel to transmit more than one bit of data, thus improving the efficiency of data transmission.

[0083] In another embodiment, determining the number of sub-bus groups based on the interface rate of the NAND flash memory chip 102 and the modulation rate of a single pixel 1011 in the micro-LED array 101 includes:

[0084] Calculate the ratio of the interface rate of the NAND flash memory chip 102 to the modulation rate of a single pixel 1011, and use this ratio upwards as the number of sub-bus groups.

[0085] In some embodiments, if the interface rate is 2.4Gbps and the modulation rate of a single pixel 1011 is 1.2Gbps, the ratio of the two is 2, and the number of sub-bus groups is 2 after rounding up. If the interface rate is 3.0Gbps and the modulation rate is still 1.2Gbps, the ratio is 2.5, and the number of sub-bus groups is 3 after rounding up. In some other optional embodiments, to satisfy design symmetry, the number of sub-bus groups can also be rounded up to a multiple of 2.

[0086] This embodiment determines the number of sub-bus groups by calculating the ratio of the interface rate to the modulation rate and rounding it up. This allows for precise matching of the bandwidth requirements of the flash memory interface with the minimum number of optical channels. This avoids data congestion caused by insufficient channels and prevents power consumption and hardware waste caused by excess channels, providing a clear quantitative basis for bandwidth adaptation.

[0087] In another embodiment, configuring the data mapping logic of the main control chip 103 includes: step 301, step 302.

[0088] Step 301: Dynamically calculate the number of sub-bus groups based on the detected interface rate of the NAND flash memory chip and the modulation rate of a single pixel.

[0089] Step 302: Update the split relationship between the parallel data bus and the sub-bus by configuring the cross switch or lookup table.

[0090] In this embodiment, the main control chip 103 integrates a configurable crossbar switch or lookup table. The main control chip 103 detects the interface rate of the NAND flash memory chip 102 and the modulation rate of a single pixel 1011 in real time or periodically. When a change in the interface rate or modulation rate is detected, the main control chip 103 dynamically calculates the new number of sub-bus groups again according to the calculation method described in the previous embodiment. Then, the main control chip 103 automatically updates the original parallel data bus to sub-bus splitting relationship to a splitting method that matches the new number of groups by configuring the connection path of the crossbar switch or updating the mapping entries in the lookup table. For example, when the interface rate increases, causing the required number of sub-bus groups to increase from 2 to 4, the main control chip 103 only needs to reconfigure the crossbar switch to split the original 2 groups of 4 bits into 4 groups of 2 bits to complete the adaptation.

[0091] This embodiment improves device compatibility and environmental adaptability by employing a configurable crossbar switch or lookup table and dynamically calculating the number of sub-bus groups based on the detected interface rate and modulation rate, and automatically updating the splitting relationship.

[0092] In another embodiment, the bandwidth adaptation method further includes:

[0093] The pixel 1011 is time-aligned so that the pixel 1011 emits light simultaneously or emits light according to a set timing sequence.

[0094] In this embodiment, in one operating mode, the main control chip 103 controls all pixels 1011 to start emitting light on the same clock edge or triggered by a unified enable signal, and maintains the same light emission duration, thereby enabling multiple pixels 1011 to emit light simultaneously, ensuring that multiple optical signals can be received simultaneously at the receiving end. This mode can guarantee the instantaneous bandwidth during signal transmission and is suitable for scenarios where the receiving end can simultaneously acquire multiple optical signals. In another operating mode, the main control chip 103 causes each pixel 1011 to emit light sequentially according to a preset light emission sequence. For example, the first pixel 1011 emits light first, and the second pixel 1011 emits light after a fixed delay following the first pixel 1011's emission. This mode can avoid crosstalk between different optical signals at the receiving end.

[0095] This embodiment enables at least two pixels 1011 to emit light simultaneously or in a set timing sequence, which can fully utilize the bandwidth superposition characteristics of parallel optical channels, making the total transmission rate equal to the sum of the modulation rates of each pixel 1011. This allows for efficient matching with high-speed flash memory interfaces or flexible adaptation to the synchronization requirements of different receivers, avoiding competition and crosstalk caused by the simultaneous arrival of multiple optical signals, and improving the system's anti-interference capability and compatibility.

[0096] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A solid-state storage device, characterized in that, include: A miniature light-emitting diode array containing at least two pixels; At least one NAND flash memory chip with a parallel data bus; The main control chip is connected to the micro light-emitting diode array and the NAND flash memory chip, and is used to split the parallel data bus of each NAND flash memory chip into at least two sets of sub-buses according to the bit width. Each set of sub-buses independently drives one pixel, and each set of sub-buses contains at least two data bits. The main control chip is also used to drive at least two pixels to emit light simultaneously through the at least two sets of sub-buses. The main control chip is also used to determine the number of sub-bus groups based on the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel.

2. The solid-state storage device according to claim 1, characterized in that, The main control chip includes a configurable crossbar switch or lookup table. The main control chip dynamically calculates the number of sub-bus groups based on the detected interface rate of the NAND flash memory chip and the modulation rate of a single pixel, and updates the splitting relationship between the parallel data bus and the sub-bus by configuring the crossbar switch or lookup table.

3. The solid-state storage device according to claim 1, characterized in that, Each sub-bus contains at least two data bits that are jointly encoded into an optical signal output by the modulation depth, pulse width, or pulse sequence of the pixel.

4. The solid-state storage device according to claim 1, characterized in that, The main control chip is also used to make the at least two pixels emit light simultaneously or emit light in a set timing sequence.

5. The solid-state storage device according to claim 1, characterized in that, The parallel data bus is divided into at least two groups of sub-buses in bit-width order.

6. The device according to claim 1, characterized in that, The micro light-emitting diode array also includes at least one redundant pixel; The main control chip is also used to monitor the working status of the at least two pixels. When any of the pixels fails, the sub-bus corresponding to the pixel is remapped to the redundant pixel.

7. A bandwidth adaptation method, applied to the solid-state storage device according to any one of claims 1 to 6, characterized in that, Includes the following steps: The interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro LED array are detected. The number of sub-bus groups is determined based on the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro-LED array; Configure the data mapping logic of the main control chip so that the data of the NAND flash memory chip is transmitted in parallel through a number of pixels corresponding to the number of sub-bus groups.

8. The method according to claim 7, characterized in that, The data mapping logic for configuring the main control chip includes: Maintaining the bit width structure of the parallel data bus, the parallel data bus is divided into multiple groups, each group containing at least two consecutive data bits, and the multiple data bits of each group are mapped as a whole to a corresponding pixel.

9. The method according to claim 7, characterized in that, The step of determining the number of sub-bus groups based on the interface rate of the NAND flash memory chip and the modulation rate of a single pixel in the micro-LED array includes: Calculate the ratio of the interface rate of the NAND flash memory chip to the modulation rate of a single pixel, and round it up to get the number of sub-bus groups.

10. The bandwidth adaptation method according to claim 9, characterized in that, The data mapping logic for configuring the main control chip includes: The number of sub-bus groups is dynamically calculated based on the detected interface rate of the NAND flash memory chip and the modulation rate of a single pixel. The splitting relationship between the parallel data bus and the sub-bus is updated by configuring a crossbar switch or a lookup table.

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