A method and system for on-chip bus interrupt messaging and wire interrupt reconstruction

Abstract

This application relates to the fields of on-chip system interconnect, bus communication, and interrupt handling technology, and provides a method and system for on-chip bus interrupt message transmission and line interrupt reconstructing. The method involves: acquiring interrupt signals generated by at least one bus component; encapsulating the interrupt signals into bus transmission messages using an interrupt conversion module located near the bus component; routing the transmissions via the on-chip bus based on the identification information in the bus transmission messages; when a bus transmission message carrying an interrupt competes for bus resources with a bus transmission message carrying a normal request, a fair arbitration mechanism is used to schedule the transmissions to a unified interrupt aggregation node; the interrupt aggregation node receives the bus transmission messages, parses them using a message parsing and reconstructing module, and then uniformly outputs all line interrupt signals for use by the target processing unit. This method reduces chip routing complexity and timing convergence difficulty, saving routing resources and chip area.

Description

Technical Field

[0001] This application relates to the fields of system-on-chip interconnection, bus communication and interrupt handling technology, and in particular to a method and system for on-chip bus interrupt message transmission and line interrupt reconfiguration. Background Technology

[0002] In existing system-on-a-chip (SoC) designs, distributed bus components are often directly connected to the interrupt control terminal using independent interrupt lines. As bus size and component count increase, the number of interrupt lines grows rapidly, leading to increased chip routing complexity, higher routing resource consumption, and longer lines across regions, which also increases timing convergence difficulty. When multiple component interrupts converge directly to the same control terminal, a significant fan-out burden is generated, affecting signal integrity and making it difficult to adapt to configurable multi-level bus topologies. Existing message-based interrupt solutions only address routing issues in the transmission stage and are not directly compatible with traditional line interrupt control architectures. They lack a complete processing mechanism for completing interrupt message conversion at the component side and message-to-line interrupt reconstructing at the unified convergence side, making it difficult to simultaneously meet the requirements of scalability, compatibility, and implementation efficiency. Summary of the Invention

[0003] This application provides an on-chip bus interrupt message transmission and line interrupt reconfiguration method and system, which aims to solve the problem that in the existing on-chip system design, the distributed bus components are mostly directly connected to the interrupt control terminal by independent interrupt lines. As the bus scale expands and the number of components increases, the number of interrupt lines grows rapidly, which leads to increased chip routing complexity, increased routing resource consumption, and long cross-region lines also increase the difficulty of timing convergence.

[0004] In a first aspect, embodiments of this application provide a method for on-chip bus interrupt message transmission and line interrupt reconfiguration, the method comprising: The interrupt signal generated by at least one bus component is collected. All bus components are distributed in different physical locations on the chip. The interrupt signal is encapsulated into a bus transmission message by an interrupt conversion module located close to the bus component. The bus transmission message contains source identifier, destination identifier, message type, device type and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The on-chip bus routes the transmission based on the identification information in the bus transmission message. When a bus transmission message carrying an interrupt competes with a bus transmission message carrying a normal request for bus resources, a fair arbitration mechanism is used to schedule the transmission and send it to a unified interrupt aggregation node. The interrupt aggregation node receives bus transmission messages, parses the bus transmission messages through the message parsing and reconstruction module, and obtains the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type. The message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship. The interrupt aggregation node outputs all line interrupt signals to the target processing unit for use.

[0005] In some embodiments, the acquisition of interrupt signals generated by at least one bus component includes: level sampling of the interrupt signal output by each bus component; synchronously acquiring the current state of multiple interrupt signals at a fixed clock cycle; and recording the trigger state of each interrupt signal and the corresponding bus component number.

[0006] In some embodiments, the process of encapsulating the interrupt signal into a bus transmission message by an interrupt conversion module located near the bus component includes: concatenating and combining the collected multi-channel interrupt status information with the corresponding source identifier, target identifier, message type, device type, and interrupt type; generating a single bus transmission message conforming to the bus transmission format; and writing the single bus transmission message into the bus transmission buffer.

[0007] In some embodiments, the routing transmission via the on-chip bus based on the identification information in the bus transmission message includes: reading the target identifier in the bus transmission message; matching the bus routing table to determine the transmission path; and forwarding the bus transmission message hop-by-hop along the determined transmission path until the bus transmission message reaches the bus port corresponding to the interrupt aggregation node.

[0008] In some embodiments, when a bus transmission message carrying an interruption competes with a bus transmission message carrying a normal request for bus resources, the message is scheduled and sent to a unified interrupt aggregation node using a fair arbitration mechanism. This includes: counting the number of all interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent in the current period; allocating bus transmission time slots in sequence according to a preset arbitration quota; and sending various types of bus transmission messages to the next-level bus node in the order of the allocated time slots.

[0009] In some embodiments, the step of receiving bus transmission messages by the interrupt aggregation node and parsing the bus transmission messages through the message parsing and reconstruction module includes: receiving the arriving bus transmission messages by the bus interface of the interrupt aggregation node; performing format verification on the bus transmission messages; and splitting the information content of each segment in the bus transmission messages according to preset field division rules after the verification passes.

[0010] In some embodiments, obtaining the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type includes: extracting four types of information—source identifier, target identifier, device type, and interrupt type—from the split bus transmission message; mapping the extracted four types of information to attribute parameters of the corresponding interrupt channel; and storing the attribute parameters in the interrupt attribute register.

[0011] In some embodiments, the message parsing and reconstruction module reconstructs the bus transmission message into one or more line interrupt signals according to a preset mapping configuration relationship, including: reading a preset mapping configuration table; matching each set of interrupt attribute parameters to the corresponding physical interrupt channel; generating a line interrupt signal with a corresponding valid level according to the interrupt type information; and updating the output status of the corresponding physical interrupt channel.

[0012] In some embodiments, the step of uniformly outputting all line interrupt signals from the interrupt aggregation node to the target processing unit includes: synchronously latching the output states of all physical interrupt channels; outputting all line interrupt signals in parallel through the unified output port of the interrupt aggregation node; and transmitting the output line interrupt signals to the interrupt input port of the target processing unit.

[0013] Secondly, this application provides an on-chip bus interrupt message transmission and line interrupt reconfiguration system, the system comprising: The signal acquisition unit is used to acquire interrupt signals generated by at least one bus component. All bus components are distributed in different physical locations on the chip. The interrupt signal is encapsulated into a bus transmission message by an interrupt conversion module located close to the bus component. The bus transmission message contains source identifier, destination identifier, message type, device type and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The routing transmission unit is used to route transmissions based on the identification information in the bus transmission messages via the on-chip bus. When a bus transmission message carrying an interrupt competes for bus resources with a bus transmission message carrying a normal request, it is scheduled and sent to a unified interrupt aggregation node after using a fair arbitration mechanism. The interrupt usage unit is used to receive bus transmission messages from the interrupt aggregation node, parse the bus transmission messages through the message parsing and reconstruction module to obtain the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type; the message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship; and the interrupt aggregation node outputs all line interrupt signals to the target processing unit for use.

[0014] This application significantly reduces the number of cross-regional physical interrupt lines, thereby lowering chip routing complexity and timing convergence difficulty, and saving routing resources and chip area. By leveraging the native routing capabilities of the on-chip bus through interrupt transmission multiplexing, it adapts to large-scale chip architectures with dispersed bus components, supporting multi-level, configurable bus topologies and improving system scalability. At a unified aggregation node, bus messages are reconstructed into standard line interrupt outputs, directly compatible with traditional line interrupt control architectures, requiring no significant modifications to downstream interrupt handling logic and reducing system integration and adaptation costs. The application employs a division of labor architecture, with component-side message conversion and aggregation-side parsing and reconstruction, improving design modularity, reducing source-end design coupling, and facilitating centralized management of interrupt resources.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic flowchart illustrating the steps of an on-chip bus interrupt message transmission and line interrupt reconfiguration method according to an embodiment of this application; Figure 2 This is a schematic diagram of the overall architecture provided in one embodiment of this application; Figure 3 This is an overall flowchart provided in one embodiment of this application; Figure 4 This is a schematic diagram of interrupt message encapsulation provided in an embodiment of this application; Figure 5 This is a schematic diagram of the output of an interrupt-dedicated conversion module provided in an embodiment of this application; Figure 6 This is a schematic block diagram of an on-chip bus interrupt message transmission and line interrupt reconfiguration system provided in one embodiment of this application; Figure 7 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0021] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0022] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] In existing system-on-a-chip (SoC) designs, distributed bus components are often directly connected to the interrupt control terminal using independent interrupt lines. As bus size and component count increase, the number of interrupt lines grows rapidly, leading to increased chip routing complexity, higher routing resource consumption, and longer lines across regions, which also increases timing convergence difficulty. When multiple component interrupts converge directly to the same control terminal, a significant fan-out burden is generated, affecting signal integrity and making it difficult to adapt to configurable multi-level bus topologies. Existing message-based interrupt solutions only address routing issues in the transmission stage and are not directly compatible with traditional line interrupt control architectures. They lack a complete processing mechanism for completing interrupt message conversion at the component side and message-to-line interrupt reconstructing at the unified convergence side, making it difficult to simultaneously meet the requirements of scalability, compatibility, and implementation efficiency.

[0025] Please refer to Figure 1This application provides an on-chip bus interrupt message transmission and line interrupt reconfiguration method, applied to computer devices. The computer device can be deployed on a single server or server cluster. It can also be deployed on handheld terminals, laptops, wearable devices, or robots, etc. It should be noted that all information involved in the method provided in this application is extracted with the authorization of the relevant user and in accordance with relevant regulations, and will not infringe on user privacy.

[0026] This embodiment provides a method for on-chip bus interrupt message transmission and line interrupt reconstructing, which can be applied to on-chip system and bus interconnection designs of various distributed architectures. It converts the interrupt signals of dispersed bus components into standardized bus transmission messages for cross-region transmission, and restores them as line interrupt signals at a unified node, reducing wiring complexity while maintaining compatibility with traditional interrupt handling systems. (Refer to...) Figure 1 and Figure 3 As shown, this method is divided into three core execution stages: interrupt signal acquisition and message encapsulation, bus arbitration and routing transmission, and convergence parsing and line interrupt reconstruction output, corresponding to steps S101 to S103, which are detailed below: Step S101. Collect interrupt signals generated by at least one bus component. All bus components are distributed in different physical locations on the chip. The interrupt signals are encapsulated into bus transmission messages by an interrupt conversion module located near the bus components. The bus transmission messages contain source identifier, target identifier, message type, device type and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components.

[0027] Specifically, this step is executed in the local area where each bus component is located, and the execution entity is the interrupt conversion module deployed close to each bus component.

[0028] First, the interrupt conversion module acquires interrupt signals generated by at least one bus component. In actual chip deployment, all bus components are distributed across different physical areas of the chip. Each physical area can deploy one or more bus components, and each bus component can generate one or more independent interrupt signals. The interrupt conversion module is physically close to the bus components within the same area, eliminating the need to lay long interrupt lines across areas. It can acquire the interrupt output signals of all local bus components through short-distance connections.

[0029] Subsequently, the interrupt conversion module encapsulates the collected multiple interrupt signals into a single bus transmission message. The bus transmission message adopts a unified standardized format, containing five core information categories: source identifier, destination identifier, message type, device type, and interrupt type. The source identifier identifies the region or module number to which the bus component generating the interrupt belongs; the destination identifier identifies the interrupt aggregation node number to which the interrupt must ultimately be delivered; the message type identifies that the current bus transmission message is an interrupt message, distinguishing it from other types of messages transmitted on the bus, such as normal data requests and responses; the device type identifies the functional category of the bus component generating the interrupt; and the interrupt type identifies the trigger type and validity status of each interrupt. A single bus transmission message can simultaneously carry multiple interrupt information from multiple bus components, completing the synchronous transmission of multiple interrupts with a single message, thus improving the utilization rate of bus transmission resources.

[0030] After encapsulation, the interrupt conversion module sends the generated bus transmission message to the local bus interface, waiting to enter the on-chip bus for transmission.

[0031] Step S102. The on-chip bus is used to route the transmission according to the identification information in the bus transmission message. When the bus transmission message carrying the interrupt competes with the bus transmission message carrying the normal request for bus resources, the message is sent to the unified interrupt aggregation node after scheduling by a fair arbitration mechanism.

[0032] Specifically, this step is executed in the routing nodes at each level of the on-chip bus, relying on the native routing and arbitration capabilities of the on-chip bus to complete the cross-regional transmission of interrupt messages.

[0033] First, the routing nodes of the on-chip bus read the target identifier information from the header of the bus transmission message, query the locally stored bus routing table, and match the optimal transmission path from the current node to the target interrupt aggregation node. The on-chip bus adopts a distributed routing architecture, with multiple routing nodes connected tier by tier to form a complete interconnection network. The bus transmission message starts from the routing node where the source is located and is forwarded hop by hop along the matched transmission path. A route lookup and forwarding operation is performed once at each routing node until the message reaches the bus access port corresponding to the target interrupt aggregation node.

[0034] During transmission, when interrupted bus transmission messages and normal service request transmission messages compete for transmission resources on the same bus port, the arbitration module built into the bus node employs a fair arbitration mechanism to schedule all messages to be sent. This fair arbitration mechanism can be based on preset arbitration quotas, polling priorities, or token passing rules, ensuring that both interrupted and normal request messages receive bus transmission bandwidth according to preset proportions. This prevents one type of message from occupying bus resources for an extended period, causing transmission congestion for the other type. After scheduling, all messages are output sequentially according to their allocated transmission slots and transmitted to the next-level routing node or the final interrupt aggregation node.

[0035] Step S103. The interrupt aggregation node receives the bus transmission message, parses the bus transmission message through the message parsing and reconstruction module, and obtains the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type. The message parsing and reconstruction module reconstructs the bus transmission message into one or more interrupt signals according to the preset mapping configuration relationship. The interrupt aggregation node outputs all line interrupt signals to the outside for use by the target processing unit.

[0036] Specifically, this step is executed on a unified interrupt aggregation node, and the execution entity is the message parsing and reconstruction module deployed inside the interrupt aggregation node.

[0037] First, the interrupt aggregation node receives all delivered bus transmission messages through its own bus interface and sends the messages to the internal message parsing and reconstruction module for processing. The message parsing and reconstruction module first performs format verification on the received bus transmission messages. After confirming that the message format conforms to the preset specification, it splits the message content according to the preset field division rules, extracts all information contained in the message, including source identifier, target identifier, device type, and interrupt type, and converts it into the attribute information of the corresponding interrupt channel.

[0038] Subsequently, the message parsing and reconstruction module reads the preset mapping configuration relationship stored internally. Based on the extracted interrupt attribute information, it matches each interrupt message to the corresponding physical interrupt channel. The preset mapping configuration relationship can be modified through register configuration, supporting flexible adjustment of the correspondence between different source interrupts and output channels to adapt to different system interrupt mapping requirements. After matching is completed, the message parsing and reconstruction module generates a line interrupt signal with a corresponding valid level based on the interrupt type information, updates the output status of the corresponding physical interrupt channel, and completes the reconstruction conversion from bus transmission message to line interrupt signal.

[0039] Finally, after synchronizing the output status of all physical interrupt channels, the interrupt aggregation node outputs all reconstructed line interrupt signals in parallel through a unified output port. The output line interrupt signals are directly connected to the downstream target processing unit, interrupt controller or other interrupt processing logic for downstream modules to perform unified interrupt response and processing.

[0040] In some embodiments, the acquisition of interrupt signals generated by at least one bus component includes: level sampling of the interrupt signal output by each bus component; synchronously acquiring the current state of multiple interrupt signals at a fixed clock cycle; and recording the trigger state of each interrupt signal and the corresponding bus component number.

[0041] First, the interrupt conversion module samples the interrupt signals output by each connected bus component. The input ports of the interrupt conversion module are connected one-to-one with the interrupt output ports of the bus components. Each input port has a built-in level sampling circuit that can recognize various interrupt signal types, including active high, active low, rising edge triggered, and falling edge triggered. The sampling circuit uses the chip's global synchronization clock as a reference to continuously sample the input interrupt signals, eliminating signal glitches and metastability risks, and ensuring stable and reliable sampling results.

[0042] Secondly, the interrupt conversion module synchronously collects the current status of all connected multi-channel interrupt signals at a fixed clock cycle. A full-channel synchronous acquisition operation is performed once per clock cycle. All interrupt states acquired within the same cycle belong to the same time slice, ensuring time consistency of the multi-channel interrupt signals and avoiding state misalignment caused by sampling time differences between different channels. The acquired interrupt states are stored in binary form, corresponding to the triggered or untriggered state of each interrupt.

[0043] Finally, the interrupt conversion module records the trigger status of each interrupt signal and its corresponding bus component number. Each interrupt signal is pre-assigned a unique channel number, which is bound one-to-one with the physical number of the bus component. After data acquisition, the interrupt conversion module associates and stores the interrupt status of each channel with its corresponding channel number, providing an accurate data source for subsequent message encapsulation. For untriggered interrupt channels, their current status is also recorded to ensure that a single message can fully carry the real-time status of all local interrupts.

[0044] In some embodiments, the process of encapsulating the interrupt signal into a bus transmission message by an interrupt conversion module located near the bus component includes: concatenating and combining the collected multi-channel interrupt status information with the corresponding source identifier, target identifier, message type, device type, and interrupt type; generating a single bus transmission message conforming to the bus transmission format; and writing the single bus transmission message into the bus transmission buffer.

[0045] First, the interrupt conversion module concatenates the collected multi-channel interrupt status information with the corresponding source identifier, target identifier, message type, device type, and interrupt type. The concatenation operation is performed according to a preset message field order. The message header sequentially places the target identifier, source identifier, and message type fields, while the message body sequentially places each group of device types and their corresponding interrupt status and interrupt type information. The bit width of each field is pre-fixed and conforms to the bus protocol's message format specifications, ensuring that bus nodes can directly recognize and parse it.

[0046] Secondly, the interrupt conversion module generates a single bus transmission message conforming to the bus transmission format. After concatenation, the module adds a frame start identifier and frame check field as specified by the bus protocol to the beginning and end of the message to form a complete transmittable message frame. A single message can accommodate multiple interrupt information corresponding to multiple devices, eliminating the need to generate a separate message for each interrupt, effectively reducing the number of bus messages and lowering the bus transmission load.

[0047] Finally, the interrupt conversion module writes the generated single bus transmission message into the bus transmit buffer. The transmit buffer adopts a first-in, first-out storage structure, and its depth can be configured according to the bus load. Messages written to the buffer are queued in the order they are written, waiting for scheduling by the bus transmit port. When the buffer is full, packet loss or backpressure processing can be performed according to a preset strategy to ensure the orderly transmission of messages.

[0048] In some embodiments, the routing transmission via the on-chip bus based on the identification information in the bus transmission message includes: reading the target identifier in the bus transmission message; matching the bus routing table to determine the transmission path; and forwarding the bus transmission message hop-by-hop along the determined transmission path until the bus transmission message reaches the bus port corresponding to the interrupt aggregation node.

[0049] First, the bus routing node reads the destination identifier field from the bus transmission message entering the node. After the message enters the input port of the routing node, the node first extracts the destination identifier field from the message header, using it as the key field for routing lookup. The destination identifier is written during message encapsulation and remains unchanged throughout the entire transmission process, serving as the sole addressing basis for message routing.

[0050] Secondly, the bus routing node matches the locally stored bus routing table to determine the next-hop transmission path for the current message. The bus routing table is pre-configured into each routing node through system configuration, and the table stores the mapping relationship between all target node numbers and their corresponding output ports. The routing node matches the extracted target identifier with the routing table entries one by one. If a match is successful, the corresponding output port number is obtained, and the forwarding direction of the message is determined.

[0051] Finally, the bus routing node forwards the bus transmission message hop-by-hop along the determined transmission path. The message is sent from the matched output port to the next-level routing node, which repeats the above-mentioned target identifier reading, routing table matching, and forwarding operations. After hop-by-hop forwarding by multiple levels of routing nodes, the bus transmission message finally reaches the bus access port corresponding to the interrupt aggregation node, completing the entire routing transmission.

[0052] In some embodiments, when a bus transmission message carrying an interruption competes with a bus transmission message carrying a normal request for bus resources, the message is scheduled and sent to a unified interrupt aggregation node using a fair arbitration mechanism. This includes: counting the number of all interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent in the current period; allocating bus transmission time slots in sequence according to a preset arbitration quota; and sending various types of bus transmission messages to the next-level bus node in the order of the allocated time slots.

[0053] First, the bus node counts the number of interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent in the current cycle. Each input port of the bus node corresponds to a receive queue, and messages from all input ports are sent to a unified receive queue group for buffering. The arbitration module scans all receive queues every clock cycle, counts the number of interrupt-type messages and normal request-type messages buffered in the queues, and records the waiting time of each queue.

[0054] Secondly, the arbitration module allocates bus transmission time slots sequentially according to preset arbitration quotas. The preset arbitration quotas can be configured as fixed-ratio quotas, for example, allocating a fixed proportion of transmission bandwidth to interrupt messages and the remaining bandwidth to normal request messages; alternatively, a round-robin quota method can be used, allocating transmission opportunities in turn according to queue order, with each queue able to send one message at a time. The arbitration rules support a combination of constraints such as priority, time order, and node level, allowing the arbitration strategy to be adjusted according to system requirements, ensuring fairness while also considering the transmission needs of different services.

[0055] Finally, the arbitration module sends various bus transmission messages to the next-level bus node in the order of the allocated time slots. Each time a queue is allocated transmission rights, it outputs the head message to the bus transmission port, updates the queue status and quota count after transmission, and enters the next arbitration cycle. Through quota-based arbitration scheduling, both interrupt messages and normal request messages can reliably obtain transmission opportunities, avoiding situations where certain types of messages are blocked for extended periods.

[0056] In some embodiments, the step of receiving bus transmission messages by the interrupt aggregation node and parsing the bus transmission messages through the message parsing and reconstruction module includes: receiving the arriving bus transmission messages by the bus interface of the interrupt aggregation node; performing format verification on the bus transmission messages; and splitting the information content of each segment in the bus transmission messages according to preset field division rules after the verification passes.

[0057] First, the bus interface of the interrupt aggregation node receives the arriving bus transmission messages. The bus interface is directly connected to the end routing node of the on-chip bus and continuously listens for messages on the bus transmission channel. When a message whose target identifier matches its own node number is detected, the message is fully received and sent to the internal message parsing and reconstruction module.

[0058] Secondly, the message parsing and reconstruction module performs format verification on the received bus transmission messages. The verification includes three items: message frame start identifier verification, message length verification, and verification field verification. If the verification fails, the error message is discarded and its status is recorded; if the verification passes, the process proceeds to the subsequent field splitting stage. Format verification filters out error messages generated during transmission, preventing erroneous data from causing anomalies in subsequent reconstruction logic.

[0059] Finally, after successful verification, the message parsing and reconstruction module splits the information content of each segment in the bus transmission message according to the preset field division rules. The splitting rules correspond completely to the field order during source encapsulation, sequentially splitting out all fields such as target identifier, source identifier, message type, device type, interrupt status, and interrupt type, and storing the split field content into the corresponding data register for subsequent attribute extraction.

[0060] In some embodiments, obtaining the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type includes: extracting four types of information—source identifier, target identifier, device type, and interrupt type—from the split bus transmission message; mapping the extracted four types of information to attribute parameters of the corresponding interrupt channel; and storing the attribute parameters in the interrupt attribute register.

[0061] First, the message parsing and reconstruction module extracts four core pieces of information from the split bus transmission messages: source identifier, destination identifier, device type, and interrupt type. The source identifier is used to trace the origin of the interrupt, the destination identifier confirms the correctness of message delivery, the device type distinguishes different functional categories of bus components, and the interrupt type identifies the interrupt's triggering method and valid status.

[0062] Secondly, the message parsing and reconstruction module maps the extracted four types of information to the attribute parameters of the corresponding interrupt channels. Each output physical interrupt channel corresponds to a set of attribute parameters, including channel number, source device, trigger type, and valid level. The module matches the corresponding channel attributes for each interrupt based on the extracted information, completing the conversion from message fields to channel attributes.

[0063] Finally, the message parsing and reconstruction module stores the converted attribute parameters in the interrupt attribute register. Each physical interrupt channel corresponds to an independent set of attribute registers, which can be read by downstream control logic for interrupt tracing, status querying, and system debugging. The interrupt status update operation is triggered synchronously with the attribute parameter update to ensure that the channel output status and attribute information remain consistent.

[0064] In some embodiments, the message parsing and reconstruction module reconstructs the bus transmission message into one or more line interrupt signals according to a preset mapping configuration relationship, including: reading a preset mapping configuration table; matching each set of interrupt attribute parameters to the corresponding physical interrupt channel; generating a line interrupt signal with a corresponding valid level according to the interrupt type information; and updating the output status of the corresponding physical interrupt channel.

[0065] First, the message parsing and reconstruction module reads the preset mapping configuration table stored internally. The preset mapping configuration table stores a one-to-one correspondence between active interrupt identifiers and physical output interrupt channels. The configuration table supports dynamic modification by software, allowing for flexible adjustment of interrupt mapping relationships to adapt to different system interrupt planning requirements.

[0066] Secondly, the message parsing and reconstruction module matches each set of interrupt attribute parameters to the corresponding physical interrupt channel. Based on the entries in the mapping configuration table, interrupt information from different sources and different devices is mapped to the specified physical output channels. This supports mapping multiple source interrupts to the same output channel, as well as mapping one source interrupt to multiple output channels, meeting different interrupt aggregation and distribution needs.

[0067] Finally, the message parsing and reconstruction module generates a line interrupt signal with the corresponding valid level based on the interrupt type information. For level-type interrupts, it directly outputs the corresponding high or low level according to the interrupt status; for pulse-type interrupts, it generates a pulse signal of a specified width according to the interrupt trigger status. The signal level standard is fully compatible with the input standard of the downstream interrupt processing module, requiring no additional level conversion circuitry.

[0068] Simultaneously, the message parsing and reconstruction module updates the output status of the corresponding physical interrupt channel. The channel output status update adopts a synchronous update method, with the output status of all channels being refreshed synchronously on the same clock edge to avoid timing deviations between different channels.

[0069] In some embodiments, the step of uniformly outputting all line interrupt signals from the interrupt aggregation node to the target processing unit includes: synchronously latching the output states of all physical interrupt channels; outputting all line interrupt signals in parallel through the unified output port of the interrupt aggregation node; and transmitting the output line interrupt signals to the interrupt input port of the target processing unit.

[0070] First, the interrupt aggregation node synchronously latches the output states of all physical interrupt channels. Before being output, the output signals of all channels are latched by a synchronization register, using the global system clock as the synchronization reference. This eliminates glitches and timing deviations caused by combinational logic, ensuring the stability and synchronization of the output signals.

[0071] Secondly, the interrupt aggregation node outputs all line interrupt signals in parallel through a unified output port. The unified output port contains multiple parallel interrupt output pins, all of which are centrally located in the interface area of ​​the interrupt aggregation node, forming a standardized interrupt output interface that facilitates connection with downstream interrupt controllers or processors.

[0072] Finally, the interrupt aggregation node transmits the output line interrupt signal to the interrupt input port of the target processing unit. The output line interrupt signal retains the signal characteristics of a traditional line interrupt, and the downstream target processing unit and interrupt controller can directly respond according to the original line interrupt processing method without modifying the internal interrupt processing logic, achieving seamless compatibility with the traditional interrupt system.

[0073] In some embodiments, refer to Figure 2 As shown, the entire system comprises multiple interrupt translation modules, multi-level routing nodes, an interrupt parsing module, and downstream interrupt controllers or processors. The multiple interrupt translation modules are distributed across different physical regions of the chip, each connected to one or more local bus components, receiving interrupt input signals from these components. All routing nodes are interconnected via bus links, forming a distributed on-chip interconnect network. The interrupt parsing module is deployed at a unified interrupt aggregation node, serving as the final receiving and reconstructing processing unit for all interrupt messages.

[0074] Reference Figure 4 As shown, the bus transmission message adopts a fixed-width format design. The message, from least significant bit to most significant bit, sequentially includes the target identifier, source identifier, message type, first group of device types, first group of interrupt information, second group of device types, and second group of interrupt information fields. Each field occupies a fixed bit width. The target identifier and source identifier are used for routing, the message type distinguishes interrupt messages from other bus messages, the device type identifies the component category that generated the interrupt, and the interrupt information field carries the specific interrupt status and interrupt type information. A single message can carry multiple interrupt information corresponding to multiple devices, enabling the packetized transmission of multiple interrupts.

[0075] The complete system workflow includes: First, each bus component distributed in different areas generates an interrupt signal. The interrupt conversion module in the corresponding area collects the interrupt input signals of all local bus components and then... Figure 4 The message format shown encapsulates multiple interrupt messages into a single bus transmission message. After encapsulation, the interrupt translation module sends the message to the first-level routing node of the local connection.

[0076] Subsequently, the bus transmission messages enter the on-chip bus network composed of multi-level routing nodes. Each level of routing node contains... Figure 5 The arbitration structure shown includes multiple source node input queues, a receive queue group, an arbitration module, and a bus routing output module. Interrupt messages and normal service messages from different source nodes enter different receive queues. The arbitration module schedules all queues according to preset arbitration rules and allocates bus transmission bandwidth according to quotas. After scheduling, the messages are forwarded to the next-level routing node through the bus routing module. After multi-level hop-by-hop transmission, all interrupt messages are finally delivered to the interrupt aggregation node equipped with an interrupt parsing module.

[0077] Next, the interrupt parsing module of the interrupt aggregation node receives all arriving bus transmission messages, verifies and splits the messages, and extracts the attribute information of each interrupt. Based on the internally preset mapping configuration, the module matches each interrupt information to the corresponding physical output channel, generates the corresponding line interrupt level signal, and completes the reconstruction conversion from message to line interrupt.

[0078] Finally, the interrupt parsing module outputs all reconstructed line interrupt signals in parallel through a unified interrupt output port. The output interrupt signals are directly sent to the downstream interrupt controller or processor, where the interrupt controller or processor performs unified interrupt priority arbitration, response, and processing.

[0079] Through the above architecture and process, bus component interrupts distributed in different areas of the chip do not need to be laid out separately across regions. Interrupt transmission can be completed by simply reusing existing bus resources. At the same time, the interrupt is restored to a standard line interrupt output at the aggregation end. This reduces wiring complexity, improves system scalability, and is fully compatible with the traditional line interrupt handling system.

[0080] Please see Figure 6 As shown, Figure 6This is a schematic diagram of the structure of the on-chip bus interrupt message transmission and line interrupt reconfiguration system 200 provided in this application embodiment. The on-chip bus interrupt message transmission and line interrupt reconfiguration system 200 is used to execute the steps of the on-chip bus interrupt message transmission and line interrupt reconfiguration methods shown in the above embodiments. The on-chip bus interrupt message transmission and line interrupt reconfiguration system 200 can be a single server or a server cluster, or it can be a terminal, such as a handheld terminal, a laptop computer, a wearable device, or a robot.

[0081] like Figure 6 As shown, the on-chip bus interrupt message transmission and line interrupt reconfiguration system 200 includes: The signal acquisition unit 201 is used to acquire interrupt signals generated by at least one bus component. All bus components are distributed in different physical locations on the chip. The interrupt signal is encapsulated into a bus transmission message by an interrupt conversion module located close to the bus component. The bus transmission message contains source identifier, target identifier, message type, device type and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The routing transmission unit 202 is used to perform routing transmission based on the identification information in the bus transmission message through the on-chip bus. When the bus transmission message carrying the interrupt competes with the bus transmission message carrying the normal request for bus resources, it is scheduled to be sent to the unified interrupt aggregation node after using a fair arbitration mechanism. Interrupt usage unit 203 is used to receive bus transmission messages from the interrupt aggregation node, parse the bus transmission messages through the message parsing and reconstruction module to obtain interrupt attribute information corresponding to the source identifier, target identifier, device type and interrupt type; the message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship; and the interrupt aggregation node outputs all line interrupt signals to the outside for use by the target processing unit.

[0082] In some embodiments, the acquisition of interrupt signals generated by at least one bus component includes: level sampling of the interrupt signal output by each bus component; synchronously acquiring the current state of multiple interrupt signals at a fixed clock cycle; and recording the trigger state of each interrupt signal and the corresponding bus component number.

[0083] In some embodiments, the process of encapsulating the interrupt signal into a bus transmission message by an interrupt conversion module located near the bus component includes: concatenating and combining the collected multi-channel interrupt status information with the corresponding source identifier, target identifier, message type, device type, and interrupt type; generating a single bus transmission message conforming to the bus transmission format; and writing the single bus transmission message into the bus transmission buffer.

[0084] In some embodiments, the routing transmission via the on-chip bus based on the identification information in the bus transmission message includes: reading the target identifier in the bus transmission message; matching the bus routing table to determine the transmission path; and forwarding the bus transmission message hop-by-hop along the determined transmission path until the bus transmission message reaches the bus port corresponding to the interrupt aggregation node.

[0085] In some embodiments, when a bus transmission message carrying an interruption competes with a bus transmission message carrying a normal request for bus resources, the message is scheduled and sent to a unified interrupt aggregation node using a fair arbitration mechanism. This includes: counting the number of all interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent in the current period; allocating bus transmission time slots in sequence according to a preset arbitration quota; and sending various types of bus transmission messages to the next-level bus node in the order of the allocated time slots.

[0086] In some embodiments, the step of receiving bus transmission messages by the interrupt aggregation node and parsing the bus transmission messages through the message parsing and reconstruction module includes: receiving the arriving bus transmission messages by the bus interface of the interrupt aggregation node; performing format verification on the bus transmission messages; and splitting the information content of each segment in the bus transmission messages according to preset field division rules after the verification passes.

[0087] In some embodiments, obtaining the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type includes: extracting four types of information—source identifier, target identifier, device type, and interrupt type—from the split bus transmission message; mapping the extracted four types of information to attribute parameters of the corresponding interrupt channel; and storing the attribute parameters in the interrupt attribute register.

[0088] In some embodiments, the message parsing and reconstruction module reconstructs the bus transmission message into one or more line interrupt signals according to a preset mapping configuration relationship, including: reading a preset mapping configuration table; matching each set of interrupt attribute parameters to the corresponding physical interrupt channel; generating a line interrupt signal with a corresponding valid level according to the interrupt type information; and updating the output status of the corresponding physical interrupt channel.

[0089] In some embodiments, the step of uniformly outputting all line interrupt signals from the interrupt aggregation node to the target processing unit includes: synchronously latching the output states of all physical interrupt channels; outputting all line interrupt signals in parallel through the unified output port of the interrupt aggregation node; and transmitting the output line interrupt signals to the interrupt input port of the target processing unit.

[0090] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the on-chip bus interrupt message transmission and line interrupt reconfiguration system and its modules described above can be referred to the corresponding content in the various embodiments of the on-chip bus interrupt message transmission and line interrupt reconfiguration method, and will not be repeated here.

[0091] The above-described on-chip bus interrupt message transmission and line interrupt reconfiguration method can be implemented as a computer program, which can be used in, for example... Figure 6 It runs on the system shown.

[0092] Please see Figure 7 , Figure 7 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application. The computer device includes a processor, a memory, and a network interface connected via a device bus, wherein the memory may include a storage medium and internal memory.

[0093] The storage medium can store operating devices and computer programs. The computer program includes program instructions that, when executed, cause the processor to perform any on-chip bus interrupt message transmission and line interrupt reconfiguration method.

[0094] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0095] Internal memory provides an environment for the execution of computer programs stored in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to perform any on-chip bus interrupt message transmission and line interrupt reconfiguration method.

[0096] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the terminal to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0097] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0098] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: The interrupt signal generated by at least one bus component is collected. All bus components are distributed in different physical locations on the chip. The interrupt signal is encapsulated into a bus transmission message by an interrupt conversion module located close to the bus component. The bus transmission message contains source identifier, destination identifier, message type, device type and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The on-chip bus routes the transmission based on the identification information in the bus transmission message. When a bus transmission message carrying an interrupt competes with a bus transmission message carrying a normal request for bus resources, a fair arbitration mechanism is used to schedule the transmission and send it to a unified interrupt aggregation node. The interrupt aggregation node receives bus transmission messages, parses the bus transmission messages through the message parsing and reconstruction module, and obtains the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type. The message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship. The interrupt aggregation node outputs all line interrupt signals to the target processing unit for use.

[0099] In some embodiments, the acquisition of interrupt signals generated by at least one bus component includes: level sampling of the interrupt signal output by each bus component; synchronously acquiring the current state of multiple interrupt signals at a fixed clock cycle; and recording the trigger state of each interrupt signal and the corresponding bus component number.

[0100] In some embodiments, the process of encapsulating the interrupt signal into a bus transmission message by an interrupt conversion module located near the bus component includes: concatenating and combining the collected multi-channel interrupt status information with the corresponding source identifier, target identifier, message type, device type, and interrupt type; generating a single bus transmission message conforming to the bus transmission format; and writing the single bus transmission message into the bus transmission buffer.

[0101] In some embodiments, the routing transmission via the on-chip bus based on the identification information in the bus transmission message includes: reading the target identifier in the bus transmission message; matching the bus routing table to determine the transmission path; and forwarding the bus transmission message hop-by-hop along the determined transmission path until the bus transmission message reaches the bus port corresponding to the interrupt aggregation node.

[0102] In some embodiments, when a bus transmission message carrying an interruption competes with a bus transmission message carrying a normal request for bus resources, the message is scheduled and sent to a unified interrupt aggregation node using a fair arbitration mechanism. This includes: counting the number of all interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent in the current period; allocating bus transmission time slots in sequence according to a preset arbitration quota; and sending various types of bus transmission messages to the next-level bus node in the order of the allocated time slots.

[0103] In some embodiments, the step of receiving bus transmission messages by the interrupt aggregation node and parsing the bus transmission messages through the message parsing and reconstruction module includes: receiving the arriving bus transmission messages by the bus interface of the interrupt aggregation node; performing format verification on the bus transmission messages; and splitting the information content of each segment in the bus transmission messages according to preset field division rules after the verification passes.

[0104] In some embodiments, obtaining the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type includes: extracting four types of information—source identifier, target identifier, device type, and interrupt type—from the split bus transmission message; mapping the extracted four types of information to attribute parameters of the corresponding interrupt channel; and storing the attribute parameters in the interrupt attribute register.

[0105] In some embodiments, the message parsing and reconstruction module reconstructs the bus transmission message into one or more line interrupt signals according to a preset mapping configuration relationship, including: reading a preset mapping configuration table; matching each set of interrupt attribute parameters to the corresponding physical interrupt channel; generating a line interrupt signal with a corresponding valid level according to the interrupt type information; and updating the output status of the corresponding physical interrupt channel.

[0106] In some embodiments, the step of uniformly outputting all line interrupt signals from the interrupt aggregation node to the target processing unit includes: synchronously latching the output states of all physical interrupt channels; outputting all line interrupt signals in parallel through the unified output port of the interrupt aggregation node; and transmitting the output line interrupt signals to the interrupt input port of the target processing unit.

[0107] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the steps of the on-chip bus interrupt message transmission and line interrupt reconfiguration method provided in any embodiment of this application.

[0108] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for on-chip bus interrupt message transmission and line interrupt reconfiguration, characterized in that, include: At least one bus component generates an interrupt signal, and all bus components are distributed at different physical locations on the chip. Interrupt signals are encapsulated into bus transmission messages by an interrupt conversion module located near the bus components. The bus transmission message contains source identifier, destination identifier, message type, device type, and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The on-chip bus routes the transmission based on the identification information in the bus transmission message. When a bus transmission message carrying an interrupt competes with a bus transmission message carrying a normal request for bus resources, a fair arbitration mechanism is used to schedule the transmission and send it to a unified interrupt aggregation node. The interrupt aggregation node receives bus transmission messages, parses the bus transmission messages through the message parsing and reconstruction module, and obtains the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type. The message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship. The interrupt aggregation node outputs all line interrupt signals to the target processing unit for use.

2. The method according to claim 1, characterized in that, The acquisition of interrupt signals generated by at least one bus component includes: Level sampling is performed on the interrupt signal output by each bus component; The current status of multiple interrupt signals is synchronously acquired according to a fixed clock cycle; Record the trigger status of each interrupt signal and its corresponding bus component number.

3. The method according to claim 1, characterized in that, The interrupt conversion module, located near the bus component, encapsulates the interrupt signal into a bus transmission message, including: The collected multi-channel interrupt status information is combined with the corresponding source identifier, target identifier, message type, device type, and interrupt type. Generate a single bus transmission message conforming to the bus transmission format; write the single bus transmission message into the bus transmit buffer.

4. The method according to claim 1, characterized in that, The routing transmission via the on-chip bus based on the identification information in the bus transmission message includes: Read the target identifier from the bus transmission message; The transmission path is determined by matching the bus routing table. The bus transmission message is forwarded hop-by-hop along the defined transmission path until it reaches the bus port corresponding to the interrupt aggregation node.

5. The method according to claim 4, characterized in that, When a bus transmission message carrying an interruption competes for bus resources with a bus transmission message carrying a normal request, a fair arbitration mechanism is used to schedule the transmission and send it to a unified interrupt aggregation node, including: Count the number of all interrupt-type bus transmission messages and normal request-type bus transmission messages to be sent within the current period; Bus transmission time slots are allocated sequentially according to the preset arbitration quota; The various bus transmission messages are sent to the next-level bus node in the order of the allocated time slots.

6. The method according to claim 1, characterized in that, The process of receiving bus transmission messages by the interrupt aggregation node and parsing the bus transmission messages through the message parsing and reconstruction module includes: The bus transmission message is received by the bus interface of the interrupt aggregation node; the format of the bus transmission message is validated; after the validation is passed, the information content of each segment in the bus transmission message is split according to the preset field division rules.

7. The method according to claim 1, characterized in that, The process of obtaining the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type includes: Extract four types of information from the split bus transmission message: source identifier, destination identifier, device type, and interrupt type; map the extracted four types of information to the attribute parameters of the corresponding interrupt channel; and store the attribute parameters in the interrupt attribute register.

8. The method according to claim 1, characterized in that, The message parsing and reconstruction module reconstructs bus transmission messages into one or more interrupt signals according to a preset mapping configuration relationship, including: Read the preset mapping configuration table; match each set of interrupt attribute parameters to the corresponding physical interrupt channel; generate a line interrupt signal with the corresponding valid level according to the interrupt type information; update the output status of the corresponding physical interrupt channel.

9. The method according to claim 1, characterized in that, The process of uniformly outputting all line interrupt signals from the interrupt aggregation node to the target processing unit for use includes: Synchronously latch the output states of all physical interrupt channels; All line interrupt signals are output in parallel through the unified output port of the interrupt aggregation node; The output line interrupt signal is transmitted to the interrupt input port of the target processing unit.

10. An on-chip bus interrupt message transmission and line interrupt reconfiguration system, used to implement the method as described in any one of claims 1-9, characterized in that, include: The signal acquisition unit is used to acquire interrupt signals generated by at least one bus component, and all bus components are distributed in different physical locations on the chip. Interrupt signals are encapsulated into bus transmission messages by an interrupt conversion module located near the bus components. The bus transmission message contains source identifier, destination identifier, message type, device type, and interrupt type information. A single bus transmission message is used to transmit multiple interrupt information from multiple bus components. The routing transmission unit is used to route transmissions based on the identification information in the bus transmission messages via the on-chip bus. When a bus transmission message carrying an interrupt competes for bus resources with a bus transmission message carrying a normal request, it is scheduled and sent to a unified interrupt aggregation node after using a fair arbitration mechanism. The interrupt usage unit is used to receive bus transmission messages from the interrupt aggregation node, parse the bus transmission messages through the message parsing and reconstruction module to obtain the interrupt attribute information corresponding to the source identifier, target identifier, device type, and interrupt type; the message parsing and reconstruction module reconstructs the bus transmission messages into one or more interrupt signals according to the preset mapping configuration relationship; and the interrupt aggregation node outputs all line interrupt signals to the target processing unit for use.

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