Multi-protocol compatible data interaction adaptation method and system for memory

Abstract

This invention relates to the field of memory chip bus interconnect technology and discloses a method and system for adapting multi-protocol compatible data interaction in memory. The method includes: parsing memory access requests from the master control logic chip, extracting the target chip identifier and core semantic fields; mapping the core semantic fields to a general flow control unit (GCU) that is independent of protocol attributes, wherein the GCU includes a dynamic bit-width bypass segment; statistically analyzing the rate of change in request density and adjusting the real-time credit count accordingly to obtain an equivalent dynamic credit value; when the equivalent dynamic credit value meets a threshold, extracting the intrinsic interface bit width of the target memory chip within the physical layer sampling period, and reconstructing the bit width of the GCU to obtain the target physical cell. This invention, through the combination of a GCU and a physical boundary delay reorganization mechanism, eliminates the static buffer overhead generated by adapting to heterogeneous protocols, releases the chip coastline area, and ensures the timing determinism of memory consistency in heterogeneous systems.

Description

Technical Field

[0001] This invention relates to a multi-protocol compatible data interaction adaptation method and system for memory, belonging to the field of chip bus interconnect technology. Background Technology

[0002] In the current advanced packaging architecture of high-performance computing and artificial intelligence processors, logic chips and storage chips are heterogeneously integrated through 2.5D or 3D stacking technology. In order to support high-bandwidth data flow between logic chips and multiple storage chips, establishing an interconnect bus architecture between chips has become a necessary path to ensure the throughput of computing systems. Such interconnect buses usually adopt a layered protocol architecture, using the vertical collaboration of the transaction layer, data link layer and physical layer to ensure the complete transmission of data, and cooperating with the credit flow control mechanism at the physical layer boundary to maintain the stability of the link.

[0003] Besides the aforementioned physical evolution at the hardware level, the adaptation efficiency of interconnect control logic is also a key factor restricting system real-time performance. For example, Chinese invention patent application CN119025453A discloses a chip and chip system that achieves encapsulation conversion of the internal bus to the standard interconnect protocol by constructing specific transport layer protocol packet assembly logic between the AXI bus and the UCIe link. With the evolution of memory technology, logic chips need to be able to adapt to multiple heterogeneous memory protocols simultaneously. The current common practice is to independently deploy a complete set of bridging units and dedicated asynchronous cache queues for each memory protocol within the logic chip, forming a parallel adaptation structure based on static hierarchical coupling. This architecture requires that data complete protocol unpacking and packet conversion be completed within the logic chip before crossing the physical layer boundary. This parallel... In engineering practice, the adaptation structure faces significant physical constraints. Because the multi-protocol bridging units use hard-wired logic and each occupies an independent static buffer pool, a large amount of silicon wafer coastline area at the edge of the logic chip is consumed. At the same time, the asymmetry of latency between different protocol conversion paths can cause a lack of determinism in the data flow process. Under ultra-high bandwidth pressure, latency jitter is easily generated, which in turn violates the memory consistency timing requirements of heterogeneous computing systems. The industry has tried to compensate for the conversion latency by increasing the bus width or increasing the interface clock frequency, but such linear improvement schemes cannot avoid the intrinsic latency caused by static protocol stack coupling, and blindly expanding the width will exacerbate the difficulty of wiring congestion and physical layer alignment. Existing technical solutions have irreconcilable structural contradictions between multi-protocol compatibility, interface area efficiency, and transmission determinism.

[0004] Therefore, how to eliminate hardware redundancy and latency jitter caused by multi-protocol adaptation by reconstructing the bus interaction logic, and achieve low-latency transmission and area optimization in a high-density integrated environment, has become the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A multi-protocol compatible data interaction adaptation method for a memory, comprising the following steps: Step S1: Parse the original transaction layer request output by the main control logic core and extract the target core identifier and core semantic fields; Step S2: Based on the mapping relationship between the core semantic fields and the general transmission format, the core semantic fields are mapped to a general flow control unit sequence that is independent of the specific physical protocol header attributes. The general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions. Step S3: Obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and determine the current available physical cell balance; Step S4: Calculate the request distribution density of the corresponding target core identifier within the preset time window and calculate the rate of change of the request distribution density over time. Determine the pre-judgment deduction parameter based on the rate of change and offset the current available physical cell balance to obtain the equivalent dynamic credit amount. Step S5: Within the sampling period when the equivalent dynamic credit volume meets the release threshold and the general flow control unit sequence crosses the physical layer boundary, extract the intrinsic interface bit width parameter of the target storage chip, and perform bit width reorganization on the general flow control unit sequence according to the intrinsic interface bit width parameter to obtain the target physical cell aligned with the intrinsic interface bit width parameter. At the same time, calculate the effective bandwidth conversion rate according to the product relationship between the effective payload bits of the general flow control unit sequence and the intrinsic interface bit width parameter. Step S6: Drive the physical layer interface to output the target physical cell.

[0006] Preferably, step S4 further includes: step S41, monitoring the credit increment pulse signal fed back by the target storage chip; step S42, calculating the instantaneous throughput gradient of the original transaction layer request according to the preset sliding window period, and defining the instantaneous throughput gradient as the rate of change.

[0007] Preferably, in step S4, the calculation rule for the equivalent dynamic credit amount follows the following relationship: ,in, This is the equivalent dynamic credit volume. This represents the current available physical cell reserve. This is the cumulative value of the credit increment pulse signal. For the rate of change, As a credit compensation factor, This represents the congestion prediction coefficient.

[0008] Preferably, the step of reassembling the general flow control unit sequence in step S5 includes: step S51, using combinational logic circuits to compare the original bit width of the general flow control unit sequence with the intrinsic interface bit width parameter to determine the number of bit width overflow bits; step S52, when the original bit width is greater than the intrinsic interface bit width parameter, splitting the general flow control unit sequence into a multi-step timing sequence output; step S53, when the original bit width is less than the intrinsic interface bit width parameter, filling the end of the frame of the target physical cell with a protocol-defined idle symbol sequence up to the clock edge of the aligned sampling period.

[0009] Preferably, step S2 further includes: step S21, matching private instruction fields in the core semantic field that are incompatible with the standard memory access protocol; step S22, determining the number of placeholder bits for the private instruction field, and adjusting the bit width of the bypass transparent segment to adapt to the private instruction field.

[0010] Preferably, after step S6, the method further includes: step S71, extracting a response flow control unit containing response semantics from the data stream fed back by the target storage chip; step S72, sending the data back to the corresponding cache address of the master control logic chip according to the address routing field in the response flow control unit.

[0011] Preferably, in step S5, the frequency range of the sampling period is set to 1 GHz to 4 GHz, and the trigger time of the sampling period lags behind the system clock edge of the chip interconnect system by 10 ps to 50 ps.

[0012] Preferably, in step S3, the credit status data is transmitted back in real time via physical layer sideband signals.

[0013] Preferably, the original transaction layer request includes a memory access request based on a general computing fast link protocol or a memory access request based on a cache coherence protocol. In step S5, a general flow control unit sequence is mapped by an unbuffered combinational logic array composed of multiplexers, so that the logic delay from parsing to output is constant at 3 to 5 clock cycles.

[0014] A multi-protocol compatible data interaction adaptation system for a memory, comprising: The parsing unit is used to parse the original transaction layer requests output by the main control logic core and extract the target core identifier and core semantic fields; The protocol conversion unit is used to map the core semantic fields into a general flow control unit sequence that is independent of the specific physical protocol header attributes, based on the mapping relationship between the core semantic fields and the general transmission format; wherein, the general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions; The credit monitoring unit is used to obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and to determine the current available physical cell balance. The congestion control unit is used to count the request distribution density of the corresponding target core identifier within a preset time window and calculate the rate of change of the request distribution density over time. Based on the rate of change, it determines the pre-judgment deduction parameter and offsets the current available physical cell balance to obtain an equivalent dynamic credit amount. The bit-width reassembly unit is used to extract the intrinsic interface bit-width parameters of the target memory chip within a sampling period when the equivalent dynamic credit meets the release threshold and the general flow control unit sequence crosses the physical layer boundary. It then performs bit-width reassembly on the general flow control unit sequence based on the intrinsic interface bit-width parameters to obtain the target physical cell aligned with the intrinsic interface bit-width parameters. The bit-width reassembly unit is also used to calculate the effective bandwidth conversion rate based on the product relationship between the payload bits of the general flow control unit sequence and the intrinsic interface bit-width parameters. The physical layer communication interface is used to output target physical cells.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In the multi-protocol compatible data interaction adaptation of memory, a general microchip structure is adopted in conjunction with a delayed reorganization mechanism at the physical boundary. By stripping the attributes of specific physical protocols at the transaction layer, the processing path of multi-protocol data is logically normalized. This mechanism avoids instantiating a complete set of static state machines and dedicated asynchronous cache queues for each target storage protocol inside the logical chip, reducing the size of the logic gate array at the interface, thereby releasing valuable chip physical coastline resources.

[0016] 2. By placing the protocol-specific conversion action limit within the sampling period of the physical layer clock boundary, the incompressible serial hard delay during cross-protocol conversion is eliminated. Instantaneous bit width pruning and boundary alignment are performed through pure combinational logic. The data stream maintains absolute determinism of end-to-end latency when crossing physical boundaries, solving the latency jitter problem caused by different protocol stack thicknesses when accessing heterogeneous storage, and ensuring the memory consistency requirements of heterogeneous computing systems.

[0017] 3. By deeply coupling the real-time credit feedback value with the time derivative of the request distribution density, a flow control closed loop with predictive capabilities is constructed. When the system detects a sudden memory access request, this mechanism actively adjusts the equivalent dynamic credit amount, pushing potential congestion back to the transaction layer's general queue. This cross-level dynamic collaboration avoids the risk of link deadlock caused by physical layer cache overflow without relying on a complex flow control state machine, thus enhancing the operational stability of the ultra-high density core-particle integrated system. Attached Figure Description

[0018] Figure 1This is a flowchart of the heterogeneous storage protocol interaction adaptation and bit width reconstruction method of the present invention; Figure 2 This is a diagram of the multi-protocol adaptation system architecture of the chip interconnect plane of the present invention.

[0019] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A method for adapting multi-protocol compatible data interaction in a memory includes the following steps: Step S1: Parse the original transaction layer request output by the main control logic core and extract the target core identifier and core semantic fields; Step S2: Based on the mapping relationship between the core semantic fields and the general transmission format, the core semantic fields are mapped to a general flow control unit sequence that is independent of the specific physical protocol header attributes. The general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions. Step S3: Obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and determine the current available physical cell balance; Step S4: Calculate the request distribution density of the corresponding target core identifier within the preset time window and calculate the rate of change of the request distribution density over time. Determine the pre-judgment deduction parameter based on the rate of change and offset the current available physical cell balance to obtain the equivalent dynamic credit amount. Step S5: Within the sampling period when the equivalent dynamic credit volume meets the release threshold and the general flow control unit sequence crosses the physical layer boundary, extract the intrinsic interface bit width parameter of the target storage chip, and perform bit width reorganization on the general flow control unit sequence according to the intrinsic interface bit width parameter to obtain the target physical cell aligned with the intrinsic interface bit width parameter. At the same time, calculate the effective bandwidth conversion rate according to the product relationship between the effective payload bits of the general flow control unit sequence and the intrinsic interface bit width parameter. Step S6: Drive the physical layer interface to output the target physical cell.

[0022] Preferably, step S4 further includes: step S41, monitoring the credit increment pulse signal fed back by the target storage chip; step S42, calculating the instantaneous throughput gradient of the original transaction layer request according to the preset sliding window period, and defining the instantaneous throughput gradient as the rate of change.

[0023] Preferably, in step S4, the calculation rule for the equivalent dynamic credit amount follows the following relationship: ,in, This is the equivalent dynamic credit volume. This represents the current available physical cell reserve. This is the cumulative value of the credit increment pulse signal. For the rate of change, As a credit compensation factor, This represents the congestion prediction coefficient.

[0024] Preferably, the step of reassembling the general flow control unit sequence in step S5 includes: step S51, using combinational logic circuits to compare the original bit width of the general flow control unit sequence with the intrinsic interface bit width parameter to determine the number of bit width overflow bits; step S52, when the original bit width is greater than the intrinsic interface bit width parameter, splitting the general flow control unit sequence into a multi-step timing sequence output; step S53, when the original bit width is less than the intrinsic interface bit width parameter, filling the end of the frame of the target physical cell with a protocol-defined idle symbol sequence up to the clock edge of the aligned sampling period.

[0025] Preferably, step S2 further includes: step S21, matching private instruction fields in the core semantic field that are incompatible with the standard memory access protocol; step S22, determining the number of placeholder bits for the private instruction field, and adjusting the bit width of the bypass transparent segment to adapt to the private instruction field.

[0026] Preferably, after step S6, the method further includes: step S71, extracting a response flow control unit containing response semantics from the data stream fed back by the target storage chip; step S72, sending the data back to the corresponding cache address of the master control logic chip according to the address routing field in the response flow control unit.

[0027] Preferably, in step S5, the frequency range of the sampling period is set to 1 GHz to 4 GHz, and the trigger time of the sampling period lags behind the system clock edge of the chip interconnect system by 10 ps to 50 ps.

[0028] Preferably, in step S3, the credit status data is transmitted back in real time via physical layer sideband signals.

[0029] Preferably, the original transaction layer request includes a memory access request based on a general computing fast link protocol or a memory access request based on a cache coherence protocol. In step S5, a general flow control unit sequence is mapped by an unbuffered combinational logic array composed of multiplexers, so that the logic delay from parsing to output is constant at 3 to 5 clock cycles.

[0030] A multi-protocol compatible data interaction adaptation system for memory includes: The parsing unit is used to parse the original transaction layer requests output by the main control logic core and extract the target core identifier and core semantic fields; The protocol conversion unit is used to map the core semantic fields into a general flow control unit sequence that is independent of the specific physical protocol header attributes, based on the mapping relationship between the core semantic fields and the general transmission format; wherein, the general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions; The credit monitoring unit is used to obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and to determine the current available physical cell balance. The congestion control unit is used to count the request distribution density of the corresponding target core identifier within a preset time window and calculate the rate of change of the request distribution density over time. Based on the rate of change, it determines the pre-judgment deduction parameter and offsets the current available physical cell balance to obtain an equivalent dynamic credit amount. The bit-width reassembly unit is used to extract the intrinsic interface bit-width parameters of the target memory chip within a sampling period when the equivalent dynamic credit meets the release threshold and the general flow control unit sequence crosses the physical layer boundary. It then performs bit-width reassembly on the general flow control unit sequence based on the intrinsic interface bit-width parameters to obtain the target physical cell aligned with the intrinsic interface bit-width parameters. The bit-width reassembly unit is also used to calculate the effective bandwidth conversion rate based on the product relationship between the payload bits of the general flow control unit sequence and the intrinsic interface bit-width parameters. The physical layer communication interface is used to output target physical cells.

[0031] Example 1: In a 3D advanced packaging system under a specific heterogeneous computing architecture, the main control logic chip crosses physical boundaries to achieve high-bandwidth and deterministic data flow with multiple memory chips using heterogeneous communication protocols. Because existing interconnect architectures typically instantiate multiple independent protocol conversion hardware units in parallel on the logic chip side when handling multi-protocol data interaction, this statically layered coupling-based architecture design requires each heterogeneous protocol to maintain an independent static data buffer pool at the logic layer to complete the protocol state machine handshake. The resulting protocol conversion hard latency consumes the silicon wafer coastline area at the edge of the logic chip, and the unaligned data fragmentation phenomenon generated during the conversion process undermines the heterogeneous system's cache consistency requirements for end-to-end deterministic latency. The operation mode of the technical solution of this invention under the above conditions is as follows: parsing the original transaction layer request output by the main control logic chip and providing... The target kernel identifier and core semantic fields are retrieved. The semantic feature index table, embedded in the non-volatile storage module of the main control logic kernel, is called. Hardware addressing logic directly compares each discrete transaction operation instruction into a unified bit-width binary feature code. Based on the mapping relationship between the core semantic fields and the general transmission format, the core semantic fields are mapped into a general flow control unit sequence that is independent of specific physical protocol header attributes. The general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions. The credit status data fed back by the target storage kernel corresponding to the target kernel identifier is obtained. The current available physical cell balance is determined, and the rate of change of the request distribution density corresponding to the target kernel identifier over time within a preset time window is calculated. Based on this rate of change, a pre-deduction parameter is determined and offset against the current available physical cell balance to obtain an equivalent dynamic credit amount. Its calculation rules follow the following relationship: ,in, This is the equivalent dynamic credit volume. This represents the current available physical cell reserve. This is the cumulative value of the credit increment pulse signal. To request the rate of change of density, As a credit compensation factor, The congestion prediction coefficient is used; based on the deadlock-free boundary control principle of the data link layer, the physical trigger boundary of the release threshold is directly set as the equivalent dynamic credit value. Greater than Within the sampling period when the equivalent dynamic credit meets the release threshold and the general flow control unit sequence crosses the physical layer boundary, the intrinsic interface bit width parameter of the target memory chip is extracted. Combinational logic circuits are used to compare the original bit width of the general flow control unit sequence with the intrinsic interface bit width parameter to determine the number of bit width overflow bits.

[0032] When the original bit width exceeds the intrinsic interface bit width parameter, the general flow control unit sequence is split into multi-step timing sequences for output. During this multi-step timing splitting operation, the underlying hardware does not rely on a deep asynchronous buffer queue to temporarily store the split subsequent frames. Instead, a stateless barrel shift selector, natively driven by the system clock, is configured at the cross-clock physical boundary. When the ultra-wide flow control unit reaches this boundary array, the shallow counter toggles the selector's addressing gating bit according to the clock cycle. On the subsequent valid clock edge, the data stream is physically truncated and sent to the physical interface in batches using pure spatial pin routing, thus eliminating the need for static dwell depth. Under the premise of completing the transient serialization transition from parallel to serial flow; when the original bit width is less than the intrinsic interface bit width parameter, the idle symbol sequence defined by the protocol is filled into the end of the target physical cell frame until the clock edge of the aligned sampling period, to obtain the target physical cell aligned with the intrinsic interface bit width parameter. Based on the closed-loop negative feedback control principle, the bit width reassembly unit records the current general flow control unit sequence payload bit number and multiplies it with the intrinsic interface bit width parameter to obtain the bandwidth conversion rate, which is transmitted back to the congestion control unit in real time through the physical layer sideband channel. The congestion control unit extracts the reciprocal of the bandwidth conversion rate as a dynamic compensation weight, and directly multiplies it by the congestion prediction coefficient in the aforementioned formula in the next sampling period. By updating the values ​​and continuously adjusting the upper-layer front-end credit offset deduction range using the actual hardware transmission conversion efficiency of the physical layer, the physical layer interface is driven to output the target physical cell. The sampling frequency is set to 1GHz to 4GHz, and the triggering time of the sampling period lags behind the system clock edge of the chip interconnect system by 10ps to 50ps. The above process, through the deep collaboration of constructing a general flow control unit structure for the transaction layer and a physical boundary delay reassembly mechanism, shields the differences in heterogeneous physical protocols in the final cell reassembly step, unifying the core processing path of multi-protocol data in the general flow control unit sequence generation stage. This eliminates the multi-level protocol bridging and static caching deep overhead required by the existing interconnect architecture, and converges the end-to-end data transmission latency caused by cross-protocol conversion to the physical transmission level of basic logic gate circuits. While reducing the silicon area overhead of the logic chip edge interface, it ensures the timing determinism of memory consistency in heterogeneous systems.

[0033] Example 2: In a physical verification platform simulating heterogeneous chip interconnects, the main control logic chip and the memory chip are electrically connected through an advanced packaging substrate with a bandwidth density of 100Tbps / mm. This verification platform includes a high-precision logic analyzer to capture the data transition timing from the transaction layer to the physical layer, with a time resolution set to 0.5ps and a sampling rate of no less than 20GS / s. To simulate signal uncertainties in the interconnect channel, Gaussian white noise with a signal-to-noise ratio of 20dB is actively superimposed on the credit status data fed back by the memory chip to characterize electromagnetic interference under actual operating conditions. The sampling frequency... With trigger lag time The setting logic stems from the need to balance timing convergence and dynamic power consumption. When the data transmission rate of the inter-chip link is in the range of 16Gbps to 32Gbps, the following setting is selected. The frequency is set to 2GHz to capture sub-nanosecond signal jitter without increasing the static power consumption of the physical layer, while setting... To offset the intrinsic skew caused by substrate wiring with a delay of 30ps, and to achieve precise locking and maintenance of the aforementioned picosecond-level static bias under the harsh physical conditions of wafer fabrication deviations and fluctuations in ambient temperature and core operating voltage, the physical layer interfaces within the main control logic chip all integrate multi-stage adjustable inverter chains and high-resolution phase interpolators directly driven by digitally controlled current sources. This hardware timing control loop dynamically fine-tunes the intrinsic capacitance charging and discharging slope of specific inverter nodes by receiving the negative feedback voltage signal from the on-chip temperature control probe in real time. This allows for the continuous and stable extraction of this 10ps to 50ps absolute physical delay on an independent clock tree branch unaffected by the main logic pipeline. The purpose of the experiment is to verify the equivalent dynamic credit value through objective data. The performance in reducing latency during heterogeneous protocol conversion, and the degree of optimization of the logic chip edge area by the general flow control unit sequence structure.

[0034] The experiment was conducted in parallel with a control group, a control group with missing features, and the sample group of the present invention. The original input data was set to be a mixed traffic consisting of 50% CXL protocol transaction requests and 50% HBM protocol transaction requests, with an original request density of Irregular fluctuations were observed within the high load range of 0.75 to 0.95. In the comparative sample group, the physical layer interface incurred handshake overhead due to the parallel instantiated protocol conversion hardware units. The measured end-to-end data conversion latency fluctuated drastically between 18.64ns and 25.42ns, and the silicon area consumption at the logic chip edge reached 14.52. In the prototype of this invention, after parsing the original transaction layer request output by the main control logic chip, the core semantic fields are mapped to a general flow control unit sequence. When the rate of change in the request issuance density is detected... When the congestion threshold of 1.15 / ns is reached, the system calculates the equivalent dynamic credit. And generate corresponding credit offsetting amounts, of which The change rate is used; measured data shows that, under the condition of maintaining the same throughput, the end-to-end data conversion delay of the sample group of this invention converges to the range of 4.22ns to 5.08ns, and the delay jitter deviation is reduced from 6.81ns in the comparison sample group to 0.88ns; further testing was conducted on a control group with missing features, and the congestion prediction coefficient was removed. The associated dynamic adjustment logic revealed that its cache utilization rate surged from 45.2% to 91.8% under sudden traffic surges, triggering a backpressure signal, proving the equivalent dynamic credit volume. It provides feedforward adjustment support for physical layer cell reassembly.

[0035] In boundary condition stress testing, the sampling frequency will be... Set to 4GHz, and will trigger lag time. Set to 50ps; when the original bit width of the general flow control unit sequence is set to 256 bits and the intrinsic interface bit width parameter of the target memory chip is set to 64 bits, the bit width reconstruction mechanism splits the general flow control unit sequence into a 4-step timing sequence output through combinational logic; data shows that when the original request density Beyond the overload region of 0.98, the data conversion efficiency exhibits a non-linear saturation trend, meaning the throughput gain slope slows down with increasing frequency. This aligns with the transmission limit of physical pins, thus confirming that the sampling frequency range of 1GHz to 4GHz is the preferred operating window for heterogeneous memory interaction. Because the prototype of this invention eliminates redundant protocol conversion buffers, its measured silicon wafer area overhead is only 2.83. Compared to the control sample, it achieves an area reduction of 80.5%. The experimental results confirm that by using a general flow control unit sequence in conjunction with a delay reassembly mechanism at the physical boundary, the hard latency of multi-protocol adaptation is reduced to the physical transmission level of logic gate circuits while ensuring the semantic integrity of heterogeneous protocols, thus maintaining the timing determinism of memory consistency in heterogeneous computing systems.

[0036] Example 3: This example combines Figures 1 to 2 Description of multi-protocol compatible data interaction adaptation methods and systems for memory, such as Figure 1 As shown, firstly, step S1 is executed to parse the original transaction layer request output by the main control logic core, and extract the target core identifier and core semantic fields. Then, step S2 is executed to map the core semantic fields into a general flow control unit sequence, which includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions. Next, in step S3, the credit status data fed back by the target storage core corresponding to the target core identifier is obtained, and the current available physical cell balance is determined. Then, in step S4, the change rate of request issuance density over time is statistically analyzed and the pre-deduction parameter is determined. The equivalent dynamic credit amount is obtained by offsetting the physical cell balance. In step S5, the intrinsic interface bit width parameter of the target storage core is extracted and bit width reassembly is performed to obtain the target physical cell and calculate the effective bandwidth conversion rate. Finally, step S6 is executed to drive the physical layer interface to output the target physical cell.

[0037] like Figure 2As shown, the system consists of a master control logic core domain, a core bus interconnect plane, and a heterogeneous storage core cluster. The master control logic core domain is equipped with a parsing unit and a protocol conversion unit. The parsing unit is responsible for transmitting the generated original transaction layer request to the congestion control unit in the core bus interconnect plane, while the protocol conversion unit inputs the mapped general flow control unit sequence to the bit width reconstruction unit. The core core bus interconnect plane contains a congestion control unit, a credit monitoring unit, a bit width reconstruction unit, and a physical layer communication interface. The credit monitoring unit receives the credit status data returned by target storage core A or target storage core B in the heterogeneous storage core cluster, calculates and outputs an equivalent dynamic credit value to the bit width reconstruction unit. The bit width reconstruction unit completes the processing under the joint drive of the general flow control unit sequence and the equivalent dynamic credit value. The final target physical cell is sent to the corresponding node in the heterogeneous storage core cluster via the physical layer communication interface.

[0038] Example 4: In a chip cluster system containing multiple computing units and multiple memory nodes, the main control logic chip interacts with memory chips using a heterogeneous interconnect protocol via a parallel bus interface. Due to the micrometer-level manufacturing tolerance in the physical link length between each chip and the difference in the internal instruction pipeline depth of each memory chip, short-term congestion caused by credit feedback lag at the physical layer boundary occurs when memory access instructions issued by the transaction layer. This transaction-level blocking caused by physical layer disturbance triggers an upward backpressure signal, causing the cache consistency maintenance state of the chip system to deviate from the preset timing interval. The operation mode of the technical solution of the present invention under the above conditions is as follows: Analyzing the main control logic chip... The system outputs the original transaction layer request and extracts the target kernel identifier and core semantic fields. Based on the mapping relationship between the core semantic fields and the general transmission format, it maps the core semantic fields into a sequence of general flow control units that are independent of specific physical protocol header attributes. Specifically, it extracts the read / write operation type, memory address span, and atomic operation identifier from the core semantic fields. Using the protocol feature index table within the logic circuit, the extracted information is converted into a fixed-width basic header segment. At the same time, the special instruction segments in the original transaction request that exceed the standard protocol definition are encapsulated in a dynamic-width bypass transparent segment. The system also obtains the credit status data fed back by the target memory kernel corresponding to the target kernel identifier to determine the current available physical cell balance. Simultaneously, by monitoring the accumulated value of the credit increment pulse signal returned from the physical link layer. Correct the credit account and calculate the rate of change of request distribution density for the corresponding target chip identifier over time within a preset time window. Based on this, the system measures the round-trip delay of the physical layer link. Determine the credit compensation factor and congestion prediction coefficient ,in Values The ratio to the system clock cycle, The value is the product of a preset congestion sensitivity threshold and the link bandwidth utilization rate, and then the equivalent dynamic credit is calculated according to the formula. Its calculation rules follow the following relationship: ,in, This is the equivalent dynamic credit volume. This represents the current available physical cell reserve. This is the cumulative value of the credit increment pulse signal. For the rate of change, As a credit compensation factor, Here, β represents the congestion prediction coefficient. During the aforementioned multi-parameter hardwired calculations, the underlying computational logic unit of the system activates a dimensionally normalized mapping engine for the congestion prediction coefficient β. This engine, essentially a cross-scale physical transformation operator, can automatically convert the captured transient request slope in the time domain into a dimensionless predicted overdraft information cell compensation integer based on the current physical link's baseline main frequency oscillation period. This ensures the rigorous self-consistency of all operands in the system's flow control formula in terms of engineering meaning and mathematical dimensions before the underlying adder performs the offsetting action, thus achieving equivalent dynamic credit volume. Within the sampling period when the general flow control unit sequence crosses the physical layer boundary and is greater than zero, the intrinsic interface bit width parameter of the target memory chip is extracted. Combinational logic circuits are used to compare the original bit width of the general flow control unit sequence with the intrinsic interface bit width parameter to determine the number of bit width overflow bits. When the original bit width is greater than the intrinsic interface bit width parameter, the general flow control unit sequence is split into multi-phase timing sequences for output. When the original bit width is less than the intrinsic interface bit width parameter, a protocol-defined idle symbol sequence is padded to the end of the target physical cell frame up to the clock edge aligned with the sampling period, obtaining the target physical cell aligned with the intrinsic interface bit width parameter. The physical layer interface is then driven to output the target physical cell, where the sampling frequency... Set to 3.2GHz, trigger lag time The setting is 25ps to compensate for substrate wiring deviation; the above process deconstructs the heterogeneous protocol conversion logic into a general feature vector mapping and dynamic credit adjustment mechanism, enabling the system to have feedforward perception capability for physical layer congestion risk. Since the equivalent dynamic credit hedging algorithm is introduced at the physical layer boundary, the risk of buffer pool overflow caused by credit feedback delay is eliminated. The measured data shows that when dealing with transient burst traffic, the data interaction latency fluctuation of the system is suppressed to within 0.5ns. While compressing the asynchronous cache depth on the logic chip side, the timing determinism of heterogeneous storage interaction is maintained.

[0039] Example 5: In the feature library initialization scenario of the chip interconnect system, the main control logic chip establishes a semantic feature index table based on the binary encoding rules corresponding to the storage protocol instruction set; through the normalization processing circuit built into the logic layer, heterogeneous protocol fields, including read / write transaction types, memory address ranges, and consistency status bits, are converted into binary semantic identifiers with a uniform bit width; for custom extended instructions that exceed the scope of standard protocols, they are segmented and encapsulated according to the bit width length of the original bit stream of the instruction, and their corresponding bits are mapped to the dynamic bit width bypass transparent transmission segment of the general flow control unit sequence; finally, the obtained semantic mapping data is solidified in the non-volatile storage module of the main control logic chip.

[0040] When the chip interconnect system is in the baseline calibration condition of field deployment, the system determines the congestion prediction coefficient based on the measured data during the link training phase. The initial quantization value; the specific execution process includes issuing a set of memory access request sequences with gradient characteristics, and recording the end-to-end latency in real time according to the request issuance density through the physical layer monitoring circuit. The system tracks the evolution trajectory of latency changes. When a performance inflection point is detected in the latency change trend that satisfies the condition that the second derivative is greater than zero and the amplitude exceeds the preset jitter tolerance, the system sets the link bandwidth utilization and round-trip latency corresponding to this inflection point as follows: The product is determined as To ensure accurate digital feature extraction of the aforementioned performance inflection point even in the white noise interference range of a substrate environment with extremely low signal-to-noise ratio and high-frequency glitches, the front-end hardware of the physical layer monitoring circuit is connected in series with a set of moving average digital low-pass filters composed of shift registers. After the continuously acquired discrete time delay transition edges are cleaned and smoothed and reconstructed by this filtering hardware array, it drives the customized pure digital differential multiply-add operator in the subsequent stage to continuously perform two-order recursion on the smoothed sampled values ​​of adjacent periods at nanosecond clock beats. In this way, the second derivative quantification index is forcibly approximated and locked by extremely simple hard-wired logic. Within the dynamic window of continuous system operation, the cumulative value of the credit increment pulse signal returned by the physical link layer is captured using a sampling clock with a frequency of 2.8 GHz. And equivalent dynamic credit volume Perform frame-by-frame correction to ensure the physical layer interface is based on... The real-time numerical adjustment of the target physical information cell transmission timing keeps the end-to-end data interaction latency fluctuation within 0.5ns.

[0041] Example 6: When the interconnect system is deployed in packaging environments with different physical link lengths, the master control logic chip sends a set of bit-width aligned pseudo-random training sequences through the physical layer interface; the master control logic chip starts its internal logic counting circuit when sending the first training packet header, and stops counting when it receives the handshake signal packet header fed back by the target memory chip, and determines the total number of recorded clock pulses as the round-trip delay. The initial baseline value is determined, and simultaneously, the main control logic chip reads the receive buffer pool bit width and depth data stored in the target memory chip configuration register. The current available physical cell margin is determined by calculating the ratio of the total receive buffer pool capacity to the sequence bit width of the general flow control unit. The initial count value is used as the credit benchmark for issuing memory access requests at the transaction layer, ensuring that the credit flow control loop establishes an initial baseline based on physical link length and hardware buffer capacity before data transactions are transferred.

[0042] When the system is in online operation where link impedance shifts due to ambient temperature fluctuations or operating voltage drift, the system initiates an automatic calibration procedure. This procedure utilizes the physical layer monitoring circuitry to statistically analyze the effective switching ratio of signal lines within a preset sliding time window. Specifically, the system uses the effective switching ratio as a quantitative input for link bandwidth utilization and calculates the product of link bandwidth utilization and a preset congestion sensitivity level. The result of this product is then used as the congestion prediction coefficient. In the aforementioned closed-loop operation sequence, the real-time updated value of the preset congestion sensitivity level, which serves as a key multiplier factor, is directly generated by the master control chip during the initial handshake phase. This level is derived from the physical buffer width and flow control backpressure tolerance parameters burned into the target heterogeneous storage chip's configuration firmware. After feature comparison via a pre-set static lookup table logic on the master control side, a discrete attenuation dimensionless constant between 0.1 and 1.0 is generated. This provides a deterministic initial baseline pool for the hardware-level tolerance of the heterogeneous protocol to burst traffic. Based on this, the system uses the real-time detection data obtained from the physical layer... Volatility-Adjusted Credit Compensation Factor The amplitude is used to drive logic gate circuits to calculate the equivalent dynamic credit value. The system is based on the real-time updates Adjust the timing of the general flow control unit sequence across the physical layer boundary to keep the end-to-end data interaction latency fluctuation within 0.5ns.

[0043] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for adapting multi-protocol compatible data interaction in a memory, characterized in that, Includes the following steps: Step S1: Parse the original transaction layer request output by the main control logic core and extract the target core identifier and core semantic fields; Step S2: Based on the mapping relationship between the core semantic fields and the general transmission format, the core semantic fields are mapped to a general flow control unit sequence that is independent of the specific physical protocol header attributes. The general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions. Step S3: Obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and determine the current available physical cell balance; Step S4: Calculate the request distribution density of the corresponding target core identifier within the preset time window and calculate the rate of change of the request distribution density over time. Determine the pre-judgment deduction parameter based on the rate of change and offset the current available physical cell balance to obtain the equivalent dynamic credit amount. Step S5: Within the sampling period when the equivalent dynamic credit volume meets the release threshold and the general flow control unit sequence crosses the physical layer boundary, extract the intrinsic interface bit width parameter of the target storage chip, and perform bit width reorganization on the general flow control unit sequence according to the intrinsic interface bit width parameter to obtain the target physical cell aligned with the intrinsic interface bit width parameter. At the same time, calculate the effective bandwidth conversion rate according to the product relationship between the effective payload bits of the general flow control unit sequence and the intrinsic interface bit width parameter. Step S6: Drive the physical layer interface to output the target physical cell.

2. The multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, Step S4 further includes: step S41, monitoring the credit increment pulse signal fed back by the target storage chip; step S42, calculating the instantaneous throughput gradient of the original transaction layer request according to the preset sliding window period, and defining the instantaneous throughput gradient as the rate of change.

3. The multi-protocol compatible data interaction adaptation method for a memory according to claim 2, characterized in that, In step S4, the calculation rules for equivalent dynamic credit amount follow the following relationship: ,in, This is the equivalent dynamic credit volume. This represents the current available physical cell reserve. This is the cumulative value of the credit increment pulse signal. For the rate of change, As a credit compensation factor, This represents the congestion prediction coefficient.

4. The multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, The steps in step S5 to reassemble the general flow control unit sequence include: step S51, using combinational logic circuits to compare the original bit width of the general flow control unit sequence with the intrinsic interface bit width parameter to determine the number of bit width overflow bits; step S52, when the original bit width is greater than the intrinsic interface bit width parameter, splitting the general flow control unit sequence into a multi-step timing sequence output; step S53, when the original bit width is less than the intrinsic interface bit width parameter, filling the end of the frame of the target physical cell with a protocol-defined idle symbol sequence up to the clock edge of the aligned sampling period.

5. A multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, Step S2 also includes: Step S21, matching private instruction fields in the core semantic field that are incompatible with the standard memory access protocol; Step S22, determining the number of placeholder bits for the private instruction field and adjusting the bit width of the bypass transparent segment to adapt to the private instruction field.

6. A multi-protocol compatible data interaction adaptation method for a memory according to claim 5, characterized in that, After step S6, the method further includes: step S71, extracting a response flow control unit containing response semantics from the data stream fed back by the target storage chip; step S72, sending the data back to the corresponding cache address of the master control logic chip according to the address routing field in the response flow control unit.

7. A multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, In step S5, the frequency range of the sampling period is set to 1 GHz to 4 GHz, and the trigger time of the sampling period lags behind the system clock edge of the chip interconnect system by 10 ps to 50 ps.

8. A multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, In step S3, the credit status data is transmitted back in real time via physical layer sideband signals.

9. A multi-protocol compatible data interaction adaptation method for a memory according to claim 1, characterized in that, The original transaction layer request includes a memory access request based on a general computing fast link protocol or a memory access request based on a cache coherence protocol. In step S5, a general flow control unit sequence is mapped by an unbuffered combinational logic array composed of multiplexers, so that the logic delay from parsing to output is constant at 3 to 5 clock cycles.

10. A multi-protocol compatible data interaction adaptation system for a memory, used to implement the multi-protocol compatible data interaction adaptation method for a memory as described in claim 1, characterized in that, include: The parsing unit is used to parse the original transaction layer requests output by the main control logic core and extract the target core identifier and core semantic fields; The protocol conversion unit is used to map the core semantic fields into a general flow control unit sequence that is independent of the specific physical protocol header attributes, based on the mapping relationship between the core semantic fields and the general transmission format; wherein, the general flow control unit sequence includes a fixed-width basic header segment and a dynamic-width bypass transparent segment for accommodating non-standard instructions; The credit monitoring unit is used to obtain the credit status data fed back by the target storage core corresponding to the target core identifier, and to determine the current available physical cell balance. The congestion control unit is used to count the request distribution density of the corresponding target core identifier within a preset time window and calculate the rate of change of the request distribution density over time. Based on the rate of change, it determines the pre-judgment deduction parameter and offsets the current available physical cell balance to obtain an equivalent dynamic credit amount. The bit-width reassembly unit is used to extract the intrinsic interface bit-width parameters of the target memory chip within a sampling period when the equivalent dynamic credit meets the release threshold and the general flow control unit sequence crosses the physical layer boundary. It then performs bit-width reassembly on the general flow control unit sequence based on the intrinsic interface bit-width parameters to obtain the target physical cell aligned with the intrinsic interface bit-width parameters. The bit-width reassembly unit is also used to calculate the effective bandwidth conversion rate based on the product relationship between the payload bits of the general flow control unit sequence and the intrinsic interface bit-width parameters. The physical layer communication interface is used to output target physical cells.

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