Pulse power synchronous output method and device, computer device and storage medium

Abstract

This invention belongs to the technical field of signal output methods, and particularly relates to a pulse power supply synchronous output method, apparatus, computer device, and storage medium based on DSP-simulated CAN communication. The method includes: a custom simulated CAN communication protocol; based on the simulated CAN communication protocol, each pulse power supply node performs dynamic competition on a differential bus, with the winning pulse power supply node becoming the master node. The master node sends a synchronous data frame containing a timing period parameter to the differential bus at a fixed timing period; slave nodes listen to the differential bus, respond to a capture interrupt triggered by the start bit of the synchronous data frame, receive and parse the data in the synchronous data frame bit by bit, obtain the interrupt response time deviation value, and control a local timer based on the difference between the timing period parameter and the interrupt response time deviation value. This invention significantly improves system reliability, achieving high-precision synchronous output at the microsecond or even nanosecond level under extremely simplified hardware conditions.

Description

Technical Field

[0001] This invention belongs to the technical field of signal output methods, and particularly relates to a pulse power synchronous output method, device, computer equipment and storage medium based on DSP-simulated CAN communication. Background Technology

[0002] A pulsed power supply is a device that converts mains or DC power into pulsed electrical energy with specific waveform parameters (such as frequency, duty cycle, and amplitude). It is widely used in industrial and scientific research fields such as electroplating, electrolysis, plasma treatment, laser driving, and pulsed power. In practical applications, multiple pulsed power supplies often need to work together, and the output pulses of each power supply must maintain strict time synchronization to ensure processing quality or experimental accuracy. For example, in a large electroplating production line, dozens of pulsed power supplies need to output the same pulse waveform synchronously. If the synchronization deviation is too large, it will lead to uneven coating thickness. In laser driving systems, nanosecond-level synchronization deviations between multiple power supplies can directly affect the energy stability of the laser pulse.

[0003] Existing pulse power synchronization technologies mainly fall into two categories: The first type is the traditional hardware synchronization solution, which uses a phase-locked loop (PLL), a dedicated synchronization chip, or an analog conditioning circuit as its core to achieve multi-machine synchronization through hardware signal coupling. This type of solution is technically mature and has strong anti-interference capabilities, but the synchronization accuracy is usually only at the millisecond level. It also requires the integration of a large number of discrete components, resulting in complex circuit wiring, high debugging difficulty, and difficulty in controlling hardware cost and size. It is only suitable for ordinary electroplating or small-scale experimental scenarios where the synchronization accuracy requirement is not high.

[0004] The second category is digital synchronization solutions, which rely on FPGA chips, microcontrollers, or DSP chips to achieve synchronization control. FPGA chip solutions, leveraging the parallel processing capabilities of FPGAs, can achieve synchronization accuracy at the microsecond or nanosecond level, making them the mainstream choice for high-end aerospace and laser processing. However, FPGA chips are expensive, have complex peripheral driver circuits, are difficult to debug, and lack versatility, limiting their large-scale application in mid-range scenarios. Microcontroller solutions are less expensive, but limited by processing speed, their synchronization accuracy is typically only 10 to 50 microseconds, failing to meet the needs of mid-to-high-end industrial scenarios. DSP combined with a standard digital CAN bus solution is a common choice for industrial applications. This solution utilizes the differential transmission characteristics of the CAN bus to achieve strong anti-interference capabilities, while leveraging the high-speed computing power of the DSP to improve synchronization performance. However, the standard digital CAN bus solution requires additional dedicated communication devices such as a CAN controller, CAN transceiver, and signal isolation chip, resulting in a complex hardware structure. Furthermore, it is affected by the combined effects of digital protocol parsing delays, signal transmission losses, and interrupt response uncertainties, making it difficult to achieve synchronization accuracy exceeding 1 microsecond. In high-frequency pulse scenarios, synchronization drift and jitter are prone to occur.

[0005] Existing pulse power synchronization technology faces technical bottlenecks that mutually restrict each other in terms of hardware complexity, synchronization accuracy, and system reliability. The industry urgently needs a new technology solution that can achieve high-precision and high-reliability synchronization control under a minimal hardware architecture. Summary of the Invention

[0006] The purpose of this invention is to provide a pulse power supply synchronization output method, device, computer equipment, and storage medium based on DSP-simulated CAN communication, aiming to solve the problem of mutual constraints between existing pulse power supply synchronization technologies in terms of hardware complexity, synchronization accuracy, and system reliability.

[0007] The present invention is implemented as follows: a pulse power supply synchronization output method based on DSP-simulated CAN communication is provided, comprising the following steps: Step 1: Each pulse power supply node is connected to the same differential bus through the differential bus interface of the DSP chip, and a custom simulated CAN communication protocol is defined. The simulated CAN communication protocol includes communication data frames and bit timing. Step 2: Based on the simulated CAN communication protocol, each pulse power supply node performs dynamic contention on the differential bus. The winning pulse power supply node becomes the master node, and the remaining pulse power supply nodes become slave nodes. The master node sends synchronization data frames containing timing period parameters to the differential bus at a fixed timing period; and Step 3: The slave node listens to the differential bus, responds to the capture interrupt triggered by the start bit of the synchronization data frame, receives and parses the data in the synchronization data frame according to the bit timing, obtains the interrupt response time deviation value, and controls the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

[0008] In some implementations, in step 1, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

[0009] In some implementations, step 2 includes the following steps: Each pulse power node defaults to slave mode after startup and listens to whether the differential bus is idle. If the differential bus is in an idle state, the pulse power node starts sending data and monitors in real time whether the level of the differential bus is consistent with its own data during the transmission of the start bit and the ID bit. If they are consistent, the corresponding pulse power node is identified as the master node and sends a synchronization data frame containing timing period parameters to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the node switches back to the slave state.

[0010] In some implementations, step 3 includes the following steps: In response to a capture interrupt triggered by a falling edge of the differential bus level, the capture interrupt is disabled, and bus data is acquired bit by bit according to the bit timing sequence until a complete frame of data is received. The received complete frame data is verified by the check bit. If the verification passes and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The timing period of the local timer is set to the difference between the timing period parameter and the interrupt response time deviation value, and the pulse power supply is controlled to output when the timing period arrives.

[0011] Another embodiment of the present invention provides a pulse power supply synchronization output device based on DSP-simulated CAN communication, comprising: The protocol customization unit is used for each pulse power supply node to connect to the same differential bus through the differential bus interface of the DSP chip, and to customize the simulated CAN communication protocol, which includes communication data frames and bit timing. A master dynamic contention unit is used to dynamically compete for dominance on the differential bus based on the analog CAN communication protocol. The winning pulse power node becomes the master node, and the remaining pulse power nodes become slave nodes. The master node sends synchronization data frames containing timing period parameters to the differential bus at a fixed timing period. The signal output unit is used by the slave node to listen to the differential bus, respond to the capture interrupt triggered by the start bit of the synchronization data frame, receive and parse the data in the synchronization data frame according to the bit timing, obtain the interrupt response time deviation value, and control the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

[0012] In some implementations, within the protocol customization unit, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

[0013] In some embodiments, the host dynamic contention unit includes: The slave monitoring module is used to assume a slave state by default after each pulse power node is started, and to monitor whether the differential bus is in an idle state. The master identification module is used to, if the differential bus is in an idle state, start the pulse power node to send data, and during the transmission of the start bit and the ID bit, monitor in real time whether the level of the differential bus is consistent with the data it is sending. If they are consistent, the corresponding pulse power node is identified as the master node, and a synchronization data frame containing the timing period parameter is sent to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the module switches back to the slave state.

[0014] In some embodiments, the signal output unit includes: The data receiving module is configured to respond to a capture interrupt triggered by the falling edge of the differential bus level, disable the capture interrupt, and acquire bus data bit by bit according to the bit timing sequence until a complete frame of data is received. The deviation value calculation module is used to verify the check bit of the received complete frame data. If the verification is successful and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The signal output module is used to set the timing period of the local timer to the difference between the timing period parameter and the interrupt response time deviation value, and to control the pulse power supply output when the timing period arrives.

[0015] Another embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the pulse power supply synchronous output method based on DSP simulated CAN communication as described in any of the above embodiments.

[0016] Another embodiment of the present invention provides a storage medium storing a computer program that can be executed to implement the steps of the pulse power supply synchronous output method based on DSP simulated CAN communication as described in any of the above embodiments.

[0017] The pulse power supply synchronization output method, device, computer equipment, and storage medium based on DSP-simulated CAN communication provided in this invention replace the standard digital CAN bus protocol with a custom simulated CAN communication protocol. Multi-pulse power supply node networking communication can be achieved using only a DSP chip and a differential bus, significantly simplifying the hardware structure and reducing costs. A dynamic competition mechanism enables each pulse power supply node to autonomously elect a host, and by capturing interrupt timestamp deviations and compensating for them, signal transmission delay, interrupt preemption delay, and DSP computation delay are accurately quantified and deducted in real time. This effectively offsets the impact of interrupt response uncertainty on synchronization accuracy, greatly improving system reliability and achieving high-precision synchronization output at the microsecond or even nanosecond level under extremely simplified hardware conditions. Attached Figure Description

[0018] Figure 1 This is a flowchart of a pulse power supply synchronous output method based on DSP simulated CAN communication provided by an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a communication data frame of a 33-bit analog CAN communication protocol provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a pulse power synchronous output device based on DSP-simulated CAN communication provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] In the description of this invention, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0024] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0025] This invention provides a pulse power supply synchronization output method based on DSP-simulated CAN communication, referencing... Figure 1 This includes the following steps: Step 1: Each pulse power supply node is connected to the same differential bus through the differential bus interface of the DSP chip, and a custom simulated CAN communication protocol is defined. The simulated CAN communication protocol includes communication data frames and bit timing. Step 2: Based on the simulated CAN communication protocol, each pulse power supply node performs dynamic contention on the differential bus. The winning pulse power supply node becomes the master node, and the remaining pulse power supply nodes become slave nodes. The master node sends synchronization data frames containing timing period parameters to the differential bus at a fixed timing period; and Step 3: The slave node listens to the differential bus, responds to the capture interrupt triggered by the start bit of the synchronization data frame, receives and parses the data in the synchronization data frame according to the bit timing, obtains the interrupt response time deviation value, and controls the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

[0026] The pulse power supply synchronous output method based on DSP simulated CAN communication provided in this embodiment is based on the following technical concept: using the differential bus interface built into the DSP chip as the physical communication link, eliminating the need for an additional communication protocol processing chip; by customizing and simplifying the simulated CAN communication protocol, the time delay introduced by the cumbersome protocol stack parsing in the standard digital CAN protocol is avoided; and by combining the dynamic competition mechanism executed autonomously by each pulse power supply node to determine the temporary master-slave relationship, the slave node finally achieves precise alignment with the master node on the output time base by capturing interrupt triggers and timing deviation compensation.

[0027] Specifically, the method includes three sequentially executed and logically interconnected steps: The first step involves preparing the physical and protocol layers. At the physical layer, each pulse power node is equipped with a DSP chip. This DSP chip has a differential bus interface, such as a built-in CAN module interface or a general differential interface after level conversion. Each pulse power node connects to the same differential bus through its corresponding differential bus interface, thus forming a multi-point shared communication medium at the hardware level. At the protocol layer, the DSP software running in each pulse power node defines its own simulated CAN communication protocol. "Simulated CAN communication" means that this protocol only borrows the physical layer differential signal transmission characteristics of the standard CAN bus, without adopting the complex data link layer protocols defined by the standard CAN bus, such as standard 11-bit / 29-bit identifiers, CRC checks, bit stuffing, and acknowledgment mechanisms. The simulated CAN communication protocol includes at least two aspects: firstly, the definition of the communication data frame, which specifies the organization of data in a single communication transmission, such as which fields are included, the bit length of each field, and their arrangement order; secondly, the definition of bit timing, which specifies the duration of each bit level on the differential bus, and when each pulse power node samples and reads the bus level, among other timing parameters. Through this simulated CAN communication protocol, subsequent data transmission and parsing have a unified set of rules, ensuring that each pulse power node on the differential bus can correctly identify and parse the information sent by each other. It is worth emphasizing that in this step, the "customization" executed by each pulse power node is consistent with each other; that is, all pulse power nodes use the same protocol definition, which is a prerequisite for the normal operation of differential bus communication.

[0028] In the second step, each pulse power node performs a dynamic contention process on the differential bus within the framework of a pre-defined simulated CAN communication protocol. The core technical problem this step addresses is how to determine a single pulse power node from multiple peers as the initiator of the synchronization signal (i.e., the master node) in a bus network without a fixed master device or a pre-defined master node, while simultaneously avoiding bus conflicts caused by multiple pulse power nodes simultaneously transmitting data. Specifically, each pulse power node is initially on an equal footing. Any pulse power node wishing to become the master node and send synchronization data must "compete" on the differential bus according to the rules of the simulated CAN communication protocol. The essence of this competition is that each pulse power node sends its own information bit by bit on the differential bus according to predetermined rules while simultaneously reading back the bus level to determine if other higher-priority pulse power nodes are also attempting to send. The winning pulse power node is determined as the current master node, and the remaining pulse power nodes automatically become slave nodes. Once the master-slave relationship is established, the master node assumes the role of a synchronization reference signal source, periodically sending synchronization data frames to the differential bus according to its internally set fixed timing period. This synchronization data frame contains at least the crucial timing period parameter, which represents the output pulse period that the master node expects all slave nodes to maintain consistency with. Furthermore, after completing a synchronization data frame transmission, the master node does not permanently retain its master status but instead re-enters a listening state. If the master node detects a data frame on the differential bus that matches its timing period parameter, it indicates that a new slave node is vying to become the master node, and the original master node automatically degrades to a slave node, following the new synchronization reference. Conversely, if a slave node does not receive a synchronization data frame from the master node within several consecutive fixed timing periods, it determines that the current master node may be faulty, actively initiates a transmission mechanism to participate in the master contention, and becomes the new master node upon successful contention. This ensures that the system can self-recover and continue to operate stably in the event of node failure.

[0029] In the third step, each pulse power node, already identified as a slave node, needs to accurately receive and respond to the synchronization data frames sent by the master node. Specifically, the slave nodes continuously listen for level changes on the differential bus. When the master node begins sending a synchronization data frame, the start bit of the synchronization data frame generates a level transition on the differential bus (from idle to active). This level transition signal is transmitted through the differential bus to the capture input of the DSP chip in each slave node, triggering a capture interrupt in the DSP chip. After responding to the capture interrupt, the slave node receives and parses all the data content contained in the synchronization data frame, including the timing period parameters, bit by bit from the differential bus according to the bit timing rules defined in the first step (including the duration of each bit, when to read the bus level to obtain the correct bit value, etc.). Simultaneously with the capture interrupt being triggered, the DSP chip of the slave node automatically records the timestamp information corresponding to the trigger moment. However, when the slave node's software actually enters the interrupt service routine to begin processing, a certain time lag has occurred; this lag is the interrupt response time deviation value. After obtaining the interrupt response time deviation value, the slave node subtracts this deviation value from the timing period parameter required by the master node, and uses the difference to set the timing duration of the local timer. The technical advantage of this is that since the slave node has already consumed a certain amount of time between triggering and actually starting processing, if the local timer is directly set to the standard timing period, the actual output time will lag behind the theoretical synchronization time. However, by subtracting the interrupt response time deviation value from the timing period parameter, it is equivalent to starting the local timer earlier, thus accurately compensating for the aforementioned lag when the local timer arrives. This allows the slave node to ultimately control its own pulse power supply output at the synchronized time point after the deviation is compensated, achieving synchronized output with the master node and other slave nodes.

[0030] In this invention, a custom analog CAN communication protocol replaces the standard digital CAN bus protocol, eliminating the need for dedicated CAN controllers, transceivers, and signal isolation chips required in traditional solutions. Multi-pulse power node networking communication can be achieved using only a DSP chip and a differential bus, significantly simplifying the hardware structure and reducing costs. A dynamic contention mechanism enables each pulse power node to autonomously elect a master and supports automatic redundant reconstruction after a master node failure, eliminating the single-point-of-failure risk of a fixed master-slave architecture and greatly improving system reliability. By capturing interrupt timestamp deviation compensation, signal transmission delay, interrupt preemption delay, and DSP computation delay are accurately quantified and deducted in real time, effectively offsetting the impact of interrupt response uncertainty on synchronization accuracy. This achieves high-precision synchronization output at the microsecond or even nanosecond level under extremely simplified hardware conditions, while also considering adaptability to strong electromagnetic interference environments and the versatility of multi-node expansion without hardware modifications.

[0031] In some specific embodiments of this application, in step 1, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

[0032] refer to Figure 2 A communication data frame consists of a start bit, an ID bit, data bits, and a check bit arranged sequentially. The start bit, located at the very beginning of the data frame, serves two purposes: first, it marks the start of a data frame transmission, allowing receiving nodes on the differential bus to clearly identify frame boundaries; second, the level transition of the start bit (from high to low) simultaneously acts as a hardware trigger signal for interrupt capture, enabling slave nodes to initiate the receiving process at the start of frame transmission, ensuring no subsequent valid data is missed. The ID bit follows immediately after the start bit and carries the identification information of the transmitting node. In the contention mechanism of a multi-node differential bus, the content of the ID bit determines the priority order of each pulse power supply node and is the core basis for contention judgment. The data bits, located after the ID bit, carry the core synchronization parameter of the effective timing period, which, as described in the above implementation, is determined by the data bits. The check bit is located at the end of the communication data frame and carries the result of the check operation on the ID bit and data bits. In this embodiment, the check method specifically adopts byte summation check, that is, the sending end adds the value of the ID bit and the value of the data bit, and sends the sum as the content of the check bit; after receiving the complete data frame, the receiving end performs the same algorithm to sum the received ID bit and data bits, compares the calculation result with the check bit, if they match, it means that the data transmission is error-free, if they do not match, it means that a bit error occurred during the transmission, and the data frame should be discarded. Compared with the 15-bit CRC cyclic redundancy check used by the standard CAN bus, this summation check method significantly reduces the amount of calculation, which helps to reduce the computational overhead of the DSP chip and improve the protocol processing efficiency. In other embodiments, parity check or simple CRC check can be used alone or in combination to improve the accuracy of error detection. Only the check operation logic of the DSP chip needs to be modified, without adjusting the hardware structure.

[0033] In some implementations, the communication data frame consists of four parts: a start bit, an ID bit (8 bits), data bits (16 bits), and a parity bit (8 bits), totaling 33 bits. The start bit has 1 bit, the ID bit has 8 bits, the data bits have 16 bits, and the parity bit has 8 bits. In other implementations, the communication data frame can also have more bits, such as 64 bits or 128 bits depending on actual needs. By increasing the width of the data bits and parity bits, it can accommodate more complex pulse parameter synchronization (e.g., phase and duty cycle synchronization), requiring only modification to the DSP chip's protocol parsing logic without adjusting the hardware structure.

[0034] refer to Figure 2 In this bit timing scheme, the duration of each bit is divided into three periods: a first de-interference period, a steady-state acquisition period, and a second de-interference period. Specifically, a first de-interference period is set at the beginning of each bit to avoid transient noise such as ringing and overshoot that may occur during differential bus level transitions. This noise is particularly significant in strong electromagnetic interference environments, such as industrial sites. A steady-state acquisition period is set in the middle of each bit, when the differential bus level has stabilized to the effective state driven by the transmitter. This is the optimal time to acquire reliable bit data by sampling the level value. Therefore, this implementation limits the sampling and parsing of the differential bus level to the steady-state acquisition period only. A second de-interference period is set at the end of each bit to resist possible trailing edge noise interference and to reserve recovery time for the start transition of the next bit. Through the above bit timing design, the acquisition accuracy of the bus signal in harsh electromagnetic environments is significantly improved without the need for additional hardware filtering circuits.

[0035] In some implementations, the duration of each bit is fixed at 75 μs, with the first 25 μs being the first interference removal period, the middle 25 μs being the steady-state acquisition period, and the last 25 μs being the second interference removal period. In other implementations, the duration of each bit can also be different, as can the first interference removal period, the steady-state acquisition period, and the second interference removal period. These can be flexibly adjusted by the DSP chip's software to adapt to differential bus networks with different transmission distances. For example, for long-distance transmission, the bit duration can be increased to improve signal stability.

[0036] Regarding the triggering method for the capture interrupt, the design is such that the idle state of the differential bus is high, while the start of the data frame is a falling edge, i.e., a transition from high to low. This falling edge serves as the trigger signal for the capture interrupt. Setting the idle state of the differential bus to high serves two purposes: firstly, a high-level idle state helps the differential bus driver circuit maintain a stable output state when there is no data transmission, reducing power consumption; secondly, the transition from high to low (i.e., the falling edge) serves as a frame start marker, which is easily and reliably detected and identified by the capture unit of the DSP chip in digital circuits. Whenever the capture input of the slave node's DSP chip detects this falling edge, it immediately triggers the capture interrupt, ensuring that the slave node can begin receiving and processing data as soon as it is transmitted, minimizing response delay.

[0037] In some specific embodiments of this application, step 2 includes the following steps: Each pulse power node defaults to slave mode after startup and listens to whether the differential bus is idle. If the differential bus is in an idle state, the pulse power node starts sending data and monitors in real time whether the level of the differential bus is consistent with its own data during the transmission of the start bit and the ID bit. If they are consistent, the corresponding pulse power node is identified as the master node and sends a synchronization data frame containing timing period parameters to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the node switches back to the slave state.

[0038] Each pulse power node defaults to slave mode upon power-on. If multiple pulse power nodes power on simultaneously and all attempt to send data as master, a severe conflict will occur on the differential bus initially, preventing any node from transmitting correctly. By defaulting to slave mode, all pulse power nodes first enter a "listen-wait" mode upon startup, passively monitoring existing signals on the differential bus, thus avoiding disordered competition during the initial startup phase.

[0039] Next, any pulse power node wishing to send data must first listen to whether the differential bus is in an idle state. The idle state is determined according to the rule defined in the above embodiment: the differential bus idle state is a high level. That is, the pulse power node determines whether transmission can be initiated by detecting whether the differential bus level is continuously high and stable. Only after confirming that the differential bus is in an idle state can the pulse power node start the data transmission process; otherwise, the pulse power node must continue to wait until the differential bus is idle. This listen-before-transmit mechanism avoids differential bus data conflicts, ensuring that at most one pulse power node is transmitting valid data on the differential bus at any given time.

[0040] After a pulse power node begins transmitting data, especially during the transmission of the start and ID bits, it needs to monitor in real time whether the actual level of the differential bus matches the data it is transmitting. The emphasis on monitoring during the start and ID bits is crucial because the start bit marks the beginning of data transmission, while the ID bit carries the priority information of the pulse power node. In scenarios where multiple pulse power nodes begin transmitting data almost simultaneously, conflicts first occur during the bit-by-bit comparison of the start and ID bits. If a pulse power node reads back a differential bus level that is inconsistent with its own transmitted level while transmitting a certain bit, it indicates that another pulse power node with a higher priority is also transmitting data on the differential bus, and the differential bus level driven by this higher-priority pulse power node overrides the level of this pulse power node. Upon detecting this inconsistency, this pulse power node immediately terminates its transmission operation and quickly switches back to slave mode, entering receive mode to receive and process the complete data frame transmitted by the higher-priority pulse power node. Conversely, if no inconsistency is detected by the pulse power node throughout the entire transmission process, it indicates that no other pulse power node with higher priority initiated contention during the transmission period. This pulse power node is the winner of the contention and is designated as the master node. Once designated as the master node, it gains control of the differential bus and periodically sends synchronization data frames containing timing period parameters to the differential bus according to its internally set fixed timing period, thus assuming the role of a synchronization signal source.

[0041] In some specific embodiments of this application, step 3 includes the following steps: In response to a capture interrupt triggered by a falling edge of the differential bus level, the capture interrupt is disabled, and bus data is acquired bit by bit according to the bit timing sequence until a complete frame of data is received. The received complete frame data is verified by the check bit. If the verification passes and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The timing period of the local timer is set to the difference between the timing period parameter and the interrupt response time deviation value, and the pulse power supply is controlled to output when the timing period arrives.

[0042] When a slave node detects a falling edge of the differential bus level (i.e., the start bit of a data frame) and triggers a capture interrupt, this capture interrupt must first be disabled. In the DSP chip's interrupt unit, if the trigger source is not disabled during the interrupt service routine execution, continuous level changes in the same data bit or subsequent data bits may trigger the interrupt again, causing interrupt nesting or repeated responses, leading to chaotic data reception. By disabling the capture interrupt at the interrupt service routine entry point and then re-enabling it after the complete frame of data has been received, it is ensured that the slave node can continuously and stably complete bit-by-bit acquisition during the reception of a data frame, unaffected by repeated interrupt triggers. Subsequently, the slave node acquires the level values ​​from the differential bus bit by bit according to the bit timing sequence until the complete frame of data is received.

[0043] After receiving a complete frame of data, the slave node needs to verify the checksum bit. Using a byte-accumulation checksum algorithm, the received ID bit and data bits are summed, and the result is compared with the received checksum bit. If they match, the checksum passes, indicating that no errors occurred during transmission and the frame content is reliable; further processing continues. If they don't match, the checksum fails, indicating interference or errors during transmission; the frame is unusable, and the slave node discards it, returning to the differential bus listening state to wait for the next valid frame. Furthermore, after successful checksum verification, the slave node also needs to compare the timing period parameter carried in the data bits with its own set parameters. This comparison ensures that the slave node only responds to data sent by the master node with the same synchronization target, avoiding missynchronization between nodes with different parameter configurations.

[0044] After confirming the data's validity, the slave node needs to read two key hardware registers in the DSP chip: the capture interrupt timestamp register and the capture interrupt count register. The capture interrupt timestamp register is automatically latched by the DSP chip when a capture interrupt is triggered by hardware; this value reflects the absolute moment of the trigger. The capture interrupt count register records the count from when the slave node actually enters the interrupt service routine and processes the data until the read time. The difference between the read values ​​of the two registers yields the interrupt response time deviation value between the slave node's capture trigger and its actual response. This interrupt response time deviation value incorporates the combined effects of multiple factors, including signal transmission delay on the differential bus, DSP chip interrupt response delay, preemption delay of other higher-priority interrupts, and computational delay consumed in the initial processing of the interrupt service routine. By quantifying all these delay factors into a unified interrupt response time deviation value, accurate numerical data is provided for subsequent precise compensation.

[0045] After obtaining the interrupt response time deviation value, the slave node sets the timing period of its local timer to the difference between the timing period parameter parsed from the data frame and the interrupt response time deviation value. The underlying principle is that the slave node aims to control the pulse power supply output at the theoretical synchronization moment (i.e., the moment specified by the timing period parameter). However, since the actual start time of the slave node processing the synchronization request is already later than the theoretical moment corresponding to the interrupt response time deviation value, directly setting the local timer to the value of the timing period parameter would result in the actual output time lagging behind the theoretical synchronization moment when the local timer arrives. To avoid this lag, the slave node sets the local timer value to the timing period parameter minus the interrupt response time deviation value, effectively starting the local timer "earlier," ensuring that the arrival time of the local timer precisely compensates for the aforementioned lag. When the local timer's timing period arrives, the slave node controls the pulse power supply output at that moment. At this time, the deviation between the slave node's output time and the theoretical synchronization moment required by the master node is effectively canceled out, thus achieving precise alignment between the slave and master nodes at the synchronization point.

[0046] The present invention also provides a pulse power supply synchronization output device based on DSP-simulated CAN communication, see reference. Figure 3 ,include: The protocol customization unit is used for each pulse power supply node to connect to the same differential bus through the differential bus interface of the DSP chip, and to customize the simulated CAN communication protocol, which includes communication data frames and bit timing. A master dynamic contention unit is used to dynamically compete for dominance on the differential bus based on the analog CAN communication protocol. The winning pulse power node becomes the master node, and the remaining pulse power nodes become slave nodes. The master node sends synchronization data frames containing timing period parameters to the differential bus at a fixed timing period. The signal output unit is used by the slave node to listen to the differential bus, respond to the capture interrupt triggered by the start bit of the synchronization data frame, receive and parse the data in the synchronization data frame according to the bit timing, obtain the interrupt response time deviation value, and control the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

[0047] The pulse power supply synchronous output device based on DSP-simulated CAN communication provided in this embodiment has the following overall technical concept: using the differential bus interface built into the DSP chip as the physical communication link, eliminating the need for an additional communication protocol processing chip; by customizing and simplifying the simulated CAN communication protocol, the time delay introduced by the cumbersome protocol stack parsing in the standard digital CAN protocol is avoided; and by combining the dynamic competition mechanism executed autonomously by each pulse power supply node to determine the temporary master-slave relationship, the slave node finally achieves precise alignment with the master node on the output time base by capturing interrupt triggers and timing deviation compensation.

[0048] Specifically, the device comprises three sequentially executed and logically interconnected units: In the protocol customization unit, the preparation work for the physical layer and protocol layer needs to be completed first. At the physical layer, each pulse power node is equipped with a DSP chip, which has a differential bus interface, such as a built-in CAN module interface or a general differential interface after level conversion. Each pulse power node connects to the same differential bus through its corresponding differential bus interface, thus forming a multi-point shared communication medium at the hardware level. At the protocol layer, the DSP software running in each pulse power node customizes a set of simulated CAN communication protocols. "Simulated CAN communication" means that this protocol only borrows the physical layer differential signal transmission characteristics of the standard CAN bus, without adopting the complex data link layer protocols defined by the standard CAN bus, such as standard 11-bit / 29-bit identifiers, CRC checksums, bit stuffing, and acknowledgment mechanisms. The simulated CAN communication protocol includes at least two aspects: firstly, the definition of the communication data frame, which specifies the organization of data in a single communication transmission, such as which fields are included, the bit length of each field, and their arrangement order; secondly, the definition of bit timing, which specifies the duration of each bit level on the differential bus, and when each pulse power node samples and reads the bus level, among other timing parameters. Through this simulated CAN communication protocol, subsequent data transmission and parsing in subsequent units have a unified set of rules, ensuring that each pulse power node on the differential bus can correctly identify and parse the information sent by each other. It is worth emphasizing that in this protocol customization unit, the "customization" executed by each pulse power node is consistent with each other; that is, all pulse power nodes use the same protocol definition, which is a prerequisite for the normal operation of differential bus communication.

[0049] In the master dynamic contention unit, each pulse power node performs a dynamic contention process on the differential bus within the framework of a pre-defined simulated CAN communication protocol. The core technical problem this master dynamic contention unit addresses is: in a bus network without a fixed master device or a pre-defined master node, how to determine a single pulse power node from multiple peers as the initiator of the synchronization signal (i.e., the master node), while simultaneously avoiding bus conflicts caused by multiple pulse power nodes simultaneously transmitting data. Specifically, each pulse power node is in an equal position after startup. Any pulse power node wishing to become the master node and send synchronization data must "compete" on the differential bus according to the rules of the simulated CAN communication protocol. The essence of the competition is that each pulse power node sends its own information bit by bit on the differential bus according to predetermined rules while simultaneously reading back the bus level to determine if other pulse power nodes with higher priority are also attempting to send. The pulse power node that wins the competition is determined as the current master node, and the remaining pulse power nodes automatically become slave nodes. Once the master-slave relationship is established, the master node assumes the role of a synchronization reference signal source, periodically sending synchronization data frames to the differential bus according to its internally set fixed timing period. This synchronization data frame contains at least the crucial timing period parameter, which represents the output pulse period that the master node expects all slave nodes to maintain consistency with. Furthermore, after completing a synchronization data frame transmission, the master node does not permanently retain its master status but instead re-enters a listening state. If the master node detects a data frame on the differential bus that matches its timing period parameter, it indicates that a new slave node is vying to become the master node, and the original master node automatically degrades to a slave node, following the new synchronization reference. Conversely, if a slave node does not receive a synchronization data frame from the master node within several consecutive fixed timing periods, it determines that the current master node may be faulty, actively initiates a transmission mechanism to participate in the master contention, and becomes the new master node upon successful contention. This ensures that the system can self-recover and continue to operate stably in the event of node failure.

[0050] In the signal output unit, each pulse power node, designated as a slave node, needs to accurately receive and respond to the synchronization data frames sent by the master node. Specifically, the slave nodes continuously listen for level changes on the differential bus. When the master node begins sending a synchronization data frame, the start bit of the synchronization data frame generates a level transition (from idle to active) on the differential bus. This level transition signal is transmitted through the differential bus to the capture input of the DSP chip of each slave node, triggering a capture interrupt in the DSP chip. After responding to the capture interrupt, the slave node receives and parses all the data content contained in the synchronization data frame, including the timing period parameters, bit by bit from the differential bus according to the bit timing rules defined in the protocol user-defined unit (including the duration of each bit, when to read the bus level to obtain the correct bit value, etc.). Simultaneously with the capture interrupt being triggered, the DSP chip of the slave node automatically records the timestamp information corresponding to the trigger moment. However, when the slave node's software actually enters the interrupt service routine to begin processing, a certain time lag has occurred; this lag is the interrupt response time deviation value. After obtaining the interrupt response time deviation value, the slave node subtracts this deviation value from the timing period parameter required by the master node, and uses the difference to set the timing duration of the local timer. The technical advantage of this is that since the slave node has already consumed a certain amount of time between triggering and actually starting processing, if the local timer is directly set to the standard timing period, the actual output time will lag behind the theoretical synchronization time. However, by subtracting the interrupt response time deviation value from the timing period parameter, it is equivalent to starting the local timer earlier, thus accurately compensating for the aforementioned lag when the local timer arrives. This allows the slave node to ultimately control its own pulse power supply output at the synchronized time point after the deviation is compensated, achieving synchronized output with the master node and other slave nodes.

[0051] In this invention, a custom analog CAN communication protocol replaces the standard digital CAN bus protocol, eliminating the need for dedicated CAN controllers, transceivers, and signal isolation chips required in traditional solutions. Multi-pulse power node networking communication can be achieved using only a DSP chip and a differential bus, significantly simplifying the hardware structure and reducing costs. A dynamic contention mechanism enables each pulse power node to autonomously elect a master and supports automatic redundant reconstruction after a master node failure, eliminating the single-point-of-failure risk of a fixed master-slave architecture and greatly improving system reliability. By capturing interrupt timestamp deviation compensation, signal transmission delay, interrupt preemption delay, and DSP computation delay are accurately quantified and deducted in real time, effectively offsetting the impact of interrupt response uncertainty on synchronization accuracy. This achieves high-precision synchronization output at the microsecond or even nanosecond level under extremely simplified hardware conditions, while also considering adaptability to strong electromagnetic interference environments and the versatility of multi-node expansion without hardware modifications.

[0052] In some specific embodiments of this application, in the protocol customization unit, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

[0053] refer to Figure 2 A communication data frame consists of a start bit, an ID bit, data bits, and a check bit arranged sequentially. The start bit, located at the very beginning of the data frame, serves two purposes: first, it marks the start of a data frame transmission, allowing receiving nodes on the differential bus to clearly identify frame boundaries; second, the level transition of the start bit (from high to low) simultaneously acts as a hardware trigger signal for interrupt capture, enabling slave nodes to initiate the receiving process at the start of frame transmission, ensuring no subsequent valid data is missed. The ID bit follows immediately after the start bit and carries the identification information of the transmitting node. In the contention mechanism of a multi-node differential bus, the content of the ID bit determines the priority order of each pulse power supply node and is the core basis for contention judgment. The data bits, located after the ID bit, carry the core synchronization parameter of the effective timing period, which, as described in the above implementation, is determined by the data bits. The check bit is located at the end of the communication data frame and carries the result of the check operation on the ID bit and data bits. In this embodiment, the check method specifically adopts byte summation check, that is, the sending end adds the value of the ID bit and the value of the data bit, and sends the sum as the content of the check bit; after receiving the complete data frame, the receiving end performs the same algorithm to sum the received ID bit and data bits, compares the calculation result with the check bit, if they match, it means that the data transmission is error-free, if they do not match, it means that a bit error occurred during the transmission, and the data frame should be discarded. Compared with the 15-bit CRC cyclic redundancy check used by the standard CAN bus, this summation check method significantly reduces the amount of calculation, which helps to reduce the computational overhead of the DSP chip and improve the protocol processing efficiency. In other embodiments, parity check or simple CRC check can be used alone or in combination to improve the accuracy of error detection. Only the check operation logic of the DSP chip needs to be modified, without adjusting the hardware structure.

[0054] In some implementations, the communication data frame consists of four parts: a start bit, an ID bit (8 bits), data bits (16 bits), and a parity bit (8 bits), totaling 33 bits. The start bit has 1 bit, the ID bit has 8 bits, the data bits have 16 bits, and the parity bit has 8 bits. In other implementations, the communication data frame can also have more bits, such as 64 bits or 128 bits depending on actual needs. By increasing the width of the data bits and parity bits, it can accommodate more complex pulse parameter synchronization (e.g., phase and duty cycle synchronization), requiring only modification to the DSP chip's protocol parsing logic without adjusting the hardware structure.

[0055] refer to Figure 2 In this bit timing scheme, the duration of each bit is divided into three periods: a first de-interference period, a steady-state acquisition period, and a second de-interference period. Specifically, a first de-interference period is set at the beginning of each bit to avoid transient noise such as ringing and overshoot that may occur during differential bus level transitions. This noise is particularly significant in strong electromagnetic interference environments, such as industrial sites. A steady-state acquisition period is set in the middle of each bit, when the differential bus level has stabilized to the effective state driven by the transmitter. This is the optimal time to acquire reliable bit data by sampling the level value. Therefore, this implementation limits the sampling and parsing of the differential bus level to the steady-state acquisition period only. A second de-interference period is set at the end of each bit to resist possible trailing edge noise interference and to reserve recovery time for the start transition of the next bit. Through the above bit timing design, the acquisition accuracy of the bus signal in harsh electromagnetic environments is significantly improved without the need for additional hardware filtering circuits.

[0056] In some implementations, the duration of each bit is fixed at 75 μs, with the first 25 μs being the first interference removal period, the middle 25 μs being the steady-state acquisition period, and the last 25 μs being the second interference removal period. In other implementations, the duration of each bit can also be different, as can the first interference removal period, the steady-state acquisition period, and the second interference removal period. These can be flexibly adjusted by the DSP chip's software to adapt to differential bus networks with different transmission distances. For example, for long-distance transmission, the bit duration can be increased to improve signal stability.

[0057] Regarding the triggering method for the capture interrupt, the design is such that the idle state of the differential bus is high, while the start of the data frame is a falling edge, i.e., a transition from high to low. This falling edge serves as the trigger signal for the capture interrupt. Setting the idle state of the differential bus to high serves two purposes: firstly, a high-level idle state helps the differential bus driver circuit maintain a stable output state when there is no data transmission, reducing power consumption; secondly, the transition from high to low (i.e., the falling edge) serves as a frame start marker, which is easily and reliably detected and identified by the capture unit of the DSP chip in digital circuits. Whenever the capture input of the slave node's DSP chip detects this falling edge, it immediately triggers the capture interrupt, ensuring that the slave node can begin receiving and processing data as soon as it is transmitted, minimizing response delay.

[0058] In some specific embodiments of this application, the host dynamic contention unit includes: The slave monitoring module is used to assume a slave state by default after each pulse power node is started, and to monitor whether the differential bus is in an idle state. The master identification module is used to, if the differential bus is in an idle state, start the pulse power node to send data, and during the transmission of the start bit and the ID bit, monitor in real time whether the level of the differential bus is consistent with the data it is sending. If they are consistent, the corresponding pulse power node is identified as the master node, and a synchronization data frame containing the timing period parameter is sent to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the module switches back to the slave state.

[0059] Each pulse power node defaults to slave mode upon power-on. If multiple pulse power nodes power on simultaneously and all attempt to send data as master, a severe conflict will occur on the differential bus initially, preventing any node from transmitting correctly. By defaulting to slave mode, all pulse power nodes first enter a "listen-wait" mode upon startup, passively monitoring existing signals on the differential bus, thus avoiding disordered competition during the initial startup phase.

[0060] Next, any pulse power node wishing to send data must first listen to whether the differential bus is in an idle state. The idle state is determined according to the rule defined in the above embodiment: the differential bus idle state is a high level. That is, the pulse power node determines whether transmission can be initiated by detecting whether the differential bus level is continuously high and stable. Only after confirming that the differential bus is in an idle state can the pulse power node start the data transmission process; otherwise, the pulse power node must continue to wait until the differential bus is idle. This listen-before-transmit mechanism avoids differential bus data conflicts, ensuring that at most one pulse power node is transmitting valid data on the differential bus at any given time.

[0061] After a pulse power node begins transmitting data, especially during the transmission of the start and ID bits, it needs to monitor in real time whether the actual level of the differential bus matches the data it is transmitting. The emphasis on monitoring during the start and ID bits is crucial because the start bit marks the beginning of data transmission, while the ID bit carries the priority information of the pulse power node. In scenarios where multiple pulse power nodes begin transmitting data almost simultaneously, conflicts first occur during the bit-by-bit comparison of the start and ID bits. If a pulse power node reads back a differential bus level that is inconsistent with its own transmitted level while transmitting a certain bit, it indicates that another pulse power node with a higher priority is also transmitting data on the differential bus, and the differential bus level driven by this higher-priority pulse power node overrides the level of this pulse power node. Upon detecting this inconsistency, this pulse power node immediately terminates its transmission operation and quickly switches back to slave mode, entering receive mode to receive and process the complete data frame transmitted by the higher-priority pulse power node. Conversely, if no inconsistency is detected by the pulse power node throughout the entire transmission process, it indicates that no other pulse power node with higher priority initiated contention during the transmission period. This pulse power node is the winner of the contention and is designated as the master node. Once designated as the master node, it gains control of the differential bus and periodically sends synchronization data frames containing timing period parameters to the differential bus according to its internally set fixed timing period, thus assuming the role of a synchronization signal source.

[0062] In some specific embodiments of this application, the signal output unit includes: The data receiving module is configured to respond to a capture interrupt triggered by the falling edge of the differential bus level, disable the capture interrupt, and acquire bus data bit by bit according to the bit timing sequence until a complete frame of data is received. The deviation value calculation module is used to verify the check bit of the received complete frame data. If the verification is successful and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The signal output module is used to set the timing period of the local timer to the difference between the timing period parameter and the interrupt response time deviation value, and to control the pulse power supply output when the timing period arrives.

[0063] When a slave node detects a falling edge of the differential bus level (i.e., the start bit of a data frame) and triggers a capture interrupt, this capture interrupt must first be disabled. In the DSP chip's interrupt unit, if the trigger source is not disabled during the interrupt service routine execution, continuous level changes in the same data bit or subsequent data bits may trigger the interrupt again, causing interrupt nesting or repeated responses, leading to chaotic data reception. By disabling the capture interrupt at the interrupt service routine entry point and then re-enabling it after the complete frame of data has been received, it is ensured that the slave node can continuously and stably complete bit-by-bit acquisition during the reception of a data frame, unaffected by repeated interrupt triggers. Subsequently, the slave node acquires the level values ​​from the differential bus bit by bit according to the bit timing sequence until the complete frame of data is received.

[0064] After receiving a complete frame of data, the slave node needs to verify the checksum bit. Using a byte-accumulation checksum algorithm, the received ID bit and data bits are summed, and the result is compared with the received checksum bit. If they match, the checksum passes, indicating that no errors occurred during transmission and the frame content is reliable; further processing continues. If they don't match, the checksum fails, indicating interference or errors during transmission; the frame is unusable, and the slave node discards it, returning to the differential bus listening state to wait for the next valid frame. Furthermore, after successful checksum verification, the slave node also needs to compare the timing period parameter carried in the data bits with its own set parameters. This comparison ensures that the slave node only responds to data sent by the master node with the same synchronization target, avoiding missynchronization between nodes with different parameter configurations.

[0065] After confirming the data's validity, the slave node needs to read two key hardware registers in the DSP chip: the capture interrupt timestamp register and the capture interrupt count register. The capture interrupt timestamp register is automatically latched by the DSP chip when a capture interrupt is triggered by hardware; this value reflects the absolute moment of the trigger. The capture interrupt count register records the count from when the slave node actually enters the interrupt service routine and processes the data until the read time. The difference between the read values ​​of the two registers yields the interrupt response time deviation value between the slave node's capture trigger and its actual response. This interrupt response time deviation value incorporates the combined effects of multiple factors, including signal transmission delay on the differential bus, DSP chip interrupt response delay, preemption delay of other higher-priority interrupts, and computational delay consumed in the initial processing of the interrupt service routine. By quantifying all these delay factors into a unified interrupt response time deviation value, accurate numerical data is provided for subsequent precise compensation.

[0066] After obtaining the interrupt response time deviation value, the slave node sets the timing period of its local timer to the difference between the timing period parameter parsed from the data frame and the interrupt response time deviation value. The underlying principle is that the slave node aims to control the pulse power supply output at the theoretical synchronization moment (i.e., the moment specified by the timing period parameter). However, since the actual start time of the slave node processing the synchronization request is already later than the theoretical moment corresponding to the interrupt response time deviation value, directly setting the local timer to the value of the timing period parameter would result in the actual output time lagging behind the theoretical synchronization moment when the local timer arrives. To avoid this lag, the slave node sets the local timer value to the timing period parameter minus the interrupt response time deviation value, effectively starting the local timer "earlier," ensuring that the arrival time of the local timer precisely compensates for the aforementioned lag. When the local timer's timing period arrives, the slave node controls the pulse power supply output at that moment. At this time, the deviation between the slave node's output time and the theoretical synchronization moment required by the master node is effectively canceled out, thus achieving precise alignment between the slave and master nodes at the synchronization point.

[0067] This invention, through its original design of a custom simulated CAN communication protocol, a host dynamic contention mechanism, and a DSP timestamp deviation compensation algorithm, achieves comprehensive technical advantages of high precision, low cost, simple structure, high reliability, and high versatility. It provides a completely new technical route for pulse power supply synchronous output technology, with the following specific benefits: 1. The hardware is extremely simple, resulting in a significant reduction in cost.

[0068] This invention eliminates the phase-locked loops and triggers of traditional solutions, as well as the dedicated CAN controllers / transceivers and signal isolation chips of existing digital solutions. It uses only DSP chips and differential buses as the core, reducing the number of hardware components by more than 60% and reducing hardware procurement costs by 30% to 50%. The circuit structure is simple, the wiring and debugging difficulty is greatly reduced, the production efficiency is increased by more than 40%, and the equipment size is reduced by 50%, which is conducive to the integrated design of miniaturized and portable pulse power supplies and adapts to the needs of equipment in all scenarios.

[0069] 2. Breakthrough in precision, adapting to high-precision needs across all scenarios.

[0070] Leveraging the nanosecond-level computing speed of DSP chips, combined with the delay-free digital protocol parsing characteristic of the custom analog CAN communication protocol, and equipped with a timestamp deviation compensation algorithm, the inherent delay of interrupt response is offset, achieving a synchronization accuracy of 1 to 10 microseconds in normal cases and 100 to 500 nanoseconds in optimal cases. This far exceeds traditional hardware solutions (millisecond level) and microcontroller solutions (10 to 50 microseconds), and is comparable to FPGA solutions in accuracy but with a cost reduction of more than 70%. It fills the gap in high-precision synchronization solutions that offer high cost-effectiveness in mid-range scenarios and low cost in high-end scenarios.

[0071] 3. High anti-interference and high reliability, suitable for harsh environments.

[0072] Analog CAN communication inherits the differential communication advantages of the CAN bus, has extremely strong anti-electromagnetic interference capabilities, and can adapt to strong interference environments such as electroplating, plasma processing, and aerospace. Combined with bit timing interference removal design, it only collects data during steady-state acquisition periods, further improving signal reliability. Through the host dynamic competition and redundancy reconstruction mechanism, it realizes automatic election of host nodes and fault self-recovery. The failure of a single node does not affect the operation of the entire synchronization system, and the difficulty of fault diagnosis is small, reducing maintenance costs by more than 40%. The system's mean time between failures (MTBF) is increased to more than twice that of existing solutions.

[0073] 4. High versatility, flexible expansion and adaptation.

[0074] The DSP chip is programmable, and synchronization parameters (frequency, phase, duty cycle, timing period) can be flexibly adjusted through software programming without modifying the hardware circuit. It is compatible with pulse power supplies of different power levels and pulse parameters. The differential bus supports multi-node expansion without hardware modification, and hundreds of nodes can be directly networked without redesigning the topology. It is suitable for networking needs in all scenarios, such as small experimental equipment, medium-sized industrial production lines, and large aerospace clusters. Its versatility is far superior to existing fixed and customized solutions.

[0075] 5. Deep integration of software and hardware, high technological barriers.

[0076] This invention integrates all the core logic of synchronization control into the software of the DSP chip. Through software design of custom protocol, competition logic, and deviation compensation, it replaces the hardware implementation of existing solutions, realizing "software-defined synchronization" and breaking through the hardware's constraints on accuracy, cost, and versatility. At the same time, the software logic is deeply matched with the hardware characteristics of the DSP chip, forming a technical fusion advantage of hardware simplicity and software efficiency, which has a high technical barrier and is difficult to be easily imitated.

[0077] This invention provides a computer device, which includes a processor. The processor executes a computer program stored in a memory to implement the steps of the pulse power supply synchronous output method based on DSP simulated CAN communication as described above.

[0078] The present invention also provides a computer-readable storage medium storing a computer program (instructions) thereon, which, when executed by a processor, implements the steps of the pulse power supply synchronous output method based on DSP simulated CAN communication as described above.

[0079] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to complete the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a computer device. For example, the computer program can be divided into the steps of the pulse power supply synchronization output method based on DSP-simulated CAN communication provided in the above-described method embodiments.

[0080] Those skilled in the art will understand that the above description of the computer device is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than described above, or a combination of certain components, or different components, such as input / output devices, network access devices, buses, etc.

[0081] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the computer device, connecting various parts of the computer device via various interfaces and lines.

[0082] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the computer device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as interface display function, interface interaction function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as map interface, selection interface, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0083] If the modules / units integrated into the computer device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, an electrical signal, and a software distribution medium, etc.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for synchronous output of pulse power supply based on DSP-simulated CAN communication, characterized in that, Includes the following steps: Step 1: Each pulse power supply node is connected to the same differential bus through the differential bus interface of the DSP chip, and a custom simulated CAN communication protocol is defined. The simulated CAN communication protocol includes communication data frames and bit timing. Step 2: Based on the simulated CAN communication protocol, each pulse power node performs dynamic competition on the differential bus. The pulse power node that wins the competition becomes the master node, and the remaining pulse power nodes become slave nodes. The master node sends a synchronization data frame containing timing period parameters to the differential bus at a fixed timing period. as well as Step 3: The slave node listens to the differential bus, responds to the capture interrupt triggered by the start bit of the synchronization data frame, receives and parses the data in the synchronization data frame according to the bit timing, obtains the interrupt response time deviation value, and controls the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

2. The pulse power supply synchronous output method based on DSP-simulated CAN communication according to claim 1, characterized in that, In step 1, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

3. The pulse power supply synchronous output method based on DSP-simulated CAN communication according to claim 2, characterized in that, Step 2 includes the following steps: Each pulse power node defaults to slave mode after startup and listens to whether the differential bus is idle. If the differential bus is in an idle state, the pulse power node starts sending data and monitors in real time whether the level of the differential bus is consistent with its own data during the transmission of the start bit and the ID bit. If they are consistent, the corresponding pulse power node is identified as the master node and sends a synchronization data frame containing timing period parameters to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the node switches back to the slave state.

4. The pulse power supply synchronous output method based on DSP-simulated CAN communication according to claim 2, characterized in that, Step 3 includes the following steps: In response to a capture interrupt triggered by a falling edge of the differential bus level, the capture interrupt is disabled, and bus data is acquired bit by bit according to the bit timing sequence until a complete frame of data is received. The received complete frame data is verified by the check bit. If the verification passes and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The timing period of the local timer is set to the difference between the timing period parameter and the interrupt response time deviation value, and the pulse power supply is controlled to output when the timing period arrives.

5. A pulse power supply synchronous output device based on DSP-simulated CAN communication, characterized in that, include: The protocol customization unit is used for each pulse power supply node to connect to the same differential bus through the differential bus interface of the DSP chip, and to customize the simulated CAN communication protocol, which includes communication data frames and bit timing. The host dynamic contention unit is used to perform dynamic contention on the differential bus based on the analog CAN communication protocol. The pulse power node that wins the contention becomes the host node, and the remaining pulse power nodes become slave nodes. The host node sends a synchronization data frame containing timing period parameters to the differential bus at a fixed timing period. as well as The signal output unit is used by the slave node to listen to the differential bus, respond to the capture interrupt triggered by the start bit of the synchronization data frame, receive and parse the data in the synchronization data frame according to the bit timing, obtain the interrupt response time deviation value, and control the local timer according to the difference between the timing period parameter and the interrupt response time deviation value, so as to control the pulse power supply output at the synchronization time point after the deviation is compensated.

6. The pulse power supply synchronous output device based on DSP-simulated CAN communication according to claim 5, characterized in that, In the protocol customization unit, The communication data frame is composed of a start bit, an ID bit, data bits, and a check bit in sequence. The timing period parameter is determined by the data bits, and the check bit is the byte sum of the ID bit and the data bits. In the bit timing sequence, the duration of each bit is sequentially divided into a first de-interference period, a steady-state acquisition period, and a second de-interference period, and the data in the synchronization data frame is received and parsed only during the steady-state acquisition period; The idle state of the differential bus is high, and the falling edge of the differential bus level serves as the trigger signal for the capture interrupt.

7. The pulse power supply synchronous output device based on DSP-simulated CAN communication according to claim 6, characterized in that, The host dynamic contention unit includes: The slave monitoring module is used to assume a slave state by default after each pulse power node is started, and to monitor whether the differential bus is in an idle state. The master identification module is used to, if the differential bus is in an idle state, start the pulse power node to send data, and during the transmission of the start bit and the ID bit, monitor in real time whether the level of the differential bus is consistent with the data it is sending. If they are consistent, the corresponding pulse power node is identified as the master node, and a synchronization data frame containing the timing period parameter is sent to the differential bus at a fixed timing period. If they are inconsistent, the transmission is immediately terminated and the module switches back to the slave state.

8. The pulse power supply synchronous output device based on DSP-simulated CAN communication according to claim 6, characterized in that, The signal output unit includes: The data receiving module is configured to respond to a capture interrupt triggered by the falling edge of the differential bus level, disable the capture interrupt, and acquire bus data bit by bit according to the bit timing sequence until a complete frame of data is received. The deviation value calculation module is used to verify the check bit of the received complete frame data. If the verification is successful and the timing period parameter is consistent with its own setting, the capture interrupt timestamp register value and the capture interrupt count register value are read, and the difference between the two is calculated as the interrupt response time deviation value. The signal output module is used to set the timing period of the local timer to the difference between the timing period parameter and the interrupt response time deviation value, and to control the pulse power supply output when the timing period arrives.

9. A computer device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the pulse power supply synchronous output method based on DSP simulated CAN communication as described in any one of claims 1 to 4.

10. A storage medium, characterized in that, The storage medium stores a computer program that can be executed to implement the steps of the pulse power supply synchronization output method based on DSP-simulated CAN communication as described in any one of claims 1 to 4.

Images