A multi-type audio and video master control board cooperative scheduling control system and method

Abstract

This invention relates to the field of industrial control computer and system manufacturing technology, and discloses a collaborative scheduling control system and method for multiple types of audio and video main control boards, including: a time-division multiplexing bus module, a clock dynamic compensation module, a state machine arbitration module, and a timing burst truncation control module. The clock dynamic compensation module monotonically reduces the number of bus timing judgment threshold cycles when the temperature rises. The state machine arbitration module opens a 15ns rest window and locks the flip detection when the bus request signal changes to a high level transiently. The timing burst truncation control module pulls down the bus enable signal when the bus occupancy time parameter is greater than the time threshold. This invention solves the problem of bus state arbitration misjudgment in industrial control systems under complex operating conditions, eliminates time slot waste, and ensures deterministic convergence of transmission delay between multiple audio and video nodes.

Description

Technical Field

[0001] This invention relates to a collaborative scheduling control system and method for multiple types of audio and video main control boards, belonging to the field of industrial control computer and system manufacturing technology. Background Technology

[0002] Currently, industrial control computers typically employ a distributed industrial control backplane bus architecture where multiple boards work together. When multiple different types of data are processed concurrently, each main control board shares a communication channel through a time-division multiplexed physical bus to transmit video streams, audio streams, and control commands with large screen changes. Since each board operates in a clock domain that is not synchronized with each other, their operating frequencies and priority settings differ. During burst transmission of large amounts of data, cross-clock domain transmission will cause the phase deviation between nodes to accumulate continuously, resulting in short-term bus contention and channel congestion at the bus pins.

[0003] While existing technologies attempt to improve upon hardware limitations such as device topology or physical architecture, their internal software, including data interaction and timing matching, also suffers from shortcomings. For example, Chinese invention patent CN112463693A discloses a multi-board communication system and method based on the M-LVDS bus. This system avoids bus usage contention by setting a single master node and polling each slave node according to a fixed timing sequence. However, this design implicitly relies on the underlying objective attributes of a fixed number of communication nodes and linear data transmission load. Faced with the millisecond-level dynamic burst loads within large-capacity audio and video streams and the transient influx of high-frequency concurrent data components, this fixed polling mechanism and rigid timing response are prone to causing multi-channel... Mutual exclusion lockout and severe congestion of communication links lead to the backlog or even overflow and loss of core audio and video data packets, making it impossible to maintain the continuous transmission of high-precision audio and video data over time and according to topology. Existing solutions usually involve increasing hardware bandwidth margin or setting up a centralized switching chip, using a fixed global clock synchronization and polling arbitration method. However, a higher frequency global clock increases system power consumption and cannot effectively reduce data queuing delay. Under continuous high load, the action of the central arbiter pulling down the bus enable signal can easily cause a short-term timing conflict with the burst transmission inside the board at the intersection of clock domains, causing the bus transceiver pins to be in a metastable state for a long time, which in turn increases the possibility of bus hardware deadlock.

[0004] Therefore, existing technologies still need to address the following issues: how to dynamically adjust the duty cycle triggered by discrete events of distributed nodes, and to force control of bus pin levels when necessary, in order to resolve bus contention under asynchronous clock domains and avoid local buffer overflows and system deadlock. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A multi-type audio and video main control board collaborative scheduling and control system, the system comprising: The clock dynamic compensation module is connected to the temperature acquisition interface module to obtain the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. The state machine arbitration module, including a time counting unit and a shielding gate unit, is used to control the time counting unit to start a 15ns rest window countdown and lock the bus request signal flip detection within the rest window through the shielding gate unit during the transient state when the time-division multiplexing bus module releases the right to use the multi-type audio and video main control board and the bus request signal in the time-division multiplexing bus module changes to a high level. The timing burst truncation control module includes an internal counting unit and a drive control unit. It is used to continuously monitor the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through the internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board and generates a bus release control signal.

[0006] Preferably, the system also includes a discrete hardware watchdog reset module; the discrete hardware watchdog reset module is connected to the timing burst cutoff control module and is used to monitor the duration of the bus release control signal; when the duration exceeds the time limit and the time-division multiplexed bus module is locked for more than 50ms, the internal discharge circuit of the discrete hardware watchdog reset module outputs a reset pulse level to the global reset pin of multiple multi-type audio and video main control boards to clear the bus lockout state.

[0007] Preferably, the state machine arbitration module includes: an internal time counting unit that starts a 15ns rest window countdown; within the 15ns rest window, the state machine arbitration module uses an internal shielding gating unit to lock the toggle detection of the bus request signal and block the pulse signal from being written to the local bus configuration register.

[0008] Preferably, the timing burst truncation control module includes: the timing burst truncation control module continuously accumulates the number of continuous transmission cycles of a single main control board on the time-division multiplexing bus module through an internal counting unit to generate a bus occupancy time parameter; when the bus occupancy time parameter is greater than a constant time threshold, the timing burst truncation control module adjusts the bus enable signal corresponding to the single main control board to a low level state through a drive control unit.

[0009] Preferably, the multi-type audio and video main control board is plugged into the backplane slot inside the external industrial control chassis; the state machine arbitration module maintains a resting window of 15ns when the external mechanical vibration acceleration reaches 2g and the contact resistance at the connection between the multi-type audio and video main control board and the backplane slot fluctuates between 1Ω and 100Ω.

[0010] Preferably, the temperature drift characteristic curve built into the clock dynamic compensation module is a monotonically decreasing curve; when the real-time temperature parameter output by the temperature acquisition interface module rises to 65°C, the clock dynamic compensation module reduces the number of bus timing judgment threshold cycles from 40 to 25 according to the monotonically decreasing curve.

[0011] Preferably, the system also includes a performance management module; the performance management module is connected to the timing burst truncation control module, which is used to accumulate the number of truncations when the bus occupancy time parameter is greater than a constant time threshold within the system transmission cycle, and to determine the bus occupancy trend index based on the time distribution of the truncation frequency; when the bus occupancy trend index is greater than a fixed threshold, the performance management module outputs a warning signal.

[0012] Preferably, the topology of the time-division multiplexing bus module is a PCIe bus topology architecture, the bus request signal is transmitted using a physical request link, and the bus enable signal is transmitted using a bus enable link; the physical request link is connected to the input of the state machine arbitration module, and the bus enable link is connected to the output of the timing burst truncation control module.

[0013] Preferably, the system includes an industrial control backplane and a video decoding main control board and an audio processing main control board respectively plugged into the industrial control backplane; the clock dynamic compensation module and the state machine arbitration module are built into the internal chip of the video decoding main control board, and the timing burst truncation control module and the discrete hardware watchdog reset module are built into the control chip of the industrial control backplane.

[0014] A collaborative scheduling and control method for multiple types of audio and video main control boards, used to run a collaborative scheduling and control system for multiple types of audio and video main control boards, includes the following steps: Step S1: The clock dynamic compensation module connects to the temperature acquisition interface module and obtains the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. Step S2: When the multi-type audio and video main control board releases the right to use the time-division multiplexing bus module and the bus request signal in the bus request signal link becomes high-level transient, the state machine arbitration module controls the time counting unit to start a 15ns rest window countdown, and locks the toggle detection of the bus request signal through the shielding gate control unit within the rest window. Step S3: The timing burst cutoff control module continuously monitors the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through its internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board in the bus enable signal link, and generates a bus release control signal.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In the collaborative scheduling and control of multiple types of audio and video main control boards, by dynamically adjusting the duty cycle of the bus request signal according to the sending queue depth of the local sending buffer and the bus idle status, the idle time slices in the time-division multiplexing scheduling can be reduced, enabling the main control board with a large amount of data backlog to obtain the right to use the bus in a timely manner. This can alleviate the data queuing and backlog in the local sending buffer and improve the timeliness and stability of audio and video data transmission under high load conditions.

[0016] 2. The clock dynamic compensation module adjusts the number of bus timing judgment threshold cycles according to temperature changes, which can reduce the impact of temperature drift on bus timing judgment and reduce the possibility of incorrect judgment by the state machine. The state machine arbitration module shields the flip detection of the bus request signal during the brief period after the main control board releases the bus, which can block the level glitches caused by slot contact resistance fluctuations and reduce the impact of external interference on bus state arbitration.

[0017] 3. The timing burst truncation control module limits the time a single main control board continuously occupies the time-division multiplexing bus module and forcibly releases the bus when the occupation timeout occurs. This can prevent a single main control board from monopolizing the bus for a long time, thus reserving transmission opportunities for other audio and video main control boards, reducing the transmission delay difference between nodes, and reducing the possibility of screen tearing and jitter in splicing display devices. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the hardware topology of the collaborative scheduling control system of the present invention; Figure 2 This is a state transition diagram for bus arbitration and burst truncation in this invention.

[0019] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A collaborative scheduling and control system for multiple types of audio and video main control boards, the system comprising: The clock dynamic compensation module is connected to the temperature acquisition interface module to obtain the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. The state machine arbitration module, including a time counting unit and a shielding gate unit, is used to control the time counting unit to start a 15ns rest window countdown and lock the bus request signal flip detection within the rest window through the shielding gate unit during the transient state when the time-division multiplexing bus module releases the right to use the multi-type audio and video main control board and the bus request signal in the time-division multiplexing bus module changes to a high level. The timing burst truncation control module includes an internal counting unit and a drive control unit. It is used to continuously monitor the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through the internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board and generates a bus release control signal.

[0022] Preferably, the system also includes a discrete hardware watchdog reset module; the discrete hardware watchdog reset module is connected to the timing burst cutoff control module and is used to monitor the duration of the bus release control signal; when the duration exceeds the time limit and the time-division multiplexed bus module is locked for more than 50ms, the internal discharge circuit of the discrete hardware watchdog reset module outputs a reset pulse level to the global reset pin of multiple multi-type audio and video main control boards to clear the bus lockout state.

[0023] Preferably, the state machine arbitration module includes: an internal time counting unit that starts a 15ns rest window countdown; within the 15ns rest window, the state machine arbitration module uses an internal shielding gating unit to lock the toggle detection of the bus request signal and block the pulse signal from being written to the local bus configuration register.

[0024] Preferably, the timing burst truncation control module includes: the timing burst truncation control module continuously accumulates the number of continuous transmission cycles of a single main control board on the time-division multiplexing bus module through an internal counting unit to generate a bus occupancy time parameter; when the bus occupancy time parameter is greater than a constant time threshold, the timing burst truncation control module adjusts the bus enable signal corresponding to the single main control board to a low level state through a drive control unit.

[0025] Preferably, the multi-type audio and video main control board is plugged into the backplane slot inside the external industrial control chassis; the state machine arbitration module maintains a resting window of 15ns when the external mechanical vibration acceleration reaches 2g and the contact resistance at the connection between the multi-type audio and video main control board and the backplane slot fluctuates between 1Ω and 100Ω.

[0026] Preferably, the temperature drift characteristic curve built into the clock dynamic compensation module is a monotonically decreasing curve; when the real-time temperature parameter output by the temperature acquisition interface module rises to 65°C, the clock dynamic compensation module reduces the number of bus timing judgment threshold cycles from 40 to 25 according to the monotonically decreasing curve.

[0027] Preferably, the system also includes a performance management module; the performance management module is connected to the timing burst truncation control module, which is used to accumulate the number of truncations when the bus occupancy time parameter is greater than a constant time threshold within the system transmission cycle, and to determine the bus occupancy trend index based on the time distribution of the truncation frequency; when the bus occupancy trend index is greater than a fixed threshold, the performance management module outputs a warning signal.

[0028] Preferably, the topology of the time-division multiplexing bus module is a PCIe bus topology architecture, the bus request signal is transmitted using a physical request link, and the bus enable signal is transmitted using a bus enable link; the physical request link is connected to the input of the state machine arbitration module, and the bus enable link is connected to the output of the timing burst truncation control module.

[0029] Preferably, the system includes an industrial control backplane and a video decoding main control board and an audio processing main control board respectively plugged into the industrial control backplane; the clock dynamic compensation module and the state machine arbitration module are built into the internal chip of the video decoding main control board, and the timing burst truncation control module and the discrete hardware watchdog reset module are built into the control chip of the industrial control backplane.

[0030] A collaborative scheduling and control method for multiple types of audio and video main control boards, used to run a collaborative scheduling and control system for multiple types of audio and video main control boards, includes the following steps: Step S1: The clock dynamic compensation module connects to the temperature acquisition interface module and obtains the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. Step S2: When the multi-type audio and video main control board releases the right to use the time-division multiplexing bus module and the bus request signal in the bus request signal link becomes high-level transient, the state machine arbitration module controls the time counting unit to start a 15ns rest window countdown, and locks the toggle detection of the bus request signal through the shielding gate control unit within the rest window. Step S3: The timing burst cutoff control module continuously monitors the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through its internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board in the bus enable signal link, and generates a bus release control signal.

[0031] Example 1: The current multi-type audio and video main control board collaborative scheduling control system is used to process multiple high-bitrate audio and video streams. The video decoding main control board A, audio processing main control board B, and streaming media forwarding main control board C are respectively plugged into the industrial control backplane. Each main control board adopts a different chip architecture and runs in an asynchronous clock domain that is not synchronized with each other. The time-division multiplexing bus module adopts a PCIe bus topology architecture. Among them, the physical request link is used to transmit the bus request signal and connects to the input of the state machine arbitration module; the bus enable link is used to transmit the bus enable signal and connects to the output of the timing burst truncation control module. The state machine arbitration module is built into the internal chip of the video decoding main control board A, and the timing burst truncation control module and the discrete hardware watchdog reset module are built into the control chip of the industrial control backplane.

[0032] High-frequency electromagnetic radiation in industrial environments can cause bus level jitter and bit errors. Multi-channel video decompression can also cause timing queuing delays in the direct memory access controller. When these two situations overlap, uncertain data accumulation occurs in the local transmit buffers of each main control board, leading to contention and sudden channel congestion in the time-division multiplexing bus module. The queuing delay between boards fluctuates accordingly, resulting in frame rate jitter or screen tearing in the monitoring screen. When the backplane-side bus enable signal goes low and a sudden transmission action inside the board occurs at the asynchronous clock overlap point, the time-division multiplexing bus module may also enter a locked state.

[0033] The streaming media forwarding main control board C has an asynchronous bus load balancing unit within its bus communication control integrated circuit. This unit reads the memory address write pointer register and read pointer register of the local video transmission buffer through a hardware status counter, and the arithmetic logic unit calculates the address difference between the two to obtain the raw queue depth in bytes. The on-chip timer synchronously monitors the number of idle pulses on the bus status response line and converts it into a bus response idle time constant. Its unit is the number of clock cycles. When the original queue depth exceeds the preset memory safety capacity threshold, and When the timing threshold is greater than the threshold, the arithmetic logic unit calculates the bus adjustment factor. .

[0034] Before calculation, the arithmetic logic unit divides the original queue depth by the standard physical bus width of the interconnect bus, which is 32 bits (4 bytes). This conversion yields a dimensionless queue depth data variable expressed in bus transmission cycles. Preset maximum time constant Adopted and The same number of clock cycles is used as the unit, and the bus adjustment factor is marked with a single-level subscript. The calculation formula is: ,in, This is a dimensionless bus adjustment factor. This is the queue depth data variable converted from the standard physical bus width. This is the bus response idle time constant. To preset the maximum time constant, after bit width conversion, The value is dimensionless. and Using the same units, the calculated results Maintain dimensionless.

[0035] Asynchronous bus load balancing unit according to Modify the control word in the local bus configuration register to adjust the pulse width modulation duty cycle of the bus request signal in the physical request link. As the load increases, the duty cycle of the bus request signal also increases. The streaming media forwarding main control board C outputs the bus priority occupation control command through the physical request link and sends the audio and video data packets in the local transmission buffer to the time-division multiplexing bus module to shorten the transmission waiting time of high-load boards.

[0036] The timing burst cutoff control module within the industrial control backplane control chip limits the continuous occupancy time of a single main control board. Its internal counting unit accumulates the number of continuous transmission cycles of a single main control board on the time-division multiplexing bus module cycle by cycle, generating the bus occupancy time parameter. ,when When the time exceeds the constant time threshold, the drive control unit does not wait for the software protocol layer to complete the handshake, but directly adjusts the bus enable signal corresponding to the main control board in the bus enable link to a low level, generates a bus release control signal, stops the main control board from continuing to occupy the time-division multiplexed bus module, the asynchronous bus load balancing unit adjusts the duty cycle of the bus request signal, and the timing burst truncation control module limits the continuous occupation time of a single main control board. The two work together to adjust the transmission cycle obtained by each main control board.

[0037] The performance management module connects to the timing burst truncation control module, and uses the system transmission cycle as the statistical interval. Each time the timing burst truncation control module... When a bus release control signal is generated due to a time limit exceeding a constant threshold, the performance management module accumulates one truncation frequency and records the time of occurrence of this truncation within the system transmission cycle. The performance management module determines the bus occupancy trend index according to the sequential changes in the truncation frequency within a continuous system transmission cycle. When the truncation frequency increases cycle by cycle, the bus occupancy trend index increases accordingly; when the truncation frequency decreases cycle by cycle, the index decreases accordingly. The fixed threshold is calibrated based on the truncation frequency allowed under normal system load. When the bus occupancy trend index exceeds the fixed threshold, the performance management module outputs a warning signal.

[0038] When any multi-type audio / video main control board releases the right to use the time-division multiplexing bus module, and the bus request signal in the physical request link changes to a high level, the state machine arbitration module inside the video decoding main control board A controls the time counting unit to start a 15ns rest window countdown. Within the rest window, the shielding gate unit locks the flip detection of the bus request signal, blocks high-frequency parasitic level interference on the physical request link, and prevents the pulse signal generated by contact resistance fluctuation from being written into the local bus configuration register, thereby avoiding pulse glitches from participating in the bus state arbitration.

[0039] When the timing burst interruption control module pulls down the bus enable signal and the burst direct memory access transmission action inside the board causes a transient timing collision at the clock overlap, resulting in the time-division multiplexing bus module being locked, the discrete hardware watchdog reset module monitors the duration of the bus release control signal through a hardware timer. When the duration of the bus release control signal exceeds the time limit and the locked state of the time-division multiplexing bus module lasts for more than 50ms, the discharge circuit inside the discrete hardware watchdog reset module is turned on, outputting a reset pulse level to the global reset pins of the video decoding main control board A, the audio processing main control board B, and the streaming media forwarding main control board C. This clears the bus occupancy status register of each main control board and resets the hardware state machine, restoring the system to the polling timing sequence. This process controls the data transmission delay difference of multiple video streams to within 8ms and clears the bus lock-up state caused by the asynchronous clock domain overlap.

[0040] The local bus request signal duty cycle adjustment and the backplane-side bus enable signal cutoff form a two-layer control structure. Without changing the industrial control backplane wiring topology, the system allocates the bus transmission cycle according to the local transmit buffer state, and limits the conflict propagation in the asynchronous clock domain through hardware state machine interlocking and discharge circuit reset, so that the bus transmission data flow converges with the load state, reducing the dependence of bus bandwidth allocation on the external synchronous clock, and forming a closed loop driven by the local transient state to control the link level.

[0041] Example 2: The current industrial control computer hardware simulation test cabinet is equipped with a physical measurement system consisting of a high-speed differential signal generator and a logic analyzer array. The high-speed differential signal generator provides initial data streams to various types of audio and video main control boards. The logic analyzer array collects bus status with a signal sampling rate of 10GHz and a voltage measurement accuracy of 1mV to evaluate the bus access efficiency of each main control board. During the test, external mechanical vibration applies 2g of mechanical resonance interference to the time-division multiplexed bus module, causing the contact resistance at the connection between the video decoding main control board A and the gold finger of the backplane slot to fluctuate randomly between 1Ω and 100Ω, and generating transient level glitches with a frequency of 100MHz to 500MHz at the pins of the physical request link.

[0042] The system uses the queue state sampling interval parameter Adjust the queue overload detection frequency. The peak packet arrival density varies with the audio and video data stream: as the packet arrival rate increases, Adjust the value range towards the lower limit to increase the sampling frequency; when the system is in a low throughput state, The monotonically increasing frequency reduces register toggling losses in the control chip, achieving a high-definition multi-channel aggregation throughput of 4.2Gbps. Take 2.5 μs.

[0043] The bus communication control integrated circuit within the streaming media forwarding main control board C activates the asynchronous bus load balancing unit. Its hardware status counter reads the memory address write pointer register and read pointer register of the local video transmission buffer, calculates the address difference between the two, and obtains the queue depth input in bytes. This input is then normalized to the standard physical bus width to form... The on-chip timer synchronously monitors the number of idle pulses on the bus status acknowledge line and converts it into a bus acknowledge idle time constant. When the queue depth input exceeds the preset memory safety capacity threshold, and When the timing threshold is exceeded, the on-chip hard-core arithmetic logic unit will... and Send to the arithmetic unit, to As a normalization parameter, the output bus adjustment factor Then, adjust the duty cycle of the bus request signal in the physical request link accordingly.

[0044] The test subjects were divided into four equal groups: the experimental group used a complete system; control group 1 did not have an asynchronous bus load balancing unit; control group 2 did not have a timing burst truncation control module; and control group 3... The test conditions were set below the lower limit of the range, sequentially passing through three levels: low load, medium load, and high load. During the simultaneous application of mechanical and electromagnetic interference, the queue depth input was continuously recorded. , Bus request signal duty cycle, inter-node transmission delay jitter deviation, and latch-up occurrence count.

[0045] In the low-load stage of the test group, the queue depth input size was 1024 bytes. The arithmetic logic unit outputs 45 clock cycles. The asynchronous bus load balancing unit adjusted the bus request signal duty cycle to 15.5% with a value of 0.12. The measured inter-node transmission delay jitter deviation was 1.25ms, the latch-up occurrence count was 0, and after the load increased to the medium load level, the queue depth input increased to 4096 bytes. Reduced to 32 clock cycles; obtained through calculation The bus request signal duty cycle is adjusted to 38.2% to 0.34, the inter-node transmission delay jitter deviation is 3.48ms, the latch-up count is still 0, and when entering the high load stage, the queue depth input reaches 8192 bytes. It takes 15 clock cycles; The bus request signal duty cycle was increased to 0.68, the inter-node transmission delay jitter deviation was 7.62ms, and the latch-up occurrence count was 0.

[0046] Control group 1 used the same 8192-byte queue depth input and 15 clock cycles as the experimental group during high-load conditions. Because this group does not have an asynchronous bus load balancing unit, the control word of the bus configuration register does not change with the load. The bus request signal duty cycle remains at 10%, the inter-node transmission delay jitter deviation increases to 45.18ms, and the latch-up occurrence count is 0.

[0047] In control group two, the queue depth input was 12288 bytes under high load conditions. The asynchronous bus load balancing unit outputs for 5 clock cycles. The value was 0.95, and the duty cycle of the bus request signal was adjusted to 95%. Since the group did not have a timing burst cutoff control module, the continuous transmission of a single master control board was not limited by the bus occupancy time parameter. The burst transmission actions of each master control board continued to cause timing contention at the asynchronous clock domain boundary. The bus transceiver pins entered a level metastable state, and the transmission delay jitter deviation between nodes reached 88.55ms. The latch-up occurrence count was 4.

[0048] In control group three, the queue depth input was 8192 bytes under high load. For 15 clock cycles, After setting the value below the lower limit of the range, the arithmetic logic unit outputs... The bus request signal duty cycle was 1.85, rising to 99%. The timing burst cutoff control module repeatedly pulled the bus enable signal low due to the bus occupancy time parameter frequently exceeding the constant time threshold, causing each main control board to continuously yield during bus control. The inter-node transmission delay jitter deviation increased to 124.36 ms, and the latchup occurrence count was 0. This data was used to determine... The operating range is limited to avoid excessively frequent truncation of the bus enable signal.

[0049] When the queue depth input exceeds 85% of the local transmit buffer's safe capacity, the bus request signal duty cycle enters the saturation region limited by the bus's physical bandwidth, and continues to increase thereafter. The increase in duty cycle cannot provide the corresponding effective bus bandwidth. Instead, the jitter deviation of the transmission delay between nodes increases with frequent bus yielding. The test group adjusts the duty cycle of the bus request signal through the asynchronous bus load balancing unit, and limits the continuous occupation time of a single main control board by the timing burst truncation control module, so that the jitter deviation of the transmission delay between nodes under high load conditions is kept within 8ms.

[0050] When mechanical vibration and contact resistance fluctuations coexist, the state machine arbitration module inside the video decoding main control board A controls the time counting unit to start a 15ns rest window countdown when the bus request signal changes to a high level. The shielding gate unit locks the bus request signal flip detection within this rest window, blocking the parasitic level glitches caused by contact resistance fluctuations from being written to the local bus configuration register.

[0051] After the rest window timer ends, the state machine arbitration module initiates a 2.5ns secondary hardware verification cycle and resamples the bus request signal three times within this cycle. If all three resampling results are stable high levels, the state machine arbitration module determines the signal as a normal bus request and allows it to be written to the local bus configuration register. If the resampling results still show transitions, the state machine arbitration module rejects the signal trigger and maintains the current polling state. This process ensures that signal verification continues during the transition phase after the rest window ends and distinguishes stable bus request signals from persistent parasitic level glitches.

[0052] When the timing collision occurs between the timing interruption control module pulling down the bus enable signal and the sudden transmission action inside the main control board, the discrete hardware watchdog reset module monitors the bus release control signal and the latching state of the time-division multiplexed bus module. If the latching state lasts for more than 50ms, its internal discharge circuit outputs a reset pulse level to the global reset pin of each type of audio and video main control board, resetting the hardware state machine and clearing the latching state.

[0053] Test results show that the bus request signal duty cycle adjustment and bus enable signal truncation together limit the burst transmission time of each main control board. The shielding gating unit and secondary hardware verification cycle block the level glitches caused by contact resistance fluctuations. The discrete hardware watchdog reset module restores the bus polling state after the lockout timeout. As a result, the burst transmission of each main control board is completed within a certain time range, and the bandwidth allocation and lockout recovery of the time-division multiplexing bus module are kept within the set working range.

[0054] Example 3: In this example, the clock dynamic compensation module is used in the central interconnection backplane of an industrial control computer for high-capacity, dense video stream conversion. The transmitting and receiving main control boards are continuously under high load computing. The local ambient temperature inside the chassis gradually rises to the set physical limit of 65°C. The quartz crystal oscillator on the video decoding main control board A is affected by thermal stress, resulting in nonlinear frequency drift. This causes timing broadening of the data waveform of the asynchronous physical bus, accompanied by phase drift of the differential clock signal. If the bus timing judgment threshold cycle number is not adjusted in time, the state machine arbitration module will capture metastable levels due to insufficient setup time when sampling asynchronous data pins, thereby erroneously triggering sudden transmission interruption or forming bus lockout, thus causing abnormal audio and video data display in the upper-layer system.

[0055] The onboard bus communication control integrated circuit of the video decoding main control board A includes a clock dynamic compensation module and a decision threshold calibrator. The temperature acquisition interface module is connected to the on-chip negative temperature coefficient thermistor network to acquire real-time temperature parameters of the local area of ​​the backplane slot. The analog-to-digital converter within the threshold calibrator will... The corresponding voltage signal is converted into an 8-bit digital logic control word. The clock dynamic compensation module, based on the on-chip subtractor logic circuit, corrects the threshold control register according to this digital logic control word and calculates the number of bus timing judgment threshold cycles. The calculation relationship is as follows: ,in, The number of cycles for determining the bus timing threshold. To preset the baseline threshold number of cycles, This is the gain coefficient for temperature drift compensation. For real-time temperature parameters, subscript Indicates the decision threshold. Indicates the reference, Indicates temperature drift compensation. Indicates temperature.

[0056] The clock dynamic compensation module uses cascaded shift registers to... Discretized step mapping is performed, and the temperature acquisition interface module reads the digital temperature register every 2.5μs through the serial peripheral interface to update it. ,when When the temperature is between 25℃ and 40℃, Maintaining the first preset slope, the discretized mapping yields... Stable for 40 clock cycles; when When the temperature exceeds 40°C and continues to rise to 65°C, the threshold calibrator will... Switching to the second preset slope with a higher weighting causes the built-in temperature drift characteristic curve to decrease monotonically within this temperature range. The time was gradually reduced in a nonlinear step manner, and decreased to 25 clock cycles at 65°C.

[0057] The clock dynamic compensation module will The corresponding numerical control word is written to the time counting unit of the state machine arbitration module. At the same time, it triggers the switched capacitor array in the differential clock jitter phase-locked loop to change the bias current and fine-tune the time-domain phase of the local sampling clock to compensate for the 0.15ns pin transmission delay. The state machine arbitration module thus completes the level latching of the bus request signal and the bus status response line within the shortened decision window, avoiding timing overlap misjudgment caused by temperature drift.

[0058] along with As the temperature gradually decreases to 25 clock cycles, the setup and hold times of the hardware state machine remain within the tolerances allowed by the bus physical specifications. After running continuously for 168 hours at 65°C, the bus configuration registers of various types of audio and video main control boards do not experience latch-up errors due to timing collisions. The bit error rate of asynchronous bus data packets on the interconnect backplane drops to less than one billionth. The lag in high-definition audio and video stream transmission caused by timing widening is effectively suppressed, and the frame rate of multi-channel splicing output from the industrial control computer remains stable.

[0059] Example 4: This example combines Figures 1 to 2 This paper describes a collaborative scheduling control system and method for multiple types of audio and video main control boards, such as... Figure 1 As shown, the real-time temperature parameters output by the temperature acquisition interface module are connected to the input of the clock dynamic compensation module. The output of the clock dynamic compensation module is connected to the time-division multiplexing bus module by adjusting the judgment threshold. The multi-type audio and video main control board is connected to the state machine arbitration module by releasing and high-level signal. The state machine arbitration module includes a time counting unit and a shielding gate control unit. The output of the state machine arbitration module is connected to the time-division multiplexing bus module by starting the rest window. The multi-type audio and video main control board is connected to the timing burst truncation control module by continuously occupying the bus. The timing burst truncation control module includes an internal counting unit and a drive control unit. The output of the timing burst truncation control module is connected to the time-division multiplexing bus module by pulling low enable release.

[0060] like Figure 2As shown, when the bus request signal changes and is transiently triggered, the system transitions to the resting window counting state. The time counting unit starts a 15ns countdown. After completing the level latch within the decision window, the system enters the bus occupancy state, and the internal counting unit begins to accumulate. There are two transition paths thereafter: if the multi-type audio and video main control board releases its usage rights, the system returns to the bus idle state. At this time, the bus request signal remains high and the toggle detection is locked. If the bus occupancy time parameter is greater than the time threshold, the system transitions to the burst cutoff control state, pulls the bus enable signal low, and executes the bus release through the drive control unit, ultimately causing the system to return to the bus idle state.

[0061] Example 5: During the power-on initialization phase, the current video decoding main control board A connects to the time-division multiplexing bus module. Due to the difference in lead lengths on the interconnect backplane, the judgment threshold calibrator in the bus communication control integrated circuit initiates the pre-physical calibration timing sequence, sending a fixed number of probe pulse waveforms to the time-division multiplexing bus module. The on-chip hardware counter measures the round-trip physical delay of the probe pulse waveforms. The on-chip arithmetic logic unit converts the measured round-trip physical delay into a reference clock cycle control word and writes this control word into the control register to reset the preset reference threshold cycle number. .

[0062] During bus idle periods, the streaming media forwarding main control board C reads the reference clock cycle control word from the control register, uses it as the initialization control word, and drives the on-chip negative temperature coefficient thermistor network to output the initial reference voltage under cold conditions. The analog-to-digital converter in the threshold calibrator converts the initial reference voltage into a zero-point compensation control word and writes it to the bias register of the clock dynamic compensation module to compensate for the inherent hardware deviation of the real-time temperature parameter acquisition link. After zero-point compensation is completed, the bus communication control integrated circuit calculates the number of bus timing determination threshold cycles based on the real-time temperature parameters. At that time, it is no longer affected by the inherent deviation of the hardware, thereby completing the initial reference alignment of the bus configuration registers between various types of audio and video main control boards.

[0063] Example 6: When dynamic impedance fluctuations occur at the contacts of the centralized control slot, the multi-type audio and video main control board collaborative scheduling control system initiates the parameter calibration process. The frequency division cascaded phase loop in the state machine arbitration module captures the degradation time of the rising edge of the transmission line waveform. The time counting unit converts this time into a delay impedance control word and writes it into the local bus configuration register to compensate for burst transmission delay lag. The threshold calibrator simultaneously calls the internal logic gate array to calculate the time slice configuration reference based on the voltage sampling value of the bus physical pins, and sets the constant time threshold of the timing burst truncation control module accordingly. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit pulls down the bus enable signal of the corresponding multi-type audio and video main control board and generates a bus release control signal. This calibration process enables the time-division multiplexing bus module to adjust the multiplexing timing when the signal time domain shifts, reducing the state machine lockout caused by pulse glitches generated by contact impedance fluctuations.

[0064] After the state machine arbitration module writes the delay impedance control word, the time-division multiplexing bus module maintains the transmission delay jitter deviation between nodes within 8ms under 1000h of high temperature vibration stress. The shielding gate unit locks the toggle detection of the bus request signal within the resting window, blocks the pulse glitches caused by sudden changes in pin impedance from being written to the local bus configuration register, and keeps the asynchronous data stream between the streaming media forwarding main control board C and the video decoding main control board A in throughput matching.

[0065] In high-noise environments, the discrete hardware watchdog reset module monitors the duration of the bus release control signal and the latching status of the time-division multiplexing bus module. When the duration of the bus release control signal exceeds the time limit and the latching of the time-division multiplexing bus module exceeds 50ms, its internal discharge circuit outputs a reset pulse level to the global reset pin of each type of audio and video main control board to clear the cascaded communication latching caused by clock timing collision, so that the slot topology is restored to the initial polling cycle. After the polling is restored, the queuing delay fluctuation amplitude of multiple audio and video streams decreases monotonically, and the effective bandwidth utilization of the system bus remains stable.

[0066] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A collaborative scheduling and control system for multiple types of audio and video main control boards, characterized in that, The system includes: The clock dynamic compensation module is connected to the temperature acquisition interface module to obtain the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. The state machine arbitration module, including a time counting unit and a shielding gate unit, is used to control the time counting unit to start a 15ns rest window countdown and lock the bus request signal flip detection within the rest window through the shielding gate unit during the transient state when the time-division multiplexing bus module releases the right to use the multi-type audio and video main control board and the bus request signal in the time-division multiplexing bus module changes to a high level. The timing burst truncation control module includes an internal counting unit and a drive control unit. It is used to continuously monitor the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through the internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board and generates a bus release control signal.

2. The multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The system also includes a discrete hardware watchdog reset module; the discrete hardware watchdog reset module is connected to the timing burst cutoff control module to monitor the duration of the bus release control signal; when the duration exceeds the time limit and the time-division multiplexed bus module is locked for more than 50ms, the internal discharge circuit of the discrete hardware watchdog reset module outputs a reset pulse level to the global reset pin of multiple multi-type audio and video main control boards to clear the bus lockout state.

3. The multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The state machine arbitration module includes: an internal time counting unit that starts a 15ns rest window countdown; within the 15ns rest window, the state machine arbitration module uses an internal shielding gating unit to lock the toggle detection of the bus request signal and block the pulse signal from being written to the local bus configuration register.

4. The multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The timing burst truncation control module includes: the timing burst truncation control module continuously accumulates the number of continuous transmission cycles of a single main control board on the time-division multiplexing bus module through the internal counting unit to generate the bus occupancy time parameter; when the bus occupancy time parameter is greater than the constant time threshold, the timing burst truncation control module adjusts the bus enable signal corresponding to the single main control board to a low level through the drive control unit.

5. A multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The multi-type audio and video main control board is plugged into the backplane slot inside the external industrial control chassis; the state machine arbitration module maintains a 15ns resting window when the external mechanical vibration acceleration reaches 2g and the contact resistance at the connection between the multi-type audio and video main control board and the backplane slot fluctuates between 1Ω and 100Ω.

6. The multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The built-in temperature drift characteristic curve of the clock dynamic compensation module is a monotonically decreasing curve; when the real-time temperature parameter output by the temperature acquisition interface module rises to 65°C, the clock dynamic compensation module reduces the number of bus timing judgment threshold cycles from 40 to 25 according to the monotonically decreasing curve.

7. The multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The system also includes a performance management module; the performance management module is connected to the timing burst truncation control module, which is used to accumulate the number of times the bus occupancy time parameter is greater than the constant time threshold within the system transmission cycle and determine the bus occupancy trend index based on the time distribution of the truncation frequency. When the bus occupancy trend indicator exceeds a fixed threshold, the performance management module outputs a warning signal.

8. A multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The topology of the time-division multiplexing bus module is a PCIe bus topology architecture. The bus request signal is transmitted using the physical request link, and the bus enable signal is transmitted using the bus enable link. The input terminal of the physical request link connection state machine arbitration module, and the output terminal of the bus enable link connection timing burst truncation control module.

9. A multi-type audio / video main control board collaborative scheduling and control system according to claim 1, characterized in that, The system includes an industrial control backplane and a video decoding main control board and an audio processing main control board, which are respectively plugged into the industrial control backplane; the clock dynamic compensation module and the state machine arbitration module are built into the internal chip of the video decoding main control board, and the timing burst truncation control module and the discrete hardware watchdog reset module are built into the control chip of the industrial control backplane.

10. A collaborative scheduling and control method for multiple types of audio and video main control boards, used to run the collaborative scheduling and control system for multiple types of audio and video main control boards as described in claim 1, characterized in that, Includes the following steps: Step S1: The clock dynamic compensation module connects to the temperature acquisition interface module and obtains the real-time temperature parameters output by the temperature acquisition interface module. When the real-time temperature parameters rise, the threshold cycle number is determined by monotonically reducing the bus timing according to the built-in temperature drift characteristic curve. Step S2: When the multi-type audio and video main control board releases the right to use the time-division multiplexing bus module and the bus request signal in the bus request signal link becomes high-level transient, the state machine arbitration module controls the time counting unit to start a 15ns rest window countdown, and locks the toggle detection of the bus request signal through the shielding gate control unit within the rest window. Step S3: The timing burst cutoff control module continuously monitors the bus occupancy time parameter of a single main control board continuously occupying the time-division multiplexing bus module through its internal counting unit. When the bus occupancy time parameter is greater than the constant time threshold, the drive control unit forcibly pulls down the bus enable signal corresponding to the single main control board in the bus enable signal link, and generates a bus release control signal.

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