A multi-chip system and a reset method thereof, and a server

Abstract

This application relates to a multi-chip system and its reset method, as well as a server. The system includes a first computing card, a second computing card, and a first switching chip; the first computing card includes a first chip and a second chip; the second computing card includes a third chip and a fourth chip; the management bus interface of the first switching chip is only connected to the first chip; the second, third, and fourth chips are all directly connected to the first chip; after power-on, the first chip is used to detect its own PCIe link; after completing its own PCIe link detection, it sequentially detects the PCIe links of the second, third, and fourth chips; if the PCIe links of the first, second, third, and fourth chips are all abnormal, the first chip is also used to control the uplink port of the first switching chip to simultaneously perform a reset operation on all chips through the management bus interface. This application can improve the problem of poor universality in existing PCIe link abnormality repair schemes.

Description

Technical Field

[0001] This application belongs to the field of computer science, specifically relating to a multi-chip system and its reset method, and a server. Background Technology

[0002] With the development of artificial intelligence and high-performance computing, graphics processing units (GPUs), as core PCIe (Peripheral Component Interconnect express) devices, are widely used in various server scenarios due to their powerful parallel computing capabilities. However, during PCIe link negotiation between the GPU and the server motherboard's CPU (Central Processing Unit), occasional failures sometimes occur, mainly manifesting as bandwidth loss or speed reduction. Although such problems are rare, once they occur, they directly affect the GPU's computing performance, leading to a decrease in the efficiency of AI training or inference tasks.

[0003] To address the aforementioned PCIe link anomalies, existing technologies have proposed several remediation solutions, but most of these solutions rely on the complete server system. For example, the remediation logic typically requires firmware from the server system's BIOS (Basic Input / Output System) and BMC (Baseboard Management Controller). Different manufacturers and server models often exhibit significant differences in firmware interfaces, command structures, and underlying implementations. This necessitates that developers perform specialized adaptation and debugging for each new server platform. Due to the diverse sources of hardware and firmware and varying interface standards within server systems, extensive customization is required for each server adaptation. This not only results in poor universality of the remediation solutions but also significantly increases deployment and maintenance costs.

[0004] Therefore, how to quickly and accurately reset abnormal GPUs without relying on a complete server system and without customizing adaptations for different servers has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a multi-chip system and its reset method and server, so as to improve the problem of insufficient universality caused by the reliance on server system in the existing PCIe link anomaly repair scheme.

[0006] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a multi-chip system, including: a first computing card, a second computing card, and a first switching chip; a first downlink port of the first switching chip is connected to the first computing card, and a second downlink port of the first switching chip is connected to the second computing card; the first computing card includes a first chip and a second chip; the second computing card includes a third chip and a fourth chip; the management bus interface of the first switching chip is only connected to the first chip; the second chip, the third chip, and the fourth chip are all directly connected to the first chip. Upon power-up, the first chip is used to detect its own PCIe link; after completing its own PCIe link detection, it sequentially detects the PCIe links of the second chip, the third chip, and the fourth chip; it determines whether the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal; if the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal, the first chip is also used to control the uplink port of the first switching chip to simultaneously perform a reset operation on all chips through the management bus interface.

[0007] In the above implementation scheme, the multi-chip system with the aforementioned structure allows the entire multi-chip system to function as a single PCIe device, connected to the server system via a single PCIe slot. This allows for the placement of more chips within the same server space, effectively improving overall computing performance to meet the increasing demands of AI computing power. Furthermore, this multi-chip system structure enables the management module in the first chip to directly access and control the first switching chip via the management bus interface. Upon power-up, the first chip sequentially checks the PCIe links of the first, second, third, and fourth chips, further determining whether all four PCIe links are abnormal. If so, the uplink port of the first switching chip simultaneously performs a reset operation on all four chips. This allows for rapid recovery of abnormal links, providing a reset method that does not rely on a complete server system or require customized adaptation for different servers. It enables rapid and accurate reset of abnormal PCIe links by relying on the PCIe device itself, improving the poor versatility of existing PCIe link anomaly repair solutions.

[0008] In one possible implementation of the first aspect embodiment, when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, the first chip is further configured to determine whether the PCIe links of the first chip and the second chip are all abnormal; when the PCIe links of the first chip and the second chip are all abnormal, the first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0009] In the above implementation scheme, when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, it is further determined whether the PCIe links of the first chip and the second chip are abnormal. If they are, the first downlink port of the first switching chip is controlled to realize the overall reset operation of the first chip and the second chip. Compared with resetting them one by one, this can greatly improve efficiency.

[0010] In one possible implementation of the first aspect embodiment, the first computing card further includes: a second switching chip, wherein the management bus interface of the second switching chip is connected only to the first chip, the downlink port of the second switching chip is connected to the first chip and the second chip is connected, and the uplink port of the second switching chip is connected to the first downlink port of the first switching chip; when the first chip is abnormal and the second chip is normal, the first chip is further configured to control the second switching chip through the management bus interface to perform a reset operation on the first chip; or, when the second chip is abnormal and the first chip is normal, the first chip is further configured to control the second switching chip through the management bus interface to perform a reset operation on the second chip.

[0011] In the above implementation scheme, a second switching chip can be further configured to connect the first chip and the second chip. When the PCIe link of any chip in the first chip or the second chip is abnormal, the corresponding downlink port of the second switching chip can be controlled to perform a targeted reset of the chip with abnormal PCIe link without affecting the chip with normal PCIe link. This can accurately restore the link status of the abnormal chip and avoid interference with the normal chip, thereby improving the overall stability and availability of the system.

[0012] In one possible implementation of the first aspect embodiment, the first computing card further includes: a second switching chip, wherein the management bus interface of the second switching chip is connected only to the first chip, the downlink port of the second switching chip is connected to the first chip and the second chip, and the uplink port of the second switching chip is connected to the first downlink port of the first switching chip; when the PCIe links of the first chip and the second chip are both abnormal, but the PCIe link of at least one of the third chip and the fourth chip is normal, the first chip is further configured to control the uplink port of the second switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0013] In the above implementation scheme, a second switching chip can be further configured to connect the first chip and the second chip. Since the uplink port of the second switching chip is connected to the first downlink port of the first switching chip, when the PCIe links of the first chip and the second chip are both abnormal, in addition to controlling the first downlink port of the first switching chip to perform a reset operation on the first chip and the second chip, the uplink port of the second switching chip can also be controlled to perform a reset operation on the first chip and the second chip. In this way, the reset efficiency is improved while increasing the implementation flexibility of the scheme.

[0014] In one possible implementation of the first aspect embodiment, when not all PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, the first chip is further configured to determine whether the PCIe links of the third chip and the fourth chip are all abnormal; when the PCIe links of the third chip and the fourth chip are all abnormal, the first chip controls the second downlink port of the first switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

[0015] In the above implementation scheme, when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, it is further determined whether the PCIe links of the third chip and the fourth chip are all abnormal. If they are, the second downlink port of the first switching chip is controlled to realize the overall reset operation of the third chip and the fourth chip. Compared with resetting them one by one, this can greatly improve efficiency.

[0016] In one possible implementation of the first aspect embodiment, the second computing card further includes: a third switching chip, wherein the management bus interface of the third switching chip is connected only to the first chip, the downlink port of the third switching chip is connected to the third chip and the fourth chip, and the uplink port of the third switching chip is connected to the second downlink port of the first switching chip; when the third chip is malfunctioning and the fourth chip is functioning normally, the first chip is further configured to control the third switching chip through the management bus interface to perform a reset operation on the third chip; or, when the fourth chip is malfunctioning and the third chip is functioning normally, the first chip is further configured to control the third switching chip through the management bus interface to perform a reset operation on the fourth chip.

[0017] In the above implementation scheme, a third switching chip can be further set up to connect the third chip and the fourth chip. When the PCIe link of any chip in the third chip or the fourth chip is abnormal, the corresponding downlink port of the third switching chip can be controlled to achieve targeted reset of the chip with abnormal PCIe link without affecting the chip with normal PCIe link. This can accurately restore the link status of the abnormal chip and avoid interference with the normal chip, thereby improving the overall stability and availability of the system.

[0018] In one possible implementation of the first aspect embodiment, the second computing card further includes: a third switching chip, the management bus interface of which is connected only to the first chip, the downlink port of which is connected to the third chip and the fourth chip, and the uplink port of which is connected to the second downlink port of the first switching chip; in the case that the PCIe links of the third chip and the fourth chip are both abnormal, but the PCIe link of at least one of the first chip and the second chip is normal, the first chip is further configured to control the uplink port of the third switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

[0019] In the above implementation scheme, a third switching chip can be further configured to connect the third chip and the fourth chip. Since the uplink port of the third switching chip is connected to the second downlink port of the first switching chip, when the PCIe links of the third chip and the fourth chip are both abnormal, in addition to controlling the second downlink port of the first switching chip to perform a reset operation on the third chip and the fourth chip, the uplink port of the third switching chip can also be controlled to perform a reset operation on the third chip and the fourth chip. In this way, the reset efficiency is improved while increasing the implementation flexibility of the scheme.

[0020] In one possible implementation of the first aspect embodiment, when the PCIe links of the second chip, the third chip, and the fourth chip are abnormal, they all send abnormal information indicating their own link abnormality to the first chip; the first chip is specifically used to detect the PCIe link of the corresponding chip by sequentially detecting whether it receives the abnormal information sent by the second chip, the third chip, and the fourth chip.

[0021] In the above implementation, when the PCIe links of the second chip, the third chip, and the fourth chip are abnormal, they actively send abnormal information indicating their own link abnormality to the first chip. In this way, the first chip only needs to determine whether the other party's link is abnormal by judging whether it has received the abnormal information sent by the other party. Compared with the method of the first chip actively accessing the other party to obtain the other party's PCIe link, the processing overhead of the first chip can be reduced, while improving the response speed of abnormality detection.

[0022] In one possible implementation of the first aspect embodiment, the target chip is connected to the first chip via an I / O pin; wherein the target chip is one of the second chip, the third chip, and the fourth chip; the target chip is configured to send an abnormal signal indicating its own link abnormality to the first chip by setting the I / O pin high; and after a preset time interval, set the I / O pin low.

[0023] In the above implementation scheme, when the target chip and the first chip are connected through IO pins, the target chip only needs to set the IO pins high to send an abnormal signal indicating its own link abnormality to the first chip. This not only achieves fast and reliable transmission between chips, but also has simple hardware implementation and low cost. At the same time, after a preset interval, the IO pins are set low to restore the initial value, which makes it easy to set the IO pins high again in the future.

[0024] In one possible implementation of the first aspect embodiment, the target chip is further configured to: obtain the current number of times the abnormal information is sent before sending abnormal information indicating its own link abnormality to the first chip; determine whether the number of times the abnormal information is sent is greater than a preset number; and if the number of times the abnormal information is sent is less than the preset number, send the abnormal information indicating its own link abnormality to the first chip and update the number of times the abnormal information is sent.

[0025] In the above implementation scheme, before sending the abnormal information, it is first determined whether the current number of transmissions is greater than the preset number. Only when the number of transmissions is less than the preset number, the abnormal information is sent and the number of transmissions is updated. This can not only restore the abnormal PCIe device as much as possible through a limited number of operations, but also terminate invalid operations in time after reaching the preset limit, avoiding the system from falling into an infinite loop. Thus, while ensuring the success rate of recovery, the overall repair time is effectively controlled.

[0026] In one possible implementation of the first aspect embodiment, the IO pin includes a first IO pin and a second IO pin. The first IO pin is used by the target chip to send the abnormal information, and the second IO pin is used by the first chip to send feedback information indicating that the target chip has been reset. The first chip is also used to return the feedback information to the target chip through the second IO pin after completing the reset operation on the target chip. The target chip is also used to re-detect its own PCIe link after receiving the feedback information returned by the first chip. If the PCIe link is still abnormal, it sends the abnormal information to the first chip again. This continues until the PCIe link is normal or the number of transmissions reaches a preset number.

[0027] In the above implementation scheme, a second I / O pin can be added. After the first chip completes the reset operation on the target chip, it can pull the second I / O pin high to send feedback to the target chip. This allows the target chip to re-check its PCIe link upon receiving the feedback, avoiding invalid checks due to incomplete reset, thereby improving the reliability and efficiency of the coordinated reset. Simultaneously, by setting a preset number of transmissions, the system is forcibly terminated when the preset number of transmissions is reached, preventing the system from entering an infinite loop. This ensures a high recovery success rate while effectively controlling the overall repair time.

[0028] In one possible implementation of the first aspect embodiment, the first chip is further configured to, after completing the reset operation of all chips with link abnormalities, sequentially detect the PCIe links of the first chip, the second chip, the third chip, and the fourth chip again, and perform a reset operation on the chips with link abnormalities.

[0029] In the above implementation scheme, after completing the reset operation for all chips with link anomalies, the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are repeatedly tested, and the chips with link anomalies are reset. By resetting multiple times, link failures caused by persistent anomalies can be effectively reduced, and the recovery success rate can be improved.

[0030] Secondly, embodiments of this application also provide a server, including: a server motherboard and a multi-chip system provided as described in the first aspect embodiment and / or in combination with any possible implementation of the first aspect embodiment; the uplink port of a first switching chip in the multi-chip system is connected to a PCIe slot of the server motherboard.

[0031] Thirdly, embodiments of this application also provide a reset method for a multi-chip system, the multi-chip system comprising: a first computing card, a second computing card, and a first switching chip, wherein a first downlink port of the first switching chip is connected to the first computing card, and a second downlink port of the first switching chip is connected to the second computing card; the first computing card comprises a first chip and a second chip; the second computing card comprises a third chip and a fourth chip; the management bus interface of the first switching chip is only connected to the first chip; the second chip, the third chip, and the fourth chip are all directly connected to the first chip; the method comprises: after power-on, the first chip detects its own PCIe link; after completing its own PCIe link detection, the first chip sequentially detects the PCIe links of the second chip, the third chip, and the fourth chip; determining whether the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal; if the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal, the first chip controls the uplink port of the first switching chip through the management bus interface to simultaneously perform a reset operation on all chips.

[0032] In one possible implementation of the third aspect embodiment, the method further includes: when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, determining whether the PCIe links of the first chip and the second chip are all abnormal; when the PCIe links of the first chip and the second chip are all abnormal, the first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0033] In one possible implementation of the third aspect embodiment, the first computing card further includes: a second switching chip, wherein the management bus interface of the second switching chip is connected only to the first chip, the downlink port of the second switching chip is connected to the first chip and the second chip is connected, and the uplink port of the second switching chip is connected to the first downlink port of the first switching chip. The method further includes: when the first chip is abnormal and the second chip is normal, the first chip controls the second switching chip through the management bus interface to perform a reset operation on the first chip; or, when the second chip is abnormal and the first chip is normal, the first chip controls the second switching chip through the management bus interface to perform a reset operation on the second chip.

[0034] In one possible implementation of the third aspect embodiment, the first computing card further includes: a second switching chip, the management bus interface of the second switching chip being connected only to the first chip, the downlink port of the second switching chip being connected to the first chip and the second chip, and the uplink port of the second switching chip being connected to the first downlink port of the first switching chip; the method further includes: when the PCIe links of the first chip and the second chip are both abnormal, but the PCIe link of at least one of the third chip and the fourth chip is normal, the first chip controls the uplink port of the second switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0035] In one possible implementation of the third aspect embodiment, the method further includes: when not all PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, determining whether the PCIe links of the third chip and the fourth chip are all abnormal; when the PCIe links of the third chip and the fourth chip are all abnormal, the first chip controls the second downlink port of the first switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

[0036] In one possible implementation of the third aspect embodiment, the second computing card further includes: a third switching chip, the management bus interface of which is connected only to the first chip, the downlink port of which is connected to the third chip and the fourth chip, and the uplink port of which is connected to the second downlink port of the first switching chip; the method further includes: when the third chip is abnormal and the fourth chip is normal, the first chip controls the third switching chip through the management bus interface to perform a reset operation on the third chip; or, when the fourth chip is abnormal and the third chip is normal, the first chip controls the third switching chip through the management bus interface to perform a reset operation on the fourth chip.

[0037] In one possible implementation of the third aspect embodiment, the second computing card further includes: a third switching chip, the management bus interface of which is connected only to the first chip, the downlink port of which is connected to the third chip and the fourth chip, and the uplink port of which is connected to the second downlink port of the first switching chip; the method further includes: when the PCIe links of the third chip and the fourth chip are both abnormal, but the PCIe link of at least one of the first chip and the second chip is normal, the first chip controls the uplink port of the third switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

[0038] In one possible implementation of the third aspect embodiment, the method further includes: when the PCIe links of the second chip, the third chip, and the fourth chip are abnormal, each of them sends abnormal information indicating its own link abnormality to the first chip; correspondingly, the first chip sequentially detects the PCIe links of the second chip, the third chip, and the fourth chip, including: the first chip sequentially detects the PCIe links of the corresponding chips by detecting whether it receives abnormal information sent by the second chip, the third chip, and the fourth chip.

[0039] In one possible implementation of the third aspect embodiment, the target chip is connected to the first chip via an I / O pin; the target chip is one of the second chip, the third chip, and the fourth chip; sending abnormal information indicating its own link abnormality to the first chip includes: sending an abnormal signal indicating its own link abnormality to the first chip by setting the I / O pin high; and setting the I / O pin low after a preset time interval.

[0040] In one possible implementation of the third aspect embodiment, before sending abnormal information indicating a link abnormality to the first chip, the method further includes: obtaining the current number of times the abnormal information is sent; determining whether the number of times the information is sent is greater than a preset number; if the number of times the information is sent is less than the preset number, sending abnormal information indicating a link abnormality to the first chip, and updating the number of times the information is sent.

[0041] In one possible implementation of the third aspect embodiment, the IO pin includes a first IO pin and a second IO pin. The first IO pin is used by the target chip to send the abnormal information, and the second IO pin is used by the first chip to send feedback information indicating that the target chip has been reset. The method further includes: after completing the reset operation on the target chip, the first chip returns the feedback information to the target chip through the second IO pin; after receiving the feedback information returned by the first chip, the target chip checks its own PCIe link again; if the PCIe link is still abnormal, it sends the abnormal information to the first chip again; until the PCIe link is normal, or the number of times it sends the information reaches a preset number.

[0042] In one possible implementation of the third aspect embodiment, the method further includes: after the first chip completes the reset operation for all chips with link abnormalities, it sequentially detects the PCIe links of the first chip, the second chip, the third chip, and the fourth chip again, and performs a reset operation on the chips with link abnormalities.

[0043] The technical effects of any of the implementation methods in the second to third aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0044] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0046] Figure 1a A schematic diagram of the structure of a first multi-chip system provided in an embodiment of this application is shown.

[0047] Figure 1b A schematic diagram of the structure of a second multi-chip system provided in an embodiment of this application is shown.

[0048] Figure 2a A schematic diagram of the SMBus topology of the first multi-GPU system provided in this application embodiment is shown.

[0049] Figure 2b A schematic diagram of the SMBus topology of a second multi-GPU system provided in this application embodiment is shown.

[0050] Figure 3 It shows Figure 2a The diagram shows a possible reset procedure for a multi-chip system with the topology shown.

[0051] Figure 4 It shows Figure 2b The diagram shows a possible reset process for the target chip under the topology shown.

[0052] Figure 5 It shows Figure 2b The diagram shows a possible reset procedure for a multi-chip system with the topology shown.

[0053] Figure 6 A flowchart illustrating a reset method for a multi-chip system provided in an embodiment of this application is shown. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0055] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0056] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0057] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0058] This application provides a multi-chip system and its reset method and server, which can quickly and accurately reset abnormal PCIe devices without relying on a complete server system or requiring customized adaptation for different servers, thereby improving the lack of universality of existing PCIe link anomaly repair solutions due to reliance on server systems.

[0059] The following is combined Figure 1a , Figure 1b The structure of the multi-chip system provided in this application embodiment will be described. The multi-chip system includes: a first computing card, a second computing card, and a first switching chip; a first downlink port of the first switching chip is connected to the first computing card, a second downlink port of the first switching chip is connected to the second computing card, and an uplink port of the first switching chip is used to connect to a PCIe slot on a server motherboard, enabling the multi-chip system to be accessed by a single PCIe slot into a server system (including the server motherboard). By connecting to the server motherboard through the uplink port of the first switching chip, the multi-chip system can be accessed as a single PCIe device by the CPU in the server motherboard.

[0060] The multi-chip system in this application is a single-slot multi-chip PCIe device that can be connected to a server system through a single PCIe slot. Since the multi-chip system contains multiple chips (such as a first chip, a second chip, a third chip, and a fourth chip), it can accommodate a larger number of chips (such as GPU chips) in the same server space.

[0061] In some implementations, such as Figure 1a As shown, the first computing card includes a first chip and a second chip; the second computing card includes a third chip and a fourth chip. By controlling the first downlink port of the first switching chip, the first computing card can be reset. Resetting the first computing card simultaneously resets both the first and second chips. Similarly, by controlling the second downlink port of the first switching chip, the second computing card can be reset. Resetting the second computing card simultaneously resets both the third and fourth chips.

[0062] In some possible implementations, such as Figure 1b As shown, the first computing card also includes a second switching chip. That is, the first computing card includes a first chip, a second chip, and a second switching chip. The downlink ports of the second switching chip are connected to the first chip and the second chip, with one downlink port connecting to one chip. For example, the first downlink port of the second switching chip is connected to the first chip, and the second downlink port of the second switching chip is connected to the second chip; the first downlink port of the third switching chip is connected to the third chip, and the second downlink port of the third switching chip is connected to the fourth chip. The uplink port of the second switching chip is connected to the first downlink port of the first switching chip. Because the uplink port of the second switching chip is connected to the first downlink port of the first switching chip, controlling the first downlink port of the first switching chip (equivalent to controlling the uplink port of the second switching chip) can reset all downlink port chips connected to the second switching chip.

[0063] In some possible implementations, the second computing card further includes a third switching chip. That is, the second computing card includes a third chip, a fourth chip, and a third switching chip. The downlink ports of the third switching chip are connected to the third chip and the fourth chip, with one downlink port connected to one chip. The uplink port of the third switching chip is connected to the second downlink port of the second switching chip. Since the uplink port of the third switching chip is connected to the second downlink port of the first switching chip, controlling the second downlink port of the first switching chip (equivalent to controlling the uplink port of the third switching chip) can reset all downlink port chips connected to the third switching chip.

[0064] The first, second, third, and fourth chips in this application can be of the same type, different types, or some of them can be the same type while others are of different types, to adapt to diverse application needs. In the following examples, only chips of the same type will be used.

[0065] The first, second, third, and fourth chips in this application include, but are not limited to, GPU chips, AI chips, and other acceleration chips, such as accelerated processing units (APs), or other processors, such as network processors (NPs), multimedia application processors (MAPs), microprocessors, etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; and they can also be other conventional processors, etc. Subsequent examples primarily use GPUs as examples.

[0066] In this application, the second, third, and fourth chips are all directly connected to the first chip, enabling unidirectional or bidirectional information (including data or signals) transmission via this direct connection. In some implementations, the first chip can access the second, third, and fourth chips through this direct connection to obtain the PCIe link status (i.e., whether the PCIe link is normal or abnormal). In other implementations, the second, third, and fourth chips may proactively send abnormal information indicating their own link abnormality to the first chip when an abnormality occurs.

[0067] In some implementations, direct connection can be achieved via I / O (input / output) pins. I / O pins may include only one pin, or they may include a first I / O pin and a second I / O pin.

[0068] In addition to direct connection via IO pins, direct communication can also be achieved through other communication interfaces. For example, the first chip and the second chip, the third chip, and the fourth chip can communicate directly through serial communication interfaces such as I²C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), and SPI (Serial Peripheral Interface).

[0069] In an SMBus (System Management Bus) topology, the first switching chip acts as a slave, and its management bus interface is connected only to the chip acting as the master (i.e., the first chip). Similarly, the second switching chip acts as a slave, and its management bus interface is connected only to the chip acting as the master (i.e., the first chip). Likewise, the third switching chip acts as a slave, and its management bus interface is connected only to the chip acting as the master (i.e., the first chip).

[0070] It is understandable that the first computing card and / or the second computing card may also include more chips. For example, the number of second chips in the first computing card may be greater than one, and similarly, the number of third and / or fourth chips in the second computing card may be greater than one.

[0071] The first, second, and third switching chips in this application may have the same structure. In some implementations, the switching chip in this application may be a switch chip. In some scenarios, the switching chip may also be a customized programmable logic device (PLD). By programming the programmable logic device, the effect of a switch chip or a simulated switch function can be achieved.

[0072] In one possible implementation, the structure of the multi-chip system provided in this application can be as follows: Figure 2a , Figure 2b As shown. Figure 2a , Figure 2b In this context, GPU0 corresponds to the first chip mentioned above, GPU1 corresponds to the second chip, GPU2 corresponds to the third chip, and GPU3 corresponds to the fourth chip. Switch2 corresponds to the first switching chip, Switch0 corresponds to the second switching chip, and Switch1 corresponds to the third switching chip. It is understandable that... Figure 2aThe diagram only shows the case where GPU1, GPU2, GPU3 and GPU0 are directly connected through a single GPIO pin. In this case, GPU1, GPU2, and GPU3 can only send information to GPU0 through this GPIO pin, but cannot receive information sent by GPU0.

[0073] Understandable Figure 2a The diagram only shows GPU1, GPU2, GPU3 connected to GPU0 via a single unidirectional GPIO pin. In this example, GPU1, GPU2, and GPU3 can only send information to GPU0 by pulling the GPIO pin high or low. In some scenarios, GPU1, GPU2, and GPU3 can also be directly connected to GPU0 via more GPIO pins. This allows GPU1, GPU2, and GPU3 to send information to GPU0 via GPIO pins (such as the first GPIO pin) and to receive feedback from GPU0 via GPIO pins (such as the second GPIO pin). Figure 2b As shown, GPU0 can send information to GPU1, GPU2, and GPU3 by pulling GPIO3 high.

[0074] In addition, GPU1, GPU2, GPU3 and GPU0 can also be directly connected in other ways. GPU0 can directly access the PCIe links of GPU1, GPU2 and GPU3.

[0075] The "PCIe 4.0 x16" designation indicates that the link supports PCIe Gen4 (fourth generation) speeds and has 16 lanes of bandwidth. Specifically, PCIe 4.0 refers to the fourth generation PCIe interface standard, with a single lane speed of 16 GT / s (gigabits per second); x16 indicates that the link consists of 16 physical lanes.

[0076] It should be noted that the Switch chip itself does not increase bandwidth. When the uplink port is only an x16 link, even if both GPUs are fully loaded simultaneously, the total bandwidth is still limited to approximately 32 GB / s (corresponding to the theoretical bandwidth of PCIe Gen4 x16). However, since the peak burst bandwidth and independent address space of each GPU are preserved, the overall computing power of the compute card can still be doubled.

[0077] It is understandable that the aforementioned computing card may also include other peripheral chips or modules, such as temperature sensors for detecting temperature, and power management integrated circuits (PMICs) for detecting power consumption and other data. Temperature sensors and PMICs are used in... Figure 1a , Figure 1b or Figure 2a , Figure 2b Not shown in the image.

[0078] Figure 2a , Figure 2b In the Switch2 chip, GPU0, GPU1, GPU2, and GPU3 are not hierarchically ranked in terms of hardware. For ease of distinction, the GPU connected to the SMBus slave interface of the Switch2 chip is designated as GPU0. The management module integrated into the GPU (such as SCPU (System Control Processing Unit) or MCU (Micro-Controller Unit)) can distinguish itself as GPU0, GPU1, GPU2, or GPU3 based on the GPU ID after power-on.

[0079] In the above architecture, since the Switch chip, as a slave device, has only one SMBus interface, it can only be accessed by one GPU (such as GPU0). When a PCIe link failure occurs in GPU1, GPU2, or GPU3, although it cannot directly control the Switch chip to perform a reset operation, it can complete the reset of GPU1, GPU2, or GPU3 through the coordination mechanism of GPU0.

[0080] After introducing the architecture of the multi-chip system shown in this application, the reset process of the multi-chip system will be explained below.

[0081] After power-on, the first chip detects its own PCIe link. After completing its own PCIe link detection, the first chip sequentially detects the PCIe links of the second, third, and fourth chips. After completing the detection of all four chips, based on the results, it determines whether the PCIe links of the first, second, third, and fourth chips are all abnormal. If the PCIe links of the first, second, third, and fourth chips are all abnormal, the first chip controls the uplink port of the first switching chip through the management bus interface to simultaneously perform a chip reset operation.

[0082] The reset operation in this application can be a hot reset operation. This can be achieved by configuring the bridge control register in the uplink port of the first switching chip through the management bus interface, thereby enabling a hot reset of all devices (including the first chip, second chip, third chip, fourth chip, etc.) connected to the first switching chip. Specifically, the secondary bus reset bit (default value 0) in the bridge control register is first written to 1 to generate a hot reset, and then the bit is written to 0 to exit the hot reset. It should be noted that when the uplink port of the switching chip receives a hot reset signal, this signal is broadcast to all downlink ports, thereby resetting all devices connected to each downlink port. Therefore, by performing a hot reset on the uplink port, the reset operation of all chips can be completed at once.

[0083] In the first implementation, when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal (i.e., at least one chip's PCIe link is normal), it can be further determined whether the PCIe links of the first chip and the second chip are both abnormal. If the PCIe links of the first chip and the second chip are both abnormal, the first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0084] Understandably, when the first computing card does not include the second switching chip, even if only one of the first or second chips experiences a PCIe link malfunction, resetting the malfunctioning chip requires controlling the first downlink port of the first switching chip to perform a complete reset of both the first and second chips. Since both the first and second chips are connected to the second downlink port of the first switching chip, a complete reset of both chips can be achieved by configuring the bridge control register in the first downlink port of the first switching chip through the management bus interface.

[0085] When the first computing card also includes a second switching chip, if the PCIe link of only one of the first and second chips is faulty, the chip with the faulty PCIe link can be reset without affecting the normal chips. For example, when the first chip is faulty and the second chip is normal, the first chip controls the first downlink port of the second switching chip through the management bus interface to perform a reset operation on the first chip; or, when the second chip is faulty and the first chip is normal, the first chip controls the second downlink port of the second switching chip through the management bus interface to perform a reset operation on the second chip.

[0086] When the first computing card also includes a second switching chip, if the PCIe links of the first chip and the second chip are both abnormal, but the PCIe link of at least one of the third chip and the fourth chip is normal, in order to perform a complete reset operation on the first chip and the second chip, the first chip can not only control the first downlink port of the first switching chip through the management bus interface to perform the reset operation on the first chip and the second chip, but also control the uplink port of the second switching chip through the management bus interface to perform the reset operation on the first chip and the second chip.

[0087] In the second implementation, when not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal (i.e., at least one chip's PCIe link is normal), it can be further determined whether the PCIe links of the third chip and the fourth chip are both abnormal. If the PCIe links of the third chip and the fourth chip are both abnormal, the first chip controls the second downlink port of the first switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

[0088] Understandably, when the second computing card does not include the third switching chip, even if only one of the third or fourth chips has a faulty PCIe link, resetting the faulty chip requires controlling the second downlink port of the first switching chip to perform a complete reset of both the third and fourth chips. Since both the third and fourth chips are connected to the second downlink port of the first switching chip, a complete reset of both chips can be achieved by configuring the bridge control register in the second downlink port of the first switching chip through the management bus interface.

[0089] When the second computing card also includes a third switching chip, if the PCIe link of only one of the third or fourth chips is faulty, the chip with the faulty PCIe link can be reset without affecting the normal chips. For example, if the third chip is faulty and the fourth chip is normal, the first chip can control the first downlink port of the third switching chip through the management bus interface to perform a reset operation on the third chip; or, if the fourth chip is faulty and the third chip is normal, the first chip can control the second downlink port of the third switching chip through the management bus interface to perform a reset operation on the fourth chip.

[0090] When the second computing card also includes a third switching chip, if the PCIe links of the third and fourth chips are both abnormal, but the PCIe link of at least one of the first and second chips is normal, in order to perform a complete reset operation on the third and fourth chips, the first chip can not only control the second downlink port of the first switching chip through the management bus interface to perform the reset operation on the third and fourth chips, but also control the uplink port of the third switching chip through the management bus interface to perform the reset operation on the third and fourth chips.

[0091] After power-on, the first, second, third, and fourth chips can each detect their own PCIe links. The management module (such as the SCPU) in each chip detects its own PCIe link by reading data (such as expected rate and expected bandwidth) from the configuration space. It compares the current bandwidth and expected rate of the PCIe link with those of the expected bandwidth and expected rate. If the current bandwidth is lower than the expected bandwidth and / or the current rate is lower than the expected rate, the PCIe link is considered abnormal. If the current bandwidth and current rate are the expected bandwidth and expected rate, the PCIe link is considered normal or meets expectations.

[0092] Understandably, in some scenarios, it is possible to compare rate and bandwidth at the same time, or to compare only rate or bandwidth.

[0093] In some implementations, when the first chip sequentially detects the PCIe links of the second, third, and fourth chips, the first chip can access the second, third, and fourth chips to obtain their PCIe link status. For example, after power-on, the second, third, and fourth chips each detect their own PCIe links and write their own PCIe link status into their internal memory. The first chip can then read the memory in the second, third, and fourth chips to obtain the PCIe link status stored in the memory.

[0094] In some implementations, the second, third, and fourth chips may not store their own PCIe link status in memory, but only write their own PCIe link's current bandwidth and current rate into memory. The first chip detects the corresponding chip's PCIe link by reading the current bandwidth and current rate and comparing them with the expected value.

[0095] The memory may be, but is not limited to, Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0096] In some implementations, the second, third, and fourth chips may proactively send their own PCIe link status to the first chip. For example, when the PCIe links of the second, third, and fourth chips are abnormal, they each send abnormal information indicating their link abnormality to the first chip. Correspondingly, the process by which the first chip sequentially detects the PCIe links of the second, third, and fourth chips may include: the first chip sequentially detecting whether it receives abnormal information from the second, third, and fourth chips to check the corresponding chip's PCIe link. If abnormal information is received, it indicates that the corresponding chip's PCIe link is abnormal; conversely, if no abnormal information is received, it indicates that the corresponding chip's PCIe link is normal.

[0097] In this application, the second chip, the third chip, and the fourth chip may have the same function. For ease of description, the target chip (one of the second chip, the third chip, and the fourth chip) will be used to refer to the second chip, the third chip, or the fourth chip in the following text.

[0098] The abnormal information may include an abnormal signal. If the target chip and the first chip are connected via IO pins, the target chip sends an abnormal information indicating its own link abnormality to the first chip. This may include: sending an abnormal signal indicating its own link abnormality to the first chip by setting the IO pin high; and after a preset time interval (configurable, such as 20ms), setting the IO pin low to restore the initial value, so that the IO pin can be set high again in the future.

[0099] It is understandable that if the first chip and the target chip are directly connected through other means (such as UART, SPI, etc.), the target chip can send reset information to the first chip by sending messages or data packets through the corresponding communication protocol. In this case, the reset information can be a message or a data packet.

[0100] In some implementations, the target chip and the first chip can be connected via one I / O pin or two I / O pins (a first I / O pin and a second I / O pin). When connected via one I / O pin, the I / O pin on the target chip side is configured as an output, and the I / O pin on the first chip side is configured as an input. When connected via two I / O pins, the first I / O pin on the target chip side is configured as an output, and the first I / O pin on the first chip side is configured as an input; the second I / O pin on the target chip side is configured as an input, and the second I / O pin on the first chip side is configured as an output. The first I / O pin is used by the target chip to send exception information, and the second I / O pin is used by the first chip to send feedback information indicating that the target chip has been reset. In this case, after the first chip controls the switching chip to complete the reset of the target chip, it can also send feedback to the target chip that the reset operation has been completed by setting the second I / O pin high, so that the target chip can accurately know that the reset operation has been completed.

[0101] In some possible implementations, the target chip may pull the first I / O pin low only after the second I / O pin is detected to be high, after the first I / O pin is brought high. If the second I / O pin is detected to be low, the level of the second I / O pin is checked again after a fixed interval (e.g., 0.5ms) until the level of the second I / O pin is high, or the number of checks reaches a preset limit (e.g., 60 times).

[0102] In some possible scenarios, when the target chip detects an anomaly in its own PCIe link, it directly sends an anomaly message indicating the link's abnormality to the first chip. In other possible scenarios, before sending the anomaly message, it first obtains the current number of times the anomaly message has been sent and determines whether this number is greater than a preset number (denoted as the first preset number, which is configurable, such as 3 times). If the number of times sent is less than the preset number, it sends the anomaly message indicating the link's abnormality to the first chip and updates the number of times sent. If the number of times sent is greater than the preset number, it stops sending the message to avoid an infinite loop.

[0103] In some possible implementations, the target chip can further inspect its own PCIe link; if the PCIe link is still abnormal, it can send the abnormal information to the first chip again; this continues until the PCIe link is normal, or the number of transmissions reaches a preset number. Specifically, the target chip may inspect its own PCIe link again after a fixed time interval has elapsed since the last abnormal information transmission. Alternatively, it may inspect its own PCIe link again after receiving feedback information from the first chip.

[0104] In some possible implementations, after the first chip completes the reset operation for all chips with link anomalies, it sequentially checks the PCIe links of the first chip, the second chip, the third chip, and the fourth chip again, and resets the chips with link anomalies, until the PCIe links of all chips are normal, or the repetition reaches a preset number (for ease of distribution with the aforementioned preset number, this preset number can be called the second preset number). It is understood that this preset number may differ from the aforementioned preset number.

[0105] It is understood that the functions of the first chip and the target chip (which can be one of the second, third, or fourth chips) can be combined to generate more embodiments. To better understand the reset process described above, several typical embodiments will be used for illustration below.

[0106] Example 1 by Figure 2a Taking the topology shown as an example, in one possible implementation, the reset process of a multi-chip system is as follows: Figure 3 As shown. After power-on, each GPU chip begins initializing its relevant hardware or configuration. Each GPU chip can be distinguished by its GPU ID, such as GPU0, GPU1, GPU2, or GPU3. GPU1, GPU2, and GPU3 can have the same functions, including: Set GPIO0 to output mode, set the maximum allowed number of attempts (allow_time = 3, corresponding to the first preset number mentioned above), and set the current GPU attempt count (retry_time) to 0. After setting, the GPU's SCPU reads its own chip's PCIe link status register. If the current link speed or width does not meet the expected value, the GPU enters the recovery process: if the current attempt count (retry_time) < allow_time, the GPU's SCPU sets the GPIO0 pin to a high level, then waits for a delay T1 = 20ms to allow the GPU chip to recover the relevant configuration, and then sets the GPIO0 pin to a low level. The current GPU attempt count (retry_time) is incremented by 1. The process returns to the above steps: the GPU's SCPU reads its own chip's PCIe link status register until retry_time exceeds 3 times (i.e., greater than allow_time) or the link status meets the expected value.

[0107] GPU0 acts as the control core, defining signal0 (corresponding to GPU0), signal1 (corresponding to GPU1), signal2 (corresponding to GPU2), and signal3 (corresponding to GPU3). The default value for each signal is 0. If the PCIe link of the GPU corresponding to a signal is faulty, the signal value is set to 1 to indicate the fault. For example, if the PCIe link of GPU0 is faulty, then signal0 = 1; if the PCIe link of GPU1 is faulty, then signal1 = 1. Other examples are not provided. Figure 3 In the code, signal0,1,2,3 are abbreviations for signal0, signal1, signal2, and signal3; similarly, GPU1,2,3 are abbreviations for GPU1, GPU2, and GPU3; and GPIO 0,1,2 are abbreviations for GPIO0, GPIO1, and GPIO2.

[0108] GPU0 sets its GPIO0, GPIO1, and GPIO2 to input mode. GPU0 also sets the maximum allowed number of attempts (allow_time = 3, corresponding to the second preset number mentioned above), and sets the current number of attempts (retry_time) to 0 and the pause duration (timeout) to 0. Afterward, GPU0 checks its own PCIe link status and then sequentially checks the PCIe links of GPU1, GPU2, and GPU3, continuously monitoring for 3ms (corresponding to timeout < 3, to ensure accurate detection of the link status of GPU1, GPU2, and GPU3). If a PCIe link anomaly is detected, the corresponding signal value is set to 1, and then centralized processing is performed based on the signal.

[0109] The system checks if signal0, signal1, signal2, and signal3 are all high simultaneously. If they are, the uplink port of the first switching chip (SW2) is hot-reset (triggering a secondary bus reset). This reset signal is broadcast to all downlink ports, thus resetting all GPUs connected to all downlink ports at once. If not, the system further checks if signal0 and signal1 or signal2 and signal3 are both high simultaneously. If signal0 and signal1 are both high, the downlink port of the first switching chip (SW2) connected to the second switching chip (SW0) is hot-reset, thus resetting all GPUs connected to SW0 at once. If signal2 and signal3 are both high, the downlink port of the first switching chip (SW2) connected to the third switching chip (SW1) is hot-reset, thus resetting all GPUs connected to SW1 at once. If signal0... If signal 1 is high, the downstream port of the second switching chip (SW0) will be hot-reset, thus resetting only the single GPU with the malfunction. If signal 2 or signal 3 is high, the downstream port of the third switching chip (SW1) will be hot-reset, thus resetting only the single GPU with the malfunction.

[0110] After all hot resets are completed, after a delay of T1 = 20ms (it only takes a few milliseconds from the hot reset to the link re-establishment), the current number of attempts, retry_time_0, of GPU0 is incremented by 1. Then, it is checked whether signal0, signal1, signal2, and signal3 are 1 (high level). If any signal is 1, GPU0 is initialized. The above process is then repeated until retry_time exceeds 3 times (i.e., greater than allow_time) or the PCIe link status meets the expected value.

[0111] Example 2 by Figure 2b Taking the topology shown as an example, in one possible implementation, Figure 3 The reset procedures for GPU1, GPU2, and GPU3 in the multi-chip system shown can be replaced with: Figure 4 The reset procedure is shown. Since GPU0 has a newly added GPIO3 pin that connects to GPU1, GPU2, and GPU3, only the reset procedure needs to be adjusted. Figure 3 The reset procedure for GPU0 can be adaptively modified, for example, by modifying the GPU0 reset procedure. Figure 3Replace "GPIO 0,1,2 set to input mode" with "GPIO 0,1,2 set to input mode, GPIO3 set to output mode, default is low level". Figure 3 The steps of "set GPIO3 high" and "set GPIO3 low" are added before and after "delay T1=20ms". Accordingly, "delay T1=20ms" is modified to "delay T1=10ms". That is, after the SCPU issues a hot reset command to trigger a simultaneous reset or a single reset, the "set GPIO3 high" action is triggered first, followed by "delay T1=10ms", then "set GPIO3 low", after which retry_time++ is executed. The remaining processes of GPU0 are the same. Figure 3 The rest of the process in GPU0 remains consistent.

[0112] In one possible implementation, the reset procedure for a multi-chip system can be as follows: Figure 5 As shown, Figure 5 Compared to the reset process shown in 4, GPU1, GPU2, and GPU3 will check whether GPIO1 is high again after a T3 interval.

[0113] It is understood that the reset process in the above example is only one of the many implementation schemes described in this application. Based on this, those skilled in the art can derive more variations by adding or reducing steps, changing the order between steps, or adjusting the start or end point of repeated steps.

[0114] After introducing the roles of the first chip and the target chip in the reset process of a multi-chip system, the following section combines... Figure 6 A brief description is provided of the reset method for the multi-chip system provided in the embodiments of this application.

[0115] S1: After power-on, the first chip detects its own PCIe link.

[0116] S2: After completing its own PCIe link detection, the first chip sequentially detects the PCIe links of the second, third, and fourth chips.

[0117] Optionally, when the PCIe links of the second chip, the third chip, and the fourth chip are abnormal, they all send abnormal information indicating their own link abnormality to the first chip. The first chip can detect the PCIe link of the corresponding chip by sequentially detecting whether it receives the abnormal information sent by the second chip, the third chip, and the fourth chip.

[0118] Optionally, the target chip (one of the second, third, and fourth chips) is connected to the first chip via an I / O pin; when the target chip sends abnormal information indicating its own link abnormality to the first chip, it can do so by setting the I / O pin high to send an abnormal signal indicating its own link abnormality to the first chip; and after a preset time interval, setting the I / O pin low.

[0119] Optionally, before sending the abnormal information indicating its own link abnormality to the first chip, the target chip obtains the current number of times the abnormal information is sent and determines whether the number of times it is sent is greater than a preset number; if the number of times it is sent is less than the preset number, the target chip sends the abnormal information indicating its own link abnormality to the first chip and updates the number of times it is sent.

[0120] Optionally, the IO pin includes a first IO pin and a second IO pin. The first IO pin is used by the target chip to send the abnormal information, and the second IO pin is used by the first chip to send feedback information indicating that the target chip has been reset. The method further includes: after completing the reset operation on the target chip, the first chip returns the feedback information to the target chip through the second IO pin; after receiving the feedback information returned by the first chip, the target chip checks its own PCIe link again; if the PCIe link is still abnormal, it sends the abnormal information to the first chip again; until the PCIe link is normal or the number of transmissions reaches a preset number.

[0121] S3: Determine whether the PCIe links of the first chip, second chip, third chip, and fourth chip are all abnormal.

[0122] If the PCIe links of the first chip, second chip, third chip, and fourth chip are all abnormal (if true), execute S4; if false, further execute S5 and S8.

[0123] S4: The first chip controls the uplink port of the first switching chip through the management bus interface to simultaneously perform a reset operation on all chips.

[0124] If the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal, the first chip controls the uplink port of the first switching chip through the management bus interface to simultaneously perform a reset operation on all chips.

[0125] S5: Determine whether the PCIe links of the first chip and the second chip are both abnormal.

[0126] If both the first and second chip PCIe links are faulty (when they are not), execute S6; if either the first or second chip PCIe link is faulty, execute S7.

[0127] S6: The first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0128] When both the PCIe links of the first chip and the second chip malfunction, the first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

[0129] S7: The first chip controls the second switching chip through the management bus interface to perform a reset operation on the first chip or the second chip.

[0130] When the first chip malfunctions and the second chip is functioning normally, the first chip controls the second switching chip through the management bus interface to perform a reset operation on the first chip; or, when the second chip malfunctions and the first chip is functioning normally, the first chip controls the second switching chip through the management bus interface to perform a reset operation on the second chip.

[0131] S8: Determine whether the PCIe links of the third and fourth chips are both abnormal.

[0132] If the PCIe links of the third and fourth chips are both abnormal (when they are not), execute S9; if the PCIe link of the third or fourth chip is abnormal, execute S10.

[0133] S9: The first chip controls the second downlink port of the first switching chip through the management bus interface to perform reset operations on the third and fourth chips.

[0134] When the PCIe links of the third and fourth chips both malfunction, the first chip controls the second downlink port of the first switching chip through the management bus interface to perform a reset operation on the third and fourth chips.

[0135] S10: The first chip controls the third switching chip through the management bus interface to perform a reset operation on the third or fourth chip.

[0136] When the third chip malfunctions and the fourth chip is functioning normally, the first chip controls the third switching chip through the management bus interface to perform a reset operation on the third chip; or, when the fourth chip malfunctions and the third chip is functioning normally, the first chip controls the third switching chip through the management bus interface to perform a reset operation on the fourth chip.

[0137] Optionally, the method further includes: after completing the reset operation for all chips with link abnormalities, sequentially detecting the PCIe links of the first chip, the second chip, the third chip, and the fourth chip, and performing a reset operation on the chips with link abnormalities.

[0138] The reset method for a multi-chip system provided in this application has the same implementation principle and technical effect as the aforementioned multi-chip system embodiments. For the sake of brevity, any parts not mentioned in the method embodiments can be referred to the corresponding content in the aforementioned multi-chip system embodiments.

[0139] This application also provides a server, including: the aforementioned multi-chip system and a server motherboard; wherein the server motherboard is the core component of the server system and includes a PCIe slot. The uplink port of the first switching chip in the multi-chip system is connected to the PCIe slot on the server motherboard. The multi-chip system, as a PCIe device, is inserted and removed from the PCIe slot via its gold fingers, thereby connecting to the server system and establishing a connection and communication with the CPU on the server motherboard.

[0140] The aforementioned servers include, but are not limited to, general-purpose servers, dedicated servers, cloud servers, edge servers, data center servers, network servers, database servers, and computer equipment, workstations, and mainframes with similar computing and management capabilities. Any computing device capable of deploying the aforementioned multi-chip system and capable of detecting and repairing PCIe device anomalies during power-on self-test (POST) is suitable for the methods described in this application.

[0141] The server provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the server embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0142] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0143] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multi-chip system, characterized in that, include: First computing card, second computing card, and first switching chip; The first downlink port of the first switching chip is connected to the first computing card, and the second downlink port of the first switching chip is connected to the second computing card. The first computing card includes a first chip and a second chip; the second computing card includes a third chip and a fourth chip; the management bus interface of the first switching chip is only connected to the first chip; the second chip, the third chip, and the fourth chip are all directly connected to the first chip; After power-on, the first chip is used to detect its own PCIe link; After completing its own PCIe link detection, the PCIe links of the second chip, the third chip, and the fourth chip are detected in sequence. Determine whether the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal; In the event that the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal, the first chip is also used to control the uplink port of the first switching chip to simultaneously perform a reset operation on all chips through the management bus interface.

2. The multi-chip system according to claim 1, characterized in that, When not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, the first chip is also used to determine whether the PCIe links of the first chip and the second chip are all abnormal; when the PCIe links of the first chip and the second chip are both abnormal, the first chip controls the first downlink port of the first switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

3. The multi-chip system according to claim 2, characterized in that, The first computing card further includes: a second switching chip, wherein the management bus interface of the second switching chip is connected only to the first chip, the downlink port of the second switching chip is connected to the first chip and the second chip, and the uplink port of the second switching chip is connected to the first downlink port of the first switching chip; When the first chip malfunctions and the second chip is functioning normally, the first chip is also used to control the second switching chip through the management bus interface to perform a reset operation on the first chip. Alternatively, when the second chip malfunctions and the first chip is functioning normally, the first chip may also control the second switching chip via the management bus interface to perform a reset operation on the second chip.

4. The multi-chip system according to claim 1, characterized in that, The first computing card further includes: a second switching chip, wherein the management bus interface of the second switching chip is connected only to the first chip, the downlink port of the second switching chip is connected to the first chip and the second chip, and the uplink port of the second switching chip is connected to the first downlink port of the first switching chip; If the PCIe links of the first chip and the second chip are both abnormal, but the PCIe link of at least one of the third chip and the fourth chip is normal, the first chip is also used to control the uplink port of the second switching chip through the management bus interface to perform a reset operation on the first chip and the second chip.

5. The multi-chip system according to claim 1, characterized in that, When not all of the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are abnormal, the first chip is also used to determine whether the PCIe links of the third chip and the fourth chip are all abnormal. When the PCIe links of the third chip and the fourth chip are both abnormal, the first chip controls the second downlink port of the first switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

6. The multi-chip system according to claim 5, characterized in that, The second computing card further includes: a third switching chip, wherein the management bus interface of the third switching chip is connected only to the first chip, the downlink port of the third switching chip is connected to the third chip and the fourth chip, and the uplink port of the third switching chip is connected to the second downlink port of the first switching chip; When the third chip malfunctions and the fourth chip is functioning normally, the first chip is also used to control the third switching chip through the management bus interface to perform a reset operation on the third chip. Alternatively, when the fourth chip malfunctions and the third chip is functioning normally, the first chip is also used to control the third switching chip through the management bus interface to perform a reset operation on the fourth chip.

7. The multi-chip system according to claim 1, characterized in that, The second computing card further includes: a third switching chip, wherein the management bus interface of the third switching chip is connected only to the first chip, the downlink port of the third switching chip is connected to the third chip and the fourth chip, and the uplink port of the third switching chip is connected to the second downlink port of the first switching chip; If the PCIe links of the third chip and the fourth chip are both abnormal, but the PCIe link of at least one of the first chip and the second chip is normal, the first chip is also used to control the uplink port of the third switching chip through the management bus interface to perform a reset operation on the third chip and the fourth chip.

8. The multi-chip system according to any one of claims 1-7, characterized in that, When the PCIe links of the second chip, the third chip, and the fourth chip are abnormal, they all send abnormal information indicating their own link abnormality to the first chip. The first chip is specifically used to detect the PCIe link of the corresponding chip by sequentially detecting whether it receives abnormal information sent by the second chip, the third chip, and the fourth chip.

9. The multi-chip system according to claim 8, characterized in that, The target chip is connected to the first chip via an I / O pin; wherein, the target chip is one of the second chip, the third chip, and the fourth chip; the target chip is used to send an abnormal signal indicating its own link abnormality to the first chip by setting the I / O pin high; and after a preset time interval, set the I / O pin low.

10. The multi-chip system according to claim 9, characterized in that, The target chip is further configured to, before sending abnormal information indicating its own link abnormality to the first chip, obtain the current number of times the abnormal information is sent; determine whether the number of times the information is sent is greater than a preset number; and when the number of times the information is sent is less than the preset number, send abnormal information indicating its own link abnormality to the first chip and update the number of times the information is sent.

11. The multi-chip system according to claim 9, characterized in that, The IO pins include a first IO pin and a second IO pin. The first IO pin is used for the target chip to send the abnormal information, and the second IO pin is used for the first chip to send feedback information indicating that the target chip has been reset. The first chip is also configured to return the feedback information to the target chip via the second IO pin after completing the reset operation on the target chip; The target chip is also used to detect its own PCIe link again after receiving the feedback information returned by the first chip; if the PCIe link is still abnormal, it sends the abnormal information to the first chip again; until the PCIe link is normal or the number of times it sends the information reaches a preset number.

12. The multi-chip system according to any one of claims 1-11, characterized in that, The first chip is also used to, after completing the reset operation of all chips with link abnormalities, sequentially detect the PCIe links of the first chip, the second chip, the third chip, and the fourth chip, and perform a reset operation on the chips with link abnormalities.

13. A server, characterized in that, include: Server motherboard and multi-chip system as described in any one of claims 1-12; The uplink port of the first switching chip in the multi-chip system is connected to the PCIe slot of the server motherboard.

14. A reset method for a multi-chip system, characterized in that, The multi-chip system includes: a first computing card, a second computing card, and a first switching chip. A first downlink port of the first switching chip is connected to the first computing card, and a second downlink port of the first switching chip is connected to the second computing card. The first computing card includes a first chip and a second chip. The second computing card includes a third chip and a fourth chip. The management bus interface of the first switching chip is only connected to the first chip. The second chip, the third chip, and the fourth chip are all directly connected to the first chip. The method includes: After power-on, the first chip detects its own PCIe link; After completing its own PCIe link detection, the first chip sequentially detects the PCIe links of the second chip, the third chip, and the fourth chip. Determine whether the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal; If the PCIe links of the first chip, the second chip, the third chip, and the fourth chip are all abnormal, the first chip controls the uplink port of the first switching chip to simultaneously perform a reset operation on all chips through the management bus interface.

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