A multi-core scalable inter-chip on-chip interconnect method and system for limited radius communication
Patent Information
- Application Number
- CN202611275396.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-21
- Publication Date
- 2026-10-20
AI Technical Summary
[0011]本发明的目的是解决现有通用互连技术无法在保证低延迟、高带宽的前提下，高效支持具有规则有限半径通信模式的应用在超大规模多核多芯片系统上运行的难题
[0038]1）本发明方法及系统提出一种统一数据包格式。该格式的包头域包含用于片内路由的目标核心标识符和用于片间路由的源路由位图字段。技术效果：实现了片内与片间通信协议的归一化，简化了网络接口设计，降低了协议转换开销。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of data communication technology in massively parallel computing systems. Specifically, it relates to a communication protocol and routing method for achieving efficient and low-latency data transmission within and between chips in multi-core processors and multi-chip systems. This method is particularly suitable for handling computational workloads with regular spatial locality communication patterns. Background Technology
[0002] Existing massively parallel computing systems typically employ communication libraries (such as MPI) based on message passing interfaces or shared memory models to achieve inter-node communication. At the hardware level, the system relies on general-purpose high-performance network interconnect technologies, such as InfiniBand, or dedicated interconnect architectures. To achieve versatility and support communication between arbitrary node pairs, these technologies often have complex communication protocol stacks, involving multi-layered protocol encapsulation and sophisticated flow control and error recovery mechanisms.
[0003] A typical prior art solution describes a multi-core system based on on-chip networks, which optimizes data movement within the chip by integrating on-chip memory and a dedicated DMA controller. However, this method mainly focuses on communication optimization at the single-chip level. When the system scales up to multiple chips, inter-chip communication still requires the aforementioned general, non-custom interconnect protocols. Data packets need to undergo complex protocol conversions when entering and leaving the chip, and traverse a general network that is not optimized for specific application communication modes.
[0004] The main problem with existing technologies lies in the mismatch between their "general-purpose" design and the needs of "specific" applications. Specific drawbacks are as follows:
[0005] High communication latency: The general protocol stack and complex routing arbitration logic introduce significant latency overhead, making it difficult to meet the extreme requirements of fine-grained communication for low latency.
[0006] Low bandwidth utilization: The protocol headers designed to handle various communication modes have high overhead, and the flow control mechanism may not be agile enough, resulting in a decrease in effective bandwidth utilization.
[0007] Limited scalability: The system's communication performance cannot scale linearly with the increase in the number of chips, and inter-chip communication quickly becomes the performance bottleneck of the entire system.
[0008] The programming model is complex: application programmers need to explicitly manage the movement and synchronization of data between distributed memories, which increases the programming complexity.
[0009] The root of these shortcomings lies in the fact that existing methods do not fully consider and utilize the key feature of the regular and predictable communication patterns of the target applications (such as Stencil computation, convolution, etc.), but instead are designed for the worst-case random communication patterns.
[0010] In summary, there is an urgent need to design a novel communication method that is "specialized for application characteristics," which can simplify the complex routing calculations of intermediate network nodes into simple parsing and execution of packet header information. This is the core challenge currently facing this field. Summary of the Invention
[0011] The purpose of this invention is to solve the problem that existing general interconnect technologies cannot efficiently support applications with regular finite radius communication patterns to run on ultra-large-scale multi-core multi-chip systems while ensuring low latency and high bandwidth.
[0012] In a first aspect, embodiments of this application provide a method for multi-core scalable on-chip interconnection for finite radius communication, the method comprising the following steps:
[0013] Data encapsulation steps: In multi-core processors and multi-chip systems, a unified data packet format is used to encapsulate data packets to be forwarded within and between chips. The header field of the data packet format includes the target core identifier for intra-chip routing and the source routing bitmap field for inter-chip routing.
[0014] Decoupling and coordination steps: A decoupling and coordination mechanism for intra-chip and inter-chip routing is adopted to determine whether a data packet enters the intra-chip routing process or the inter-chip routing process.
[0015] Inter-chip and intra-chip routing forwarding steps: For data packets that have been encapsulated, inter-chip or intra-chip routing forwarding is performed based on the inter-chip routing of the source routing bitmap forward shifted and the target core identifier.
[0016] Optionally, in this embodiment of the invention, the above data encapsulation step includes:
[0017] The communication library or hardware thread running on the source core resolves the global address of the target neighbor into the target chip ID and the target core ID based on the pre-generated routing table;
[0018] The target core ID is filled into the on-chip routing field of the packet header, and a bitmap is generated according to the topology between the source and target chips. The bitmap field is filled into the source routing of the data packet header. The bitmap uses multi-base to represent the output port direction, which includes: the six basic communication dimensions and directions for data exchange and the data packets that have been routed to the target chip or on-chip communication.
[0019] The payload data is encapsulated to form a complete data packet.
[0020] Optionally, in this embodiment of the invention, the above-mentioned decoupling and coordination steps include:
[0021] After decoupling the encapsulated data packet, an initial route determination is performed. The data packet is injected into the local on-chip network. The first-hop router checks the target core ID. If the target core ID belongs to this chip, the on-chip routing process is executed; otherwise, the data packet is routed to the chip's inter-chip gateway, and the inter-chip routing process is executed.
[0022] Optionally, in this embodiment of the invention, the above-mentioned inter-chip and intra-chip routing forwarding steps include:
[0023] Intra-chip routing steps: Based on the routing decision, intra-chip routing forwarding is performed. Then, on the intra-chip network, the data packet is routed hop by hop to the target processor core according to its target core ID through table lookup or dimension order routing.
[0024] Optionally, in this embodiment of the invention, the above-mentioned inter-chip and intra-chip routing forwarding steps include:
[0025] Inter-chip routing steps: Based on the routing determination, inter-chip source routing forwarding is performed. When the data packet arrives at the inter-chip gateway, the gateway reads the source routing bitmap field, selects the corresponding output port according to the value of the bitmap field, and sends the data packet out through the port;
[0026] Before or after transmission, the inter-chip gateway performs a logical offset operation on the bitmap by a preset number of bits, so that the indicator bit of the next port moves to the preset offset area.
[0027] Optionally, in this embodiment of the invention, the above-mentioned inter-chip routing step includes:
[0028] Check whether the shifted target bitmap field has reached the preset target value. If the bitmap field has reached the preset target value, the data packet has arrived at the target chip. Otherwise, continue to execute the inter-chip routing steps.
[0029] Optionally, in this embodiment of the invention, the above-mentioned inter-chip routing step includes:
[0030] For data packets that have arrived at the target chip, after the inter-chip gateway of the target chip identifies the bit map as the preset target value, it calculates the route of the target inter-chip channel through the target core ID and injects the data packets into the inter-chip network; the inter-chip network of the target chip then routes the data packets to the target core.
[0031] Secondly, embodiments of this application provide a multi-core scalable on-chip interconnect system for finite radius communication, the system comprising the following modules:
[0032] Data encapsulation module: In multi-core processor and multi-chip systems, a unified data packet format is used to encapsulate data packets to be forwarded within and between chips. The header field of the data packet format includes the target core identifier for intra-chip routing and the source routing bitmap field for inter-chip routing.
[0033] Decoupling and coordination module: It adopts a decoupling and coordination mechanism between intra-chip and inter-chip routing to decide whether a data packet enters the intra-chip routing process or the inter-chip routing process.
[0034] Inter-chip and intra-chip routing and forwarding module: For data packets that have been encapsulated, it performs inter-chip or intra-chip routing and forwarding based on the inter-chip routing of the source routing bitmap by forward shift.
[0035] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method for multi-core scalable inter-chip on-chip interconnection for finite radius communication.
[0036] Fourthly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the multi-core scalable inter-chip interconnect method for finite radius communication as described above.
[0037] Compared with existing technologies, it has the following outstanding advantages:
[0038] 1) The method and system of this invention propose a unified data packet format. The header field of this format includes a target core identifier for intra-chip routing and a source routing bitmap field for inter-chip routing. Technical effects: It achieves normalization of intra-chip and inter-chip communication protocols, simplifies network interface design, and reduces protocol conversion overhead.
[0039] 2) The method and system of this invention propose an inter-segment routing method based on forward shifting of the source routing bitmap. Intermediate network nodes only need to forward packets according to the currently valid bits of the bitmap and perform shifting operations on the bitmap. Technical effects: By transferring routing decisions from intermediate network nodes to the communication initiator, the routing calculation delay of intermediate nodes is eliminated, making the routing delay constant and predictable, and greatly reducing communication latency.
[0040] 3) The method and system of this invention propose a decoupling and coordination mechanism for intra-chip and inter-chip routing. By determining the target core identifier, it decides whether a data packet should undergo intra-chip routing or enter the inter-chip routing process. Technical effects: It achieves decoupling between fast processing of limited-radius communication and global forwarding of long-range communication, optimizes resource utilization, reduces the long-tail effect, and improves the overall system efficiency. Attached Figure Description
[0041] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0042] Figure 1 This is a schematic diagram of the multi-core scalable on-chip interconnect method for finite radius communication according to the present invention;
[0043] Figure 2 This invention provides a unified data packet format for a multi-core scalable on-chip interconnect method for finite radius communication.
[0044] Figure 3 This is a flowchart illustrating the steps of a multi-core scalable on-chip interconnect method for finite radius communication according to an embodiment of the present invention.
[0045] Figure 4 This is a schematic diagram of the multi-core scalable inter-chip on-chip interconnect system for finite radius communication according to the present invention;
[0046] Figure 5 This is a schematic diagram of the computer hardware of the present invention. Detailed Implementation
[0047] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.
[0048] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.
[0049] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0050] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0051] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0052] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0053] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0054] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.
[0055] This invention proposes a communication protocol and routing method for achieving efficient, low-latency data transmission within and between chips in multi-core processor and multi-chip systems. This method is particularly suitable for handling computational workloads with regular spatial locality communication patterns. Such methods demonstrate great potential in handling core scientific computing and artificial intelligence workloads such as structured grid computing (including computational fluid dynamics and finite element analysis), convolutional neural network training and inference, molecular dynamics simulations, and template computation in image signal processing.
[0056] These computational workloads with regular spatial locality communication patterns share a common and crucial characteristic: their computation process exhibits high spatial locality, meaning that any computational unit, during runtime, only needs to exchange data with a fixed, finite number of neighboring units (e.g., in a three-dimensional mesh, each unit may communicate with 27 directly adjacent units, including itself). In such application contexts, traditional on-chip interconnect network architectures oriented towards general communication patterns face significant efficiency bottlenecks. General-purpose networks are designed to handle random communication between arbitrary node pairs, and therefore typically possess complex routing structures, cache coherence protocols, and global arbitration mechanisms, inevitably introducing substantial hardware overhead, power consumption, and communication latency. This invention addresses this specific technical problem by proposing an innovative interconnect network solution.
[0057] While designing dedicated acceleration systems for large-scale scientific computing and artificial intelligence workloads, the inventors discovered that the aforementioned performance bottleneck stemmed from the design philosophy of the communication architecture. The shortcomings of existing technologies arise from the attempt to use a complex, general-purpose network to handle all scenarios, failing to consider that the communication topology for some high-performance computing workloads is fixed and local, with communication paths determined before program execution.
[0058] After in-depth research into application communication patterns, the inventors realized that this deficiency could be addressed through a novel communication method that "specializes for application characteristics." The core idea of this method is to pre-calculate and encode global routing information in the packet header before the data packet is injected into the network, thereby simplifying the complex routing calculations of intermediate network nodes to simple parsing and execution of the packet header information. This is a completely new solution, and its entire process includes: 1) defining a minimalist, unified data packet format containing source routing information; 2) designing a forwarding mechanism based on this packet format that eliminates the need for intermediate nodes to perform routing calculations; and 3) achieving protocol unification and process decoupling between on-chip and inter-chip communication.
[0059] The system of this application embodiment will be described in detail below with reference to specific embodiments:
[0060] like Figure 1As shown, this invention provides a method for multi-core scalable on-chip interconnection for finite radius communication, the method comprising the following steps:
[0061] Data encapsulation step 101: In multi-core processor and multi-chip systems, a unified data packet format is used to encapsulate the data packets to be forwarded within and between chips. The header field of the data packet format includes the target core identifier for intra-chip routing and the source routing bitmap field for inter-chip routing.
[0062] Decoupling and coordination step 102: Adopt the decoupling and coordination mechanism of intra-chip and inter-chip routing to decide whether the data packet enters the intra-chip routing process or the inter-chip routing process;
[0063] Inter-chip and intra-chip routing forwarding step 103: For data packets that have been encapsulated, perform inter-chip or intra-chip routing forwarding based on the inter-chip routing of the source routing bitmap forward shift and the target core identifier.
[0064] Optionally, in this embodiment of the invention, the above data encapsulation step 101 includes:
[0065] The communication library or hardware thread running on the source core resolves the global address of the target neighbor into the target chip ID and the target core ID based on the pre-generated routing table;
[0066] The target core ID is filled into the on-chip routing field of the packet header, and a bitmap is generated according to the topology between the source and target chips. The bitmap field is filled into the source routing of the data packet header. The bitmap uses multi-base to represent the output port direction, which includes: the six basic communication dimensions and directions for data exchange and the data packets that have been routed to the target chip or on-chip communication.
[0067] The payload data is encapsulated to form a complete data packet.
[0068] Optionally, in this embodiment of the invention, the above-mentioned decoupling and coordination step 102 includes:
[0069] After decoupling the encapsulated data packet, an initial route determination is performed. The data packet is injected into the local on-chip network. The first-hop router checks the target core ID. If the target core ID belongs to this chip, the on-chip routing process is executed; otherwise, the data packet is routed to the chip's inter-chip gateway, and the inter-chip routing process is executed.
[0070] Optionally, in this embodiment of the invention, the above-mentioned inter-chip and intra-chip routing forwarding step 103 includes:
[0071] Intra-chip routing steps: Based on the routing decision, intra-chip routing forwarding is performed. Then, on the intra-chip network, the data packet is routed hop by hop to the target processor core according to its target core ID through table lookup or dimension order routing.
[0072] Optionally, in this embodiment of the invention, the above-mentioned inter-chip and intra-chip routing forwarding step 103 includes:
[0073] Inter-chip routing steps: Based on the routing determination, inter-chip source routing forwarding is performed. When the data packet arrives at the inter-chip gateway, the gateway reads the source routing bitmap field, selects the corresponding output port according to the value of the bitmap field, and sends the data packet out through the port;
[0074] Before or after transmission, the inter-chip gateway performs a logical offset operation on the bitmap by a preset number of bits, so that the indicator bit of the next port moves to the preset offset area.
[0075] Optionally, in this embodiment of the invention, the above-mentioned inter-chip routing step includes:
[0076] Check whether the shifted target bitmap field has reached the preset target value. If the bitmap field has reached the preset target value, the data packet has arrived at the target chip. Otherwise, continue to execute the inter-chip routing steps.
[0077] Optionally, in this embodiment of the invention, the above-mentioned inter-chip routing step includes:
[0078] For data packets that have arrived at the target chip, after the inter-chip gateway of the target chip identifies the bit map as the preset target value, it calculates the route of the target inter-chip channel through the target core ID and injects the data packets into the inter-chip network; the inter-chip network of the target chip then routes the data packets to the target core.
[0079] Specifically, such as Figure 2 and Figure 3 As shown in the specific embodiments of the present invention, the implementation process of the embodiments will be described in detail below with reference to the flowcharts of the specific embodiments of the present invention.
[0080] Step S101: Communication Request Generation and Data Packet Encapsulation. When the source processor core needs to communicate with a logical neighbor core, it initiates a data access request. The communication library or hardware thread running on the source core resolves the global address of the target neighbor into the target chip ID and the target core ID based on a pre-generated routing table. Subsequently, the target core ID is filled into the on-chip routing field of the packet header, and a bitmap (six directions: X+, X-, Y+, Y-, Z+, Z-, using three digits to represent an output port direction, such as 001 for the X+ direction, 010 for the X- direction, and 000 for a data packet already routed to the target chip or for on-chip communication) is generated based on the topology between the source and target chips and filled into the source routing bitmap field of the packet header. Finally, the payload data is encapsulated to form a complete data packet.
[0081] Step S102: Initial route determination. The data packet is injected into the local on-chip network. The first-hop router checks the target core ID. If the ID belongs to this chip, proceed to step S103; otherwise, the data packet is routed to the chip's inter-chip gateway, and proceed to step S104.
[0082] Step S103: In-chip routing and delivery. On the in-chip network, data packets are routed hop-by-hop to the target processor core based on their target core ID using deterministic algorithms such as table lookup or dimensional order routing. The process ends after data delivery.
[0083] Step S104: Inter-segment source routing forwarding. The data packet arrives at the inter-segment gateway. The gateway reads the most significant three bits of the source routing bitmap field. It selects the corresponding output port based on the value of this bit. The data packet is then sent out through this port. Before or after transmission, the gateway performs a logical left shift of three bits on the bitmap, moving the indicator bit for the next port to the most significant three bits.
[0084] Step S105: Target Reach Judgment. Check if the bitmap field after shifting is all 0s.
[0085] If not, it indicates that forwarding is still required, and the process returns to step S104, where it is continued by the inter-chip gateway of the next hop chip.
[0086] If so, it means the data packet has arrived at the target chip.
[0087] Step S106: Target chip inter-chip channel identification and routing. After the target chip's inter-chip gateway recognizes that the bitmap is all 0s, it calculates which inter-chip communication channel to route to using the target core ID, and then injects the data packet into the dedicated inter-chip communication network within the chip.
[0088] Step S107: Inter-chip routing and delivery. The data packets are ultimately routed to the target core by the target chip's inter-chip network.
[0089] Variations of this method
[0090] To broaden the scope of protection, the following variations are considered:
[0091] 1. Bitmap encoding variant: The source routing bitmap is not limited to 3-bit encoding. It can use multiple bits (such as 4 bits) to encode a port, or 1 bit to encode a port. The shift operation is correspondingly changed to pointer movement or counter decrement.
[0092] 2. Routing Judgment Variation: The judgment in step S102 is not limited to the first-hop router. It can be designed so that the data packet always arrives at the inter-chip gateway first, and the gateway makes the judgment. If the target is in this chip, it will loop back to the intra-chip network.
[0093] 3. Protocol Extension Variation: The unified data packet can be extended to include fields such as virtual channel ID, service level, and CRC checksum without deviating from its core routing mechanism.
[0094] As described above, the device of the present invention can be implemented well.
[0095] Compared with existing technologies, this invention achieves significant beneficial effects through specialized design of communication protocols and routing methods: 1) Communication latency is greatly reduced, which is particularly beneficial for fine-grained communication, thereby improving application performance; 2) Network throughput is increased due to reduced protocol header overhead and simplified routing decisions; 3) System scalability is enhanced, and the trend of linear decline in communication performance with the increase of the number of nodes is effectively curbed; 4) Simpler hardware implementation simplifies the logic of the router, which helps to reduce power consumption and area; 5) It can support large-scale chip expansion, that is, there is no limit to the number of chips.
[0096] Secondly, such as Figure 4 As shown, this application provides a multi-core scalable on-chip interconnect system for finite radius communication, the system including the following modules:
[0097] Data encapsulation module 201: In multi-core processor and multi-chip systems, a unified data packet format is used to encapsulate data packets to be forwarded within and between chips. The header field of the data packet format includes a target core identifier for intra-chip routing and a source routing bitmap field for inter-chip routing.
[0098] Decoupling and Coordination Module 202: Employs a decoupling and coordination mechanism between intra-chip and inter-chip routing to determine whether a data packet enters the intra-chip routing process or the inter-chip routing process.
[0099] Inter-chip and intra-chip routing forwarding module 203: For data packets that have been encapsulated, it performs inter-chip or intra-chip routing forwarding based on the inter-chip routing of the source routing bitmap by forward shift.
[0100] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method for multi-core scalable inter-chip on-chip interconnection for finite radius communication.
[0101] Fourthly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the multi-core scalable inter-chip interconnect method for finite radius communication as described above.
[0102] In addition, combined Figure 1The multi-core scalable inter-chip on-chip interconnect method for finite radius communication described in this application embodiment can be implemented by an electronic device, such as a computer device. Figure 5 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application.
[0103] In some embodiments, the computer device may further include a communication interface 83 and a bus 80. For example, Figure 5 As shown, the processor 81, memory 82, and communication interface 83 are connected through bus 80 and complete communication with each other.
[0104] Specifically, the processor 81 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.
[0105] The memory 82 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 81.
[0106] The processor 81 reads and executes computer program instructions stored in the memory 82 to implement any of the multi-core scalable on-chip interconnect methods for finite radius communication in the above embodiments.
[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for multi-core scalable on-chip interconnection for finite radius communication, characterized in that, The method includes the following steps: Data encapsulation steps: In multi-core processor and multi-chip systems, a unified data packet format is used to encapsulate the data packets to be forwarded within and between chips. The header field of the data packet format includes a target core identifier for intra-chip routing and a source routing bitmap field for inter-chip routing. Decoupling and coordination steps: A decoupling and coordination mechanism for intra-chip and inter-chip routing is adopted to determine whether a data packet enters the intra-chip routing process or the inter-chip routing process. Inter-chip and intra-chip routing forwarding steps: For the data packet that has been encapsulated, perform inter-chip or intra-chip routing forwarding based on the inter-chip routing of the source routing bitmap forward shifted and the target core identifier.
2. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 1, characterized in that, The data encapsulation step includes: The communication library or hardware thread running on the source core resolves the global address of the target neighbor into the target chip ID and the target core ID based on the pre-generated routing table; The target core ID is filled into the on-chip routing field of the packet header, and a bitmap is generated according to the topology relationship between the source and target chips. The bitmap field is filled into the source routing of the data packet header. The bitmap uses a multi-base representation to represent the output port direction, which includes: the six basic communication dimensions and directions for data exchange and the data packets that have been routed to the target chip or on-chip communication. The payload data is encapsulated to form a complete data packet.
3. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 1, characterized in that, The decoupling and coordination steps include: After decoupling the encapsulated data packet, an initial route determination is performed. The data packet is injected into the local on-chip network. The first-hop router checks the target core ID. If the target core ID belongs to this chip, the on-chip routing process is executed; otherwise, the data packet is routed to the chip's inter-chip gateway, and the inter-chip routing process is executed.
4. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 3, characterized in that, The inter-chip and intra-chip routing forwarding steps include: Intra-chip routing steps: Based on the routing decision, intra-chip routing forwarding is performed. Then, on the intra-chip network, the data packet is routed hop by hop to the target processor core according to its target core ID through table lookup or dimension order routing.
5. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 3, characterized in that, The inter-chip and intra-chip routing forwarding steps include: Inter-chip routing steps: Based on the routing determination, inter-chip source routing forwarding is performed. When the data packet arrives at the inter-chip gateway, the gateway reads the source routing bitmap field, selects the corresponding output port according to the value of the bitmap field, and sends the data packet out through the port. Before or after transmission, the inter-chip gateway performs a logical shift operation on the bitmap by a preset number of bits, so that the indicator bit of the next port moves to the preset shift area.
6. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 5, characterized in that, The inter-chip routing steps include: Check whether the shifted target bitmap field reaches the preset target value. If the bitmap field reaches the preset target value, the data packet has arrived at the target chip; otherwise, continue to execute the inter-chip routing step.
7. The multi-core scalable inter-chip on-chip interconnect method for finite radius communication according to claim 6, characterized in that, The inter-chip routing steps include: For the data packet that has arrived at the target chip, after the inter-chip gateway of the target chip identifies the bit map as the preset target value, it calculates the route of the target inter-chip channel through the target core ID and injects the data packet into the inter-chip network; the inter-chip network of the target chip then routes the data packet to the target core.
8. A multi-core scalable on-chip interconnect system for finite radius communication, characterized in that, The system includes the following modules: Data encapsulation module: In multi-core processor and multi-chip systems, a unified data packet format is used to encapsulate data packets to be forwarded within and between chips. The header field of the data packet format includes a target core identifier for intra-chip routing and a source routing bitmap field for inter-chip routing. Decoupling and coordination module: It adopts a decoupling and coordination mechanism between intra-chip and inter-chip routing to decide whether a data packet enters the intra-chip routing process or the inter-chip routing process. Inter-chip and intra-chip routing and forwarding module: For the data packets that have been encapsulated, the module performs inter-chip or intra-chip routing and forwarding based on the inter-chip routing of the source routing bitmap.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the multi-core scalable inter-chip on-chip interconnect method for finite radius communication as described in any one of claims 1-7.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the multi-core scalable inter-chip on-chip interconnect method for finite radius communication as described in any one of claims 1-7.