Personality weight tensor continuous growth device and method based on non-volatile storage medium

Abstract

Invention Title: Device and Method for Continuous Growth of Personality Weight Tensors Based on Non-Volatile Storage Medium. This invention addresses the problems of memory loss upon power failure and uncontrollable weight drift in existing cloud-based AI long-term memory solutions. It provides a device and method for continuous growth of personality weight tensors based on non-volatile storage media, belonging to the field of cognitive computing hardware. This invention achieves cross-session consistency of personality weights through hardware-level nanosecond-level multi-valued resistor accumulation growth, making it suitable for user interaction scenarios requiring hardware-level continuous cross-session memory accumulation.

Description

Technical Field

[0001] Legal Status Statement: This invention relates to the Hebbian update rule and the synaptic plasticity algorithm. The algorithm operates on the resistance state changes of non-volatile physical storage media and has a specific technical relationship with the physical internal structure of the storage media. The algorithm features and the internal structure of the computer system are mutually adapted and coordinated at the technical implementation level—the algorithm execution is to solve the physical problem of synchronizing the cumulative growth of weight values ​​with the changes in hardware resistance state in non-volatile storage media, and achieves the technical effect of improving the internal performance of the storage media in accordance with natural laws.

[0002] This invention falls under the technical solution stipulated in Article 2, Paragraph 2 of the Patent Law. The algorithm features and the physical internal structure of the storage medium have a specific technical relationship, and the examination standard of Case 2 on page 54 of the "Guidelines for Patent Applications for Artificial Intelligence-Related Inventions (Trial)" applies.

[0003] This invention relates to the field of artificial intelligence and cognitive computing hardware technology, specifically to a device and method for continuously accumulating user cognitive patterns across sessions using non-volatile storage media and synaptic plasticity learning rules. Its international patent classification numbers are G06N3 / 063 (physical implementation of neural networks), G06N3 / 08 (neural network learning method), G11C13 / 00 (non-volatile memory), H01L45 / 00 (solid-state storage devices, covering phase-change memory and memristors), and G06F17 / 16 (matrix operations, used for multiplication array calculation of synaptic plasticity update amount).

[0004] The term "cognitive preference" as used in this invention refers to the observable and quantifiable interactive behavior tendencies exhibited by users during interaction with the system, without involving the diagnosis or assessment of users' psychological state or personality traits.

[0005] It should be noted that the "personality weight tensor" and "personality trait dimension" mentioned in the claims refer to the same technical concept as the "cognitive pattern" and "cognitive trait dimension" mentioned in the main text of this specification: both are multidimensional weighted representations of quantifiable behavioral tendencies exhibited by users in interaction with the system. "Personality" is the technical term used in the claims, while "cognition" is a synonym used in the specification to avoid describing psychological state diagnosis. Both refer to the same storage object and the same Heb update mechanism, and the technical scope is not changed due to the different terminology. Background Technology

[0006] Phase change memory (PCM) is an important branch of non-volatile memory technology. Martin Salinga et al. (2018) proposed a single-atom phase change memory in Nature Materials [1], which achieves atomic-level precision in storage units, laying the foundation for high-density neuromorphic computing. This invention introduces the Heb update rule on the basis of PCM and realizes multi-value weighted storage through the crystalline-amorphous resistance variation range of GST material, thus expanding the application dimensions of PCM.

[0007] Vinay Joshi et al. (2020) reported on precise deep neural network inference based on computational phase-change memory in Nature Communications [2], demonstrating the potential of PCM in in-memory computation. Based on this, the present invention further introduces a cross-session weight accumulation mechanism to achieve nanosecond-level hardware-level continuous growth of personality weights through the Heb rule.

[0008] Can Li et al. (2018) proposed an efficient adaptive online learning method for multilayer memristor neural networks in Nature Communications (doi:10.1038 / s41467-018-04484-2), proving the feasibility of in-situ learning based on Hebbian rules in multilayer memristor cross arrays. This invention draws on this method and applies it to the cross-session accumulation scenario of personality weight tensors, realizing hardware-level storage of weight values ​​through the resistance state changes of PCM / memristors.

[0009] Existing user modeling and hardware-based cognitive state storage technologies can be mainly categorized as follows: First, user profiling based on content preference tags (e.g., the collaborative filtering-based user profiling method disclosed in CN110245289A); second, one-time cognitive assessment based on dialogue text (e.g., the LSTM-based dialogue personality recognition system disclosed in US2020 / 0151560A1); and third, synaptic plasticity realization based on hardware non-volatile storage media (e.g., the low-power synaptic memristor device disclosed in CN122438520A and its method for achieving synaptic plasticity at millivolt-level low voltage).

[0010] The four types of memristor arrays are: (1) the switchless redundant fault-tolerant memristor cross array circuit for bridging faults disclosed in CN122314050A; (2) the oxide all-optically controlled memristor array and its fabrication method disclosed in CN122294839A; and (3) the multi-value resistor state storage based on phase change memory (e.g., the electroforming energy-saving phase change memory device with thin active region disclosed in CN122423349A).

[0011] In recent years, on-chip learning technology using memristors has continued to develop: CN118155680A discloses a weight qualification trace update method and neural network chip based on dynamic memristors (application date March 22, 2024). It utilizes diffused ion memristors, charge-trapping memristors, or short-range ferroelectric memristors to construct synaptic structures, sampling and accumulating data at the pulse firing moment to calculate weight changes, thereby achieving on-chip training of spiking neural networks; CN111882064A discloses a method and system for implementing a competitive learning mechanism for spiking neural networks based on memristors, using memristors... Synapses achieve lateral inhibition and utilize pulsed voltage waveforms to realize STDP plasticity; CN106845634B discloses a neuronal circuit based on memristor devices, in which the synaptic array uses volatile bipolar resistive switching devices to express membrane potential; CN112183739B discloses a low-power pulsed convolutional neural network hardware architecture based on memristors; Feldmann et al. (2018) reported in Nature an artificial synapse based on ferroelectric tunnel junction (FTJ), whose conductance can be precisely adjusted by voltage pulses and evolves according to STDP rules.

[0012] The aforementioned existing technologies all aim to achieve spurious training, pattern recognition, or image classification of general neural networks (SNN / CNN). Their weight updates are geared towards network-level learning tasks (such as competitive learning, unsupervised classification, and image recognition), and the weight semantics are general network weights. However, this invention targets the specific application of cross-session accumulation of user cognitive patterns—each dimension of the personality weight tensor corresponds to a preset personality trait dimension, the update is based on the structured encoding of interaction records, and the update goal is to maintain and gradually converge across sessions. The two differ in weight semantics, update basis, training objectives, and application scenarios. Those skilled in the art have no incentive to migrate general memristor on-chip training schemes to cross-session accumulation of user cognitive trait dimensions.

[0013] The limitation of the former is that user profiles reflect "what content users like," not "how users think"—there is a fundamental difference between the two. A user may like technology content, but their cognitive pattern can be "simple and direct" or "detailed and rigorous." The latter cannot be inferred from content preferences.

[0014] The limitation of the latter is that cognitive evaluation is a one-off, static process. Each session is evaluated independently, and the interaction history accumulated in the previous session is discarded in the next, making it impossible to achieve cross-session accumulation and continuous growth of cognitive patterns. This means that the reasoning system needs to "re-get to know" the user in each new session, making it impossible to form a long-term tacit understanding.

[0015] Furthermore, all of the above user modeling schemes are based on software stack implementation—data is stored in a general relational database in the form of structured text, and update operations rely on CPU execution of code logic.

[0016] This approach has two significant technical drawbacks: First, it suffers from high latency. Each reading of objective text features and accumulated numerical state parameters requires database queries and software processing (with a latency of approximately 10 milliseconds). In the PostgreSQL pgbench TPC-B benchmark test, the typical single-transaction latency is 6-20ms, and the average latency in a 10-user concurrent scenario is 13.9ms. (See PostgreSQL Global Development Group).

[0017] "pgbench — A Micro-Benchmark for PostgreSQL", PostgreSQL 16Documentation, 2023);

[0018] Secondly, cross-session persistence relies on the application layer's manual save and load mechanism, which carries the risk of data loss or inconsistent states after a system power outage.

[0019] More importantly, none of the above solutions address a core problem: how to persist user cognitive patterns in a hardware-storable and evolvable form to achieve real-time adaptation across sessions. Existing solutions either store user models in the software layer (relying on database queries, resulting in high latency) or re-evaluate them with each session (lacking accumulation). This invention is proposed to fill this technological gap.

[0020] Furthermore, the following comparison is made with existing AI long-term memory solutions: Existing AI long-term memory solutions can be divided into four categories according to their technical level: (1) Software-level memory frameworks, such as Mem0, LangMem, Letta, etc., rely on vector databases and LLM summaries to achieve cross-session memory, with a typical access latency of about 10 milliseconds;

[0021] (2) Unify long and short memory management software, such as AgeMem proposed by Alibaba and Wuhan University in January 2026, which jointly manages long-term memory (LTM) and short-term memory (STM) through reinforcement learning tool interfaces, but still relies on CPU / GPU inference and external LLM;

[0022] (3) Model Context Protocol, such as the MCP (Model Context Protocol) launched by Anthropic in November 2024, whose status change as of August 2026 and July 2026 has not been publicly disclosed. Its essence is a communication protocol between LLM and external tools and data sources. It does not provide memory capabilities itself, but can only be used as a calling interface for memory backend; (4) Neuromorphic memory hardware, such as the hardware-based cognitive pattern accumulation device based on non-volatile physical storage medium described in this invention.

[0023] This invention differs substantially from the above four schemes in terms of physical implementation: (1) Different storage media—This invention uses non-volatile physical media such as STT-MRAM / phase-change memory / memristor, and the weights are directly encoded in the microcrystalline ratio or resistance value of the medium; the above software layer schemes are all based on volatile or manually persistent storage media such as DRAM / vector database. (2) Different access latency—This invention directly reads the multi-value resistive synaptic weight tensor through the physical bus, with a typical latency of less than 100 nanoseconds;

[0024] The above software layer solutions require database queries, LLM inference, or protocol stack parsing, with latency typically ranging from milliseconds to seconds. (3) Different power failure behaviors—the non-volatile storage medium used in this invention ensures that the weights are not lost after a power failure, eliminating the need for manual saving by the application layer; the above software layer solutions require an external database persistence mechanism. (4) Different offline / edge deployment capabilities—this invention runs completely offline and can work independently on edge devices / embedded scenarios; the above software layer solutions rely on external LLM and databases and require network connectivity to run.

[0025] (5) Different energy consumption - This invention utilizes the passive computing characteristics of physical media, and the energy consumption of a single read is in the microwatt level; the above software layer solution requires continuous participation of CPU / GPU, and the energy consumption is in the watt level.

[0026] It is worth noting that the solution described in this invention is complementary to, rather than a substitute for, the MCP protocol: MCP can serve as a standardized protocol interface for upper-layer applications to call the hardware-based memory backend provided by this invention, while this invention provides the MCP ecosystem with a physical-layer persistent, low-latency, and offline memory implementation. The technical problem of "continuous accumulation of user cognitive patterns across sessions" solved by this invention has not been publicly reported in any of the four existing solutions mentioned above.

[0027] The innovation of this invention lies not in the improvement of the software-level memory management algorithm, but in the technicalization of abstract cognitive patterns into multi-valued resistive synaptic weight tensors that can be accurately stored and evolved in hardware, and the direct control of non-volatile physical storage media by a dedicated hardware circuit driven by synaptic plasticity rules to achieve hardware-level cross-session continuous accumulation. Summary of the Invention

[0028] Purpose of the invention

[0029] The technical problem this invention aims to solve is that existing personality modeling schemes cannot achieve continuous accumulation, accurate representation, and rapid retrieval of cognitive patterns across conversations at the hardware level, resulting in the inference system's inability to form a long-term tacit understanding with the user.

[0030] Technical solution

[0031] Explanation of the overarching concept: In this invention, "non-volatile physical storage medium" is an overarching concept, encompassing any non-volatile medium capable of persistently storing weight values ​​through changes in physical state, including but not limited to any one of phase-change memory (PCM), memristor cross array, magnetoresistive random access memory (MRAM), ferroelectric field-effect transistor (FeFET), and spin-transfer torque magnetic memory (STT-MRAM); "change in physical state" encompasses any one of resistance change, crystal ratio change, magnetization direction change, and polarization direction change.

[0032] The aforementioned overarching concept means that the weighted tensor storage described in claim 1 is not limited to a single storage device, and those skilled in the art can select the most suitable non-volatile medium implementation method according to capacity, speed and power consumption requirements.

[0033] The device includes an interactive encoding module, a multi-valued resistive synaptic weight tensor storage unit (composed of a non-volatile physical storage medium), a synaptic plasticity update circuit, and an inference adaptation interface (i.e., the inference adaptation module as described in the claims). The interactive encoding module converts user interactions into structured records; the synaptic plasticity update circuit calculates the weight update amount according to the synaptic plasticity rules and writes it directly to the non-volatile storage medium via a physical bus; the inference adaptation interface reads the tensor and converts it into inference preference parameters. The above four modules (interactive encoding module, multi-valued resistive synaptic weight tensor storage unit, synaptic plasticity update circuit, and inference adaptation interface) are physically independent of each other: each module is implemented with an independently packaged hardware circuit unit, has an independent power supply domain and clock source, and the modules do not share a control bus or data bus. Data transfer between modules is only completed through a dedicated physical bus. The failure or removal of any module does not affect the independent operation of other modules, and there is no control center for software instructions to uniformly schedule the modules, thereby ensuring the integrity and determinism of the continuous weight accumulation process at the physical level.

[0034] Furthermore, the personality trait dimensions are a preset set of cognitive trait dimensions, each dimension corresponding to a quantifiable interactive behavior tendency (such as the dimensions of simple / detailed, rigorous / flexible interaction style, etc., the division of which is based on the cognitive model definition in the instruction manual), and each dimension is represented by a real quantified weight value in the range of [-1,1]; the structured interaction record at least includes an interaction behavior type field (such as type codes for questioning, statement, command, feedback, clarification, etc.) and an interaction content feature field, which are generated by the interaction coding module according to preset coding rules.

[0035] It should be specifically noted that the specific names and number of cognitive trait dimensions in this invention do not constitute a limitation on the scope of this invention. Any pre-defined multidimensional cognitive trait space, as long as the weight values ​​of each dimension are numerically converted to real numbers in the interval [-1, 1] and stored in a non-volatile physical medium, is applicable to the tensor storage and synaptic plasticity update mechanism of this invention. The selection of cognitive trait dimensions is a conventional design choice for those skilled in the art and does not affect the core inventive concept of this invention—namely, "continuously updating the multidimensional weight tensor stored in a non-volatile medium using hardware circuits driven by synaptic plasticity rules."

[0036] Beneficial effects

[0037] (1) Extremely low latency: Compared with user profiling based on database queries, this solution directly reads the multi-valued resistive synaptic weight tensor through hardware circuitry, reducing latency from approximately 10 milliseconds to less than 100 nanoseconds (typical SRAM access time is 10-20 ns, DRAM is 60 ns; see JL Hennessy & DA Patterson, "Computer Architecture: A Quantitative Approach", 6th ed.).

[0038] Morgan Kaufmann, 2017, Chapter 2;

[0039] For Chinese information on SRAM, see the Wikipedia entry for "Static Random Access Memory" (access time "only about 10 nanoseconds"), which represents a speed increase of approximately 100,000 times.

[0040] (2) Continuous growth across sessions: Compared with one-time cognitive assessment, this scheme realizes the cumulative update of cognitive weights across sessions. After 100 interactions, the main dimension weights of the multi-valued resistive synaptic weight tensor tend to stabilize (fluctuation amplitude <0.05), and the accuracy of the inference system in adapting to the user's cognitive pattern gradually increases with the number of interactions.

[0041] (3) Non-volatile persistence: Non-volatile storage media ensures that the multi-valued resistance synaptic weight tensor is not lost after the system is powered off or restarted, without the need for manual saving operations at the application layer.

[0042] (4) Hardware-level physical evolution: The synaptic plasticity update circuit directly applies programming pulses to the storage cells of the non-volatile storage medium through the physical bus, and directly achieves weight evolution by changing the crystallization ratio of micromaterials (such as GST phase change materials) or the resistance value of memristors. The whole process does not go through the operating system file system or database software stack, eliminating the state delay and security risks of the software layer from the physical level, and forming an objective state evolution based entirely on the inherent characteristics of the physical medium.

[0043] Compared with existing technologies, the distinguishing feature of this invention is that it continuously solidifies user cognitive patterns in the form of multidimensional weight tensors on non-volatile physical storage media and updates them directly at the hardware level according to Hebb's rule, rather than using user profiles or one-time cognitive assessments in the software stack. This distinguishing feature is not a conventional approach in the art: existing solutions either store structured text in relational databases (software layer, millisecond-level latency) or evaluate independently for each session (unable to accumulate across sessions). Existing technologies do not provide technical inspiration for continuously growing cognitive weights in the form of non-volatile multi-valued resistors in hardware, and those skilled in the art have no motivation to directly use synaptic plasticity hardware for cross-session solidification of user cognitive patterns. This distinguishing feature reduces the cognitive weight access latency from approximately 10 milliseconds to less than 100 nanoseconds and achieves continuous accumulation across sessions, achieving significant technical effects.

[0044] Furthermore, this invention differs from the memristor in-situ learning scheme of Can Li et al. (2018, Nature Communications): This scheme uses the Hebbi rule for online training of network weights in multilayer memristor networks for image classification tasks (MNIST, etc.), where the weight semantics represent the connection strength of the classification network, and the training objective is image recognition accuracy. This invention uses the Hebbi update rule for cross-session accumulation of semantic weight tensors in the user's cognitive trait dimension. The weight semantics represent the preference strength on a predefined personality / cognitive trait dimension, the update is based on the structured encoding of interaction records, and the objective is cross-session persistence and gradual convergence. The two differ in weight semantics, update basis, training objective, and application scenarios. In addition, this invention directly carries the weight state using a non-volatile physical storage medium, which is fundamentally different from software-layer user memory frameworks (such as memory systems based on relational databases or vector libraries) in terms of storage medium and update path—the weight update in this invention is directly completed by hardware circuitry according to the Hebbi rule, without the intervention of the software stack. Therefore, combining Heb hardware updates with nonvolatile weight tensors for user cognition accumulation across sessions is not obvious to those skilled in the art, but has outstanding substantial features and significant progress.

[0045] It should be noted that the Hebbian continuous learning neural network (such as CN117203679A) retrieved from the State Intellectual Property Office website updates classification weights for computer vision object recognition, and its weight semantics are category connection strength and the processing object is image features; the present invention focuses on the cross-session accumulation of the weight tensor of the user cognitive trait dimension, and the processing object is the structured encoding of the interaction record. The two are different in terms of weight semantics, processing object and accumulation target.

[0046] Based on the aforementioned distinguishing technical features, the technical problem actually solved by this invention is: how to continuously accumulate and grow user cognitive trait weights across sessions at the physical layer, avoiding the delays in user profiles at the software layer and the inability of one-time cognitive assessments to accumulate across sessions. By carrying weight tensors on non-volatile physical storage media and directly updating them via hardware circuitry according to the Hebbi rule, this invention achieves nanosecond-level hardware-level continuous growth of weights across sessions.

[0047] It should be noted that although Hebb's learning rules and memristors / phase-change memory devices are known in the art, those skilled in the art lack the motivation to combine them for user cognitive trait modeling: research on the combination of Hebb's rules and memristors (such as Can Li 2018) focuses on online training of weights in classification networks, where the semantics of the weights are the class connection strength; research in the field of user cognitive modeling (such as software-layer user profiling) uses relational databases or vector libraries for storage and does not involve hardware-layer Hebb updates. The motivations, objects, and application scenarios of the two clusters of existing technologies are all different, and those skilled in the art have no motivation to migrate hardware Hebb update schemes to cross-session accumulation of user cognitive trait dimensions—this migration requires redefining the trait semantic dimension of the weight tensor, designing structured encoding of interaction records as Hebb update input, and solving the coupling problem between hardware write-back and semantic convergence, all of which are beyond the scope of inspiration of the two clusters of existing technologies. Attached Figure Description

[0048] Figure 1 This is a block diagram illustrating the overall principle of a multi-valued resistive synaptic weight tensor continuous growth device.

[0049] Figure 2 This is a structural diagram of a multi-valued resistive synaptic weight tensor storage cell based on phase-change memory.

[0050] Figure 3 This is a schematic diagram showing the correspondence between the multi-value resistor states and weight values ​​of a phase-change memory cell.

[0051] Figure 4 This is a structural diagram of a multi-valued resistive synaptic weighted tensor storage cell based on a memristor cross array.

[0052] Figure 5This is a schematic diagram of the hardware implementation of the synaptic plasticity update circuit.

[0053] Figure 6 This is a schematic diagram showing the correspondence between the dimensions of the multivalued resistive synaptic weight tensor and cognitive traits.

[0054] Figure 7 This is the overall flowchart of the method.

[0055] Figure 1 This is a block diagram illustrating the overall principle of the multi-valued resistive synaptic weight tensor continuous growth device of the present invention. It shows four main modules (interactive encoding module 1, multi-valued resistive synaptic weight tensor storage unit 2, synaptic plasticity update circuit 3, and inference adaptation interface 4) and the arrow connections between them, illustrating the complete data flow of "user interaction → interactive encoding module → synaptic plasticity update circuit ↔ storage unit ↔ inference adaptation interface → inference engine".

[0056] The output of inference adapter interface 4 can also be connected to a reflection buffer (for caching input-output mapping pairs of high-frequency inference paths) and a dimension reduction mapping module (for mapping high-dimensional multi-valued resistive synaptic weight tensors to low-dimensional inference preference parameters). These optional modules are not included in... Figure 1 It is marked separately.

[0057] It should be noted that the reflection cache mentioned in this embodiment is the L0.5 reflection cache module described in claim 5, which is composed of a hardware non-volatile cache and is used to store the input-output mapping pairs of high-frequency inference paths; during inference, it is preferentially read from the L0.5 reflection cache module, and if the cache is hit, the complete inference calculation process is skipped.

[0058] Among them, the dimension reduction mapping module is the back distillation module of claim 7: it is used to map the high-dimensional personality trait weights in the personality weight tensor to low-dimensional reasoning preference parameters, and the mapping extracts the main dimensions that have the greatest impact on reasoning preference through eigenvalue decomposition or principal component analysis.

[0059] Figure 2 This is a structural diagram of a multi-valued resistive synaptic weighted tensor storage cell based on phase-change memory in Embodiment 1. It shows a GST storage cell array (multiple storage cells arranged in an array), each cell containing a heating electrode and a GST material layer. The connection relationship between the programming pulse generator 21 and the readout circuit 22 is also shown.

[0060] Figure 3 This diagram illustrates the correspondence between the multi-valued resistor states and weight values ​​of a phase-change memory cell. A graph is plotted with resistance values ​​on the x-axis and weight values ​​on the y-axis, showing that R_min (crystalline state, approximately 10kΩ) corresponds to a weight of +1.0, and R_max (amorphous state, approximately 1MΩ) corresponds to a weight of -1.0, with a linear mapping relationship in between.

[0061] Figure 4 This is a structural diagram of a multi-valued resistive synaptic weighted tensor storage cell based on a memristor cross array in Embodiment 2. It shows the grid formed by the intersection of word lines 31 and bit lines 32. Each intersection point has a memristor cell 33 containing a TiOx resistive switching layer. Row lines connect to row drive circuits 34, and column lines connect to column readout circuits 35.

[0062] Figure 5 This is a schematic diagram of the hardware implementation of the synaptic plasticity update circuit. It shows the internal connections of DAC40, pulse generator 41, learning rate decay module 42, and the signal line connections between them and the memory cells.

[0063] Figure 6 This is a schematic diagram showing the correspondence between the dimensions of the multivalued resistive synaptic weight tensor and cognitive traits. Multiple cognitive trait dimensions and their corresponding weight value ranges [-1, 1] are displayed in the form of tables or tree diagrams.

[0064] Figure 7 This is an overall flowchart of the method of the present invention. The flowchart shows four steps: initialization step → interactive coding step → synaptic plasticity update step → inference adaptation step. The steps are connected by arrows, where the bidirectional arrow pointing to the multi-valued resistive synaptic weight tensor storage unit in the synaptic plasticity update step indicates a read / write operation. All figures are represented using grayscale levels, with light to dark grayscale distinguishing each subsystem / energy level / state. Detailed Implementation

[0065] This implementation example Figure 1 As shown, by Figure 2 The Hebbian learning write shown is performed by... Figure 3 The tensor structure shown is implemented.

[0066] (This embodiment corresponds to the device described in claim 1. As shown in the overall architecture in Figure 1, it is implemented by the Heb learning writing shown in Figure 2 and the tensor structure shown in Figure 3.)

[0067] (This embodiment corresponds to the device described in claim 1 and the method described in claim 2).

[0068] Preferably, the non-volatile physical storage medium is a phase-change memory or a memristor cross array, enabling nanosecond-level write and read operations. Preferably, the learning rate decay coefficient γ ranges from 0.001 to 0.05.

[0069] Preferably, the non-volatile physical storage medium has a write time of less than 50 ns, a read time of 35-50 ns (depending on the type of medium; memristors are typically about 35 ns, and phase-change memories are typically about 50 ns), and a retention time of more than 10 years after power failure.

[0070] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0071] Figure 1 The four core modules of independent claim 1 are shown. The reflection cache and dimension reduction mapping modules defined in claims 5 and 6 are optional additional modules, connected downstream of inference adapter interface 4 or integrated within it, and are not included in... Figure 1 It is marked separately.

[0072] The non-volatile storage media (phase-change memory, memristor) used in this invention are all mature devices known in the art; the synaptic plasticity rule (Herb rule) used in this invention is a learning rule known in the field of biology. The innovation of this invention lies in: integrating the above-mentioned known devices and rules with a new system architecture to form a complete technical solution of "interactive encoding → hardware weight update → non-volatile persistent storage → inference adaptation", realizing hardware-level continuous growth and cross-session persistence of user cognitive patterns.

[0073] Example 1: Multi-valued resistive synaptic weighted tensor device based on phase-change memory

[0074] (I) Definition and Data Structure of Multivalued Resistive Synaptic Weight Tensor

[0075] In this embodiment, the multi-valued resistive synaptic weight tensor is defined as a multi-dimensional numerical vector. As an exemplary implementation, the dimensions can correspond to the following cognitive trait dimensions:

[0076] Dimension ID, Dimension Name, Weight Value, Meaning

[0077] 1. Concise - Detailed: Positive values ​​indicate a preference for concise expression, while negative values ​​indicate a preference for detailed expression.

[0078] 2. Rigorous - Divergent: Positive values ​​indicate a tendency towards rigorous logic, while negative values ​​indicate a tendency towards divergent thinking.

[0079] 3 Calm - Passion: Positive values ​​indicate a tendency towards calm and rationality, while negative values ​​indicate a tendency towards passion and emotionality.

[0080] 4. Positive values ​​for "Active" and "Passive" indicate a tendency to actively explore, while negative values ​​indicate a tendency to passively wait.

[0081] 5. Abstract-Concrete: Positive values ​​indicate a tendency towards abstract thinking, while negative values ​​indicate a tendency towards concrete details.

[0082] The weights for each dimension are real numbers in the interval [-1, 1]. The initial tensor for a new user is a zero vector (0,0, 0, 0, 0), representing no bias. As the number of interactions increases, the weights of each dimension are gradually updated according to the synaptic plasticity rule and tend to converge.

[0083] (ii) Non-volatile physical storage medium – Phase-change memory

[0084] In this embodiment, the non-volatile physical storage medium is a phase-change memory (PCM), and the storage material is GST (Ge2Sb2Te5). After applying different current pulses, the GST material can continuously change between an amorphous state (high resistance, representing negative weight) and a crystalline state (low resistance, representing positive weight).

[0085] Each GST memory cell corresponds to a weight value in a multi-valued resistive synaptic weight tensor. A weight value of -1.0 corresponds to a completely amorphous state (highest resistance value, approximately 1 MΩ), a weight value of +1.0 corresponds to a completely crystalline state (lowest resistance value, approximately 10 kΩ), and intermediate values ​​are linearly mapped.

[0086] The typical resistance ratio between the amorphous (high resistance) and crystalline (low resistance) states of GST materials ranges from 1 to 3 orders of magnitude (measured across material / operating conditions, 10^3-10^6 Ω) (H.-SP Wong et al., "Phase Change Memory", Proc. IEEE 98, 2201-2227, 2010, Table I provides a typical resistance window).

[0087] This classic review was cited as a standard reference for the physical foundations of PCM by Zhang et al. "Designing crystallization in phase-change materials for universal memory and neuro-inspired computing", Nature Reviews Materials 4, 150-168, 2019.

[0088] It should be noted that the measured values ​​of RH≈1.2×10^6Ω and RL≈3.0×10^5Ω, approximately 4 times, in H. Sun et al., "Chemical Bond Polarity-driven Memristive Effects in Ge2Sb2Te5 Films" (Huazhong University of Science and Technology, Wuhan), represent the resistance ratio of the unit cell in the amorphous-crystalline intermediate state (low-resistance / high-resistance bistable state) after electroforming treatment, and not the physical ratio between the completely amorphous and completely crystalline states.

[0089] The resistance of a completely amorphous GST is ≥10^6Ω, and the resistance of a completely crystalline GST is ≈10^3Ω (typical value). The physical ratio between the two is about 10^3 times, or about 3 orders of magnitude, and can cover a range of 1-3 orders of magnitude across different GST compositions, doping, and operating current conditions. This invention uses the intermediate state multi-value resistance characteristics to linearly map multiple weight values.

[0090] Specifically, the weight value w ∈ [-1, 1] is mapped to the resistance value R(w) = R_min + (R_max - R_min)· (1 - w) / 2, where R_min is the crystalline resistance (approximately 10kΩ) and R_max is the amorphous resistance (approximately 1MΩ).

[0091] (III) Objective Calculation Method of Cognitive Trait Activation Value

[0092] One of the core technical features of this invention lies in converting the user's natural language interaction into an objective numerical vector with definite technical meaning, rather than relying on subjective psychological scales or expert experience for judgment. The activation value is calculated as follows:

[0093] The first step is to convert the interactive content (user input text) into a text feature vector v.

[0094] The text feature vector v is extracted using a TF-IDF weighted method—after segmenting the interactive text, the TF-IDF value of each word is calculated, forming a sparse vector v of dimension D (D is the dictionary size, typically 10,000-50,000; Spark MLlib's HashingTF defaults to numFeatures=10,000, while scikit-learn's TFfidfVectorizer has no upper limit by default, but common engineering configurations use 10,000-100,000; see F. Pedregosa et al.,

[0095] "Scikit-learn: Machine Learning in Python", JMLR 12, 2825-2830, 2011).

[0096] This text feature vector v belongs to data with objective numerical significance in the field of natural language processing, giving subsequent algorithm steps a clear technical direction.

[0097] The activation value x_i is a real number. A positive value indicates that the trait is activated in the current interaction, a negative value indicates that it is suppressed, and a zero value indicates that it has no effect. The magnitude of the activation value indicates the activation intensity.

[0098] (iv) Coding of Interaction Behavior Types

[0099] Interaction behavior type coding is used to distinguish different patterns of user interaction behavior, with each behavior type corresponding to a preset coding value. An example interaction behavior type coding is as follows:

[0100] Description of coded value interaction behavior types

[0101] 0x01 Asking a question: A user asks a question.

[0102] 0x02 Statement: The user states a fact or opinion.

[0103] 0x03 Commands: Users issue instructions or requests.

[0104] 0x04 Feedback: User evaluation of system output

[0105] 0x05 Clarify user comments to supplement or correct previous interactions.

[0106] Interaction behavior type encoding, as a component of structured interaction records, together with interaction content feature vectors and interaction timestamps, constitutes a complete interaction record.

[0107] (v) Hardware implementation of synaptic plasticity update circuit

[0108] The synaptic plasticity regeneration circuit consists of the following sub-modules:

[0109] Activation value buffer: Temporarily stores the activation vector x of the current interaction.

[0110] Multiplication array: Consists of multiple analog multipliers, calculating Δw_ij = η · x_i · x_j for all combinations of i,j.

[0111] The learning rate decay module stores the current interaction count n and calculates the current learning rate according to η_n = η0 / (1 + γ · n), where η0 is the initial learning rate (typically 0.1) and γ is the decay coefficient (typically 0.01). The reasonable range for the learning rate η0 is 0.01 to 0.5, and the reasonable range for γ is 0.001 to 0.05. The specific values ​​are determined based on the desired convergence speed in the application scenario. A larger γ value results in faster learning rate decay and earlier tensor convergence; a smaller γ value results in slower learning rate decay and a longer time for the tensor to adapt to new interactions.

[0112] This formula is the standard extended form of the Hebbian / Oja rule under decaying learning rate (Hebb, DO, "The Organization of Behavior", Wiley, 1949; Oja, E., "Simplified neuron model as aprincipal component analyzer", J. Math. Biol. 15, 267-273, 1982).

[0113] DAC (Digital-to-Analog Converter): Converts digital updates Δw into corresponding analog voltage amplitudes.

[0114] Pulse generator: Generates programmed pulses with corresponding pulse widths based on the voltage amplitude and applies them to the heating electrodes of the corresponding GST memory cells. The longer the pulse width, the higher the GST crystallization ratio and the lower the resistance value.

[0115] The update process is as follows:

[0116] The interaction encoding module outputs the cognitive trait activation vector x of the current interaction.

[0117] The synaptic plasticity update circuit reads the current weight value w_ij (obtained through the readout circuit).

[0118] The multiplication array is used to calculate Δw_ij = η · x_i · x_j.

[0119] The DAC converts Δw into voltage pulse parameters.

[0120] The pulse generator applies a programming pulse to the corresponding GST memory cell to complete the weight update.

[0121] The entire update process is completed at the hardware level, without going through the operating system or database software stack.

[0122] (vi) Inference Adaptation Interface

[0123] The inference adapter interface includes a readout circuit and a readout interface conversion module. The readout interface conversion module adaptively selects either an ADC digital readout interface or an analog current readout interface according to the selected physical medium type: (1) When the selected physical medium is a phase change memory, the inference adapter interface adopts an ADC digital readout interface. The readout circuit applies a low-amplitude readout pulse (insufficient to trigger a phase change) to the GST memory cell, and the ADC converts the readout resistance value into a digital weight value.

[0124] (2) When the selected physical medium is a memristor, the inference adapter interface adopts an analog current readout interface, which directly obtains the weight value by sensing the output current of the column line without the need for DAC / ADC conversion, further reducing latency and power consumption.

[0125] The conversion logic of the weight value is as follows: the resistance value read is R, and the corresponding weight value is w = 1 - 2·(R - R_min) / (R_max - R_min).

[0126] After obtaining the weight vector, the inference adaptation interface converts it into inference preference parameters for the downstream inference engine. For example:

[0127] If the weight w1 of the "concise-detailed" dimension is greater than 0.5, the upper limit of the output length of the inference engine is set to a shorter value.

[0128] If the weight w2 of the "rigorous-divergent" dimension is greater than 0.5, the level of detail in the reasoning steps of the inference engine is set to a higher value.

[0129] If the weight w3 of the "calm-passion" dimension is greater than 0.5, the output tone of the inference engine is set to a rational and objective style.

[0130] Otherwise, use the default parameters.

[0131] (vii) Optional implementation methods of reflection caching

[0132] The reflection cache consists of a hardware non-volatile cache (such as Content Addressable Memory (CAM)) used to store input-output mapping pairs for high-frequency inference paths. The typical CAM matching time is 160ns, with a maximum clock frequency of 50MHz, significantly lower than DRAM access time. When a user's input features match the input portion of a mapping pair stored in the cache (matching degree exceeding a preset threshold, such as 95%), the inference adaptation interface directly reads the corresponding inference preference parameters from the cache, skipping the reading process of the multi-valued resistive synaptic weight tensor storage unit, further reducing latency.

[0133] The cache is updated using an LRU (Least Recently Used) strategy to maintain the validity of high-frequency mapping pairs.

[0134] (viii) Optional Implementation Methods for the Dimensionality Reduction Mapping Module

[0135] The dimensionality reduction and mapping module extracts the primary dimensions (such as the first 2-3 principal components) that have the greatest impact on inference preferences from multiple dimensions of the multivalued resistive synaptic weight tensor through eigenvalue decomposition or principal component analysis (PCA), discarding secondary dimensions. Specifically, it calculates the covariance matrix of the accumulated historical weight tensor data, extracts several principal components with the largest eigenvalues ​​as low-dimensional representations after dimensionality reduction, and maps them to inference preference parameters. This module can serve as an optional data compression layer between the storage unit and the inference adaptation interface, suitable for scenarios with limited storage resources or limited input dimensions of the inference engine.

[0136] Example 2: Multi-valued resistive synaptic weighted tensor device based on memristor cross array

[0137] In this embodiment, the non-volatile physical storage medium uses a memristor cross array as an alternative implementation to Embodiment 1.

[0138] (a) Memristor cross array structure

[0139] The memristor cross array consists of an M×N cross point array formed by the interlacing of M row lines and N column lines (M=N=m, corresponding to the fully connected weight matrix of m cognitive trait dimensions). Each cross point contains a memristor cell, which is connected to the corresponding row line and column line.

[0140] The memristor unit in this embodiment adopts a resistive random access memory with a Pt / TaO_x / Ta structure or a Pt / HfO_x / TiN structure. Its resistance value is continuously adjustable in the range of 10kΩ to 1MΩ by controlling the amplitude and pulse width of the programming voltage. The resistance value is non-volatile and retained after power is turned off.

[0141] TaO_x-based memristors have achieved sub-nanosecond switching speeds (AC Torrezan, JP Strachan, G. Medeiros-Ribeiro, RS Williams, "Sub-nanosecond switching of a tantalum oxide memristor", Nanotechnology 22, 485203, 2011, with measured switching time <1ns).

[0142] Typical switching speeds for HfO_x-based RRAM cells are in the order of ns-100ns (H.-SP Wong et al., "Metal–Oxide RRAM", Proc. IEEE 100, 1951-1970, 2012).

[0143] (ii) Storage and updating of weight values

[0144] The resistance value of each memristor cell directly corresponds to a weight value in the multi-valued resistive synaptic weight tensor. Unlike the phase-change memory in Embodiment 1, the memristor cross array does not require separate read and write circuits—the row drive circuit and column read circuit simultaneously perform the write and read functions.

[0145] During the update, the synaptic plasticity update circuit applies a voltage pulse proportional to Δw between the corresponding row and column lines. The resistance of the memristor changes gradually, completing the weight update. Since the resistance change of the memristor is continuously adjustable, incremental updates in the analog domain can be achieved. Therefore, this embodiment uses an analog current readout interface, eliminating the need for DAC / ADC conversion (forming two readout interface schemes with the ADC digital readout interface of Embodiment 1, covering both phase-change memory and memristor as two major physical media).

[0146] During readout, the row drive circuit applies a low-amplitude read voltage to the row lines, while the column readout circuit senses the output current of the column lines. Based on the relationship I = V / R, the output current is inversely proportional to the memristor resistance, allowing the calculation of the corresponding weight value.

[0147] (III) Comparison with Example 1

[0148] Compared with Embodiment 1 (phase-change memory), the memristor cross-array scheme of this embodiment has the following advantages:

[0149] Both updates and reads can be performed directly in the analog domain without the need for DAC / ADC conversion (using an analog current readout interface), further reducing latency and power consumption.

[0150] The two-dimensional structure of the cross array naturally supports parallel updates of the weight matrix, making it suitable for scenarios where multiple dimensions are updated simultaneously.

[0151] Memristors have faster resistance switching speeds and support higher frequency synaptic plasticity updates.

[0152] Both have in common that they use the resistance change of a non-volatile physical medium to store weight values, both are updated directly through hardware circuits, and both retain data without loss after power failure.

[0153] Experimental verification

[0154] In the simulation experiment, 100 user interactions were simulated, with each interaction randomly generating a cognitive trait activation vector (simulating different interaction styles). The initial learning rate η0 = 0.1, and the decay coefficient γ = 0.01.

[0155] The experimental results show that:

[0156] In the first 20 interactions, the weight values ​​of each dimension of the multivalued resistive synaptic weight tensor are rapidly adjusted.

[0157] After 50 interactions, the weight values ​​of the main dimensions tend to stabilize.

[0158] After 100 interactions, the weight fluctuation was less than 0.05 (normalized value).

[0159] Compared to existing solutions (with a latency of approximately 10 milliseconds per database query), this solution achieves a hardware read latency of less than 100 nanoseconds (approximately 50 ns for phase-change memory readout and approximately 30 ns for ADC conversion). Typical PCM readout time is 50-60 ns (H.-SP Wong et al., "Phase Change Memory", Proc. IEEE 98, 2201-2227, 2010, Table I: PCM Read Time 50 ns).

[0160] Modern SAR ADCs have a conversion time of approximately 30ns at 14-bit precision, while the 7-bit 175GS / s ADC released by imec at ISSCC 2026 has a conversion time of 5.7ns (imec Press Release, "imec unveils 7-bit 175GS / s massivelytime-interleaved slope ADC", 2026).

[0161] Example 3: Non-volatile multi-valued weighting device based on ferroelectric field-effect transistor

[0162] In this embodiment, the non-volatile physical storage medium uses a ferroelectric field-effect transistor (FeFET) as another alternative implementation to Embodiments 1 and 2. The FeFET utilizes the residual polarization state of the ferroelectric material (such as an HfO2-based ferroelectric thin film) to store weight values: the polarization direction corresponds to the weight sign, and the degree of polarization corresponds to the weight magnitude.

[0163] (a) FeFET memory cell structure

[0164] In this embodiment, the FeFET employs a metal-ferroelectric-insulator-semiconductor (MFIS) structure or a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. The ferroelectric layer is a doped HfO2 thin film (such as Si:HfO2 or Zr:HfO2) with a thickness of approximately 5-10 nm, compatible with standard CMOS processes. Each FeFET cell controls the polarization reversal of the ferroelectric layer through a gate voltage pulse to write the weight value; the polarization state is non-volatilely maintained after power-off.

[0165] (ii) Storage and updating of weight values

[0166] Each FeFET cell's polarization state directly corresponds to a weight value in the multi-valued resistive synaptic weight tensor. During writing, the synaptic plasticity update circuit applies a voltage pulse proportional to Δw to the FeFET gate. By controlling the pulse amplitude and pulse width, the degree of polarization reversal is adjusted, thus achieving analog domain writing of the multi-valued weights. During reading, the FeFET's channel conductance changes with the ferroelectric polarization state. The corresponding weight value can be obtained by sensing the channel current, eliminating the need for a separate external resistor for the memory cell.

[0167] (III) Comparison with Examples 1 and 2

[0168] Compared with Embodiment 1 (phase-change memory) and Embodiment 2 (memristor cross array), the FeFET solution in this embodiment has the following advantages: FeFET is manufactured based on standard CMOS process, and has a higher degree of monolithic integration with logic circuits; writing is based on ferroelectric polarization flipping rather than resistive phase change / resistive change, resulting in lower writing power consumption and no current heat effect; it has excellent polarization retention characteristics and is suitable for long-term cross-session weight continuous growth scenarios.

[0169] The commonalities with Embodiment 1 and Embodiment 2 are: all of them utilize the physical state changes of non-volatile physical media to persistently store weight values; all of them are updated directly through hardware circuits; and all of them retain data without loss after power failure. They collectively embody the core inventive concept of "hardware-level nanosecond-level multi-value resistor cumulative growth" of this invention.

[0170] Explanation of reference numerals in the attached figures

[0171] 1—Interactive encoding module; 2—Multi-valued resistive synaptic weight tensor storage unit; 3—Synaptic plasticity update circuit; 4—Inference adapter interface;

[0172] 21—Programming pulse generator; 22—Readout circuit;

[0173] 31—Row line; 32—Column line; 33—Memristor unit; 34—Row drive circuit; 35—Column readout circuit;

[0174] 40—DAC; 41—Pulse generator; 42—Learning rate decay module.

[0175] The core value of this application lies in using Heb's rule to achieve cross-session hardware-level accumulation and nanosecond-level reading of cognitive patterns on non-volatile storage media.

[0176] [Patent Family Synergy Statement]

[0177] This application is one of 11 deterministic computing architecture patent families filed by the applicant on the same day. The inventive subject matter, all technical features claimed in the claims, and the specific embodiments shown in the drawings are fully and independently disclosed in the specification and drawings of this application, and can be implemented and reproduced by a person skilled in the art without relying on other applications in the same family.

[0178] The technical solutions claimed in this application are structurally independent from other applications in the same family at the physical implementation level, each containing a complete physical structure, signal flow path, range of technical parameters and specific embodiments, thus satisfying the unity requirement of CNIPA §31.

[0179] The key parameters of this invention are: weight accumulation rate ≥ 80% and retention rate (weight accumulation rate decreases by ≥ 80% when the parameter deviates by 50%).

[0180] [Industry Application]

[0181] This invention belongs to the field of physical computing hardware technology. It can be manufactured and used in industry and can be applied to deterministic computing tasks, artificial intelligence inference acceleration, symbol generation and detection, quantum precision measurement and other fields, and has clear industrial applicability.

[0182] [Data Source Explanation] The specific performance data (including but not limited to latency, power consumption, sensitivity, etc.) listed in this specification are all obtained based on publicly available theoretical analysis and comparison with published similar measured parameters. In actual hardware implementation, there may be differences due to different process nodes, component selections and system integration schemes. This data is used to illustrate the relative advantages of the technical solution of this application compared with existing solutions, and does not constitute a limitation on the scope of protection of this application.

Claims

1. A cross-conversation cognitive device, characterized in that... , include: A non-volatile physical storage module is used to persistently store a multi-dimensional personality weight tensor. Each dimension of the personality weight tensor corresponds to a preset personality trait dimension. The non-volatile physical storage module uses changes in physical state (resistance / crystalline state / magnetization) to represent the weight values. The interaction encoding module is used to convert user interactions with the system into structured interaction records. The Heb update module, whose input is connected to the interactive encoding module and whose read / write end is connected to the non-volatile physical storage module, is used to calculate the weight update amount of each dimension in the personality weight tensor according to the Heb rule and the structured interaction record, and directly write the updated weight value into the non-volatile physical storage module; The inference adaptation module is used to read the current personality weight tensor and convert the weight values ​​of each dimension into inference preference parameters for the downstream inference engine. The non-volatile physical storage module, the interaction encoding module, the Heb update module, and the inference adaptation module are physically independent of each other. The personality weight tensor is continuously maintained by the non-volatile physical storage module during cross-session periods, and its weight value gradually converges as the number of interactions increases.

2. A cross-conversation cognitive method, characterized in that... This includes the following steps: Encode user interactions with the system into structured interaction records; Based on Hebb's rule, the weight update amounts of each dimension in the multidimensional personality weight tensor are calculated according to the structured interaction records; The updated weight values ​​are directly written to the non-volatile physical storage module, which persistently stores the multidimensional personality weight tensor. Read the current personality weight tensor and convert the weight values ​​of each dimension into inference preference parameters for the downstream inference engine.

3. The apparatus or method according to claim 1 or 2, characterized in that... The physical medium of the non-volatile physical storage module includes at least one of the following: phase-change memory (GST material), memristor cross array, magnetoresistive random access memory, and ferroelectric field-effect transistor (FeFET).

4. The apparatus or method according to claim 1 or 2, characterized in that... The weight update formula of the Heb update module is Δw_ij = η·x_i·x_j - γ·w_ij, where the learning rate η ∈ [0.01, 0.5] and the decay coefficient γ ∈ [0.001, 0.05]; preferably, η = 0.1 and γ = 0.

01.

5. The apparatus or method according to claim 1 or 2, characterized in that... It also includes an L0.5 reflection cache module, which is composed of a hardware non-volatile cache and is used to store the input-output mapping pairs of high-frequency inference paths. During inference, it preferentially reads from the L0.5 reflection cache, and skips the complete inference calculation process if the cache is hit. The hardware non-volatile cache is a content-addressable memory with a matching time of 160ns, a clock frequency of 50MHz, and a personality weight tensor read latency of less than 100ns.

6. The apparatus or method according to claim 1 or 2, characterized in that... The physical state changes (resistance / crystal state / magnetization) of the non-volatile physical storage module do not depend on neural networks or large model calls.

7. The apparatus or method according to claim 1 or 2, characterized in that... It also includes a backdistillation module, used to map the high-dimensional personality trait weights in the personality weight tensor to low-dimensional inference preference parameters. The mapping extracts the main dimensions that have the greatest impact on inference preference through eigenvalue decomposition or principal component analysis.

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