A data processing method, apparatus and device

Abstract

A data processing method, apparatus, and device are disclosed, relating to the field of computer technology. The method is applied to a tensor computing device within a computing device. The method includes: obtaining a first matrix and a second matrix to be multiplied, wherein the first and second matrices are of a first data type; reconstructing the first and second matrices into a first matrix group and a second matrix group respectively, based on a first parameter and a second parameter; wherein the first parameter characterizes the input data type of the tensor computing device as a second data type, the second data type characterizing the matrix elements has fewer bits than the first data type characterizing the input data type; the second parameter determines the reconstruction rule, and the first and second matrix groups are of the second data type; performing a Cartesian product operation on the first and second matrix groups to obtain an intermediate result matrix; and using a fusion function matched with the second parameter, reconstructing a target matrix from the intermediate result matrix, wherein the target matrix is ​​the expected result of multiplying the first and second matrices.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus and device for data processing. Background Technology

[0002] Lattice cryptography is a post-quantum cryptographic scheme based on mathematical problems related to lattice algebra. It offers faster encryption and decryption speeds and is resistant to quantum attacks. Lattice cryptography has a wide range of applications; for example, all fully homomorphic cryptographic algorithms, which are widely used in fields such as privacy computing, are based on lattice cryptography, and it has shown potential in cloud computing, blockchain, and other scenarios.

[0003] Lattice cryptography algorithms can be categorized algebraically into structured and unstructured lattice cryptography algorithms. Structured lattice cryptography algorithms, having become industry standards, are considered to have higher practical application value, leading to more mature academic and industrial support for research on accelerating them. In contrast, research on unstructured lattice cryptography still faces numerous technical and standardization challenges. However, in reality, compared to structured lattice cryptography algorithms, unstructured lattice cryptography algorithms offer more conservative security and can resist quantum computing attacks, showing great potential in high-security scenarios. Therefore, the industry urgently needs to fill the gap in unstructured lattice cryptography acceleration technologies.

[0004] Acceleration techniques for unstructured lattice cryptography refer to using matrix units (MUs) to speed up computations on the large number of tensor data (including matrices and vectors) contained in the algorithm, thereby improving the computational efficiency of lattice cryptography. However, the computational performance of MUs in current related technologies is limited. For example, most only support small integer matrix multiplication operations. This means that MUs can only handle some informal versions of unstructured lattice cryptography algorithms (i.e., multiplication of low-bit-width matrices) and cannot support acceleration of formal versions of unstructured lattice cryptography algorithms involving large integer matrix multiplications, thus hindering the standardization process of unstructured lattice cryptography algorithms. Summary of the Invention

[0005] This application provides a data processing method, apparatus, computing device, computer storage medium, and computer program product, which can improve computing efficiency in scenarios involving large integer matrix multiplication (such as encryption and decryption scenarios based on unstructured lattice cryptography algorithms).

[0006] In a first aspect, embodiments of this application provide a data processing method applied to a tensor computing device in a computing device. The method includes: obtaining a first matrix and a second matrix to be multiplied, wherein the first matrix and the second matrix are of a first data type; reconstructing the first matrix and the second matrix into a first matrix group and a second matrix group respectively according to a first parameter and a second parameter; wherein the first parameter is used to characterize the input data type of the tensor computing device as a second data type, the number of bits of matrix elements characterized by the second data type is lower than the number of bits of matrix elements characterized by the first data type, the second parameter is used to determine the reconstruction rule, and the first matrix group and the second matrix group are of the second data type; performing a Cartesian product operation on the first matrix group and the second matrix group to obtain an intermediate result matrix; and using a fusion function matched with the second parameter to reconstruct a target matrix from the intermediate result matrix, wherein the target matrix is ​​the expected result of multiplying the first matrix and the second matrix.

[0007] In this embodiment, the tensor computing device in the computing device can provide matrix multiplication and addition capabilities as well as various operational capabilities for vector data. Its input data type can be referred to herein as the second data type, which determines the element bit width of the valid input. Thus, if the element bit width of the first matrix and / or the second matrix received by the tensor computing device exceeds the input data type (i.e., it does not match the input data type), the mismatched first or second matrix can be reconstructed into a group of small integer matrices. Then, a Cartesian product operation is performed on the matrix group, and a fusion function is used to reconstruct the expected result of the first and second matrices from the Cartesian product result. Therefore, even if the hardware performance of the current tensor computing device is limited (e.g., it does not support large integer matrix operations), this embodiment can convert large integer matrix multiplication into a group of small integer matrices that conforms to the valid input of the tensor computing device without changing the hardware performance, thereby completing the relevant calculation tasks without loss of accuracy. This expands the application scenarios of tensor computing devices in some cases involving large integer matrix multiplication and addition (such as unstructured lattice cryptographic algorithms), and can accelerate computation based on current hardware performance, improve computational efficiency, and reduce the difficulty of accelerating computation of similar unstructured lattice cryptographic algorithms.

[0008] In some possible implementations, the tensor computing device includes u matrix computing units, where u is a positive integer. If there are several first and second matrices to be multiplied, several pairs of first and second matrix groups are reconstructed. A Cartesian product operation is performed between the first and second matrix groups to obtain an intermediate result matrix, including: for the w-th matrix computing unit, determining the base addresses of all first and second matrix groups from the several pairs of first and second matrix groups; 1 ≤ w ≤ u; using an addressing function to determine the address difference of elements with the same position index between adjacent matrix groups; the w-th matrix computing unit obtains the corresponding first and second matrix groups from the address difference offset by w units from the base address and performs multiplication operations to obtain a sub-result. The sub-result is used to sum with the sub-results obtained in parallel by the remaining matrix computing units to obtain the intermediate result matrix.

[0009] Thus, the addressing strategy described above in this implementation can improve the parallel processing capability of tensor computing devices, enabling them to better support parallel data scheduling for large integer matrix multiplication tasks in scenarios such as unstructured lattice cryptography algorithms, achieve batch processing, and improve computational efficiency.

[0010] In some possible implementations, if the number of bits of the elements of the first or second matrix is ​​less than the number of bits of the matrix elements represented by the second data type, then the matrix is ​​not reconstructed.

[0011] In this way, matrices that match the input data type of the tensor computing device do not need to be reconstructed and can directly participate in matrix multiplication and addition calculations. For example, the matrix group after the reconstruction of the first matrix (such as the left matrix) is used to calculate the Cartesian product with the second matrix (such as the right matrix, which is a small integer matrix) and then subsequent processing is performed to obtain the target matrix. This reduces the amount of data processing and improves computational efficiency.

[0012] In some possible implementations, the number of bits per element in the first matrix and the second matrix are respectively the first number of bits per element and the second number of bits per element; the second parameter includes a target bit width, which does not exceed the number of bits per element of the matrix represented by the second data type; according to the first parameter and the second parameter, the first matrix and the second matrix are reconstructed into a first matrix group and a second matrix group respectively, including: according to the target bit width, each element in the first matrix is ​​ordered to be split into at least two sub-elements, and at least two first sub-blocks are obtained; the at least two first sub-blocks are concatenated in the column direction of the first matrix to obtain a first matrix group including at least two first sub-blocks; according to the target bit width, each element in the second matrix is ​​ordered to be split into at least two sub-elements, and at least two second sub-blocks are obtained; the at least two second sub-blocks are concatenated in the column direction of the second matrix to obtain a second matrix group including at least two second sub-blocks.

[0013] In this implementation, the first and / or second matrices can be element-wise split and reassembled according to a preset bit width (the second parameter). This reduces the element bit width without compromising precision, while maintaining consistent element indices before and after the split. This ensures data integrity when subsequently obtaining the Cartesian product of the matrix group.

[0014] In some possible implementations, the fusion function includes one or more elementary transformations; the target matrix is ​​recovered from the intermediate result matrix using the fusion function matched with the second parameter, including: determining the manner, number, and order of the elementary transformations included in the fusion function according to the second parameter; and performing elementary transformations on the intermediate result matrix through the fusion function to obtain the target matrix.

[0015] In this implementation, the intermediate matrix obtained by performing a Cartesian product on each pair of matrices is matched with a corresponding fusion function. The fusion function can be understood as the inverse operation of reconstructing the matrices and performing a Cartesian product to restore the product of the original input (i.e., the first matrix and the second matrix), ensuring the correctness of the acquired data.

[0016] In some possible implementations, the first matrix is ​​a random matrix in the unstructured lattice cryptography algorithm, and the second matrix is ​​used to represent the private key in the unstructured lattice cryptography algorithm. After restoring the target matrix from the intermediate result matrix, the method includes: obtaining a first random vector; performing an addition operation between the target matrix and the first random vector to obtain a first result matrix, which is used as the public key in the unstructured lattice cryptography algorithm.

[0017] In this implementation, if the first and second matrices are matrices involved in a scenario where the computing device uses an unstructured lattice cryptography algorithm to generate a public key—that is, if the first and second matrices are random matrices and a private key (a randomly generated matrix) generated by the computing device using its built-in random number generator—then the target matrix obtained by processing the first and second matrices using this method, when added to the first random vector generated by the random number generator, yields the corresponding public key (or public key vector). This expands the application scenarios of tensor computing devices with limited current computing power.

[0018] In some possible implementations, the first matrix represents the private key in the unstructured lattice cryptography algorithm, and the second matrix is ​​a concatenation matrix, which is the matrix obtained by concatenating the random matrix and the public key in the unstructured lattice cryptography algorithm, with the public key matching the private key. After restoring the target matrix from the intermediate result matrix, the method includes: obtaining the plaintext vector to be encrypted, the first random vector, and the second random vector; concatenating the sum of the plaintext vector and the second random vector with the first random vector to obtain the concatenated vector; and performing a summation operation between the concatenated vector and the target matrix to obtain the composite ciphertext of the plaintext vector.

[0019] In this implementation, if the first and second matrices are involved in a scenario where the computing device uses an unstructured lattice cryptography algorithm to encrypt ciphertext, i.e., the first matrix is ​​the private key (a randomly generated matrix) generated by the computing device's built-in random number generator, and the second matrix is ​​the concatenation result of the corresponding public key and the random matrix generated by the random number generator, then the target matrix obtained after processing the first and second matrices using this method can be added to the two types of random vectors (the first random vector and the second random vector) generated by the random number generator and the plaintext vector to complete the information encryption based on the unstructured lattice cryptography algorithm. This expands the application scenarios of tensor computing devices with limited current computing power.

[0020] In some possible implementations, the first matrix is ​​used to represent the private key in the unstructured cipher algorithm, and the second matrix is ​​the main ciphertext component obtained by the unstructured cipher algorithm. The main ciphertext component contains the corresponding plaintext vector. The main ciphertext component can be concatenated with the auxiliary ciphertext component to form a composite ciphertext. The auxiliary ciphertext component is used to obfuscate the plaintext information. After restoring the target matrix from the intermediate result matrix, the method includes: performing a vector subtraction operation between the target matrix and the auxiliary ciphertext component to obtain the plaintext vector.

[0021] In this implementation, if the first and second matrices are involved in a scenario where the computing device uses an unstructured ciphertext algorithm to decrypt ciphertext, i.e., the first matrix is ​​the private key (a randomly generated matrix) generated by the computing device's built-in random number generator, and the second matrix is ​​the main ciphertext vector encrypted by the corresponding unstructured ciphertext algorithm, then the target matrix obtained by processing the first and second matrices using this method can be subtracted from the auxiliary ciphertext vector in the ciphertext to complete the information decryption based on the unstructured ciphertext algorithm. This expands the application scenarios of tensor computing devices with limited current computing power.

[0022] Secondly, embodiments of this application provide a data processing apparatus applied to a tensor computing device in a computing device. The apparatus includes: an acquisition module for acquiring a first matrix and a second matrix to be multiplied, wherein the first and second matrices are of a first data type; a processing module for reconstructing the first and second matrices into a first matrix group and a second matrix group respectively according to a first parameter and a second parameter; wherein the first parameter characterizes the input data type of the tensor computing device as a second data type, the second data type characterizing the matrix element bit length is lower than the first data type characterizing the matrix element bit length, the second parameter determines the reconstruction rule, and the first and second matrix groups are of the second data type; the processing module is further configured to perform a Cartesian product operation on the first and second matrix groups to obtain an intermediate result matrix; the processing module is further configured to use a fusion function matched with the second parameter to reconstruct a target matrix from the intermediate result matrix, the target matrix being the expected result of multiplying the first and second matrices.

[0023] In some possible implementations, the tensor computing device includes u matrix computing units, where u is a positive integer. If there are several first and second matrices to be multiplied, several pairs of first and second matrix groups are reconstructed. The processing module is specifically used to: for the w-th matrix computing unit, determine the base addresses of all first and second matrix groups from the several pairs of first and second matrix groups; 1≤w≤u; use the addressing function to determine the address difference of elements with the same position index between adjacent matrix groups; the w-th matrix computing unit obtains the corresponding first and second matrix groups from the address difference offset by w units from the base address and performs multiplication operations to obtain sub-results. The sub-results are used to sum with the sub-results obtained in parallel by the remaining matrix computing units to obtain an intermediate result matrix.

[0024] In some possible implementations, if the number of bits of the elements of the first or second matrix is ​​less than the number of bits of the matrix elements represented by the second data type, then the matrix is ​​not reconstructed.

[0025] In some possible implementations, the number of bits per element in the first matrix and the second matrix are respectively the first number of bits and the second number of bits; the second parameter includes a target bit width, which does not exceed the number of bits per element of the matrix represented by the second data type; the processing module is specifically used to: according to the target bit width, orderly split each element in the first matrix into at least two sub-elements to obtain at least two first sub-blocks; concatenate the at least two first sub-blocks in the column direction of the first matrix to obtain a first matrix group including at least two first sub-blocks; according to the target bit width, orderly split each element in the second matrix into at least two sub-elements to obtain at least two second sub-blocks; concatenate the at least two second sub-blocks in the column direction of the second matrix to obtain a second matrix group including at least two second sub-blocks.

[0026] In some possible implementations, the fusion function includes one or more elementary transformations; the processing module is specifically used to: determine the method, number, and order of the elementary transformations included in the fusion function according to the second parameter; and perform elementary transformations on the intermediate result matrix through the fusion function to obtain the target matrix.

[0027] In some possible implementations, the first matrix is ​​a random matrix in the unstructured lattice cryptography algorithm, the second matrix is ​​used to represent the private key in the unstructured lattice cryptography algorithm, the acquisition module is further used to: acquire the first random vector; the processing module is further used to: perform an addition operation on the target matrix and the first random vector to obtain a first result matrix, the first result matrix is ​​used as the public key in the unstructured lattice cryptography algorithm.

[0028] In some possible implementations, the first matrix is ​​used to represent the private key in the unstructured lattice cryptography algorithm, and the second matrix is ​​a concatenation matrix, which is the matrix obtained by concatenating the random matrix and the public key in the unstructured lattice cryptography algorithm, and the public key is matched with the private key; the acquisition module is also used to: acquire the plaintext vector to be encrypted, the first random vector, and the second random vector; the processing module is also used to: concatenate the sum of the plaintext vector and the second random vector with the first random vector to obtain the concatenated vector; and perform a summation operation between the concatenated vector and the target matrix to obtain the composite ciphertext of the plaintext vector.

[0029] In some possible implementations, the first matrix is ​​used to represent the private key in the unstructured cipher algorithm, the second matrix is ​​the main ciphertext component obtained by the unstructured cipher algorithm, the main ciphertext component contains the corresponding plaintext vector, the main ciphertext component can be concatenated with the auxiliary ciphertext component to form a composite ciphertext, the auxiliary ciphertext component is used to obfuscate plaintext information; the processing module is also used to: perform vector subtraction operation between the target matrix and the auxiliary ciphertext component to obtain the plaintext vector.

[0030] Thirdly, embodiments of this application provide a computing device, including: at least one memory for storing a program; and at least one processor for executing the program stored in the memory; wherein, when the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0031] Fourthly, embodiments of this application provide a computing device cluster, including at least one computing device, each computing device including a processor and a memory; the processor of the at least one computing device is used to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster performs the method described in the first aspect or any possible implementation of the first aspect.

[0032] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to perform the method described in the first aspect or any possible implementation thereof.

[0033] In a sixth aspect, embodiments of this application provide a computer program product, characterized in that, when the computer program product is run on a processor, it causes the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0034] In a seventh aspect, embodiments of this application provide a chip, characterized in that it includes at least one processor and an interface; at least one processor obtains program instructions or data through the interface; at least one processor is used to execute program line instructions to implement the method described in the first aspect or any possible implementation of the first aspect.

[0035] It is understood that the beneficial effects of the second to seventh aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of data processing performed on a tensor computing device in an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of data processing performed on a tensor computing device in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of data processing performed on a tensor computing device in an embodiment of this application;

[0040] Figure 5AThis is a schematic diagram of data processing performed on a tensor computing device in an embodiment of this application;

[0041] Figure 5B This is a schematic diagram of data processing performed on a tensor computing device in an embodiment of this application.

[0042] Figure 6 This is a schematic diagram illustrating end-to-end encryption and decryption using an unstructured lattice cryptographic algorithm in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the client performing key generation for an unstructured lattice cryptography algorithm in an embodiment of this application;

[0044] Figure 8 This is a schematic diagram of the server performing encryption using an unstructured lattice cryptography algorithm in an embodiment of this application;

[0045] Figure 9 This is a schematic diagram of the client performing decryption of an unstructured lattice cryptography algorithm in an embodiment of this application;

[0046] Figure 10 This is a schematic diagram illustrating end-to-end encryption and decryption using an unstructured lattice cryptographic algorithm in an embodiment of this application;

[0047] Figure 11 This is a flowchart illustrating a data processing method provided in an embodiment of this application;

[0048] Figure 12 This is a flowchart illustrating a data processing method provided in an embodiment of this application;

[0049] Figure 13 This is a flowchart illustrating a data processing method provided in an embodiment of this application;

[0050] Figure 14 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0051] Figure 15 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0052] Figure 16 This is a schematic diagram of the architecture of a computing device cluster provided in an embodiment of this application;

[0053] Figure 17 This is a schematic diagram of the architecture of a computing device cluster provided in an embodiment of this application. Detailed Implementation

[0054] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0055] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first matrix" and "second matrix," etc., are used to distinguish different matrices, not to describe a specific order of matrices.

[0056] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0057] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0058] To facilitate understanding of the technical solutions in this application, the technical terms used in this document are explained below.

[0059] A tensor is a multidimensional array in mathematics, a higher-dimensional extension of scalars (0-dimensional), vectors (1-dimensional), and matrices (2-dimensional). In deep learning, tensors are used to represent input data (such as images and text), model parameters (such as weight matrices), and intermediate computation results.

[0060] Tensor computing devices are hardware or systems designed for tensor operations (efficient computation of multidimensional arrays), primarily used to accelerate computational tasks in fields such as artificial intelligence (AI), deep learning, scientific computing, and large-scale data processing. Examples include, but are not limited to, graphics processing units (GPUs), tensor processing units (TPUs), and neural processing units (NPUs).

[0061] A Matrix Unit (MU) is a dedicated calculator in a tensor computing device capable of rapidly performing matrix multiplication and addition. It can be used to perform mixed-precision multiply-add (FMA) operations. FMA treats multiplication and addition as two parts of a single operation, allowing multiple matrix multiplication and addition operations to be performed within a single clock cycle. It also allows for different precision data types for input and output (typically, the output has higher precision). For example, some GPU tensor cores are a type of Matrix Unit. In related technologies, each tensor core in a GPU typically performs 64 floating-point FMAs within a single clock cycle. The input for each FMA operation is a half-precision floating-point number (FP16), and the product of these inputs after multiplication is a full-precision floating-point number (FP32). Summing 64 FP32 results yields the final result. As another example, eight tensor cores in a streaming multiprocessor (SM) can perform 1024 floating-point operations per clock cycle (equivalent to 512 FMAs).

[0062] Vector Unit (VU): A vector unit in a tensor computing device is capable of performing various operations (such as addition, subtraction, and shifting) on ​​vectorized data. A vector unit can process multiple data sets of the same type within one clock cycle. The function of a vector unit is similar to that of the SIMD (Single Instruction, Multiple Data) instructions in a central processing unit (CPU).

[0063] Post-quantum cryptography (PQC), also known as quantum-resistant cryptography, addresses the challenge of solving quantum cryptanalysis attacks using quantum computers. Public-key encryption algorithms widely used in computers and the internet are based on integer factorization, discrete logarithm problems, or elliptic curve cryptography, all of which are vulnerable to quantum computing and Shor's algorithm. PQC focuses on developing public-key encryption algorithms (especially public-key algorithms) that can resist cryptanalysis attacks by quantum computers. Its research areas include lattice cryptography, fault-tolerant learning problems (LWE), multivariate cryptography, hash cryptography, coding cryptography, and supersingular elliptic curve cryptography. The goal is to construct public-key encryption systems that are immune to quantum computing threats, replacing existing solutions.

[0064] Unstructured lattice cryptography: Unstructured lattices generally refer to algebraic structures without any special or regular structure. Unstructured lattice cryptography is a cryptographic algorithm designed based on the mathematical properties of unstructured lattices. Compared to structured lattices (such as polynomial ring / modular structures) that have specific patterns or symmetries that can be used for efficient computation, unstructured lattices lack certain regularities. This leads many security experts in the industry to believe that cryptographic schemes based on difficult problems on unstructured lattices can be more secure against certain types of attacks.

[0065] A large integer matrix is ​​a two-dimensional array with a large size (usually referring to a number of rows and columns exceeding hundreds, thousands, or even millions), where each element stores an integer.

[0066] Elementary transformations mainly include the following three transformations of matrix rows or columns: performing non-zero scalar multiplication on matrix rows or columns; adding a row or column of any multiple of the matrix to another row or column; and swapping the positions of any two rows or columns of the matrix.

[0067] One acceleration scheme for unstructured lattice cryptography algorithms is the TensorFro[LSZH21] scheme. In its experimental phase, this scheme attempted to accelerate the unstructured lattice cryptography algorithm FrodoKEM using a tensor core of matrix computation units. It primarily reduces computational complexity by compressing and reconstructing the matrices in the unstructured lattice cryptography algorithm FrodoKEM (informal version) using tensor decomposition techniques. Specifically, this acceleration scheme transforms the matrix decomposition problem in the key generation and encryption process of the unstructured lattice cryptography algorithm FrodoKEM into a tensor decomposition problem (i.e., dimensionality reduction of high-dimensional tensors), utilizing the low-rank approximation property of tensors to achieve efficient computation. However, since the tensor cores used in this current acceleration scheme typically only support smaller data formats (such as 8-bit integers, 16-bit floating-point numbers, etc.), while the official version of the unstructured lattice cryptography algorithm FrodoKEM has a larger modulus and its matrix elements are approximately 15-16 bits, this acceleration scheme cannot directly compute unstructured lattice cryptography algorithms involving large integer matrix multiplications using tensor cores.

[0068] Another acceleration scheme for unstructured lattice cryptography is the DPCrypto[LSH+21] scheme. This scheme uses the vectorized instruction set of the large core of the Graphics Processing Unit (GPU) to accelerate the matrix multiplication of the official version of the unstructured lattice cryptography algorithm FrodoKEM and optimizes the data scheduling in the computation process to a certain extent. However, the overall acceleration effect of this single operator-based acceleration scheme is still slightly weaker than that of the TensorFro scheme.

[0069] Therefore, current acceleration schemes for unstructured lattice cryptography algorithms suffer from poor acceleration effects and high hardware performance requirements, making them difficult to implement.

[0070] To improve the acceleration effect of unstructured lattice cryptographic algorithms and reduce the implementation difficulty of accelerated computation, this application provides a data processing method. This scheme mainly uses matrix operation units (MUs) and vector operation units (VUs) for joint operations, transforming the large integer matrix multiplication in unstructured lattice cryptographic algorithms into a computational task consisting of matrix multiplication and vector operations. This allows matrix operation units, which only support smaller data types of input, to be used to accelerate end-to-end computation tasks (including large integer matrix multiplication) in the formal implementation of unstructured lattice cryptographic algorithms. This improves acceleration efficiency and reduces the implementation difficulty of accelerating unstructured lattice cryptographic algorithms.

[0071] For example, Figure 1 A schematic diagram of the architecture of a computing device provided in this application is shown. Figure 1 As shown, the computing device 00 includes a host side 10 and a device side 20 that communicate with each other. The host side 10 can be responsible for generating a computation task for the original matrix and sending it to the device side 20. The device side 20 can be used to perform tensor (including matrix and vector) operations on the original matrix according to the received computation task to obtain the corresponding operation results.

[0072] In this example, the host side 10, as the control core of the computing device 00, may include a processor 110, main memory 120, and bus 130. Wherein:

[0073] Processor 110 can be a Central Processing Unit (CPU) or other specific integrated circuits. Processor 110 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. In practical applications, the host side 110 may include multiple processors 110. Processors 110 can access main memory 120 and various peripheral component interconnect (PCIe) devices by running an operating system and / or other software programs.

[0074] Processor 110 can be connected to main memory 120 via a bus (such as Double Data Rate, DDR). Main memory 120 is the main memory of host-side 110. Main memory 120 can be used to store running programs and data for fast access by processor 110. As an example, main memory 120 may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), or Read-Only Memory (ROM), but is not limited thereto. This application does not limit the number or type of main memory 120.

[0075] Bus 130 is used to implement communication between the internal components of the host side 10 and the device side 20. As an example, bus 130 may include, but is not limited to: PCIe for high-speed device connections, a Universal Serial Bus (USB) supporting hot-plugging of peripherals, a synchronous half-duplex communication bus (Inter-Integrated Circuit, I2C) or a full-duplex synchronous communication bus (Serial Peripheral Interface, SPI) for managing low-speed peripherals. For ease of illustration, Figure 1 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0076] In this example, device 20, as the main tensor operation core in computing device 00, may include tensor computing device 210, local memory 220, and communication interface 130, wherein:

[0077] Tensor computing device 210 can be used to perform matrix multiplication and addition calculations and related vectorized data operations according to computing tasks issued by host device 10. Exemplarily, tensor computing device 210 may include a Graphics Processing Unit (GPU), a Tensor Processing Unit (TPU), and / or a Neural Processing Unit (NPU), but is not limited thereto. In some possible examples, tensor computing device 210 may include several matrix computation units (MU) and multiple vector computation units (VU) to be responsible for matrix multiplication calculations and vectorized data operations, respectively.

[0078] Local memory 220 is communicatively connected to tensor computing device 210 and can be used to temporarily store computational data on device 20, reducing communication latency with host device 10. For example, local memory 220 may include one or more of SRAM, on-chip cache, and high-bandwidth memory (HBM), but is not limited thereto.

[0079] The communication interface 230 is used to enable data exchange between the device side 20 and the host side 10 or other device sides (which may be the device side of other computing devices). The communication interface 230 may include, but is not limited to, a PCIe slave interface, a network interface card, or a transceiver.

[0080] Next, taking the execution of a large integer matrix multiplication task on computing device 00 as an example, the data processing process of this embodiment will be explained.

[0081] In some possible implementations, the tensor computing device 210 of computing device 00 includes u matrix computing units MU and h vector computing units VU, which can jointly perform large integer matrix operations. Here, u and h are both positive integers greater than 0.

[0082] For example, please refer to Figure 2 Suppose that tensor computing device 210 receives X sets of matrix multiplication tasks, namely D1=A1S1, D2=A2S2,…,D X =A X S X , where the matrix matrix (X is a positive integer greater than 0). Matrix A i and S i All data types can be represented as type org It is understandable that the data type of a matrix determines the number of bits in each element, and the storage space occupied by the elements of matrices of different data types may be different.

[0083] In this example, the input data type of the matrix computation unit MU in the tensor computation device 210 can be represented as type. in ,type in The number of bits in the elements of the matrix < type org The number of bits in an element of a matrix. The output data type of a matrix computation unit (MU) can be represented as type. out Therefore, for each matrix multiplication task D... i =A i S i For i = 1, 2, ..., X, the processing steps include:

[0084] According to the input data type of the matrix calculation unit MU in (For ease of explanation, this is also referred to as the first parameter in this paper), for matrix A i and S i Refactoring was performed to obtain data types of type. in matrix group A′ i and S′ i , In other words, matrix group A′ i The number of bits in the elements is less than that in matrix A. i The number of bits in the elements, matrix group A′ i It includes multiple sub-blocks, and each sub-block is a matrix A. i A segment of low-bit-width data, but matrix group A′ i The accuracy and matrix A i The same. Similarly, the matrix group S′ i The number of bits in the elements is less than that in matrix S i The number of bits of the elements in the matrix, and the matrix group S′ i It includes multiple sub-blocks, and each sub-block is a matrix S. i It is a segment of low-bit-width data, but the precision remains unchanged. Thus, by using a large integer matrix A... i and S i Each is reconstructed into a set of small integer matrices A′ i and S′ i This satisfies the input requirements of the matrix calculation unit MU, thus enabling subsequent calculations to proceed smoothly.

[0085] For example, assuming the matrix computation unit (MU) supports multiplication of multiple 8-bit or 16-bit integers, multiplication of 64-bit or larger matrices might require more clock cycles. To address this, this embodiment uses preprocessing to reconstruct large integer matrices into low-bit-width matrix groups. For instance, by splitting the 64-bit elements of the matrix into four 16-bit elements and reconstructing them in an ordered manner, the multiplication of large integer matrices can be transformed into smaller multiplications of smaller integer matrix groups. This allows the MU to adapt to the computational environment it provides without losing precision, thus achieving the goal of accelerating computation.

[0086] The principle of reconstructing large integer matrices for tensor computing device 210 in this embodiment is explained below.

[0087] In some possible implementations, such as Figure 3 As shown, assuming the above matrix A i ,S i The number of bits of the elements are b A ,b SThe matrix computation unit (MU) can receive the following valid input data types: in The number of bits in the matrix elements represented is less than b. A b S Therefore, in this implementation, we can first process matrix A. i and S i The process involves restructuring, which means splitting and then recombining the matrices to obtain a group of smaller integers. This restructuring process includes the following:

[0088] In the case of a large integer matrix A i and S i Before performing the segmentation, a temporary parameter (also referred to as the second parameter in this paper for ease of explanation) t is selected as an auxiliary parameter. This temporary parameter t is used to limit the input matrix A. i and S i The element width of the reconstructed sub-block. For example, this temporary parameter t satisfies the following condition:

[0089] t≤bitlength(type in )

[0090] 2t≤bitlenth(type out )

[0091] Next, matrix A i any element a row , col Divide into t bits of length. Each part (also called a sub-element) is filled into the position of the l-th sub-block A′[l], where l = 1, 2, ..., g; the sub-blocks obtained by splitting are concatenated in the column direction to obtain a matrix group. Similarly, split matrix S i The resulting sub-blocks are then concatenated along the row direction to obtain a matrix group.

[0092] For example, suppose matrix A... i and S i It is a 2×2 matrix, where each element is a binary number with a bit width of 5.

[0093]

[0094] So, if we consider the input data type type of the tensor computing device 210 in If the temporary parameter t = 3 is determined, then matrix A can be... i and S i Each element is split into a lower 3 bits and a higher 2 bits as sub-elements. The higher bits have only 2 significant bits, so 0 is padded in the highest bit. Thus, matrix A... iSplit into two sub-blocks and Matrix S i Split into two sub-blocks and

[0095] Next, matrix A i The sub-blocks are concatenated sequentially along the column direction to obtain the reconstructed matrix group:

[0096]

[0097] Similarly, matrix S i The sub-blocks are concatenated sequentially along the row direction to obtain the reconstructed matrix group:

[0098]

[0099] Thus, matrix A i ,S i Before and after the split, the index positions of the elements remain the same. For example, matrix A. i The element in the first row and second column is split into two sub-elements. These two sub-elements remain in the first row and second column within their respective sub-blocks. This ensures correct data transfer during subsequent calculations and guarantees the accuracy of the results.

[0100] In this embodiment, since the matrix operation unit moves a certain amount of data (determined by the input data type) into the input (left or right) matrix storage sequence for computation each time, the amount of data moved each time cannot exceed the upper limit of the input matrix storage space. Therefore, in this example, when the element bits of the matrix in the received computation task are too large, the tensor computation device 210 can split and recombine them in the above manner to construct a matrix group with g (rounded up) dimensions that are the same as the original matrix. Appropriate selection of temporary parameters ensures that the reconstructed matrix group is compatible with the data moving and computational capabilities of the matrix operation unit MU. When performing multiplication operations on these matrix groups subsequently, the requirements for register or cache space storage can be reduced, allowing for more compact storage, facilitating rapid integration of subsequent matrix operation structures, reducing memory access latency, and optimizing computational efficiency.

[0101] Next, group matrix A′ i and S′ i The Cartesian product operation is performed in the input matrix computation unit MU to obtain the intermediate result matrix C′. i , That is Data type is represented as type out It can be understood that the Cartesian product refers to the matrix group A′. i and S′ iThe set of all possible ordered pairs between A and B, that is, A′ i Each sub-block in the middle is connected to S′ one by one i The product of the sub-blocks.

[0102] Then the matrix computation unit MU will process the intermediate result matrix C′ i The input vector computation unit VU performs a fusion function operation. This fusion function is matched with the aforementioned temporary parameter t and is used to process the intermediate result matrix C′. i Perform one or more elementary matrix transformations to obtain the result matrix C from the transformed matrix. i Reconstruct the target matrix D from the middle i .in, The result matrix C i The target matrix D exists in i That is, matrix A i and S i The expected result of multiplication. (D) i The data type is type out .

[0103] In this implementation, the fusion function defines the type, number, and order of elementary transformations. The types of elementary transformations include: performing non-zero scalar multiplication on a row or column of a matrix; adding a row or column of any multiple of the matrix to another row or column; and swapping the positions of any two rows or columns of a matrix.

[0104] As an example, combined Figure 4 The principles for determining the fusion function include:

[0105] The matrix computation unit MU obtains the input parameter: intermediate result matrix C′. i Intermediate result matrix C′ i The dimensions m, n, g, and temporary parameter t are given. Based on m, n, g, and t, the corresponding fusion function is determined for the intermediate result matrix C′. i The elements in the matrix are shifted so that the elements split into lower-order parts are restored to their higher-order parts. For example, the intermediate result matrix C′... i any element a in row，col row = 0, ..., g-1; col = 0, ..., g-1, for the intermediate result matrix C′ i The shifting process of an element can be represented as:

[0106] “C′ i [m_row:m_row+m,n_col:n_col+n]←C′ i [m_row:m_row+m,n_col:n_col+n]<<(row+col)t”;

[0107] In other words, from the intermediate result matrix C′ i Extract an m×n submatrix, starting at position (m_row, n_col). The submatrix has the following element range: row indices from "m_row" to "m_row+m-1" (m rows in total), and column indices from "n_col" to "n_col+n-1" (n columns in total). Shift each element of the submatrix left by a number of bits (row+_col)t, and assign the shift result to C′. i The corresponding position.

[0108] The process of extracting the target matrix can then be represented as: C i [0:m,0:n]←C′ i [0:m,0:n]+C′ i [m row :m row +m,n col :n col +n]. That is to say, from the intermediate result matrix C′ i Extract the top-left submatrix C′ i [0:m,0:n], and the submatrix C′ of the offset region i [m row :m row +m,n col :n col +n], submatrix C′ i [0:m,0:n] and C′ i [m row :m row +m,n col :n col Add elements one by one (+n), and assign the result to C. i The target matrix is ​​obtained from the [0:m,0:n] region in the upper left corner: D i [0:m,0:n].

[0109] Thus, based on this embodiment, the computing device 00 offloads the main algebraic operations of the computational task to the tensor computing device 210. The tensor computing device 210 has two computational capabilities: a matrix computation unit MU handles matrix multiplication, and a vector computation unit VU performs operations on various vectorized data, jointly solving large integer matrix multiplication. This allows the tensor computing device 210, whose computational performance is limited (e.g., only supporting small integer matrix multiplication), to also support large integer matrix multiplication, expanding its application scenarios to include, for example, encryption and decryption processing based on unstructured lattice cryptography algorithms, completing end-to-end computational tasks.

[0110] The example above illustrates D in a single computational task. i =Ai S i The relevant processing procedures are described below for X computational tasks D1=A1S1, D2=A2S2,…,D X =A X S X The processing procedure.

[0111] For example, in this embodiment, in order to efficiently complete the calculation task involving large integer matrix multiplication, the computing power and parallel capabilities of the tensor computing device 210 can be used to realize the batch processing of the calculation task to optimize the calculation efficiency.

[0112] In this example, please refer to Figure 5A If all u matrix computation units MU in the tensor computing device 210 are operating at full capacity, then in this case, for the tensor computing device 210 to receive X sets of independent matrix multiplication computation tasks: D1=A1S1, D2=A2S2,…,D X =A X S X Each matrix computation unit (MU) can handle at least one computation task.

[0113] Furthermore, it is understandable that, for a single matrix multiplication computation task, the physical addresses of each sub-block in the matrix group reconstructed from the large integer matrix involved in the task are contiguous. And in X groups of matrix multiplication computation tasks, all A... i The reconstructed matrix group A′ is obtained from (i = 1, 2, ..., X). i Their physical address spaces are of the same size and contiguous, all S i The reconstructed matrix group S′ (i = 1, 2, ..., X) is obtained by reconstructing the matrix. i Their physical address spaces are the same size and contiguous.

[0114] Therefore, in order to ensure that each matrix computation unit MU obtains the correct matrix group sub-blocks, when reconstructing each matrix group A′ i S′ i Subsequently, the matrix computation unit MU can obtain the required sub-block through the addressing function F. The addressing function F can be used to calculate the address difference between elements with the same position index between adjacent matrix groups.

[0115] For example, to obtain matrix group A′ i Taking a sub-block as an example, the corresponding addressing function F can be defined as:

[0116]

[0117] Therefore, for any w-th (1≤w≤u) matrix computation unit MU, the pointer of this matrix computation unit MU can be set to start from all left matrix groups A′. i base address (e.g.) Figure 5A Middle pointer The address pointed to is offset by offset*(w-1) units, which is used as the address to retrieve the data, so that the w-th matrix group A′ can be moved from that address. w The neutron block enters the matrix computation unit MU. Similarly, the w-th matrix group S′ is obtained based on the corresponding addressing function F. w Neutron block. After the transfer is complete, the matrix computation unit MU can execute matrix group A′. w With matrix group S′ w The Cartesian product.

[0118] Thus, if all u matrix computation units MU on the tensor computing device 210 execute matrix group A′ i ·S′ i The calculation process, where each matrix calculation unit (MU) supports a maximum of v tasks, means that calling all MUs to complete one calculation can accomplish a maximum of uv matrix multiplication tasks. For example... Figure 5B As shown, let Δt be the time required for all MUs to complete one calculation. Then, based on this embodiment, the minimum time required is only Δt. All X computational tasks can be completed in a short time. Therefore, this embodiment can fully utilize the parallel computing capabilities between the various components of the tensor computing device 210 to parallelize the data scheduling of the large integer matrix multiplication computation tasks involved in scenarios such as unstructured lattice cryptography algorithms, thereby achieving batch processing and improving computational efficiency.

[0119] The following example illustrates the implementation process of this embodiment using encryption and decryption scenarios based on unstructured lattice cryptography algorithms.

[0120] In some possible implementations, such as Figure 6 As shown, client 02 uses an unstructured lattice cryptography algorithm (such as the Scloud+[WZZ+24] lattice cryptography algorithm) to generate a public key pk, and can send the public key pk to the server side through an insecure channel. In this way, the server side can use the public key pk to encrypt plaintext messages to conduct encrypted message interaction with client 01 in an insecure channel.

[0121] In this implementation, the client can use the built-in random number generator on the host side to generate a random number seed. Alice And based on the random number seed Alice Generate a random matrix A Alice Private key S Alice (is a randomly generated matrix) and noise vector EAlice Next, the client's host side will seed the random number. Alice Random matrix A Alice Private key S Alice and noise vector E Alice Together as raw input data U Alice The key is sent to the client's tensor computing device 002, which is then instructed to generate a public key pk.

[0122] In this implementation, combined with Figure 7 Before generating the public key pk on the tensor computing device 002, the original input data U can be processed first. Alice Data whose data type does not meet the requirements of the matrix computation unit (MU) undergoes preprocessing, while data that meets the MU requirements can directly participate in the computation. Take a random matrix A as an example. Alice For a large integer matrix, the private key S Alice Taking a small integer matrix as an example, if the random matrix A Alice The number of bits in the elements exceeds the input data type requirements of the tensor computing device 002, while the private key S Alice If the number of bits in the elements does not exceed the requirement, then the tensor computing device 002 can process the random matrix A. Alice Conduct similar activities regarding the above. Figure 3 The described reconstruction process. That is, first, the random matrix A... Alice By splitting and recombining, we can obtain, as follows Figure 3 The matrix group A′ shown includes two sub-blocks. Alice Then calculate the matrix group A′. Alice (i.e., its two sub-blocks) and private key S Alice The Cartesian product is used to obtain the intermediate result matrix C′. Alice Then the intermediate result matrix C′ Alice The vector computation unit VU performs a similar fusion function process as shown in the graph above to reconstruct the random matrix A. Alice With private key S Alice The product D Alice .

[0123] Thus, the tensor computing device 002 will use the random matrix A Alice and private key S Alice The product D Alice With noise vector E Alice By summing the results, we can obtain the public key matrix B. Then, the public key pk can be the public key matrix B and the random number seed seed. Alice The joint representation, i.e., pk = (seed Alice B).

[0124] Next, refer to again Figure 6 The client's tensor computation device 002 can send the public key pk to the server's host side via an insecure channel. The server's host side uses the same unstructured lattice cryptographic algorithm based on a random number seed. Alice Generate your own random matrix A BOb Private key S BOb and noise vector E1 BOb and E2 BOb The message is encoded into a plaintext vector M. Then, the host side uses a random matrix A. BOb Private key S BOb Noise vector E1 BOb and E2 BOb Together with the plaintext vector M, it serves as the original input data U. Bob The tensor computing device 210 is sent to server 00, and instructions are given to encrypt the plaintext vector M.

[0125] Next, as Figure 8 As shown, the tensor computing device 210 can generate composite ciphertext C1|C2 when encrypting a plaintext vector M. Here, C1 is an auxiliary ciphertext vector used to obfuscate the plaintext information, and C1 = S. BOb ·A BOb +E1 BOb C2 is the main ciphertext vector containing the plaintext vector M, C2 = S BOb ·B+E2 BOb +M. Before generating the composite ciphertext C1|C2, if the matrix multiplication calculations involved (e.g., private key S) are performed... BOb ·A BOb 、or S BOb •B) If the data type of any matrix does not match the input data type of the tensor computation device, then the matrix can be processed similarly to the above. Figure 3 The described refactoring process. This example uses A... BOb Taking a large integer matrix as an example, to simplify the calculation, the matrix calculation unit MU of the tensor calculation device 210 can calculate A... BOb Concatenated with B to form a concatenation matrix A BOb |B, then concatenate matrix A BOb |B makes a similar statement regarding the above. Figure 3 The described reconstruction process yields a matrix group (A) containing two sub-blocks. BOb |B)′. Then calculate (A)′. BOb |B)′ and private key S BOb The Cartesian product yields the intermediate result matrix C′. Bob Then through similar means as described above Figure 4 The fusion function shown processes the intermediate result matrix C′. Bob Restore ABOb |B and private key S BOb The product D Bob .

[0126] Then, the noise vector E2 BOb The sum of the plaintext vector M (E2) BOb +M) can be combined with the noise vector E1 BOb By concatenating the vectors, we obtain the concatenated vector E1. BOb |(E2 BOb +M). Concatenated vector E1 BOb |(E2 BOb +M) and product D Bob The sum of these two ciphertexts is the composite ciphertext C1|C2. The composite ciphertext C1|C2 can be processed by post-encryption operations (such as compression) to obtain the ciphertext C.

[0127] Then, tensor computing device 210 can send the generated ciphertext C to client 01's tensor computing device 002 via an insecure channel. Client 01's tensor computing device 002 decrypts the ciphertext using the same unstructured lattice cryptographic algorithm. For example... Figure 9 As shown, the decryption process includes first performing pre-decryption processing (e.g., decompression) on the ciphertext C to obtain the composite ciphertext C1|C2, and then performing the inverse operation of the above encryption process on the composite ciphertext C1|C2. That is, the plaintext vector M = C2 - C1S Alice Therefore, the matrix computation unit MU of the tensor computing device 002 first splits and reorganizes the large integer matrix C1, reconstructing it into a matrix group C1′ containing two sub-blocks. The matrix group C1′ and S Alice The Cartesian product result, after being processed by the fusion function, can be used to recover C1S. Alice The expected result. Then, the vector computation unit VU of the tensor computation device 002 performs vector subtraction C2-C1S. Alice This yields the plaintext vector M.

[0128] Understandably, in this example, since the pre-decryption processing is a scalar multiplication operation, decompressing first and then performing multiplication on the relevant data, or performing multiplication on the relevant data first and then decompressing, does not affect the final calculation result.

[0129] In other possible implementations, the encryption and decryption process between client 01 and server 00 can also be implemented using the unstructured lattice post-quantum algorithm FrodoKEM[ABD+21]. For example, Figure 10 The computational process for encryption and decryption using the unstructured lattice post-quantum algorithm FrodoKEM[ABD+21] is shown, which is consistent with... Figures 7 to 9The main difference in the computation process is that, compared to the lightweight Scloud+[WZZ+24] lattice cryptography algorithm, the unstructured lattice post-quantum algorithm FrodoKEM[ABD+21] has a larger matrix size and higher bit width to provide higher security strength. Therefore, when using the unstructured lattice post-quantum algorithm FrodoKEM[ABD+21] between ends, the tensor computing device 002 or 210 will reconstruct the large integer matrix into a matrix group with a lower bit width during matrix multiplication operations (e.g., ...). Figure 10 In the key generation, encryption, and decryption processes, the random matrix A and the concatenated matrix A|B are all split into three sub-blocks to achieve lossless precision adaptation to the computing environment provided by the tensor computing device, thus efficiently completing the process. Figure 10 The calculation process is shown below.

[0130] It is understandable that, in addition to the above-mentioned scenarios of encryption and decryption using unstructured lattice cryptography algorithms, the computational efficiency of large integer matrix multiplication calculations involved in scenarios such as end-to-end digital signatures, end-to-end key exchange protocols, and similar scenarios based on unstructured lattice cryptography algorithms can be accelerated using the principles of this embodiment, which will not be elaborated further.

[0131] Next, based on the content described above, a data processing method provided by an embodiment of this application will be introduced. It is understood that this method is proposed based on the content described above, and some or all of the content of this method can be found in the description above.

[0132] Please see Figure 11 , Figure 11 This is a flowchart illustrating a data processing method provided in an embodiment of this application. It is understood that this method can be executed by any device, equipment, platform, or device cluster with computing and processing capabilities, for example in... Figure 1 It is executed on the computing device 00 shown, but is not limited to this. For example... Figure 11 As shown, the method may include:

[0133] S1110, obtain the first and second matrices to be multiplied.

[0134] In this embodiment, the tensor computing device of the computing device can obtain the first matrix and the second matrix to be multiplied from the host side or the tensor computing device of another computing device. For example, the computing device can be a client or a server, and the tensor computing device interface may include a Graphics Processing Unit (GPU), a Tensor Processing Unit (TPU), and / or a Neural Processing Unit (NPU), but is not limited thereto. In some possible examples, the tensor computing device 210 may include several matrix computing units (MU) and multiple vector computing units (VU) to be responsible for matrix multiplication calculations and vectorized data operations, respectively.

[0135] For example, the first and second matrices to be multiplied can also be referred to as the left and right matrices, respectively. The first and second matrices can be of the same data type or different data types; however, for ease of distinction from the input data types of tensor computing devices, this paper will also refer to the data types of the first and second matrices as the first data type. It is understood that the data type of a matrix determines the number of bits in its elements.

[0136] As one possible implementation example, the first and second matrices can be large integer matrices to be multiplied in unstructured lattice cryptographic algorithms, but are not limited to this.

[0137] S1120, Based on the first parameter and the second parameter, reconstruct the first matrix and the second matrix into a first matrix group and a second matrix group, respectively.

[0138] In this embodiment, the first parameter is used to characterize that the input data type of the tensor computing device is a second data type, and the number of bits per matrix element represented by the second data type is lower than the number of bits per matrix element represented by the first data type. In other words, the first parameter reflects that the number of bits per element of the first matrix and the second matrix is ​​greater than the number of bits per element of the input matrix required by the tensor computing device.

[0139] Therefore, in this embodiment, the tensor computing device can reconstruct the first matrix and the second matrix according to the preset second parameter, so that they are both converted into small integer matrix groups, namely the first matrix group and the second matrix group, so that the data types of the first matrix group and the second matrix group match the input data type required by the tensor computing device (that is, not greater than the input data type).

[0140] For example, the second parameter is used to determine the pattern of reconstruction. The pattern of reconstruction can be expressed as the bit width of the elements of the matrix group after reconstruction and the way all sub-blocks in the matrix group are recombined (e.g., splicing in the column direction of the first matrix or splicing in the row direction of the second matrix), but is not limited to this.

[0141] Furthermore, it should be noted that in this embodiment, if the data type of the first matrix and / or the second matrix does not match the input data type required by the tensor computing device, matrix reconstruction is performed. If the data type of the first matrix or the second matrix matches the input data type required by the tensor computing device, then the matched matrix does not need to be reconstructed and can directly participate in the calculation in S1130 below. In other words, if the data type of the first matrix or the second matrix matches the input data type required by the tensor computing device, then the reconstructed matrix group of the matched matrix is ​​still the matrix itself, and then it participates in the calculation in S1130 below.

[0142] In this way, the first and second matrices can be reconstructed into a matrix group that is compatible with the computing environment provided by the tensor computing device without loss of accuracy. This allows subsequent matrix multiplication operations to be performed without changing the hardware performance, thus accelerating the computational efficiency.

[0143] S1130, perform Cartesian product operation on the first matrix group and the second matrix group to obtain the intermediate result matrix.

[0144] In this embodiment, the tensor computing device performs a Cartesian product operation on the reconstructed first matrix group and second matrix group to obtain the product of all possible ordered combinations between the first matrix group and the second matrix group. That is, the first sub-block of the first matrix group is multiplied by each sub-block in the second matrix group, the second sub-block of the first matrix group is multiplied by each sub-block in the second matrix group, and so on, thereby obtaining the intermediate result matrix.

[0145] S1140, using a fusion function matched with the second parameter, the target matrix is ​​recovered from the intermediate result matrix. The target matrix is ​​the expected result of multiplying the first matrix and the second matrix.

[0146] In this embodiment, the tensor computing device can determine a matching fusion function based on the second parameter. In other words, the fusion function is the reverse processing of the above-mentioned reconstruction pattern to restore the target matrix from the intermediate result matrix, which is the expected result of multiplying the first matrix and the second matrix. In this way, the computing device offloads the main algebraic operations of the computing task to the tensor computing device, enabling tensor computing devices with limited computing performance (e.g., only supporting small integer matrix multiplication) to also support large integer matrix multiplication. This expands the application scenarios of tensor computing devices, such as encryption and decryption processing based on unstructured lattice cryptography algorithms, to complete end-to-end computing tasks.

[0147] The data processing method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0148] For example, Figure 12 A flowchart illustrating a data processing method is shown, compared to... Figure 11 The process shown is... Figure 12 The process shown is as follows Figure 11 Further details of the illustrated process. For example... Figure 12 As shown, this method may include:

[0149] S1210, obtain the first matrix and the second matrix.

[0150] In this example, the execution principle of S1210 is similar to that of S1110 in the above example, and will not be repeated here.

[0151] S1220, if there are several pairs of first matrices and second matrices to be multiplied, then according to the first parameter and the second parameter, each pair of first matrices and second matrices is reconstructed into a first matrix group and a second matrix group respectively.

[0152] In this example, if the tensor computing device of the computing device obtains several pairs of first and second matrices to be multiplied, then for each pair of first and second matrices to be multiplied, a process similar to S1120 in the example above can be performed to obtain several groups of first and second matrices to be multiplied. The reconstruction process of each group of matrices can refer to S1120 in the example above, and will not be repeated here.

[0153] In some possible implementations, if the number of bits of the elements in the first matrix and the second matrix are respectively the number of bits of the first matrix b A Second bit number b S The second parameter includes the target bit width, and the target bit width does not exceed the number of bits of the matrix element represented by the second data type; therefore, for each pair of the first matrix and the second matrix, S1220 may specifically include;

[0154] S1221, according to the target bit width, split each element in the first matrix into at least two sub-elements in an orderly manner, and obtain at least two first sub-blocks.

[0155] In this example, the tensor computing device can split each element in the first matrix according to the target bit width to obtain the corresponding sub-blocks. This principle can be found in the previous section on matrix A. i The explanation of breaking it down into sub-blocks will not be repeated here.

[0156] S1222, at least two first sub-blocks are spliced ​​together in the column direction of the first matrix to obtain a first matrix group including at least two first sub-blocks.

[0157] In this example, the principle by which the tensor computing device splices the sub-blocks split from the first matrix can be found in the above explanation of matrix A. i The sub-blocks are reorganized into matrix group A′ i The explanation will not be repeated here.

[0158] S1223, Based on the target bit width, each element in the second matrix is ​​divided into at least two sub-elements in an orderly manner, and at least two second sub-blocks are obtained;

[0159] S1224, at least two second sub-blocks are spliced ​​together in the column direction of the second matrix to obtain a second matrix group including at least two second sub-blocks.

[0160] Similarly, in this example, the principle by which the tensor computing device splits the second matrix into sub-blocks and then reassembles them can be found in the above explanation of matrix S. i Divide into multiple sub-blocks and recombine the sub-blocks into a matrix group S′ i The explanation will not be repeated here.

[0161] After obtaining each pair of first and second matrix groups through S1220, this method includes:

[0162] S1230 performs a Cartesian product operation between the first and second matrix groups in each group to obtain an intermediate result matrix.

[0163] In this example, the tensor computation device of the computing device may include u matrix computation units, where u is a positive integer. Therefore, after reconstructing several first and second matrix groups to be multiplied, one matrix computation unit can perform the Cartesian product calculation for at least one pair of the first and second matrix groups.

[0164] For example, in order to ensure that the first matrix group and the second matrix group obtained by each matrix calculation unit are correct, in this example, S1230 may include the following S1231 to S1273.

[0165] S1231, for the w-th matrix calculation unit, determine the base addresses of all first matrix groups and all second matrix groups from several pairs of first matrix groups and second matrix groups.

[0166] In this example, a matrix computation unit can perform the Cartesian product operation on at least one pair of matrix groups. Therefore, in a batch computation, any w-th matrix computation unit can perform the Cartesian product operation on the current w-th pair of matrix groups. 1 ≤ w ≤ u.

[0167] Furthermore, the physical addresses of all sub-blocks within a matrix group are contiguous, and the physical address spaces of matrix groups reconstructed from several similar matrices (such as a left matrix or a right matrix) are of the same size and contiguous. Therefore, the base address of the first matrix group in the left and right matrices can be determined first.

[0168] S1232 uses addressing functions to determine the address difference of elements with the same position index between adjacent matrix groups.

[0169] In this example, the execution principle of S1232 can be found in the section above on using the addressing function F to determine the matrix group A. i+1 ′ and A i The address difference of ′ and the matrix group S i+1 ′ and S i The process of calculating the address difference between ' and ' will not be elaborated further.

[0170] In other words, if the maximum number of tasks supported within each matrix computation unit is 1, then when the tensor computation device receives multiple independent pairs of matrix groups, it calculates A′ on the one hand. i and A′ i+1 The address difference between them is offset_A: offset_A = address(A′) i+1 )-address(A′ i ) = m′*k′*sizeof(type in On the other hand, calculate S′ i and S′ i+1 The address difference between them is offset_S: offset_S = address(S′) i+1 )-address(S′ i )=n′*k′*sizeof(type in ).

[0171] S1233, the w-th matrix calculation unit obtains the corresponding first matrix group and second matrix group from the address difference of w units offset from the base address and performs multiplication operation to obtain a sub-result. The sub-result is used to sum with the sub-results obtained in parallel by the remaining matrix calculation units to obtain an intermediate result matrix.

[0172] In this example, the w-th matrix calculation unit obtains the corresponding first matrix group (i.e., its sub-blocks) from the base address of the first matrix by offsetting by w units, and obtains the corresponding second matrix group (i.e., its sub-blocks) from the base address of the second matrix by offsetting by w units. Then, it can perform the Cartesian product operation of the subsequent matrix groups to obtain the sub-result.

[0173] S1240 uses a fusion function that matches the second parameter to reconstruct the target matrix from the intermediate result matrix.

[0174] In this example, the execution principle of S1240 is similar to that of S1140 in the previous example, and may specifically include:

[0175] S1241, Based on the second parameter, determine the manner, number, and order of the elementary transformations included in the fusion function.

[0176] In this step, the second parameter determines the pattern of matrix reconstruction. Therefore, the tensor computing device can determine the matching fusion function based on the second parameter. As an example, the fusion function may include the manner, number, and order of one or more elementary transformations.

[0177] S1242, the intermediate result matrix is ​​transformed by the fusion function to obtain the target matrix.

[0178] In this example, the execution principle of S1242 is similar to that of S1140 in the previous example, and specifically may include the matrix C′ described above. i Reconstruct the target matrix D i The explanation will not be repeated here.

[0179] The following section describes the implementation process of the data processing method provided in this embodiment, using the encryption and decryption scenarios of unstructured lattice cryptography algorithms as an example.

[0180] For example, such as Figure 13 As shown, a first computing device (which may be a client) and a second computing device (which may be a server) can exchange encrypted data using an unstructured lattice cryptographic algorithm through an insecure channel. In this scenario, the method may include:

[0181] S1301, the tensor computing device of the first computing device obtains the random matrix and the private key.

[0182] In this step, the first device can use its built-in random number generator to generate a random number seed. Alice And based on the random number seed Alice Generate a random matrix A Alice Private key S Alice (a randomly generated matrix) and noise vector E Alice (A random vector).

[0183] Next, the host side of the first device will send the random number seed. Alice Random matrix A Aiice Private key S Alice and noise vector E Alice The message is sent to the tensor computing device side of the first computing device, and the tensor computing device is instructed to generate a public key pk.

[0184] For example, to facilitate differentiation of the input data type of the tensor computation device for the client described below, this example will use a random matrix A. Alice Private key S Alice The data type is called the first data type, but the random matrix A Alice Private key S Alice The data types can be different.

[0185] S1302, the tensor computing device of the first computing device reconstructs the random matrix and the private key into corresponding matrix groups according to the first parameter and the second parameter set thereon.

[0186] In this step, the first parameter is used to characterize the input data type of the tensor computation device in the first computing device as the second data type. Before the tensor computation device of the first computing device generates the public key pk, data whose data type does not meet the requirements of the matrix computation unit MU can be preprocessed, while data that meets the requirements of the matrix computation unit MU can directly participate in the computation. Taking a random matrix A as an example... Alice For a large integer matrix, the private key S Alice Taking a small integer matrix as an example, if the random matrix A Alice The number of bits in the elements exceeds the requirements of the tensor computing device for the input data type, and the private key S Alice If the number of bits in the elements does not exceed this requirement, then the tensor computing device can process the random matrix A. Alice Conduct similar activities regarding the above. Figure 3 The described reconstruction process. That is, first, the random matrix A... Alice By splitting and recombining, we can obtain, as follows Figure 3 The matrix group A′ shown includes two sub-blocks. Alice And the private key S Alice It does not need to be reconstructed and can also be regarded as private key S. Alice The reconstructed matrix still contains the private key S. Alice .

[0187] S1303, the tensor computing device of the first computing device performs a Cartesian product operation on the acquired matrix group to obtain an intermediate result matrix.

[0188] In this step, the tensor computation device of the first device can process matrix group A′ Alice and matrix group S Alice Perform the Cartesian product operation to obtain the intermediate result matrix C′. Alice The calculation process is similar to the description of S1130 above, and will not be repeated here.

[0189] S1304, the tensor computing device of the first computing device uses a fusion function that matches its second parameter to reconstruct the corresponding target matrix from the intermediate result matrix. The target matrix is ​​the expected result of multiplying a random matrix and a private key.

[0190] In this step, the tensor computation device of the first device can utilize a fusion function matched with the second parameter to obtain the intermediate result matrix C′. Alice Reconstruct the target matrix D from the middle Alice The restoration process is similar to the description of S1140 above, and will not be repeated here.

[0191] S1305, the tensor computing device of the first computing device performs an addition operation on the target matrix and the corresponding noise vector to obtain a first result matrix, which is used as the public key in the unstructured lattice cryptographic algorithm.

[0192] In this step, the tensor computation device of the first device can compute the target matrix D. alice With noise vector E Alice By summing the results, we can obtain the public key matrix B. Then, the public key pk can be the public key matrix B and the random number seed seed. Alice The joint representation, i.e., pk = (seed Alice B).

[0193] S1306, The second computing device receives the public key.

[0194] In this step, the host side of the second computing device can obtain the public key pk from the first computing device through an insecure channel. An insecure channel refers to a channel through which the communicating parties cannot guarantee the complete confidentiality or tamper-proof nature of the transmitted data.

[0195] S1307, the second computing device uses the public key to obtain the private key of the second computing device and the concatenation matrix, which is a matrix formed by concatenating the public key with a random matrix generated by the public key.

[0196] In this step, similar to the execution principle of S1301, the host side of the second computing device can utilize the random number seed in the public key pk. Alice Generate your own random matrix A BOb Private key S BOb and noise vector E1 BOb (a random vector) and E2 BOb (Another random vector), and together with the plaintext vector M of the message, it is sent to the tensor computing device side of the second computing device.

[0197] Next, the tensor computing device of the second computing device can compute the random matrix A BObIt is concatenated with the public key vector B (i.e., the tensor representation of the public key pk) to form a concatenation matrix.

[0198] S1308, the tensor computing device of the second computing device reconstructs the spliced ​​matrix and the corresponding private key into matrix groups according to the first and second parameters it sets.

[0199] In this example, the execution principle of step S1308 is similar to that of S1302 above, concatenating matrix A. BOb |B needs to be reconstructed and private key S BOb Taking the example of not needing reconstruction, we obtain the corresponding matrix group (A) BOb |B)′、S BOb .

[0200] It should be noted that the tensor calculation device of the second computing device performs this step based on the first and second parameters of its own side (which are different from the first and second parameters of the tensor calculation device in the first computing device).

[0201] S1309, the tensor computing device of the second computing device performs a Cartesian product operation on the concatenated vector and the target matrix to obtain an intermediate result matrix.

[0202] In this example, the execution principle of step S1309 is similar to that of S1303 above, thereby obtaining the intermediate result matrix C′. Bob .

[0203] S1310, the tensor computing device of the second computing device uses a fusion function that matches its second parameter to reconstruct the corresponding target matrix from the intermediate result matrix.

[0204] In this example, the execution principle of step S1309 is similar to that of S1304 above, thereby obtaining the target matrix D. Bob .

[0205] S1311, the tensor computing device of the second computing device concatenates the sum of the plaintext vector and one of the random vectors with another random vector to obtain the concatenated vector.

[0206] In this step, the tensor computation device of the second computing device can combine the plaintext vector M with one of the random vectors E2. BOb Sum, the summation result is combined with another random vector E1 BOb By concatenating the vectors, we obtain the concatenated vector E1. BOb |(E2 BOb +M).

[0207] S1312, the concatenated vector is added to the target matrix to obtain the composite ciphertext of the plaintext vector.

[0208] In this step, the tensor computation device of the second computing device can concatenate vector E1. BOb |(E2 BOb +M) and the target matrix D Bob The sum of these ciphertexts is the composite ciphertext C1|C2. The composite ciphertext C1|C2 can be processed through encryption post-processing (e.g., compression) to obtain ciphertext C. The tensor computing device of the second computing device can send the ciphertext C to the tensor computing device of the first computing device through an insecure channel, thus achieving encrypted information transmission.

[0209] S1313, the tensor computing device of the first computing device acquires the composite ciphertext.

[0210] In this step, the tensor computing device of the first computing device can receive the ciphertext C sent by the second computing device, and then perform corresponding pre-decryption processing (e.g., decompression) on the ciphertext C to obtain the composite ciphertext C1|C2.

[0211] S1314, the tensor computing device of the first computing device reconstructs the main ciphertext component and the private key in the composite ciphertext to obtain the corresponding matrix group.

[0212] In this step, decrypting the composite ciphertext C1|C2 is the inverse operation of the encryption process. Therefore, the plaintext vector M = C2 - C1S Alice Therefore, the tensor computation device of the first computing device first processes the master ciphertext vector C1 and its private key S. Alice The multiplication calculation. Similar to the execution principle of S1302 above, if the master ciphertext vector C1 and its private key S... Alice The matrix that does not match the tensor computation input data type of the first computing device is reconstructed to obtain the corresponding matrix group C1′ and S. Alice .

[0213] S1315, the tensor computing device of the first computing device performs a Cartesian product operation on the obtained matrix group to obtain an intermediate result matrix.

[0214] S1316, the tensor computing device of the first computing device uses a fusion function that matches its second parameter to reconstruct the corresponding target matrix from the intermediate result matrix.

[0215] In this example, steps S1315 to S1316 are similar to steps S1303 to S1304 described above. The tensor computation device of the first computing device computes the matrix group C1′ and S. Alice The Cartesian product is obtained, and C1S is reconstructed from the intermediate result matrix. Alice The expected result (i.e., the target matrix).

[0216] S1317, perform vector subtraction on the target matrix and the auxiliary ciphertext component to obtain the plaintext vector.

[0217] In this example, the tensor computation device of the first computing device performs vector subtraction C2-C1S. Alice This yields the plaintext vector M, which is returned to the host side of the first computing device and decoded into a plaintext message.

[0218] Thus, this embodiment enables tensor computing devices that do not fully support large integer matrix multiplication, and even those that only support smaller data types of input (mainly their matrix operation units), to be used to accelerate end-to-end computation tasks (including large integer matrix multiplication) of standard unstructured lattice cryptographic algorithms (including the FrodoKEM algorithm), significantly improving the overall performance of such algorithms. Furthermore, during the execution of computation tasks, the parallel computing capabilities between the various components of the tensor computing device can be fully utilized to achieve batch processing of cryptographic algorithm tasks, further improving computational efficiency.

[0219] For example, through experiments, the data processing method provided in this embodiment significantly improves the performance of each computational part (such as key generation and message encryption) implemented on the training server, as shown in Table 1 below.

[0220] Table 1

[0221]

[0222] As shown in Table 1, the reference implementation for tensor computation devices (such as CPUs) can achieve a speedup of over 100 times, and the CPU implementation optimized for AVX2 (Advanced Vector Extensions 2, an extended instruction set in CPUs) also shows a speedup of over 10 times. For the decryption part, due to the smaller dimension of matrix multiplication, the optimization speedup is approximately 6 to 7 times.

[0223] Therefore, the method of this embodiment can ensure that related products and devices, such as training servers, have quantum computing-resistant security features without changing the hardware environment, thus meeting relevant access requirements and improving the competitiveness of similar products and devices. Furthermore, it is conceivable that other devices with high-speed matrix operation capabilities, such as AIPCs and AI phones, can also apply the method provided in this embodiment to achieve efficient operation of post-quantum algorithms, providing these devices with quantum computing-resistant security features.

[0224] This application also provides a data processing apparatus, such as... Figure 14 As shown, it includes:

[0225] The acquisition module 1301 is used to acquire the first matrix and the second matrix to be multiplied, wherein the first matrix and the second matrix are of the first data type;

[0226] The processing module 1302 is used to reconstruct the first matrix and the second matrix into a first matrix group and a second matrix group respectively according to the first parameter and the second parameter; wherein, the first parameter is used to characterize the input data type of the tensor computing device as a second data type, the number of bits of the matrix elements characterized by the second data type is lower than the number of bits of the matrix elements characterized by the first data type, and the second parameter is used to determine the pattern of the reconstruction, wherein the first matrix group and the second matrix group are the second data type;

[0227] The processing module 1302 is further configured to perform a Cartesian product operation on the first matrix group and the second matrix group to obtain an intermediate result matrix.

[0228] The processing module 1302 is further configured to use a fusion function matched with the second parameter to reconstruct the target matrix from the intermediate result matrix, wherein the target matrix is ​​the expected result of multiplying the first matrix and the second matrix.

[0229] Both the acquisition module 1301 and the processing module 1302 can be implemented in software or in hardware. For example, the implementation of the acquisition module 1301 will be described below. Similarly, the implementation of the processing module 1302 can refer to the implementation of the acquisition module.

[0230] As an example of a software functional unit, module 1301 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the acquisition module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0231] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0232] As an example of a hardware functional unit, the acquisition module 1301 may include at least one computing device, such as a server. Alternatively, the acquisition module may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0233] The multiple computing devices included in the acquisition module 1301 can be distributed in the same region or in different regions. Similarly, the multiple computing devices included in the acquisition module can be distributed in the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in module A can be distributed in the same VPC or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0234] It should be noted that, in other embodiments, the acquisition module 1301 can be used to execute any step in the data processing method, and the processing module 1302 can be used to execute any step in the data processing method. The steps implemented by the acquisition module and the processing module 1302 can be specified as needed. The data processing device can realize all functions by implementing different steps in the data processing method through the acquisition module 1301 and the processing module 1302 respectively.

[0235] This application also provides a computing device 100. For example... Figure 15As shown, the computing device 100 includes a bus 102, a processor 104, a memory 106, and a communication interface 108. The processor 104, the memory 106, and the communication interface 108 communicate with each other via the bus 102. The computing device 100 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 100.

[0236] Bus 102 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 15 The bus 104 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 104 may include a path for transmitting information between various components of the computing device 100 (e.g., memory 106, processor 104, communication interface 108).

[0237] The processor 104 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0238] Memory 106 may include volatile memory, such as random access memory (RAM). Processor 104 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0239] The memory 106 stores executable program code, which the processor 104 executes to implement the functions of the aforementioned acquisition module 1301 and processing module 1302, thereby realizing the data processing method. In other words, the memory 106 stores instructions for executing the data processing method.

[0240] The communication interface 103 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 00 and other devices or communication networks.

[0241] This application also provides a computing device cluster. The computing device cluster includes at least one computing device. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone.

[0242] like Figure 16 As shown, the computing device cluster includes at least one computing device 100. The memory 106 of one or more computing devices 100 in the computing device cluster may store the same instructions for executing data processing methods.

[0243] In some possible implementations, the memory 106 of one or more computing devices 100 in the computing device cluster may also store partial instructions for executing data processing methods. In other words, a combination of one or more computing devices 100 can jointly execute instructions for executing data processing methods.

[0244] It should be noted that the memory 106 in different computing devices 100 within the computing device cluster can store different instructions, each used to execute a portion of the functions of the data processing device. That is, the instructions stored in the memory 106 of different computing devices 100 can implement the functions of one or more modules in the acquisition module 1301 and processing module 1302.

[0245] In some possible implementations, one or more computing devices in a computing device cluster can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc. Figure 17 One possible implementation is shown. For example... Figure 17 As shown, two computing devices 100A and 100B are connected via a network. Specifically, they are connected to the network through communication interfaces in each computing device. In this possible implementation, the memory 106 in computing device 100A stores instructions for executing the functions of the acquisition module 1301. Simultaneously, the memory 106 in computing device 100B stores instructions for executing the functions of the processing module 1302.

[0246] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform a data processing method, or a data processing procedure.

[0247] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform a data processing method, or instruct the computing device to perform a data processing method.

[0248] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method, characterized in that, The method is applied to a tensor computing device in a computing device, and the method includes: Obtain the first and second matrices to be multiplied, where the first and second matrices are of the first data type; Based on the first parameter and the second parameter, the first matrix and the second matrix are reconstructed into a first matrix group and a second matrix group, respectively; wherein, the first parameter is used to characterize the input data type of the tensor computing device as a second data type, the number of bits of the matrix elements characterized by the second data type is lower than the number of bits of the matrix elements characterized by the first data type, and the second parameter is used to determine the pattern of the reconstruction, wherein the first matrix group and the second matrix group are the second data type; Perform a Cartesian product operation on the first matrix group and the second matrix group to obtain an intermediate result matrix; Using a fusion function that matches the second parameter, the target matrix is ​​reconstructed from the intermediate result matrix, the target matrix being the expected result of multiplying the first matrix and the second matrix.

2. The method according to claim 1, characterized in that, The tensor computing device includes u matrix computing units, where u is a positive integer; if there are several pairs of the first and second matrices to be multiplied, then the several pairs of the first and second matrix groups are reconstructed. The step of performing a Cartesian product operation between the first matrix group and the second matrix group to obtain an intermediate result matrix includes: For the w-th matrix calculation unit, determine the base address of each of the first matrix group and the second matrix group from the plurality of pairs of first matrix groups and second matrix groups; 1≤w≤u; The address difference between elements with the same position index in adjacent matrix groups is determined using addressing functions. The w-th matrix calculation unit obtains the corresponding first matrix group and second matrix group from the address difference offset by w units from the base address and performs a multiplication operation to obtain a sub-result. The sub-result is used to sum with the sub-results obtained in parallel by the remaining matrix calculation units to obtain the intermediate result matrix.

3. The method according to claim 1 or 2, characterized in that, If the number of bits per element in the first or second matrix is ​​lower than the number of bits per element in the matrix represented by the second data type, then the reconstruction is not performed.

4. The method according to claim 1 or 2, characterized in that, The number of bits per element in the first matrix and the second matrix are respectively the first number of bits per element and the second number of bits per element; the second parameter includes a target bit width, which does not exceed the number of bits per element of the matrix represented by the second data type; The step of reconstructing the first matrix and the second matrix into a first matrix group and a second matrix group respectively according to the first parameter and the second parameter includes: Based on the target bit width, each element in the first matrix is ​​sequentially split into at least two sub-elements to obtain the at least two first sub-blocks; By concatenating the at least two first sub-blocks along the column direction of the first matrix, a first matrix group including the at least two first sub-blocks is obtained; Based on the target bit width, each element in the second matrix is ​​sequentially split into at least two sub-elements to obtain the at least two second sub-blocks; By concatenating the at least two second sub-blocks along the column direction of the second matrix, a second matrix group comprising the at least two second sub-blocks is obtained.

5. The method according to any one of claims 1-4, characterized in that, The fusion function includes one or more elementary transformations; The step of reconstructing the target matrix from the intermediate result matrix using a fusion function matched with the second parameter includes: Based on the second parameter, determine the manner, number, and order of the elementary transformations included in the fusion function; The intermediate result matrix is ​​subjected to the elementary transformation by the fusion function to obtain the target matrix.

6. The method according to any one of claims 1-4, characterized in that, The first matrix is ​​a random matrix in an unstructured cryptographic algorithm, and the second matrix is ​​used to represent the private key in the unstructured cryptographic algorithm. After restoring the target matrix from the intermediate result matrix, the method includes: Obtain the first random vector; The target matrix is ​​added to the first random vector to obtain a first result matrix, which is used as the public key in the unstructured lattice cryptography algorithm.

7. The method according to any one of claims 1-4, characterized in that, The first matrix is ​​used to represent the private key in the unstructured cryptographic algorithm, and the second matrix is ​​a concatenated matrix, which is the matrix obtained by concatenating the random matrix and the public key in the unstructured cryptographic algorithm, and the public key matches the private key. After reconstructing the target matrix from the intermediate result matrix, the method includes: Obtain the plaintext vector to be encrypted, the first random vector, and the second random vector; The sum of the plaintext vector and the second random vector is concatenated with the first random vector to obtain the concatenated vector; The concatenated vector is added to the target matrix to obtain the composite ciphertext of the plaintext vector.

8. The method according to claims 1-4, characterized in that, The first matrix is ​​used to represent the private key in the unstructured cipher algorithm. The second matrix is ​​the main ciphertext component obtained by the unstructured cipher algorithm. The main ciphertext component contains the corresponding plaintext vector. The main ciphertext component can be concatenated with the auxiliary ciphertext component to form a composite ciphertext. The auxiliary ciphertext component is used to obfuscate the plaintext information. After reconstructing the target matrix from the intermediate result matrix, the method includes: The plaintext vector is obtained by performing a vector subtraction operation between the target matrix and the auxiliary ciphertext component.

9. A data processing apparatus, characterized in that, The apparatus is used in a tensor computation device within a computing device, and the apparatus includes: The acquisition module is used to acquire the first matrix and the second matrix to be multiplied, wherein the first matrix and the second matrix are of the first data type; The processing module is configured to reconstruct the first matrix and the second matrix into a first matrix group and a second matrix group respectively according to a first parameter and a second parameter; wherein, the first parameter is used to characterize the input data type of the tensor computing device as a second data type, the number of bits of matrix elements characterized by the second data type is lower than the number of bits of matrix elements characterized by the first data type, and the second parameter is used to determine the pattern of the reconstruction, wherein the first matrix group and the second matrix group are the second data type; The processing module is also used to perform a Cartesian product operation on the first matrix group and the second matrix group to obtain an intermediate result matrix. The processing module is further configured to use a fusion function matched with the second parameter to reconstruct the target matrix from the intermediate result matrix, wherein the target matrix is ​​the expected result of multiplying the first matrix and the second matrix.

10. The apparatus according to claim 9, characterized in that, The tensor computing device includes u matrix computing units, where u is a positive integer; if there are several pairs of the first and second matrices to be multiplied, then the several pairs of the first and second matrix groups are reconstructed. The processing module is specifically used for: For the w-th matrix calculation unit, the base addresses of all the first matrix groups and all the second matrix groups are determined from the plurality of pairs of first matrix groups and second matrix groups; 1≤w≤u; The address difference between elements with the same position index in adjacent matrix groups is determined using addressing functions. The w-th matrix calculation unit obtains the corresponding first matrix group and second matrix group from the address difference offset by w units from the base address and performs a multiplication operation to obtain a sub-result. The sub-result is used to sum with the sub-results obtained in parallel by the remaining matrix calculation units to obtain the intermediate result matrix.

11. The apparatus according to claim 9 or 10, characterized in that, If the number of bits per element in the first or second matrix is ​​lower than the number of bits per element in the matrix represented by the second data type, then the reconstruction is not performed.

12. The apparatus according to claim 1 or 2, characterized in that, The number of bits per element in the first matrix and the second matrix are respectively the first number of bits per element and the second number of bits per element; the second parameter includes a target bit width, which does not exceed the number of bits per element of the matrix represented by the second data type; The processing module is specifically used for: Based on the target bit width, each element in the first matrix is ​​sequentially split into at least two sub-elements to obtain the at least two first sub-blocks; By concatenating the at least two first sub-blocks along the column direction of the first matrix, a first matrix group including the at least two first sub-blocks is obtained; Based on the target bit width, each element in the second matrix is ​​sequentially split into at least two sub-elements to obtain the at least two second sub-blocks; By concatenating the at least two second sub-blocks along the column direction of the second matrix, a second matrix group comprising the at least two second sub-blocks is obtained.

13. The apparatus according to any one of claims 9-12, characterized in that, The fusion function includes one or more elementary transformations; The processing module is specifically used for: Based on the second parameter, determine the manner, number, and order of the elementary transformations included in the fusion function; The intermediate result matrix is ​​subjected to the elementary transformation by the fusion function to obtain the target matrix.

14. The apparatus according to any one of claims 9-12, characterized in that, The first matrix is ​​a random matrix in the unstructured cryptographic algorithm, and the second matrix is ​​used to represent the private key in the unstructured cryptographic algorithm. The acquisition module is further configured to: acquire a first random vector; The processing module is further configured to: perform an addition operation on the target matrix and the first random vector to obtain a first result matrix, wherein the first result matrix is ​​used as the public key in the unstructured lattice cryptography algorithm.

15. The apparatus according to any one of claims 9-12, characterized in that, The first matrix is ​​used to represent the private key in the unstructured cryptographic algorithm, and the second matrix is ​​a concatenated matrix, which is the matrix obtained by concatenating the random matrix and the public key in the unstructured cryptographic algorithm, and the public key matches the private key. The acquisition module is further configured to: acquire the plaintext vector to be encrypted, the first random vector, and the second random vector; The processing module is further configured to: The sum of the plaintext vector and the second random vector is concatenated with the first random vector to obtain the concatenated vector; The concatenated vector is added to the target matrix to obtain the composite ciphertext of the plaintext vector.

16. The apparatus according to claims 9-12, characterized in that, The first matrix is ​​used to represent the private key in the unstructured cipher algorithm. The second matrix is ​​the main ciphertext component obtained by the unstructured cipher algorithm. The main ciphertext component contains the corresponding plaintext vector. The main ciphertext component can be concatenated with the auxiliary ciphertext component to form a composite ciphertext. The auxiliary ciphertext component is used to obfuscate the plaintext information. The processing module is further configured to: The plaintext vector is obtained by performing a vector subtraction operation between the target matrix and the auxiliary ciphertext component.

17. A computing device, characterized in that, Including processor and memory; The processor is configured to execute instructions stored in the memory to cause the processor to perform the method as described in any one of claims 1-8.

18. A computing device cluster, characterized in that, It includes at least one computing device, each computing device including a processor and memory; The processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device to cause the cluster of computing devices to perform the method as described in any one of claims 1-8.

19. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device, the computing device performs the method as described in any one of claims 1-8.

20. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, cause the computing device to perform the method as described in any one of claims 1-8.

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